diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip
deleted file mode 100644
index d4cdb1bed7da2be475ed2080c23c8bfc9f534897..0000000000000000000000000000000000000000
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip
+++ /dev/null
@@ -1,1535 +0,0 @@
-<?xml version="1.0" ?>
-<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2b_adc_ram_st_histogram</ipxact:library>
- <ipxact:name>qsys_lofar2_unb2b_adc_ram_st_histogram</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- <ipxact:busInterfaces>
- <ipxact:busInterface>
- <ipxact:name>system</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>clk</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_clk</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="clockRate" type="longint">
- <ipxact:name>clockRate</ipxact:name>
- <ipxact:displayName>Clock rate</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="externallyDriven" type="bit">
- <ipxact:name>externallyDriven</ipxact:name>
- <ipxact:displayName>Externally driven</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="ptfSchematicName" type="string">
- <ipxact:name>ptfSchematicName</ipxact:name>
- <ipxact:displayName>PTF schematic name</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>system_reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>reset</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>csi_system_reset</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="synchronousEdges" type="string">
- <ipxact:name>synchronousEdges</ipxact:name>
- <ipxact:displayName>Synchronous edges</ipxact:displayName>
- <ipxact:value>DEASSERT</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>mem</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>address</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_address</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>write</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_write</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>writedata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>read</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_read</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>readdata</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="addressAlignment" type="string">
- <ipxact:name>addressAlignment</ipxact:name>
- <ipxact:displayName>Slave addressing</ipxact:displayName>
- <ipxact:value>DYNAMIC</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressGroup" type="int">
- <ipxact:name>addressGroup</ipxact:name>
- <ipxact:displayName>Address group</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressSpan" type="string">
- <ipxact:name>addressSpan</ipxact:name>
- <ipxact:displayName>Address span</ipxact:displayName>
- <ipxact:value>32768</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="addressUnits" type="string">
- <ipxact:name>addressUnits</ipxact:name>
- <ipxact:displayName>Address units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
- <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
- <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>Associated clock</ipxact:displayName>
- <ipxact:value>system</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>Associated reset</ipxact:displayName>
- <ipxact:value>system_reset</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bitsPerSymbol" type="int">
- <ipxact:name>bitsPerSymbol</ipxact:name>
- <ipxact:displayName>Bits per symbol</ipxact:displayName>
- <ipxact:value>8</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
- <ipxact:name>bridgedAddressOffset</ipxact:name>
- <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bridgesToMaster" type="string">
- <ipxact:name>bridgesToMaster</ipxact:name>
- <ipxact:displayName>Bridges to master</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
- <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
- <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="burstcountUnits" type="string">
- <ipxact:name>burstcountUnits</ipxact:name>
- <ipxact:displayName>Burstcount units</ipxact:displayName>
- <ipxact:value>WORDS</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
- <ipxact:name>constantBurstBehavior</ipxact:name>
- <ipxact:displayName>Constant burst behavior</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="explicitAddressSpan" type="string">
- <ipxact:name>explicitAddressSpan</ipxact:name>
- <ipxact:displayName>Explicit address span</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="holdTime" type="int">
- <ipxact:name>holdTime</ipxact:name>
- <ipxact:displayName>Hold</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="interleaveBursts" type="bit">
- <ipxact:name>interleaveBursts</ipxact:name>
- <ipxact:displayName>Interleave bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isBigEndian" type="bit">
- <ipxact:name>isBigEndian</ipxact:name>
- <ipxact:displayName>Big endian</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isFlash" type="bit">
- <ipxact:name>isFlash</ipxact:name>
- <ipxact:displayName>Flash memory</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isMemoryDevice" type="bit">
- <ipxact:name>isMemoryDevice</ipxact:name>
- <ipxact:displayName>Memory device</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
- <ipxact:name>isNonVolatileStorage</ipxact:name>
- <ipxact:displayName>Non-volatile storage</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="linewrapBursts" type="bit">
- <ipxact:name>linewrapBursts</ipxact:name>
- <ipxact:displayName>Linewrap bursts</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
- <ipxact:name>maximumPendingReadTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
- <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
- <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumReadLatency" type="int">
- <ipxact:name>minimumReadLatency</ipxact:name>
- <ipxact:displayName>minimumReadLatency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumResponseLatency" type="int">
- <ipxact:name>minimumResponseLatency</ipxact:name>
- <ipxact:displayName>Minimum response latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
- <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
- <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="printableDevice" type="bit">
- <ipxact:name>printableDevice</ipxact:name>
- <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readLatency" type="int">
- <ipxact:name>readLatency</ipxact:name>
- <ipxact:displayName>Read latency</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitStates" type="int">
- <ipxact:name>readWaitStates</ipxact:name>
- <ipxact:displayName>Read wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="readWaitTime" type="int">
- <ipxact:name>readWaitTime</ipxact:name>
- <ipxact:displayName>Read wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
- <ipxact:name>registerIncomingSignals</ipxact:name>
- <ipxact:displayName>Register incoming signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
- <ipxact:name>registerOutgoingSignals</ipxact:name>
- <ipxact:displayName>Register outgoing signals</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="setupTime" type="int">
- <ipxact:name>setupTime</ipxact:name>
- <ipxact:displayName>Setup</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="timingUnits" type="string">
- <ipxact:name>timingUnits</ipxact:name>
- <ipxact:displayName>Timing units</ipxact:displayName>
- <ipxact:value>Cycles</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="transparentBridge" type="bit">
- <ipxact:name>transparentBridge</ipxact:name>
- <ipxact:displayName>Transparent bridge</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="waitrequestAllowance" type="int">
- <ipxact:name>waitrequestAllowance</ipxact:name>
- <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
- <ipxact:name>wellBehavedWaitrequest</ipxact:name>
- <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeLatency" type="int">
- <ipxact:name>writeLatency</ipxact:name>
- <ipxact:displayName>Write latency</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitStates" type="int">
- <ipxact:name>writeWaitStates</ipxact:name>
- <ipxact:displayName>Write wait states</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="writeWaitTime" type="int">
- <ipxact:name>writeWaitTime</ipxact:name>
- <ipxact:displayName>Write wait</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- <ipxact:vendorExtensions>
- <altera:altera_assignments>
- <ipxact:parameters>
- <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
- <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
- <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
- <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_assignments>
- </ipxact:vendorExtensions>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>reset</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_reset_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>clk</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_clk_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>address</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_address_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>write</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_write_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>writedata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_writedata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>read</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_read_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- <ipxact:busInterface>
- <ipxact:name>readdata</ipxact:name>
- <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
- <ipxact:abstractionTypes>
- <ipxact:abstractionType>
- <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
- <ipxact:portMaps>
- <ipxact:portMap>
- <ipxact:logicalPort>
- <ipxact:name>export</ipxact:name>
- </ipxact:logicalPort>
- <ipxact:physicalPort>
- <ipxact:name>coe_readdata_export</ipxact:name>
- </ipxact:physicalPort>
- </ipxact:portMap>
- </ipxact:portMaps>
- </ipxact:abstractionType>
- </ipxact:abstractionTypes>
- <ipxact:slave></ipxact:slave>
- <ipxact:parameters>
- <ipxact:parameter parameterId="associatedClock" type="string">
- <ipxact:name>associatedClock</ipxact:name>
- <ipxact:displayName>associatedClock</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="associatedReset" type="string">
- <ipxact:name>associatedReset</ipxact:name>
- <ipxact:displayName>associatedReset</ipxact:displayName>
- <ipxact:value></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="prSafe" type="bit">
- <ipxact:name>prSafe</ipxact:name>
- <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </ipxact:busInterface>
- </ipxact:busInterfaces>
- <ipxact:model>
- <ipxact:views>
- <ipxact:view>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
- <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
- </ipxact:view>
- </ipxact:views>
- <ipxact:instantiations>
- <ipxact:componentInstantiation>
- <ipxact:name>QUARTUS_SYNTH</ipxact:name>
- <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
- <ipxact:fileSetRef>
- <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
- </ipxact:fileSetRef>
- <ipxact:parameters></ipxact:parameters>
- </ipxact:componentInstantiation>
- </ipxact:instantiations>
- <ipxact:ports>
- <ipxact:port>
- <ipxact:name>csi_system_clk</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>csi_system_reset</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_address</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>12</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_write</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_writedata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_read</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>avs_mem_readdata</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_reset_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_clk_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_address_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>12</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_write_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_writedata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_read_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>out</ipxact:direction>
- <ipxact:vectors></ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- <ipxact:port>
- <ipxact:name>coe_readdata_export</ipxact:name>
- <ipxact:wire>
- <ipxact:direction>in</ipxact:direction>
- <ipxact:vectors>
- <ipxact:vector>
- <ipxact:left>0</ipxact:left>
- <ipxact:right>31</ipxact:right>
- </ipxact:vector>
- </ipxact:vectors>
- <ipxact:wireTypeDefs>
- <ipxact:wireTypeDef>
- <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
- <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
- </ipxact:wireTypeDef>
- </ipxact:wireTypeDefs>
- </ipxact:wire>
- </ipxact:port>
- </ipxact:ports>
- </ipxact:model>
- <ipxact:vendorExtensions>
- <altera:entity_info>
- <ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2b_adc_ram_st_histogram</ipxact:library>
- <ipxact:name>avs_common_mm</ipxact:name>
- <ipxact:version>1.0</ipxact:version>
- </altera:entity_info>
- <altera:altera_module_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="g_adr_w" type="int">
- <ipxact:name>g_adr_w</ipxact:name>
- <ipxact:displayName>g_adr_w</ipxact:displayName>
- <ipxact:value>13</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="g_dat_w" type="int">
- <ipxact:name>g_dat_w</ipxact:name>
- <ipxact:displayName>g_dat_w</ipxact:displayName>
- <ipxact:value>32</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
- <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
- <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
- <ipxact:value>100000000</ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_module_parameters>
- <altera:altera_system_parameters>
- <ipxact:parameters>
- <ipxact:parameter parameterId="device" type="string">
- <ipxact:name>device</ipxact:name>
- <ipxact:displayName>Device</ipxact:displayName>
- <ipxact:value>10AX115U2F45E1SG</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceFamily" type="string">
- <ipxact:name>deviceFamily</ipxact:name>
- <ipxact:displayName>Device family</ipxact:displayName>
- <ipxact:value>Arria 10</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
- <ipxact:name>deviceSpeedGrade</ipxact:name>
- <ipxact:displayName>Device Speed Grade</ipxact:displayName>
- <ipxact:value>1</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="generationId" type="int">
- <ipxact:name>generationId</ipxact:name>
- <ipxact:displayName>Generation Id</ipxact:displayName>
- <ipxact:value>0</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="bonusData" type="string">
- <ipxact:name>bonusData</ipxact:name>
- <ipxact:displayName>bonusData</ipxact:displayName>
- <ipxact:value>bonusData
-{
- element $system
- {
- datum _originalDeviceFamily
- {
- value = "Arria 10";
- type = "String";
- }
- }
- element qsys_lofar2_unb2b_adc_ram_st_histogram
- {
- }
-}
-</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
- <ipxact:name>hideFromIPCatalog</ipxact:name>
- <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
- <ipxact:value>false</ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
- <ipxact:name>lockedInterfaceDefinition</ipxact:name>
- <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
- <ipxact:value><boundaryDefinition>
- <interfaces>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>mem</name>
- <type>avalon</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>avs_mem_address</name>
- <role>address</role>
- <direction>Input</direction>
- <width>13</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_write</name>
- <role>write</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <role>writedata</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- <port>
- <name>avs_mem_read</name>
- <role>read</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>embeddedsw.configuration.isFlash</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isMemoryDevice</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isNonVolatileStorage</key>
- <value>0</value>
- </entry>
- <entry>
- <key>embeddedsw.configuration.isPrintableDevice</key>
- <value>0</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>addressAlignment</key>
- <value>DYNAMIC</value>
- </entry>
- <entry>
- <key>addressGroup</key>
- <value>0</value>
- </entry>
- <entry>
- <key>addressSpan</key>
- <value>32768</value>
- </entry>
- <entry>
- <key>addressUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>alwaysBurstMaxBurst</key>
- <value>false</value>
- </entry>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>associatedReset</key>
- <value>system_reset</value>
- </entry>
- <entry>
- <key>bitsPerSymbol</key>
- <value>8</value>
- </entry>
- <entry>
- <key>bridgedAddressOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToMaster</key>
- </entry>
- <entry>
- <key>burstOnBurstBoundariesOnly</key>
- <value>false</value>
- </entry>
- <entry>
- <key>burstcountUnits</key>
- <value>WORDS</value>
- </entry>
- <entry>
- <key>constantBurstBehavior</key>
- <value>false</value>
- </entry>
- <entry>
- <key>explicitAddressSpan</key>
- <value>0</value>
- </entry>
- <entry>
- <key>holdTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>interleaveBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isBigEndian</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isFlash</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isMemoryDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>isNonVolatileStorage</key>
- <value>false</value>
- </entry>
- <entry>
- <key>linewrapBursts</key>
- <value>false</value>
- </entry>
- <entry>
- <key>maximumPendingReadTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>maximumPendingWriteTransactions</key>
- <value>0</value>
- </entry>
- <entry>
- <key>minimumReadLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumResponseLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>minimumUninterruptedRunLength</key>
- <value>1</value>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- <entry>
- <key>printableDevice</key>
- <value>false</value>
- </entry>
- <entry>
- <key>readLatency</key>
- <value>1</value>
- </entry>
- <entry>
- <key>readWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>readWaitTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>registerIncomingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>registerOutgoingSignals</key>
- <value>false</value>
- </entry>
- <entry>
- <key>setupTime</key>
- <value>0</value>
- </entry>
- <entry>
- <key>timingUnits</key>
- <value>Cycles</value>
- </entry>
- <entry>
- <key>transparentBridge</key>
- <value>false</value>
- </entry>
- <entry>
- <key>waitrequestAllowance</key>
- <value>0</value>
- </entry>
- <entry>
- <key>wellBehavedWaitrequest</key>
- <value>false</value>
- </entry>
- <entry>
- <key>writeLatency</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitStates</key>
- <value>0</value>
- </entry>
- <entry>
- <key>writeWaitTime</key>
- <value>0</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>clk</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>13</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- </interfaces>
-</boundaryDefinition></ipxact:value>
- </ipxact:parameter>
- <ipxact:parameter parameterId="systemInfos" type="string">
- <ipxact:name>systemInfos</ipxact:name>
- <ipxact:displayName>systemInfos</ipxact:displayName>
- <ipxact:value><systemInfosDefinition>
- <connPtSystemInfos>
- <entry>
- <key>mem</key>
- <value>
- <connectionPointName>mem</connectionPointName>
- <suppliedSystemInfos/>
- <consumedSystemInfos>
- <entry>
- <key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
- </entry>
- <entry>
- <key>ADDRESS_WIDTH</key>
- <value>15</value>
- </entry>
- <entry>
- <key>MAX_SLAVE_DATA_WIDTH</key>
- <value>32</value>
- </entry>
- </consumedSystemInfos>
- </value>
- </entry>
- <entry>
- <key>system</key>
- <value>
- <connectionPointName>system</connectionPointName>
- <suppliedSystemInfos>
- <entry>
- <key>CLOCK_RATE</key>
- <value>100000000</value>
- </entry>
- </suppliedSystemInfos>
- <consumedSystemInfos/>
- </value>
- </entry>
- </connPtSystemInfos>
-</systemInfosDefinition></ipxact:value>
- </ipxact:parameter>
- </ipxact:parameters>
- </altera:altera_system_parameters>
- <altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.address" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.clk" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.mem" altera:type="avalon" altera:dir="end">
- <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
- <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.read" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.readdata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.reset" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.system" altera:type="clock" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.system_reset" altera:type="reset" altera:dir="end">
- <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.write" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_st_histogram.writedata" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
- </altera:interface_mapping>
- </altera:altera_interface_boundary>
- <altera:altera_has_warnings>false</altera:altera_has_warnings>
- <altera:altera_has_errors>false</altera:altera_has_errors>
- </ipxact:vendorExtensions>
-</ipxact:component>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
index 88db907ae4e4d0fdee42c635c2d240fa62304844..2edaaa62557d3216749a6fc2459b25a6d53c6c5b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
@@ -78,6 +78,5 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_st_histogram.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index add6f3addaf325a85164a38dea4a38fd939fb287..7ea39b8512ee0fe70ff874ee345277a1ef339513 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -219,10 +219,6 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
SIGNAL ram_aduh_monitor_miso : t_mem_miso;
SIGNAL reg_aduh_monitor_mosi : t_mem_mosi;
SIGNAL reg_aduh_monitor_miso : t_mem_miso;
-
- -- Histogram
- SIGNAL ram_st_histogram_mosi : t_mem_mosi;
- SIGNAL ram_st_histogram_miso : t_mem_miso;
-- QSFP leds
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
@@ -442,9 +438,7 @@ BEGIN
ram_aduh_monitor_mosi => ram_aduh_monitor_mosi,
ram_aduh_monitor_miso => ram_aduh_monitor_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso
+ reg_aduh_monitor_miso => reg_aduh_monitor_miso
);
@@ -490,13 +484,8 @@ BEGIN
ram_aduh_monitor_miso => ram_aduh_monitor_miso,
reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
reg_aduh_monitor_miso => reg_aduh_monitor_miso,
-<<<<<<< HEAD
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
-=======
jesd_ctrl_mosi => jesd_ctrl_mosi,
jesd_ctrl_miso => jesd_ctrl_miso,
->>>>>>> master
-- Jesd external IOs
jesd204b_serial_data => JESD204B_SERIAL_DATA,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index 62b30da8b44f382091b61a83d000135abea29c86..29cc850fb5b12165bad13e28a67c0dcf77247bb1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -139,11 +139,7 @@ ENTITY mmm_lofar2_unb2b_adc IS
ram_aduh_monitor_mosi : OUT t_mem_mosi;
ram_aduh_monitor_miso : IN t_mem_miso;
reg_aduh_monitor_mosi : OUT t_mem_mosi;
- reg_aduh_monitor_miso : IN t_mem_miso;
-
- -- Histogram
- ram_st_histogram_mosi : OUT t_mem_mosi;
- ram_st_histogram_miso : IN t_mem_miso
+ reg_aduh_monitor_miso : IN t_mem_miso
);
END mmm_lofar2_unb2b_adc;
@@ -474,15 +470,7 @@ BEGIN
reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
-
- ram_st_histogram_clk_export => OPEN,
- ram_st_histogram_reset_export => OPEN,
- ram_st_histogram_address_export => ram_st_histogram_mosi.address(13-1 DOWNTO 0),
- ram_st_histogram_write_export => ram_st_histogram_mosi.wr,
- ram_st_histogram_writedata_export => ram_st_histogram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_histogram_read_export => ram_st_histogram_mosi.rd,
- ram_st_histogram_readdata_export => ram_st_histogram_miso.rddata(c_word_w-1 DOWNTO 0)
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index ab25bf73aeab136ced6ca9e2bddb3afcff405eca..77501b43b2fd78bdc0690189682e352ae11ff8c6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -1,570 +1,3 @@
-<<<<<<< HEAD
--------------------------------------------------------------------------------
---
--- Copyright 2020
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- Licensed under the Apache License, Version 2.0 (the "License");
--- you may not use this file except in compliance with the License.
--- You may obtain a copy of the License at
---
--- http://www.apache.org/licenses/LICENSE-2.0
---
--- Unless required by applicable law or agreed to in writing, software
--- distributed under the License is distributed on an "AS IS" BASIS,
--- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--- See the License for the specific language governing permissions and
--- limitations under the License.
---
--------------------------------------------------------------------------------
-
--- Author : J Hargreaves
--- Purpose:
--- AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
--- Description:
--- Unb2b version for lab testing
--- Contains all the signal processing blocks to receive and time the ADC input data
--- See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
-
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib, st_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2b_board_pkg.ALL;
-USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
-USE diag_lib.diag_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE work.lofar2_unb2b_adc_pkg.ALL;
-
-ENTITY node_adc_input_and_timing IS
- GENERIC (
- g_technology : NATURAL := c_tech_arria10_e1sg;
- g_buf_nof_data : NATURAL := 8192; --1024;
- g_nof_streams : NATURAL := 12;
- g_nof_sync_n : NATURAL := 4; -- Three ADCs per RCU share a sync
- g_aduh_buffer_nof_symbols : NATURAL := 512; -- Default 512
- g_bsn_sync_timeout : NATURAL := 200000000; -- Default 200M, overide for short simulation
- g_sim : BOOLEAN := FALSE
- );
- PORT (
- -- clocks and resets
- mm_clk : IN STD_LOGIC;
- mm_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
- dp_rst : IN STD_LOGIC;
-
- -- mm control buses
- -- JESD
- jesd204b_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- jesd204b_miso : OUT t_mem_miso := c_mem_miso_rst;
-
- -- Shiftram (applies per-antenna delay)
- reg_dp_shiftram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_shiftram_miso : OUT t_mem_miso := c_mem_miso_rst;
-
- -- bsn source
- reg_bsn_source_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_source_miso : OUT t_mem_miso := c_mem_miso_rst;
-
- -- bsn scheduler
- reg_bsn_scheduler_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
-
- -- WG
- reg_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
- ram_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
-
- -- BSN MONITOR
- reg_bsn_monitor_input_mosi : IN t_mem_mosi;
- reg_bsn_monitor_input_miso : OUT t_mem_miso;
-
- -- Data buffer for raw samples
- ram_diag_data_buf_jesd_mosi : IN t_mem_mosi;
- ram_diag_data_buf_jesd_miso : OUT t_mem_miso;
- reg_diag_data_buf_jesd_mosi : IN t_mem_mosi;
- reg_diag_data_buf_jesd_miso : OUT t_mem_miso;
-
- -- Data buffer for framed samples (variable depth)
- ram_diag_data_buf_bsn_mosi : IN t_mem_mosi;
- ram_diag_data_buf_bsn_miso : OUT t_mem_miso;
- reg_diag_data_buf_bsn_mosi : IN t_mem_mosi;
- reg_diag_data_buf_bsn_miso : OUT t_mem_miso;
-
- -- Aduh (statistics) monitor
- ram_aduh_monitor_mosi : IN t_mem_mosi;
- ram_aduh_monitor_miso : OUT t_mem_miso;
- reg_aduh_monitor_mosi : IN t_mem_mosi;
- reg_aduh_monitor_miso : OUT t_mem_miso;
-
- -- Histogram
- ram_st_histogram_mosi : IN t_mem_mosi;
- ram_st_histogram_miso : OUT t_mem_miso;
-
- -- JESD io signals
- jesd204b_serial_data : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
- jesd204b_refclk : IN STD_LOGIC;
- jesd204b_sysref : IN STD_LOGIC;
- jesd204b_sync_n : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
-
- -- Streaming data output
- out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
-
- );
-END node_adc_input_and_timing;
-
-
-ARCHITECTURE str OF node_adc_input_and_timing IS
-
- -- Firmware version x.y
- CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
- CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6; -- alternate 160MHz. TODO: Use to check PPS
-
- CONSTANT c_nof_streams_jesd204b : NATURAL := 12; -- IP is set up for 12 streams
- CONSTANT c_nof_streams_db : NATURAL := 2; -- Streams of raw samples to record in db
-
- -- Waveform Generator
- CONSTANT c_wg_buf_directory : STRING := "data/";
- CONSTANT c_wg_buf_dat_w : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
- CONSTANT c_wg_buf_addr_w : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
- SIGNAL wg_out_ovr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
- SIGNAL wg_out_val : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
- SIGNAL wg_out_data : STD_LOGIC_VECTOR(g_nof_streams*c_wg_buf_dat_w-1 DOWNTO 0);
- SIGNAL wg_out_sync : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
- SIGNAL trigger_wg : STD_LOGIC;
-
- -- Frame parameters TBC
- CONSTANT c_bs_bsn_w : NATURAL := 64; --51;
- CONSTANT c_bs_block_size : NATURAL := 1024;
- CONSTANT c_bs_nof_block_per_sync : NATURAL := 390625; -- generate a sync every 2s for testing
- CONSTANT c_dp_shiftram_nof_samples: NATURAL := 4096;
- CONSTANT c_data_w : NATURAL := 16;
- CONSTANT c_dp_fifo_dc_size : NATURAL := 64;
-
- -- Histogram
- CONSTANT c_st_histogram_in_data_w : NATURAL := 14;
- CONSTANT c_st_histogram_nof_bins : NATURAL := 512;
- CONSTANT c_st_histogram_str : STRING := "freq.density";
- SIGNAL ram_st_histogram_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL ram_st_histogram_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
-
- -- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-
- -- JESD signals
- SIGNAL rx_clk : STD_LOGIC; -- formerly jesd204b_frame_clk
- SIGNAL rx_rst : STD_LOGIC;
- SIGNAL rx_sysref : STD_LOGIC;
-
- -- Sosis and sosi arrays
- SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
- SIGNAL dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
- SIGNAL ant_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
- SIGNAL diag_data_buf_snk_in_arr : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
- SIGNAL bs_sosi : t_dp_sosi;
- SIGNAL wg_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL mux_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL nxt_mux_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL st_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
-
-
-BEGIN
-
- -----------------------------------------------------------------------------
- -- JESD204B IP (ADC Handler)
- -----------------------------------------------------------------------------
-
- u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
- GENERIC MAP(
- g_sim => g_sim,
- g_nof_streams => c_nof_streams_jesd204b,
- g_nof_sync_n => g_nof_sync_n
- )
- PORT MAP(
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => jesd204b_sync_n,
-
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
-
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0)
- );
-
-
- gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
- diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= rx_sosi_arr(i).data(c_data_w-1 downto 0);
- diag_data_buf_snk_in_arr(i).valid <= rx_sosi_arr(i).valid;
- diag_data_buf_snk_in_arr(i).sop <= '0';
- diag_data_buf_snk_in_arr(i).eop <= '0';
- diag_data_buf_snk_in_arr(i).err <= (OTHERS=>'0');
- END GENERATE;
-
-
- -----------------------------------------------------------------------------
- -- Diagnostic Data Buffer (Records 8192 raw ADC samples after the PPS)
- -- ToDo: Remove this JESD DB when the second (BSN) data buffer is working correctly
- -----------------------------------------------------------------------------
-
- u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
- GENERIC MAP (
- g_technology => g_technology,
- g_nof_streams => c_nof_streams_db,
- g_data_w => c_data_w,
- g_buf_nof_data => 8192,
- g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
- ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
- reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
- reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
-
- in_sosi_arr => diag_data_buf_snk_in_arr,
- in_sync => rx_sysref
- );
-
- -----------------------------------------------------------------------------
- -- Time delay: dp_shiftram
- -- . copied from unb1_bn_capture_input (apertif)
- -- Array range reversal is not done because everything is DOWNTO
- -- . the input valid is always '1', even when there is no data
- -----------------------------------------------------------------------------
-
- gen_force_valid : FOR I IN 0 TO c_nof_streams_jesd204b-1 GENERATE
- p_sosi : PROCESS(rx_sosi_arr)
- BEGIN
- dp_shiftram_snk_in_arr(I) <= rx_sosi_arr(I);
- dp_shiftram_snk_in_arr(I).valid <= '1';
- END PROCESS;
- END GENERATE;
-
-
- u_dp_shiftram : ENTITY dp_lib.dp_shiftram
- GENERIC MAP (
- g_nof_streams => c_nof_streams_jesd204b,
- g_nof_words => c_dp_shiftram_nof_samples,
- g_data_w => c_data_w,
- g_use_sync_in => TRUE
- )
- PORT MAP (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- sync_in => bs_sosi.sync,
-
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
-
- snk_in_arr => dp_shiftram_snk_in_arr,
-
- src_out_arr => ant_sosi_arr
- );
-
- -----------------------------------------------------------------------------
- -- Timestamp
- -----------------------------------------------------------------------------
- u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source
- GENERIC MAP (
- g_cross_clock_domain => TRUE,
- g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
- g_bsn_w => c_bs_bsn_w
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- dp_pps => rx_sysref,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
-
- -- Streaming clock domain
- bs_sosi => bs_sosi
- );
-
- u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
- GENERIC MAP (
- g_cross_clock_domain => TRUE,
- g_bsn_w => c_bs_bsn_w
- )
- PORT MAP (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_miso => reg_bsn_scheduler_wg_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- snk_in => bs_sosi, -- only uses eop (= block sync), bsn[]
- trigger_out => trigger_wg
- );
-
-
- -----------------------------------------------------------------------------
- -- WG (Test Signal Generator)
- -----------------------------------------------------------------------------
-
- u_wg_arr : ENTITY diag_lib.mms_diag_wg_wideband_arr
- GENERIC MAP (
- g_nof_streams => g_nof_streams,
- g_cross_clock_domain => TRUE,
- g_buf_dir => c_wg_buf_directory,
-
- -- Wideband parameters
- g_wideband_factor => 1,
-
- -- Basic WG parameters, see diag_wg.vhd for their meaning
- g_buf_dat_w => c_wg_buf_dat_w,
- g_buf_addr_w => c_wg_buf_addr_w,
- g_calc_support => TRUE,
- g_calc_gain_w => 1,
- g_calc_dat_w => c_wg_buf_dat_w
- )
- PORT MAP (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_wg_mosi,
- reg_miso => reg_wg_miso,
-
- buf_mosi => ram_wg_mosi,
- buf_miso => ram_wg_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
- st_restart => trigger_wg,
-
- out_sosi_arr => wg_sosi_arr
- );
-
-
- -----------------------------------------------------------------------------
- -- ADC/WG Mux (Input Select)
- -----------------------------------------------------------------------------
-
- gen_mux : FOR I IN 0 TO g_nof_streams-1 GENERATE
- p_sosi : PROCESS(ant_sosi_arr(I), wg_sosi_arr(I))
- BEGIN
- -- Default use the ADC data
- nxt_mux_sosi_arr(I).data <= ant_sosi_arr(I).data;
- IF wg_sosi_arr(I).valid='1' THEN
- -- Valid WG data overrules ADC data
- nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
- END IF;
- END PROCESS;
- END GENERATE;
-
- mux_sosi_arr <= nxt_mux_sosi_arr WHEN rising_edge(rx_clk);
-
- -----------------------------------------------------------------------------
- -- Concatenate muxed data streams with bsn framing
- -----------------------------------------------------------------------------
-
- gen_concat : FOR I IN 0 TO g_nof_streams-1 GENERATE
- p_sosi : PROCESS(mux_sosi_arr(I), bs_sosi)
- BEGIN
- st_sosi_arr(I) <= bs_sosi;
- st_sosi_arr(I).data <= mux_sosi_arr(I).data;
- END PROCESS;
- END GENERATE;
-
-
- ---------------------------------------------------------------------------------------
- -- Diagnostics on the bsn-framed data
- -- . BSN Monitor (ToDo: can be removed as not part of the spec)
- -- . Aduh monitor
- -- . Data Buffer (variable depth from 1k-128k)
- ---------------------------------------------------------------------------------------
-
-
- ---------------------------------------------------------------------------------------
- -- BSN monitor (Block Checker)
- ---------------------------------------------------------------------------------------
- u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
- GENERIC MAP (
- g_nof_streams => 1, -- They're all the same
- g_sync_timeout => g_bsn_sync_timeout,
- g_bsn_w => c_bs_bsn_w,
- g_log_first_bsn => FALSE
- )
- PORT MAP (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_input_mosi,
- reg_miso => reg_bsn_monitor_input_miso,
-
- -- Streaming clock domain
- dp_rst => rx_rst,
- dp_clk => rx_clk,
- in_sosi_arr => st_sosi_arr(0 downto 0)
- );
-
-
- -----------------------------------------------------------------------------
- -- Monitor ADU/WG output
- -----------------------------------------------------------------------------
- u_aduh_monitor : ENTITY aduh_lib.mms_aduh_monitor_arr
- GENERIC MAP (
- g_cross_clock_domain => TRUE,
- g_nof_streams => g_nof_streams,
- g_symbol_w => c_data_w, --TBD 16?
- g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => 200000512, -- = 195313 blocks * 1024 samples
- g_buffer_nof_symbols => g_aduh_buffer_nof_symbols, -- default 512, larger for full design
- g_buffer_use_sync => TRUE -- True to capture all streams synchronously
- )
- PORT MAP (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
- reg_miso => reg_aduh_monitor_miso,
- buf_mosi => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
- buf_miso => ram_aduh_monitor_miso,
-
- -- Streaming clock domain
- st_rst => rx_rst,
- st_clk => rx_clk,
-
- in_sosi_arr => st_sosi_arr
- );
-
-
- -----------------------------------------------------------------------------
--- Diagnostic Data Buffer
- -----------------------------------------------------------------------------
-
- u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
- GENERIC MAP (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => c_data_w,
- g_buf_nof_data => g_buf_nof_data,
- g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
- ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
- reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
- reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
-
- in_sosi_arr => st_sosi_arr,
- in_sync => st_sosi_arr(0).sync
- );
-
-
- -----------------------------------------------------------------------------
- -- Histogram
- -----------------------------------------------------------------------------
-
- gen_st_histogram : FOR I IN 0 TO g_nof_streams-1 GENERATE
- u_st_histogram : ENTITY st_lib.st_histogram
- GENERIC MAP (
- g_in_data_w => c_st_histogram_in_data_w, -- 14, -- c_data_w,
- g_nof_bins => c_st_histogram_nof_bins, -- 512,
- g_nof_data => c_lofar2_sample_clk_freq,
- g_str => c_st_histogram_str,
- g_ram_miso_sim_mode => FALSE --g_sim -- is the specific output data even allowed when g_sim is TRUE ??
- )
- PORT MAP (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- -- Streaming
- snk_in => st_sosi_arr(I),
-
- -- DP clocked memory bus
- sla_in_ram_mosi => ram_st_histogram_mosi_arr(I), -- Beware, works in dp clock domain !
- sla_out_ram_miso => ram_st_histogram_miso_arr(I), -- '' !
-
- -- Debug bus
- dbg_ram_miso => OPEN -- '' !
- );
- END GENERATE;
-
- u_mem_mux_histogram : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_streams,
- g_mult_addr_w => ceil_log2(c_st_histogram_nof_bins)
- )
- PORT MAP (
- mosi => ram_st_histogram_mosi,
- miso => ram_st_histogram_miso,
- mosi_arr => ram_st_histogram_mosi_arr,
- miso_arr => ram_st_histogram_miso_arr
- );
-
-
- -----------------------------------------------------------------------------
- -- Output Stage
- -- . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
- -----------------------------------------------------------------------------
-
- gen_dp_fifo_dc : FOR I IN 0 TO g_nof_streams-1 GENERATE
- u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
- GENERIC MAP (
- g_data_w => c_data_w,
- g_use_empty => FALSE, --TRUE,
- g_use_ctrl => TRUE,
- g_use_sync => TRUE,
- g_use_bsn => TRUE,
- g_fifo_size => c_dp_fifo_dc_size
- )
- PORT MAP (
- wr_rst => rx_rst,
- wr_clk => rx_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
- snk_in => st_sosi_arr(I),
- src_out => out_sosi_arr(I)
- );
- END GENERATE;
-
-END str;
-=======
-------------------------------------------------------------------------------
--
-- Copyright 2020
@@ -1091,4 +524,3 @@ BEGIN
);
END str;
->>>>>>> master
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index efaece5f1e57fe793ed14bea98e0a60ee4331c08..c8d5c25862501cf4864df9487537e0ae659b0d53 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -32,226 +32,6 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
component qsys_lofar2_unb2b_adc is
port (
-<<<<<<< HEAD
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0);
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0);
- reg_bsn_monitor_input_reset_export : out std_logic;
- reg_bsn_monitor_input_clk_export : out std_logic;
- reg_bsn_monitor_input_write_export : out std_logic;
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
- reg_bsn_monitor_input_read_export : out std_logic;
- reg_wg_address_export : out std_logic_vector(5 downto 0);
- reg_wg_writedata_export : out std_logic_vector(31 downto 0);
- reg_wg_reset_export : out std_logic;
- reg_wg_clk_export : out std_logic;
- reg_wg_write_export : out std_logic;
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
- reg_wg_read_export : out std_logic;
- ram_wg_address_export : out std_logic_vector(13 downto 0);
- ram_wg_writedata_export : out std_logic_vector(31 downto 0);
- ram_wg_reset_export : out std_logic;
- ram_wg_clk_export : out std_logic;
- ram_wg_write_export : out std_logic;
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
- ram_wg_read_export : out std_logic;
- reg_dp_shiftram_address_export : out std_logic_vector(2 downto 0);
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0);
- reg_dp_shiftram_reset_export : out std_logic;
- reg_dp_shiftram_clk_export : out std_logic;
- reg_dp_shiftram_write_export : out std_logic;
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
- reg_dp_shiftram_read_export : out std_logic;
- reg_bsn_source_address_export : out std_logic_vector(1 downto 0);
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0);
- reg_bsn_source_reset_export : out std_logic;
- reg_bsn_source_clk_export : out std_logic;
- reg_bsn_source_write_export : out std_logic;
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
- reg_bsn_source_read_export : out std_logic;
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0);
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0);
- reg_bsn_scheduler_reset_export : out std_logic;
- reg_bsn_scheduler_clk_export : out std_logic;
- reg_bsn_scheduler_write_export : out std_logic;
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
- reg_bsn_scheduler_read_export : out std_logic;
- pio_pps_address_export : out std_logic_vector(0 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(9 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_jesd_address_export : out std_logic_vector(15 downto 0); -- export
- ram_diag_data_buf_jesd_clk_export : out std_logic; -- export
- ram_diag_data_buf_jesd_read_export : out std_logic; -- export
- ram_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_jesd_reset_export : out std_logic; -- export
- ram_diag_data_buf_jesd_write_export : out std_logic; -- export
- ram_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_jesd_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buf_jesd_clk_export : out std_logic; -- export
- reg_diag_data_buf_jesd_read_export : out std_logic; -- export
- reg_diag_data_buf_jesd_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_jesd_reset_export : out std_logic; -- export
- reg_diag_data_buf_jesd_write_export : out std_logic; -- export
- reg_diag_data_buf_jesd_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_aduh_monitor_address_export : out std_logic_vector(11 downto 0); -- export
- ram_aduh_monitor_clk_export : out std_logic; -- export
- ram_aduh_monitor_read_export : out std_logic; -- export
- ram_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_aduh_monitor_reset_export : out std_logic; -- export
- ram_aduh_monitor_write_export : out std_logic; -- export
- ram_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buf_bsn_address_export : out std_logic_vector(15 downto 0); -- export
- ram_diag_data_buf_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buf_bsn_read_export : out std_logic; -- export
- ram_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buf_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buf_bsn_write_export : out std_logic; -- export
- ram_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buf_bsn_address_export : out std_logic_vector(11 downto 0); -- export
- reg_diag_data_buf_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buf_bsn_read_export : out std_logic; -- export
- reg_diag_data_buf_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buf_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buf_bsn_write_export : out std_logic; -- export
- reg_diag_data_buf_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0);
- ram_st_histogram_clk_export : out std_logic;
- ram_st_histogram_read_export : out std_logic;
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
- ram_st_histogram_reset_export : out std_logic;
- ram_st_histogram_write_export : out std_logic;
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0)
-=======
avs_eth_0_clk_export : out std_logic; -- export
avs_eth_0_irq_export : in std_logic := 'X'; -- export
avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
@@ -456,7 +236,6 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
rom_system_info_reset_export : out std_logic; -- export
rom_system_info_write_export : out std_logic; -- export
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
->>>>>>> master
);
end component qsys_lofar2_unb2b_adc;
END qsys_lofar2_unb2b_adc_pkg;