From 9c7e85cd118d2c9f293cd7497e25a1aa9e321433 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Thu, 29 Jan 2015 13:42:50 +0000
Subject: [PATCH] -Used RESIZE_DP_DSP_DATA on the adder inputs and outputs: .
For human readability . This however also fixed the mismatch between the
Python model and the VHDL.
---
.../correlator/src/vhdl/corr_accumulator.vhd | 19 +++++------
.../dsp/correlator/src/vhdl/corr_adder.vhd | 34 +++++++++++++------
2 files changed, 31 insertions(+), 22 deletions(-)
diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index 081971e106..b81bd0ff01 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -93,19 +93,16 @@ BEGIN
gen_adder_inputs : FOR i IN 0 TO g_nof_inputs-1 GENERATE
-- Adder input 0: multiplier output
- nxt_corr_adder_snk_in_2arr_2(i)(0).valid <= snk_in_arr(i).valid;
- nxt_corr_adder_snk_in_2arr_2(i)(0).re(g_data_w-1 DOWNTO 0) <= snk_in_arr(i).re(g_data_w-1 DOWNTO 0);
- nxt_corr_adder_snk_in_2arr_2(i)(0).im(g_data_w-1 DOWNTO 0) <= snk_in_arr(i).im(g_data_w-1 DOWNTO 0);
- -- . Pad the complex data width zeroes so all adder input bits are defined
- nxt_corr_adder_snk_in_2arr_2(i)(0).re(c_acc_data_w-1 DOWNTO g_data_w) <= (OTHERS=>'0');
- nxt_corr_adder_snk_in_2arr_2(i)(0).im(c_acc_data_w-1 DOWNTO g_data_w) <= (OTHERS=>'0');
+ nxt_corr_adder_snk_in_2arr_2(i)(0).valid <= snk_in_arr(i).valid;
+ nxt_corr_adder_snk_in_2arr_2(i)(0).re <= RESIZE_DP_DSP_DATA(snk_in_arr(i).re(g_data_w-1 DOWNTO 0));
+ nxt_corr_adder_snk_in_2arr_2(i)(0).im <= RESIZE_DP_DSP_DATA(snk_in_arr(i).im(g_data_w-1 DOWNTO 0));
-- Adder input 1: shiftram output
- nxt_corr_adder_snk_in_2arr_2(i)(1).valid <= common_shiftram_src_out_arr(i).valid;
- nxt_corr_adder_snk_in_2arr_2(i)(1).re(c_acc_data_w-1 DOWNTO 0) <= (OTHERS=>'0') WHEN TO_UINT(acc_cnt)<=g_nof_accumulators-1 ELSE
- common_shiftram_src_out_arr(i).data(2*c_acc_data_w-1 DOWNTO c_acc_data_w);
- nxt_corr_adder_snk_in_2arr_2(i)(1).im(c_acc_data_w-1 DOWNTO 0) <= (OTHERS=>'0') WHEN TO_UINT(acc_cnt)<=g_nof_accumulators-1 ELSE
- common_shiftram_src_out_arr(i).data( c_acc_data_w-1 DOWNTO 0);
+ nxt_corr_adder_snk_in_2arr_2(i)(1).valid <= common_shiftram_src_out_arr(i).valid;
+ nxt_corr_adder_snk_in_2arr_2(i)(1).re <= (OTHERS=>'0') WHEN TO_UINT(acc_cnt) <= g_nof_accumulators-1 ELSE
+ RESIZE_DP_DSP_DATA(common_shiftram_src_out_arr(i).data(2*c_acc_data_w-1 DOWNTO c_acc_data_w));
+ nxt_corr_adder_snk_in_2arr_2(i)(1).im <= (OTHERS=>'0') WHEN TO_UINT(acc_cnt) <= g_nof_accumulators-1 ELSE
+ RESIZE_DP_DSP_DATA(common_shiftram_src_out_arr(i).data( c_acc_data_w-1 DOWNTO 0));
END GENERATE;
-----------------------------------------------------------------------------
diff --git a/libraries/dsp/correlator/src/vhdl/corr_adder.vhd b/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
index 2c280013eb..a291c85e05 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
@@ -55,6 +55,8 @@ ARCHITECTURE str OF corr_adder IS
-- Signal that carries the full adder output width
SIGNAL common_complex_add_sub_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
+ -- Same as above but minus the extra bit added by the adder.
+ SIGNAL ranged_common_complex_add_sub_src_out_arr : t_dp_sosi_arr(g_nof_inputs-1 DOWNTO 0);
BEGIN
@@ -99,21 +101,31 @@ BEGIN
END GENERATE;
-----------------------------------------------------------------------------
- -- Wire the adder output of g_data_w+1 to output with g_data_w
+ -- Wire the adder output of g_data_w+1 to output with g_data_w.
+ -- We already have the needed bit width at the adder INPUTS, so we don't need
+ -- an additional output bit.
-- . g_data_w is already wide enough to carry the full adder output
- -- range (we don't need the extra bit for that).
- -- . We do need the extra bit though, as it is the sign bit.
+ -- range (we don't need an extra bit for that).
+ -- . We do need the extra bit itself though, as it is the sign bit.
-----------------------------------------------------------------------------
- gen_signed_output_data : FOR i IN 0 TO g_nof_inputs-1 GENERATE
- -- Wire the adder output to src_out_arr, minus the two MSbits
- src_out_arr(i).re(g_data_w-1-1 DOWNTO 0) <= common_complex_add_sub_src_out_arr(i).re(g_data_w-1-1 DOWNTO 0);
- src_out_arr(i).im(g_data_w-1-1 DOWNTO 0) <= common_complex_add_sub_src_out_arr(i).im(g_data_w-1-1 DOWNTO 0);
+ gen_output_range : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+ -- Wire the adder output to ranged_common_complex_add_sub_src_out_arr, minus the two MSbits
+ ranged_common_complex_add_sub_src_out_arr(i).re(g_data_w-1-1 DOWNTO 0) <= common_complex_add_sub_src_out_arr(i).re(g_data_w-1-1 DOWNTO 0);
+ ranged_common_complex_add_sub_src_out_arr(i).im(g_data_w-1-1 DOWNTO 0) <= common_complex_add_sub_src_out_arr(i).im(g_data_w-1-1 DOWNTO 0);
-- Don't assign the adder's MSbit-1 as it shouldn't toggle (because our adder input width is already wide enough)
- -- NC <= common_complex_add_sub_src_out_arr(i).re(g_data_w-1);
- -- NC <= common_complex_add_sub_src_out_arr(i).im(g_data_w-1);
+ -- NC <= common_complex_add_sub_src_out_arr(i).re(g_data_w-1);
+ -- NC <= common_complex_add_sub_src_out_arr(i).im(g_data_w-1);
-- Wire up the adder's MSbit (sign) bit
- src_out_arr(i).re(g_data_w-1) <= common_complex_add_sub_src_out_arr(i).re(g_data_w);
- src_out_arr(i).im(g_data_w-1) <= common_complex_add_sub_src_out_arr(i).im(g_data_w);
+ ranged_common_complex_add_sub_src_out_arr(i).re(g_data_w-1) <= common_complex_add_sub_src_out_arr(i).re(g_data_w);
+ ranged_common_complex_add_sub_src_out_arr(i).im(g_data_w-1) <= common_complex_add_sub_src_out_arr(i).im(g_data_w);
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- Finally, extend the sign bit for human readability
+ -----------------------------------------------------------------------------
+ gen_sign_extend : FOR i IN 0 TO g_nof_inputs-1 GENERATE
+ src_out_arr(i).re <= RESIZE_DP_DSP_DATA(ranged_common_complex_add_sub_src_out_arr(i).re(g_data_w-1 DOWNTO 0));
+ src_out_arr(i).im <= RESIZE_DP_DSP_DATA(ranged_common_complex_add_sub_src_out_arr(i).im(g_data_w-1 DOWNTO 0));
END GENERATE;
END str;
--
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