diff --git a/libraries/technology/altera/stratixiv_hssi/hdllib.cfg b/libraries/technology/altera/stratixiv_hssi/hdllib.cfg
deleted file mode 100644
index 3c01d0c058becf98e91fc63ae13168284af0d72b..0000000000000000000000000000000000000000
--- a/libraries/technology/altera/stratixiv_hssi/hdllib.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-hdl_lib_name = ip_stratixiv_hssi
-hdl_library_clause_name = ip_stratixiv_hssi_lib
-hdl_lib_uses = technology
-
-build_sim_dir = $HDL_BUILD_DIR
-build_synth_dir =
-
-synth_files =
- ip_stratixiv_hssi_gx_generic.vhd
- ip_stratixiv_hssi_tx_generic.vhd
- ip_stratixiv_hssi_rx_generic.vhd
- ip_stratixiv_hssi_gx_16b.vhd
- ip_stratixiv_hssi_tx_16b.vhd
- ip_stratixiv_hssi_rx_16b.vhd
-
-test_bench_files =
diff --git a/libraries/technology/base/hdllib.cfg b/libraries/technology/hdllib.cfg
similarity index 100%
rename from libraries/technology/base/hdllib.cfg
rename to libraries/technology/hdllib.cfg
diff --git a/libraries/technology/ip_stratixiv/hdllib.cfg b/libraries/technology/ip_stratixiv/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..68e148b6bd2c124f6e16de0587f663290b8d68a9
--- /dev/null
+++ b/libraries/technology/ip_stratixiv/hdllib.cfg
@@ -0,0 +1,37 @@
+hdl_lib_name = ip_stratixiv
+hdl_library_clause_name = ip_stratixiv_lib
+hdl_lib_uses = technology
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir =
+
+synth_files =
+ ip_stratixiv_ram_crwk_crw.vhd
+ ip_stratixiv_ram_crw_crw.vhd
+ ip_stratixiv_ram_cr_cw.vhd
+ ip_stratixiv_ram_r_w.vhd
+ ip_stratixiv_rom_r.vhd
+
+ ip_stratixiv_fifo_dc_mixed_widths.vhd
+ ip_stratixiv_fifo_dc.vhd
+ ip_stratixiv_fifo_sc.vhd
+
+ ip_stratixiv_ddio_in.vhd
+ ip_stratixiv_ddio_out.vhd
+
+ ip_stratixiv_asmi_parallel.vhd
+ ip_stratixiv_remote_update.vhd
+
+ ip_stratixiv_gxb_reconfig_2.vhd
+ ip_stratixiv_gxb_reconfig_4.vhd
+ ip_stratixiv_gxb_reconfig_8.vhd
+ ip_stratixiv_gxb_reconfig_12.vhd
+
+ ip_stratixiv_hssi_gx_generic.vhd
+ ip_stratixiv_hssi_tx_generic.vhd
+ ip_stratixiv_hssi_rx_generic.vhd
+ ip_stratixiv_hssi_gx_16b.vhd
+ ip_stratixiv_hssi_tx_16b.vhd
+ ip_stratixiv_hssi_rx_16b.vhd
+
+test_bench_files =
diff --git a/libraries/technology/altera/stratixiv/ip_stratixiv_asmi_parallel.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_asmi_parallel.vhd
similarity index 100%
rename from libraries/technology/altera/stratixiv/ip_stratixiv_asmi_parallel.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_asmi_parallel.vhd
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_ddio_in.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_ddio_in.vhd
similarity index 94%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_ddio_in.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_ddio_in.vhd
index 0579d09ad4eaddbb467603053cb56bd7ac9ad119..1c7712498845f2749b801158fa9f6305330f339c 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_ddio_in.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_ddio_in.vhd
@@ -55,7 +55,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.ALL;
-ENTITY ip_altera_mf_ddio_in IS
+ENTITY ip_stratixiv_ddio_in IS
GENERIC(
g_device_family : STRING := "Stratix IV";
g_width : NATURAL := 1
@@ -68,10 +68,10 @@ ENTITY ip_altera_mf_ddio_in IS
out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
-END ip_altera_mf_ddio_in;
+END ip_stratixiv_ddio_in;
-ARCHITECTURE str OF ip_altera_mf_ddio_in IS
+ARCHITECTURE str OF ip_stratixiv_ddio_in IS
BEGIN
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_ddio_out.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_ddio_out.vhd
similarity index 94%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_ddio_out.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_ddio_out.vhd
index ccb5b09188252049129ec7a096380c3798cdc01e..0091150e61ce0f37d892184c9fb0a7c8d5d299e1 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_ddio_out.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_ddio_out.vhd
@@ -59,7 +59,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.ALL;
-ENTITY ip_altera_mf_ddio_out IS
+ENTITY ip_stratixiv_ddio_out IS
GENERIC(
g_device_family : STRING := "Stratix IV";
g_width : NATURAL := 1
@@ -72,9 +72,9 @@ ENTITY ip_altera_mf_ddio_out IS
in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
-END ip_altera_mf_ddio_out;
+END ip_stratixiv_ddio_out;
-ARCHITECTURE str OF ip_altera_mf_ddio_out IS
+ARCHITECTURE str OF ip_stratixiv_ddio_out IS
BEGIN
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_fifo_dc.vhd
similarity index 90%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_fifo_dc.vhd
index 53066ef46f142d88d033bd5d053dda019fa03890..420b38cadfebf16fd33011406da39489229f1fdd 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_fifo_dc.vhd
@@ -4,7 +4,7 @@
-- MODULE: dcfifo
-- ============================================================
--- File Name: ip_altera_mf_fifo_dc.vhd
+-- File Name: ip_stratixiv_fifo_dc.vhd
-- Megafunction Name(s):
-- dcfifo
--
@@ -42,7 +42,7 @@ USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY ip_altera_mf_fifo_dc IS
+ENTITY ip_stratixiv_fifo_dc IS
GENERIC (
g_dat_w : NATURAL;
g_nof_words : NATURAL
@@ -61,10 +61,10 @@ ENTITY ip_altera_mf_fifo_dc IS
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
-END ip_altera_mf_fifo_dc;
+END ip_stratixiv_fifo_dc;
-ARCHITECTURE SYN OF ip_altera_mf_fifo_dc IS
+ARCHITECTURE SYN OF ip_stratixiv_fifo_dc IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
@@ -214,11 +214,11 @@ END SYN;
-- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_fifo_dc_mixed_widths.vhd
similarity index 90%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc_mixed_widths.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_fifo_dc_mixed_widths.vhd
index bcceb7006539189b62503495c55aa031004ec02b..b86358a4dfd0bedf3b9f7df9a79e26bc221bb460 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_fifo_dc_mixed_widths.vhd
@@ -4,7 +4,7 @@
-- MODULE: dcfifo_mixed_widths
-- ============================================================
--- File Name: ip_altera_mf_fifo_dc_mixed_widths.vhd
+-- File Name: ip_stratixiv_fifo_dc_mixed_widths.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
@@ -42,7 +42,7 @@ USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY ip_altera_mf_fifo_dc_mixed_widths IS
+ENTITY ip_stratixiv_fifo_dc_mixed_widths IS
GENERIC (
g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
g_wrdat_w : NATURAL;
@@ -62,10 +62,10 @@ ENTITY ip_altera_mf_fifo_dc_mixed_widths IS
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
-END ip_altera_mf_fifo_dc_mixed_widths;
+END ip_stratixiv_fifo_dc_mixed_widths;
-ARCHITECTURE SYN OF ip_altera_mf_fifo_dc_mixed_widths IS
+ARCHITECTURE SYN OF ip_stratixiv_fifo_dc_mixed_widths IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (q'RANGE);
@@ -221,11 +221,11 @@ END SYN;
-- Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths_waveforms.html FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_dc_mixed_widths_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_mixed_widths.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_mixed_widths.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_mixed_widths.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_mixed_widths.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_mixed_widths_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_mixed_widths_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_dc_mixed_widths_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_sc.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_fifo_sc.vhd
similarity index 89%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_fifo_sc.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_fifo_sc.vhd
index 2526ea171e7741f0e76ffbfecd1ab17481d7555a..309394574ec97d547befb277d1947c15b5a343f0 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_fifo_sc.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_fifo_sc.vhd
@@ -4,7 +4,7 @@
-- MODULE: scfifo
-- ============================================================
--- File Name: ip_altera_mf_fifo_sc.vhd
+-- File Name: ip_stratixiv_fifo_sc.vhd
-- Megafunction Name(s):
-- scfifo
--
@@ -42,7 +42,7 @@ USE technology_lib.technology_pkg.ALL;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY ip_altera_mf_fifo_sc IS
+ENTITY ip_stratixiv_fifo_sc IS
GENERIC (
g_use_eab : STRING := "ON";
g_dat_w : NATURAL;
@@ -60,10 +60,10 @@ ENTITY ip_altera_mf_fifo_sc IS
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
);
-END ip_altera_mf_fifo_sc;
+END ip_stratixiv_fifo_sc;
-ARCHITECTURE SYN OF ip_altera_mf_fifo_sc IS
+ARCHITECTURE SYN OF ip_stratixiv_fifo_sc IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (usedw'RANGE);
SIGNAL sub_wire1 : STD_LOGIC ;
@@ -197,10 +197,10 @@ END SYN;
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_fifo_sc_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_sc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_sc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_sc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_sc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_sc_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_sc_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_fifo_sc_wave*.jpg FALSE
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_12_stratixiv.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_12.vhd
similarity index 95%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_12_stratixiv.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_12.vhd
index 04a65dab425aeb51b160598ab51b51699a2c54c4..52c32fa048888d727b78d282f9d81c8fa57052ac 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_12_stratixiv.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_12.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_altera_mf_gxb_reconfig_12_stratixiv.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_12.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state259w262w263w(0) OR (wire_pre_amble_cmpr_w_lg_agb260w(0) AND wire_dprio_w_lg_wr_addr_state259w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state373w374w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb260w372w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state438w439w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb260w437w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=12 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a IS
+ ENTITY ip_stratixiv_gxb_reconfig_12_mux_o7a IS
PORT
(
data : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0')
);
- END ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a;
+ END ip_stratixiv_gxb_reconfig_12_mux_o7a;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12_mux_o7a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL wire_l1_w0_n1_mux_dataout : STD_LOGIC;
@@ -1287,7 +1287,7 @@
wire_l3_w0_n1_mux_dataout <= data_wire(27) WHEN sel_wire(10) = '1' ELSE data_wire(26);
wire_l4_w0_n0_mux_dataout <= data_wire(29) WHEN sel_wire(15) = '1' ELSE data_wire(28);
- END RTL; --ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a
+ END RTL; --ip_stratixiv_gxb_reconfig_12_mux_o7a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1296,7 +1296,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm IS
+ ENTITY ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1304,9 +1304,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (203 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm;
+ END ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1386,7 +1386,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1405,7 +1405,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a
+ COMPONENT ip_stratixiv_gxb_reconfig_12_mux_o7a
PORT
(
data : IN STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
@@ -1462,7 +1462,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_altera_mf_gxb_reconfig_12_stratixiv_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_12_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1485,21 +1485,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_altera_mf_gxb_reconfig_12_stratixiv_mux_o7a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_12_mux_o7a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(3 DOWNTO 0)
);
- END RTL; --ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm
+ END RTL; --ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_altera_mf_gxb_reconfig_12_stratixiv IS
+ENTITY ip_stratixiv_gxb_reconfig_12 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1507,10 +1507,10 @@ ENTITY ip_altera_mf_gxb_reconfig_12_stratixiv IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_altera_mf_gxb_reconfig_12_stratixiv;
+END ip_stratixiv_gxb_reconfig_12;
-ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_12 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1523,7 +1523,7 @@ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_12_stratixiv IS
- COMPONENT ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm
+ COMPONENT ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1536,7 +1536,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm_component : ip_altera_mf_gxb_reconfig_12_stratixiv_alt2gxb_reconfig_5lm
+ ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm_component : ip_stratixiv_gxb_reconfig_12_alt2gxb_reconfig_5lm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1573,10 +1573,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv.bsf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_12_stratixiv_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_12_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_2_stratixiv.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_2.vhd
similarity index 94%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_2_stratixiv.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_2.vhd
index 5ac9a331b1494482977b558886dea4070df41f29..7c402d026da23ba3c998734b05746cbb5baa01bb 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_2_stratixiv.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_2.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_altera_mf_gxb_reconfig_2_stratixiv.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_2.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_2_stratixiv_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_altera_mf_gxb_reconfig_2_stratixiv_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_2_stratixiv_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state219w222w223w(0) OR (wire_pre_amble_cmpr_w_lg_agb220w(0) AND wire_dprio_w_lg_wr_addr_state219w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state333w334w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb220w332w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state398w399w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb220w397w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_altera_mf_gxb_reconfig_2_stratixiv_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=2 LPM_WIDTH=1 LPM_WIDTHS=1 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_2_stratixiv_mux_46a IS
+ ENTITY ip_stratixiv_gxb_reconfig_2_mux_46a IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0')
);
- END ip_altera_mf_gxb_reconfig_2_stratixiv_mux_46a;
+ END ip_stratixiv_gxb_reconfig_2_mux_46a;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_2_stratixiv_mux_46a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2_mux_46a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL data_wire : STD_LOGIC_VECTOR (1 DOWNTO 0);
@@ -1259,7 +1259,7 @@
sel_wire(0) <= ( sel(0));
wire_l1_w0_n0_mux_dataout <= data_wire(1) WHEN sel_wire(0) = '1' ELSE data_wire(0);
- END RTL; --ip_altera_mf_gxb_reconfig_2_stratixiv_mux_46a
+ END RTL; --ip_stratixiv_gxb_reconfig_2_mux_46a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1268,7 +1268,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_2_stratixiv_alt2gxb_reconfig_hgm IS
+ ENTITY ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1276,9 +1276,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (33 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_altera_mf_gxb_reconfig_2_stratixiv_alt2gxb_reconfig_hgm;
+ END ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_2_stratixiv_alt2gxb_reconfig_hgm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1358,7 +1358,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_2_stratixiv_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1377,7 +1377,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_2_stratixiv_mux_46a
+ COMPONENT ip_stratixiv_gxb_reconfig_2_mux_46a
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
@@ -1434,7 +1434,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_altera_mf_gxb_reconfig_2_stratixiv_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_2_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1457,21 +1457,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_altera_mf_gxb_reconfig_2_stratixiv_mux_46a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_2_mux_46a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(0 DOWNTO 0)
);
- END RTL; --ip_altera_mf_gxb_reconfig_2_stratixiv_alt2gxb_reconfig_hgm
+ END RTL; --ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_altera_mf_gxb_reconfig_2_stratixiv IS
+ENTITY ip_stratixiv_gxb_reconfig_2 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1479,10 +1479,10 @@ ENTITY ip_altera_mf_gxb_reconfig_2_stratixiv IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_altera_mf_gxb_reconfig_2_stratixiv;
+END ip_stratixiv_gxb_reconfig_2;
-ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_2_stratixiv IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_2 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1495,7 +1495,7 @@ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_2_stratixiv IS
- COMPONENT ip_altera_mf_gxb_reconfig_2_stratixiv_alt2gxb_reconfig_hgm
+ COMPONENT ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1508,7 +1508,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_altera_mf_gxb_reconfig_2_stratixiv_alt2gxb_reconfig_hgm_component : ip_altera_mf_gxb_reconfig_2_stratixiv_alt2gxb_reconfig_hgm
+ ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm_component : ip_stratixiv_gxb_reconfig_2_alt2gxb_reconfig_hgm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1545,10 +1545,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_2_stratixiv.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_2_stratixiv.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_2_stratixiv.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_2_stratixiv.bsf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_2_stratixiv_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_4_stratixiv.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_4.vhd
similarity index 97%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_4_stratixiv.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_4.vhd
index 4e78449328da4d6584d429b4ca126bb02be2b4b9..549dd580d66a5305c94404c0446ea710873888b7 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_4_stratixiv.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_4.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_altera_mf_gxb_reconfig_4_stratixiv.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_4.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state226w230w231w(0) OR (wire_pre_amble_cmpr_w_lg_agb227w(0) AND wire_dprio_w_lg_wr_addr_state226w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state341w342w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb227w339w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state406w407w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb227w404w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=4 LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a IS
+ ENTITY ip_stratixiv_gxb_reconfig_4_mux_76a IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0')
);
- END ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a;
+ END ip_stratixiv_gxb_reconfig_4_mux_76a;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4_mux_76a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL wire_l1_w0_n1_mux_dataout : STD_LOGIC;
@@ -1263,7 +1263,7 @@
wire_l1_w0_n1_mux_dataout <= data_wire(3) WHEN sel_wire(0) = '1' ELSE data_wire(2);
wire_l2_w0_n0_mux_dataout <= data_wire(5) WHEN sel_wire(3) = '1' ELSE data_wire(4);
- END RTL; --ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a
+ END RTL; --ip_stratixiv_gxb_reconfig_4_mux_76a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1272,7 +1272,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im IS
+ ENTITY ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1280,9 +1280,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (67 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im;
+ END ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1363,7 +1363,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1382,7 +1382,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a
+ COMPONENT ip_stratixiv_gxb_reconfig_4_mux_76a
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
@@ -1441,7 +1441,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_altera_mf_gxb_reconfig_4_stratixiv_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_4_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1464,21 +1464,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_altera_mf_gxb_reconfig_4_stratixiv_mux_76a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_4_mux_76a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(1 DOWNTO 0)
);
- END RTL; --ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im
+ END RTL; --ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_altera_mf_gxb_reconfig_4_stratixiv IS
+ENTITY ip_stratixiv_gxb_reconfig_4 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1486,10 +1486,10 @@ ENTITY ip_altera_mf_gxb_reconfig_4_stratixiv IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_altera_mf_gxb_reconfig_4_stratixiv;
+END ip_stratixiv_gxb_reconfig_4;
-ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_4 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1502,7 +1502,7 @@ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_4_stratixiv IS
- COMPONENT ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im
+ COMPONENT ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1515,7 +1515,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im_component : ip_altera_mf_gxb_reconfig_4_stratixiv_alt2gxb_reconfig_9im
+ ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im_component : ip_stratixiv_gxb_reconfig_4_alt2gxb_reconfig_9im
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1552,10 +1552,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 68 0 reconfig_fromgxb 0 0 68 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_4_stratixiv_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_4_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_8_stratixiv.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_8.vhd
similarity index 97%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_8_stratixiv.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_8.vhd
index e8e973e3406c2f600168694aedfe2fdbde50c2ae..c06ffc17cb72db6f555bd2a786d228144ba5e76d 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_gxb_reconfig_8_stratixiv.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_gxb_reconfig_8.vhd
@@ -4,7 +4,7 @@
-- MODULE: alt2gxb_reconfig
-- ============================================================
--- File Name: ip_altera_mf_gxb_reconfig_8_stratixiv.vhd
+-- File Name: ip_stratixiv_gxb_reconfig_8.vhd
-- Megafunction Name(s):
-- alt2gxb_reconfig
--
@@ -47,7 +47,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj IS
+ ENTITY ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj IS
PORT
(
address : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
@@ -65,9 +65,9 @@
wren : IN STD_LOGIC := '0';
wren_data : IN STD_LOGIC := '0'
);
- END ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj;
+ END ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1226,7 +1226,7 @@
);
wire_dprioin_mux_dataout <= (((wire_dprio_w_lg_w_lg_w_lg_wr_addr_state242w246w247w(0) OR (wire_pre_amble_cmpr_w_lg_agb243w(0) AND wire_dprio_w_lg_wr_addr_state242w(0))) OR (wire_dprio_w_lg_w_lg_wr_data_state357w358w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb243w355w(0))) OR (wire_dprio_w_lg_w_lg_rd_data_output_state422w423w(0) OR wire_pre_amble_cmpr_w_lg_w_lg_agb243w420w(0))) OR NOT(((write_state OR rd_addr_state) OR rd_data_output_state));
- END RTL; --ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj
+ END RTL; --ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj
--lpm_mux CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_SIZE=8 LPM_WIDTH=1 LPM_WIDTHS=3 data result sel
@@ -1236,16 +1236,16 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a IS
+ ENTITY ip_stratixiv_gxb_reconfig_8_mux_c6a IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0')
);
- END ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a;
+ END ip_stratixiv_gxb_reconfig_8_mux_c6a;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8_mux_c6a IS
SIGNAL wire_l1_w0_n0_mux_dataout : STD_LOGIC;
SIGNAL wire_l1_w0_n1_mux_dataout : STD_LOGIC;
@@ -1271,7 +1271,7 @@
wire_l2_w0_n1_mux_dataout <= data_wire(11) WHEN sel_wire(4) = '1' ELSE data_wire(10);
wire_l3_w0_n0_mux_dataout <= data_wire(13) WHEN sel_wire(8) = '1' ELSE data_wire(12);
- END RTL; --ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a
+ END RTL; --ip_stratixiv_gxb_reconfig_8_mux_c6a
LIBRARY altera_mf;
USE altera_mf.all;
@@ -1280,7 +1280,7 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
- ENTITY ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm IS
+ ENTITY ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm IS
PORT
(
busy : OUT STD_LOGIC;
@@ -1288,9 +1288,9 @@
reconfig_fromgxb : IN STD_LOGIC_VECTOR (135 DOWNTO 0);
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
- END ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm;
+ END ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm;
- ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm IS
+ ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm IS
ATTRIBUTE synthesis_clearbox : natural;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
@@ -1371,7 +1371,7 @@
transceiver_init : IN STD_LOGIC
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj
+ COMPONENT ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj
PORT
(
address : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -1390,7 +1390,7 @@
wren_data : IN STD_LOGIC := '0'
);
END COMPONENT;
- COMPONENT ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a
+ COMPONENT ip_stratixiv_gxb_reconfig_8_mux_c6a
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
@@ -1449,7 +1449,7 @@
wire_calibration_w_lg_busy13w(0) <= wire_calibration_busy AND wire_calibration_dprio_rden;
wire_dprio_wren <= wire_calibration_w_lg_busy14w(0);
wire_calibration_w_lg_busy14w(0) <= wire_calibration_busy AND wire_calibration_dprio_wren;
- dprio : ip_altera_mf_gxb_reconfig_8_stratixiv_alt_dprio_2vj
+ dprio : ip_stratixiv_gxb_reconfig_8_alt_dprio_2vj
PORT MAP (
address => wire_dprio_address,
busy => wire_dprio_busy,
@@ -1472,21 +1472,21 @@
ELSIF (reconfig_clk = '1' AND reconfig_clk'event) THEN address_pres_reg <= ( quad_address & channel_address);
END IF;
END PROCESS;
- dprioout_mux : ip_altera_mf_gxb_reconfig_8_stratixiv_mux_c6a
+ dprioout_mux : ip_stratixiv_gxb_reconfig_8_mux_c6a
PORT MAP (
data => cal_dprioout_wire,
result => wire_dprioout_mux_result,
sel => quad_address(2 DOWNTO 0)
);
- END RTL; --ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm
+ END RTL; --ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-ENTITY ip_altera_mf_gxb_reconfig_8_stratixiv IS
+ENTITY ip_stratixiv_gxb_reconfig_8 IS
PORT
(
reconfig_clk : IN STD_LOGIC ;
@@ -1494,10 +1494,10 @@ ENTITY ip_altera_mf_gxb_reconfig_8_stratixiv IS
busy : OUT STD_LOGIC ;
reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
-END ip_altera_mf_gxb_reconfig_8_stratixiv;
+END ip_stratixiv_gxb_reconfig_8;
-ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv IS
+ARCHITECTURE RTL OF ip_stratixiv_gxb_reconfig_8 IS
ATTRIBUTE synthesis_clearbox: natural;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
@@ -1510,7 +1510,7 @@ ARCHITECTURE RTL OF ip_altera_mf_gxb_reconfig_8_stratixiv IS
- COMPONENT ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm
+ COMPONENT ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm
PORT (
busy : OUT STD_LOGIC ;
reconfig_clk : IN STD_LOGIC ;
@@ -1523,7 +1523,7 @@ BEGIN
busy <= sub_wire0;
reconfig_togxb <= sub_wire1(3 DOWNTO 0);
- ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm_component : ip_altera_mf_gxb_reconfig_8_stratixiv_alt2gxb_reconfig_njm
+ ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm_component : ip_stratixiv_gxb_reconfig_8_alt2gxb_reconfig_njm
PORT MAP (
reconfig_clk => reconfig_clk,
reconfig_fromgxb => reconfig_fromgxb,
@@ -1560,10 +1560,10 @@ END RTL;
-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 136 0 reconfig_fromgxb 0 0 136 0
-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_gxb_reconfig_8_stratixiv_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_gxb_reconfig_8_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: LIB_FILE: lpm
diff --git a/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_gx_16b.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_hssi_gx_16b.vhd
similarity index 100%
rename from libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_gx_16b.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_hssi_gx_16b.vhd
diff --git a/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_gx_generic.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_hssi_gx_generic.vhd
similarity index 100%
rename from libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_gx_generic.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_hssi_gx_generic.vhd
diff --git a/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_rx_16b.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_hssi_rx_16b.vhd
similarity index 100%
rename from libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_rx_16b.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_hssi_rx_16b.vhd
diff --git a/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_rx_generic.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_hssi_rx_generic.vhd
similarity index 100%
rename from libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_rx_generic.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_hssi_rx_generic.vhd
diff --git a/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_tx_16b.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_hssi_tx_16b.vhd
similarity index 100%
rename from libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_tx_16b.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_hssi_tx_16b.vhd
diff --git a/libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_tx_generic.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_hssi_tx_generic.vhd
similarity index 100%
rename from libraries/technology/altera/stratixiv_hssi/ip_stratixiv_hssi_tx_generic.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_hssi_tx_generic.vhd
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_ram_cr_cw.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_ram_cr_cw.vhd
similarity index 95%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_ram_cr_cw.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_ram_cr_cw.vhd
index cdba78b9b10b837b3c7cb1a4123d511658e86155..fd3a9eabfa4a07ee5e6c1ba6117550b63c3bf59a 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_ram_cr_cw.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_ram_cr_cw.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: ip_altera_mf_ram_cr_cw.vhd
+-- File Name: ip_stratixiv_ram_cr_cw.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -42,7 +42,7 @@ USE altera_mf.all;
LIBRARY technology_lib;
USE technology_lib.technology_pkg.ALL;
-ENTITY ip_altera_mf_ram_cr_cw IS
+ENTITY ip_stratixiv_ram_cr_cw IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -62,10 +62,10 @@ ENTITY ip_altera_mf_ram_cr_cw IS
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
);
-END ip_altera_mf_ram_cr_cw;
+END ip_stratixiv_ram_cr_cw;
-ARCHITECTURE SYN OF ip_altera_mf_ram_cr_cw IS
+ARCHITECTURE SYN OF ip_stratixiv_ram_cr_cw IS
CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
@@ -248,9 +248,9 @@ END SYN;
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_cr_cw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_ram_crw_crw.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_ram_crw_crw.vhd
similarity index 93%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_ram_crw_crw.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_ram_crw_crw.vhd
index 17dde5f44a3ae20a35711023a23607feb1c90853..0204eab6eb66dd44e9c3e8bfd6ffa53056f504d5 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_ram_crw_crw.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_ram_crw_crw.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: ip_altera_mf_ram_crw_crw.vhd
+-- File Name: ip_stratixiv_ram_crw_crw.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -42,7 +42,7 @@ USE altera_mf.all;
LIBRARY technology_lib;
USE technology_lib.technology_pkg.ALL;
-ENTITY ip_altera_mf_ram_crw_crw IS
+ENTITY ip_stratixiv_ram_crw_crw IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -67,10 +67,10 @@ ENTITY ip_altera_mf_ram_crw_crw IS
q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
);
-END ip_altera_mf_ram_crw_crw;
+END ip_stratixiv_ram_crw_crw;
-ARCHITECTURE SYN OF ip_altera_mf_ram_crw_crw IS
+ARCHITECTURE SYN OF ip_stratixiv_ram_crw_crw IS
FUNCTION sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING IS
BEGIN
@@ -304,11 +304,11 @@ END SYN;
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
-- Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crw_crw_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crw_crw_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_ram_crwk_crw.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_ram_crwk_crw.vhd
similarity index 93%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_ram_crwk_crw.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_ram_crwk_crw.vhd
index 4bd7dcc9cf4b057b356c9515058e0d0ced84b805..f2bfc203caa70d57ee416aa01601eedf38d23ca6 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_ram_crwk_crw.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: ip_altera_mf_ram_crwk_crw.vhd
+-- File Name: ip_stratixiv_ram_crwk_crw.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -42,7 +42,7 @@ USE altera_mf.all;
LIBRARY technology_lib;
USE technology_lib.technology_pkg.ALL;
-ENTITY ip_altera_mf_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
+ENTITY ip_stratixiv_ram_crwk_crw IS -- support different port data widths and corresponding address ranges
GENERIC (
g_adr_a_w : NATURAL := 5;
g_dat_a_w : NATURAL := 32;
@@ -70,10 +70,10 @@ ENTITY ip_altera_mf_ram_crwk_crw IS -- support different port data widths and c
q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
);
-END ip_altera_mf_ram_crwk_crw;
+END ip_stratixiv_ram_crwk_crw;
-ARCHITECTURE SYN OF ip_altera_mf_ram_crwk_crw IS
+ARCHITECTURE SYN OF ip_stratixiv_ram_crwk_crw IS
FUNCTION sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING IS
BEGIN
@@ -310,11 +310,11 @@ END SYN;
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_crwk_crw_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crwk_crw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crwk_crw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crwk_crw.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crwk_crw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crwk_crw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crwk_crw_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_crwk_crw_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_ram_r_w.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_ram_r_w.vhd
similarity index 92%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_ram_r_w.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_ram_r_w.vhd
index 7dc33c5b68c499eb129c44a11c90878ede946366..c1afd1340bf99e613c529a31c53da807c73dbdcd 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_ram_r_w.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_ram_r_w.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: ip_altera_mf_ram_r_w.vhd
+-- File Name: ip_stratixiv_ram_r_w.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY ip_altera_mf_ram_r_w IS
+ENTITY ip_stratixiv_ram_r_w IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -55,10 +55,10 @@ ENTITY ip_altera_mf_ram_r_w IS
wren : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
-END ip_altera_mf_ram_r_w;
+END ip_stratixiv_ram_r_w;
-ARCHITECTURE SYN OF ip_altera_mf_ram_r_w IS
+ARCHITECTURE SYN OF ip_stratixiv_ram_r_w IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
@@ -232,11 +232,11 @@ END SYN;
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_ram_r_w_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_r_w.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_r_w.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_r_w.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_r_w.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_r_w_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_r_w_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_r_w_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/altera/stratixiv/ip_stratixiv_remote_update.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_remote_update.vhd
similarity index 100%
rename from libraries/technology/altera/stratixiv/ip_stratixiv_remote_update.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_remote_update.vhd
diff --git a/libraries/technology/altera/altera_mf/ip_altera_mf_rom_r.vhd b/libraries/technology/ip_stratixiv/ip_stratixiv_rom_r.vhd
similarity index 89%
rename from libraries/technology/altera/altera_mf/ip_altera_mf_rom_r.vhd
rename to libraries/technology/ip_stratixiv/ip_stratixiv_rom_r.vhd
index 361017f809e9079b9830a48990b8d9a81bc2f744..460ba93525e78b18c8254810d7dd610f02fbb266 100644
--- a/libraries/technology/altera/altera_mf/ip_altera_mf_rom_r.vhd
+++ b/libraries/technology/ip_stratixiv/ip_stratixiv_rom_r.vhd
@@ -4,7 +4,7 @@
-- MODULE: altsyncram
-- ============================================================
--- File Name: ip_altera_mf_rom_r.vhd
+-- File Name: ip_stratixiv_rom_r.vhd
-- Megafunction Name(s):
-- altsyncram
--
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
-ENTITY ip_altera_mf_rom_r IS
+ENTITY ip_stratixiv_rom_r IS
GENERIC (
g_adr_w : NATURAL := 5;
g_dat_w : NATURAL := 8;
@@ -52,10 +52,10 @@ ENTITY ip_altera_mf_rom_r IS
clken : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
);
-END ip_altera_mf_rom_r;
+END ip_stratixiv_rom_r;
-ARCHITECTURE SYN OF ip_altera_mf_rom_r IS
+ARCHITECTURE SYN OF ip_stratixiv_rom_r IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
@@ -169,11 +169,11 @@ END SYN;
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r_inst.vhd FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r_waveforms.html TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ip_altera_mf_rom_r_wave*.jpg FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_rom_r.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_rom_r.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_rom_r.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_rom_r.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_rom_r_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_rom_r_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_rom_r_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
diff --git a/libraries/technology/xilinx/xilinx_core/hdllib.cfg b/libraries/technology/ip_virtex4/hdllib.cfg
similarity index 59%
rename from libraries/technology/xilinx/xilinx_core/hdllib.cfg
rename to libraries/technology/ip_virtex4/hdllib.cfg
index 375f8631e4803be2785b1ec2c0ba10a28a885d9f..7c07ac5a0db2f7ee5fe75471273c3c3dcf96df07 100644
--- a/libraries/technology/xilinx/xilinx_core/hdllib.cfg
+++ b/libraries/technology/ip_virtex4/hdllib.cfg
@@ -1,5 +1,5 @@
-hdl_lib_name = ip_xilinx_core
-hdl_library_clause_name = ip_xilinx_core_lib
+hdl_lib_name = ip_virtex4
+hdl_library_clause_name = ip_virtex4_lib
hdl_lib_uses =
build_sim_dir = $HDL_BUILD_DIR
diff --git a/libraries/technology/base/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
similarity index 100%
rename from libraries/technology/base/technology_pkg.vhd
rename to libraries/technology/technology_pkg.vhd
diff --git a/libraries/technology/base/technology_select_pkg.vhd b/libraries/technology/technology_select_pkg.vhd
similarity index 100%
rename from libraries/technology/base/technology_select_pkg.vhd
rename to libraries/technology/technology_select_pkg.vhd