From 9c281f473685f649ca078d8762a1ec31de887d15 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Sun, 18 Oct 2015 13:48:37 +0000
Subject: [PATCH] Added and pass on g_technology.
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 2 ++
libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd | 2 ++
libraries/io/epcs/src/vhdl/mms_epcs.vhd | 2 ++
libraries/io/eth/src/vhdl/eth.vhd | 25 +++++++++++--------
libraries/io/eth/src/vhdl/eth_buffer.vhd | 17 ++++++++-----
libraries/io/i2c/src/vhdl/i2c_commander.vhd | 7 ++++--
libraries/io/i2c/src/vhdl/i2c_master.vhd | 5 +++-
libraries/io/i2c/src/vhdl/i2c_mm.vhd | 10 +++++---
libraries/io/ppsh/src/vhdl/mm_ppsh.vhd | 5 +++-
libraries/io/ppsh/src/vhdl/mms_ppsh.vhd | 6 +++--
libraries/io/ppsh/src/vhdl/ppsh.vhd | 12 +++++----
libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd | 2 ++
.../src/vhdl/mms_tr_nonbonded.vhd | 11 +++++---
.../io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd | 6 +++--
libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd | 5 +++-
15 files changed, 81 insertions(+), 36 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 182a004ccd..38dbd9ac2d 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -319,6 +319,7 @@ BEGIN
u_wr_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
GENERIC MAP (
+ g_technology => g_technology,
g_wr_data_w => g_wr_data_w,
g_rd_data_w => c_ctlr_data_w,
g_use_ctrl => c_wr_fifo_use_ctrl,
@@ -398,6 +399,7 @@ BEGIN
u_rd_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
GENERIC MAP (
+ g_technology => g_technology,
g_wr_data_w => c_ctlr_data_w,
g_rd_data_w => g_rd_data_w,
g_use_ctrl => FALSE,
diff --git a/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd b/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
index 236ebeae36..bd2ff825b0 100644
--- a/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
+++ b/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
@@ -225,6 +225,7 @@ BEGIN
-----------------------------------------------------------------------------
u_mms_diag_block_gen: ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP (
+ g_technology => g_technology,
-- Generate configurations
g_use_usr_input => FALSE,
g_use_bg => FALSE,
@@ -255,6 +256,7 @@ BEGIN
-----------------------------------------------------------------------------
u_mms_diag_data_buffer: ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
+ g_technology => g_technology,
-- Generate configurations
g_use_db => g_db_use_db,
g_use_rx_seq => TRUE,
diff --git a/libraries/io/epcs/src/vhdl/mms_epcs.vhd b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
index ac108c28fe..a84c9f8492 100644
--- a/libraries/io/epcs/src/vhdl/mms_epcs.vhd
+++ b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
@@ -178,6 +178,7 @@ BEGIN
u_fifo_user_to_epcs : ENTITY dp_lib.dp_fifo_dc_mixed_widths
GENERIC MAP (
+ g_technology => g_technology,
g_wr_data_w => c_user_data_w,
g_rd_data_w => c_epcs_data_w,
g_use_ctrl => FALSE,
@@ -201,6 +202,7 @@ BEGIN
u_fifo_epcs_to_user : ENTITY dp_lib.dp_fifo_dc_mixed_widths
GENERIC MAP (
+ g_technology => g_technology,
g_wr_data_w => c_epcs_data_w,
g_rd_data_w => c_user_data_w,
g_use_ctrl => FALSE,
diff --git a/libraries/io/eth/src/vhdl/eth.vhd b/libraries/io/eth/src/vhdl/eth.vhd
index 47fc980569..1a9bcb1cab 100644
--- a/libraries/io/eth/src/vhdl/eth.vhd
+++ b/libraries/io/eth/src/vhdl/eth.vhd
@@ -20,7 +20,15 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib, technology_lib;
+-- Purpose:
+-- Provide Ethernet control access to a node and some UDP ports for streaming
+-- data.
+-- Description:
+-- Connect the 1GbE TSE to the microprocessor and to streaming UDP ports. The
+-- packets for the streaming channels are directed based on the UDP port
+-- number and all other packets are transfered to the default control channel.
+
+LIBRARY IEEE, common_lib, technology_lib, dp_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
@@ -31,14 +39,6 @@ USE tech_tse_lib.tech_tse_pkg.ALL;
USE work.eth_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
--- Purpose:
--- Provide Ethernet control access to a node and some UDP ports for streaming
--- data.
--- Description:
--- Connect the 1GbE TSE to the microprocessor and to streaming UDP ports. The
--- packets for the streaming channels are directed based on the UDP port
--- number and all other packets are transfered to the default control channel.
-
ENTITY eth IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
@@ -224,7 +224,8 @@ BEGIN
-- Packet buffer
u_mm_ram : ENTITY common_lib.common_ram_crw_crw
GENERIC MAP (
- g_ram => c_mm_ram
+ g_technology => g_technology,
+ g_ram => c_mm_ram
)
PORT MAP (
rst_a => mm_rst,
@@ -400,6 +401,9 @@ BEGIN
------------------------------------------------------------------------------
u_rx_buffer : ENTITY work.eth_buffer
+ GENERIC MAP (
+ g_technology => g_technology,
+ )
PORT MAP (
-- Clocks and reset
rst => st_rst,
@@ -525,6 +529,7 @@ BEGIN
-- Multiplex the two input streams on to the single ETH stream
u_tx_mux : ENTITY dp_lib.dp_mux
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => c_eth_data_w,
g_empty_w => c_eth_empty_w,
g_in_channel_w => 1,
diff --git a/libraries/io/eth/src/vhdl/eth_buffer.vhd b/libraries/io/eth/src/vhdl/eth_buffer.vhd
index ca94e27c85..d04b92c5da 100644
--- a/libraries/io/eth/src/vhdl/eth_buffer.vhd
+++ b/libraries/io/eth/src/vhdl/eth_buffer.vhd
@@ -20,19 +20,23 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib;
+-- Description:
+-- . Store input frames in a FIFO
+-- . The sink is always ready, so a frame gets flushed when the FIFO is almost full
+-- . Output a frame from the FIFO on request when available
+
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.eth_pkg.ALL;
-
--- Description:
--- . Store input frames in a FIFO
--- . The sink is always ready, so a frame gets flushed when the FIFO is almost full
--- . Output a frame from the FIFO on request when available
+USE technology_lib.technology_select_pkg.ALL;
ENTITY eth_buffer IS
+ GENERIC (
+ g_technology : NATURAL := c_tech_select_default
+ );
PORT (
-- Clocks and reset
rst : IN STD_LOGIC; -- reset synchronous with clk
@@ -114,6 +118,7 @@ BEGIN
u_fifo : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => c_eth_data_w,
g_empty_w => c_eth_empty_w,
g_channel_w => 1,
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander.vhd b/libraries/io/i2c/src/vhdl/i2c_commander.vhd
index cad323ceea..c2460589be 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander.vhd
@@ -65,17 +65,18 @@
-- by inserting SMBUS_C_NOP in the protocol list.
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.i2c_pkg.ALL;
USE work.i2c_commander_pkg.ALL;
-
+USE technology_lib.technology_select_pkg.ALL;
ENTITY i2c_commander IS
GENERIC (
g_sim : BOOLEAN := FALSE;
+ g_technology : NATURAL := c_tech_select_default;
g_i2c_cmdr : t_c_i2c_cmdr_commander;
g_i2c_mm : t_c_i2c_mm;
g_i2c_phy : t_c_i2c_phy;
@@ -284,6 +285,7 @@ BEGIN
-- I2C protocol list register
u_protocol_ram : ENTITY common_lib.common_ram_rw_rw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_protocol_ram,
g_init_file => g_protocol_ram_init_file
)
@@ -312,6 +314,7 @@ BEGIN
-- I2C result register
u_result_ram : ENTITY common_lib.common_ram_rw_rw
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_result_ram
)
PORT MAP (
diff --git a/libraries/io/i2c/src/vhdl/i2c_master.vhd b/libraries/io/i2c/src/vhdl/i2c_master.vhd
index 1eaf984032..82bb58881c 100644
--- a/libraries/io/i2c/src/vhdl/i2c_master.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_master.vhd
@@ -19,14 +19,16 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE work.i2c_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY i2c_master IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_i2c_mm : t_c_i2c_mm := c_i2c_mm;
g_i2c_phy : t_c_i2c_phy
);
@@ -101,6 +103,7 @@ BEGIN
u_mm : ENTITY work.i2c_mm
GENERIC MAP (
+ g_technology => g_technology,
g_i2c_mm => g_i2c_mm
)
PORT MAP (
diff --git a/libraries/io/i2c/src/vhdl/i2c_mm.vhd b/libraries/io/i2c/src/vhdl/i2c_mm.vhd
index 6d971a9cd3..e3d1fc1de7 100644
--- a/libraries/io/i2c/src/vhdl/i2c_mm.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_mm.vhd
@@ -19,14 +19,16 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.i2c_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY i2c_mm IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_i2c_mm : t_c_i2c_mm := c_i2c_mm
);
PORT (
@@ -169,7 +171,8 @@ BEGIN
-- I2C protocol list register
u_ram_protocol : ENTITY common_lib.common_ram_rw_rw
GENERIC MAP (
- g_ram => c_ram_protocol
+ g_technology => g_technology,
+ g_ram => c_ram_protocol
)
PORT MAP (
rst => rst,
@@ -192,7 +195,8 @@ BEGIN
-- I2C result register
u_ram_result : ENTITY common_lib.common_ram_rw_rw
GENERIC MAP (
- g_ram => c_ram_result
+ g_technology => g_technology,
+ g_ram => c_ram_result
)
PORT MAP (
rst => rst,
diff --git a/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
index c08f6c64ff..3ae29277fd 100644
--- a/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
@@ -19,16 +19,18 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
-- Purpose : Get info from ppsh into mm_clk domain
-- Description: See ppsh.vhd
ENTITY mm_ppsh IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_ext_clk_freq : NATURAL := 200 * 10**6 -- clock frequency of clk in Hz
);
PORT (
@@ -84,6 +86,7 @@ BEGIN
u_pps : ENTITY work.ppsh
GENERIC MAP (
+ g_technology => g_technology,
g_clk_freq => g_ext_clk_freq
)
PORT MAP (
diff --git a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
index c2129901bb..bb797c033f 100644
--- a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
@@ -22,15 +22,16 @@
-- Purpose : MMS for ppsh
-- Description: See ppsh.vhd
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-
+USE technology_lib.technology_select_pkg.ALL;
ENTITY mms_ppsh IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
g_st_clk_freq : NATURAL := 200*10**6 -- clk frequency in Hz
);
@@ -82,6 +83,7 @@ BEGIN
u_ppsh : ENTITY work.ppsh
GENERIC MAP (
+ g_technology => g_technology,
g_clk_freq => g_st_clk_freq
)
PORT MAP (
diff --git a/libraries/io/ppsh/src/vhdl/ppsh.vhd b/libraries/io/ppsh/src/vhdl/ppsh.vhd
index 1d0b1ff15e..178511ce5b 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh.vhd
@@ -19,11 +19,6 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-
-- Purpose : Capture the external PPS reliably in the clk clock domain
-- Description:
-- The assumption is that the external PPS is synchronous to the clk clock
@@ -52,9 +47,15 @@ USE common_lib.common_pkg.ALL;
-- ensure that both edges capture the pps_ext in dedicated logic near the
-- pin.
+LIBRARY IEEE, common_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY ppsh IS
GENERIC (
+ g_technology : NATURAL := c_tech_select_default;
g_clk_freq : NATURAL := 200 * 10**6 -- clock frequency of clk in Hz
);
PORT (
@@ -107,6 +108,7 @@ BEGIN
u_in : ENTITY common_lib.common_ddio_in
GENERIC MAP(
+ g_technology => g_technology,
g_width => 1
)
PORT MAP(
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index b0735df70e..cf39343a10 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -200,6 +200,7 @@ BEGIN
gen_dp_fifo_fill_dc : FOR i IN 0 TO g_nof_macs-1 GENERATE
u_dp_fifo_fill_dc : ENTITY dp_lib.dp_fifo_fill_dc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => c_xgmii_data_w,
g_empty_w => c_tech_mac_10g_empty_w,
g_use_empty => TRUE,
@@ -318,6 +319,7 @@ BEGIN
gen_dp_fifo_dc_rx : FOR i IN g_nof_macs-1 DOWNTO 0 GENERATE
u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => c_xgmii_data_w,
g_empty_w => c_tech_mac_10g_empty_w,
g_use_empty => TRUE,
diff --git a/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
index 0e1a35134a..0d8cfccd34 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
@@ -22,17 +22,19 @@
-- Purpose: PHY IO interface for non-bonded gigabit transceivers
-- Description:
-LIBRARY IEEE, common_lib, dp_lib, diag_lib, diagnostics_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib, diag_lib, diagnostics_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY mms_tr_nonbonded IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0; -- Default: 0 = simulate IP. 1 = use fast behavioural model
+ g_technology : NATURAL := c_tech_select_default;
g_data_w : NATURAL := 32;
g_nof_gx : NATURAL;
g_mbps : NATURAL := 6250; -- Supported: 6250, 5000, 3125, 2500
@@ -141,11 +143,12 @@ BEGIN
u_tr_nonbonded : ENTITY work.tr_nonbonded
GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_technology => g_technology,
g_data_w => g_data_w,
g_nof_gx => g_nof_gx,
g_mbps => g_mbps,
- g_sim => g_sim,
- g_sim_level => g_sim_level,
g_tx => g_tx,
g_rx => g_rx,
g_fifos => TRUE,
@@ -266,6 +269,7 @@ BEGIN
u_dp_mux : ENTITY dp_lib.dp_mux
GENERIC MAP (
+ g_technology => g_technology,
-- Mux
g_sel_ctrl_invert => TRUE, -- We're using DOWNTO ranges in our streaming arrays, so we must invert the selection input
g_mode => 2,
@@ -329,6 +333,7 @@ BEGIN
gen_data_buf : IF g_rx=TRUE AND g_rx_use_data_buf=TRUE GENERATE
u_data_buf : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
+ g_technology => g_technology,
g_nof_streams => g_nof_gx,
g_data_w => g_data_w,
g_buf_nof_data => g_rx_data_buf_nof_words,
diff --git a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
index 827fca955a..50891829a9 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
@@ -29,6 +29,8 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY tr_nonbonded IS
GENERIC(
+ g_sim : BOOLEAN := FALSE;
+ g_sim_level : NATURAL := 0;
g_technology : NATURAL := c_tech_select_default;
g_data_w : NATURAL := 32;
g_nof_gx : NATURAL := 12;
@@ -43,8 +45,6 @@ ENTITY tr_nonbonded IS
-- |--------------------------------------------------------------------------------------------
-- | X | >1 | Not supported
------------------------------------------------------------------------------------------------
- g_sim : BOOLEAN := FALSE;
- g_sim_level : NATURAL := 0;
g_tx : BOOLEAN := TRUE;
g_rx : BOOLEAN := TRUE;
g_fifos : BOOLEAN := FALSE; -- When TRUE use dp_clk and clock domain crossing FIFO for dp->tx and for rx->dp, when FALSE use rx_clk stream and tx_clk stream
@@ -210,6 +210,7 @@ BEGIN
gen_tx_fifo : IF g_fifos = TRUE GENERATE
u_tx_fifo : ENTITY dp_lib.dp_fifo_dc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_use_ctrl => FALSE,
g_fifo_size => g_tx_fifo_depth,
@@ -255,6 +256,7 @@ BEGIN
gen_rx_fifo : IF g_fifos = TRUE GENERATE
u_rx_fifo : ENTITY dp_lib.dp_fifo_dc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_use_ctrl => FALSE,
g_fifo_size => g_rx_fifo_depth,
diff --git a/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
index ced454f39a..286eeba674 100644
--- a/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
@@ -20,7 +20,7 @@
--
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib, mdio_lib, diagnostics_lib;
+LIBRARY IEEE, common_lib, technology_lib, dp_lib, mdio_lib, diagnostics_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
@@ -28,10 +28,12 @@ USE common_lib.common_interface_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE mdio_lib.mdio_pkg.ALL;
USE mdio_lib.mdio_vitesse_vsc8486_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY mms_tr_xaui IS
GENERIC (
g_sim : BOOLEAN := FALSE;
+ g_technology : NATURAL := c_tech_select_default;
g_nof_xaui : NATURAL := 1; -- Up to 3 (hard XAUI only) supported
g_use_mdio : BOOLEAN := FALSE
);
@@ -131,6 +133,7 @@ BEGIN
u_tr_xaui: ENTITY work.tr_xaui
GENERIC MAP (
+ g_technology => g_technology,
g_sim => g_sim,
g_use_mdio => g_use_mdio,
g_nof_xaui => g_nof_xaui
--
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