diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
index fdfbf651786d04928a10ab82424fcca8108dd598..fbec2621015bcb2d8ae7ba9e228e50701cd57d39 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
@@ -56,6 +56,7 @@ entity ip_arria10_e1sg_jesd204b_v2 is
-- Data to fabric
dp_clk : in std_logic;
dp_rst : in std_logic;
+ dp_sysref : out std_logic; -- = dp_sosi_arr(0).sync, all dp_sosi_arr().sync carry the dp_sysref
dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
-- MM Control
@@ -160,8 +161,9 @@ architecture str of ip_arria10_e1sg_jesd204b_v2 is
signal dplink_data : std_logic_vector(c_jesd204b_rx_data_w - 1 downto 0);
signal dplink_data_hi : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
signal dplink_data_lo : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+
signal i_dp_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal dp_sosi : t_dp_sosi;
+ signal dp_sosi : t_dp_sosi; -- input 0
-- outputs to control ADC initialization/syncronization phase
signal jesd204b_sync_n_internal_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -268,6 +270,12 @@ architecture str of ip_arria10_e1sg_jesd204b_v2 is
);
end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
begin
+ dp_sosi_arr <= i_dp_sosi_arr;
+ dp_sosi <= i_dp_sosi_arr(0);
+
+ -- wire dp_sysref from dp_sosi_arr().sync, all sync carry the dp_sysref
+ dp_sysref <= dp_sosi.sync;
+
-- Debug signals to view input 0 in Wave Window
jesd204b_rx_link_data <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w - 1 downto 0);
jesd204b_rx_link_data_hi <= jesd204b_rx_link_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
index fcc8ee1a65dd8ebaeaca5d890065d4914aca41ac..fd4c96984c5db8310728ad607addf25ca1fdf865 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
@@ -56,6 +56,7 @@ entity ip_arria10_e2sg_jesd204b_v2 is
-- Data to fabric
dp_clk : in std_logic;
dp_rst : in std_logic;
+ dp_sysref : out std_logic; -- = dp_sosi_arr(0).sync, all dp_sosi_arr().sync carry the dp_sysref
dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
-- MM Control
@@ -160,8 +161,9 @@ architecture str of ip_arria10_e2sg_jesd204b_v2 is
signal dplink_data : std_logic_vector(c_jesd204b_rx_data_w - 1 downto 0);
signal dplink_data_hi : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
signal dplink_data_lo : std_logic_vector(c_jesd204b_rx_framer_data_w - 1 downto 0);
+
signal i_dp_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
- signal dp_sosi : t_dp_sosi;
+ signal dp_sosi : t_dp_sosi; -- input 0
-- outputs to control ADC initialization/syncronization phase
signal jesd204b_sync_n_internal_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -268,6 +270,12 @@ architecture str of ip_arria10_e2sg_jesd204b_v2 is
);
end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
begin
+ dp_sosi_arr <= i_dp_sosi_arr;
+ dp_sosi <= i_dp_sosi_arr(0);
+
+ -- wire dp_sysref from dp_sosi_arr().sync, all sync carry the dp_sysref
+ dp_sysref <= dp_sosi.sync;
+
-- Debug signals to view input 0 in Wave Window
jesd204b_rx_link_data <= jesd204b_rx_link_data_arr(c_jesd204b_rx_data_w - 1 downto 0);
jesd204b_rx_link_data_hi <= jesd204b_rx_link_data(c_jesd204b_rx_data_w - 1 downto c_jesd204b_rx_framer_data_w);
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
index 7353580328bed20578161553f0ec0fabcfd44f8f..4da60d79b3503244bdcbcc2bba437d62e4f7c352 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b_v2.vhd
@@ -134,6 +134,7 @@ architecture tb of tb_tech_jesd204b_v2 is
signal jesd204b_sampclk : std_logic := '0';
signal dp_clk : std_logic := '0';
signal dp_rst : std_logic := '0';
+ signal dp_sysref : std_logic;
signal dp_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b - 1 downto 0);
-- Debug signals for dp_sosi_arr
@@ -198,6 +199,7 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
+ dp_sysref => dp_sysref,
dp_sosi_arr => dp_sosi_arr,
-- MM
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg_v2.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg_v2.vhd
index e408df40a80463d4007627b5392a7e0e7b53c806..dfd1705abf98226374c5ae946be92d48fb5d4ad0 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg_v2.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg_v2.vhd
@@ -20,7 +20,7 @@
--
--------------------------------------------------------------------------------
--- Author: J Hargreaves
+-- Author: J Hargreaves, E. Kooistra
-- Purpose: Wrapper for the Intel Arria 10 e1sg (unb2b, unb2c) tecnology version of the
-- JESD204b interface for ADCs and DACs
-- Description
@@ -55,6 +55,7 @@ entity tech_jesd204b_arria10_e1sg_v2 is
-- Data to fabric
dp_clk : in std_logic;
dp_rst : in std_logic;
+ dp_sysref : out std_logic; -- = dp_sosi_arr(0).sync, all dp_sosi_arr().sync carry the dp_sysref
dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
-- MM Control
@@ -89,6 +90,7 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
+ dp_sysref => dp_sysref,
dp_sosi_arr => dp_sosi_arr,
-- MM
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg_v2.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg_v2.vhd
index 0b51c642c9e68d8bb7ef8bfcb7404297a0c077e3..a07c80d975782c8babeaf218fbf9b2b15c3cf0e7 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg_v2.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg_v2.vhd
@@ -20,9 +20,11 @@
--
--------------------------------------------------------------------------------
+-- Author: J Hargreaves, E. Kooistra
-- Purpose: Wrapper for the Intel Arria 10 e2sg (unb2b, unb2c) tecnology version of the
-- JESD204b interface for ADCs and DACs
-- Description
+-- Current configuration supports 12 channels receive only
--
-- . v2 uses FIFO in IP to get from rxlink_clk at 100 MHz to dp_clk at 200 MHz
@@ -53,6 +55,7 @@ entity tech_jesd204b_arria10_e2sg_v2 is
-- Data to fabric
dp_clk : in std_logic;
dp_rst : in std_logic;
+ dp_sysref : out std_logic; -- = dp_sosi_arr(0).sync, all dp_sosi_arr().sync carry the dp_sysref
dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
-- MM Control
@@ -87,6 +90,7 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
+ dp_sysref => dp_sysref,
dp_sosi_arr => dp_sosi_arr,
-- MM
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 890a3ff711e7f426b05b94b64b9f8adc9326bae6..9cbe9ea812051084e3cd645424d707cb9accdeb9 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -95,6 +95,7 @@ package tech_jesd204b_component_pkg is
-- Data to fabric
dp_clk : in std_logic;
dp_rst : in std_logic;
+ dp_sysref : out std_logic; -- = dp_sosi_arr(0).sync, all dp_sosi_arr().sync carry the dp_sysref
dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
-- MM Control
@@ -229,6 +230,7 @@ package tech_jesd204b_component_pkg is
-- Data to fabric
dp_clk : in std_logic;
dp_rst : in std_logic;
+ dp_sysref : out std_logic; -- = dp_sosi_arr(0).sync, all dp_sosi_arr().sync carry the dp_sysref
dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
-- MM Control
diff --git a/libraries/technology/jesd204b/tech_jesd204b_v2.vhd b/libraries/technology/jesd204b/tech_jesd204b_v2.vhd
index da305877b781fbbb981153265e67fc7612a79e6c..f11c2502b5177fcce911f64b9df3c339aa48a27c 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_v2.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_v2.vhd
@@ -20,14 +20,14 @@
--
--------------------------------------------------------------------------------
--- Author : J Hargreaves
+-- Author : J Hargreaves, E. Kooistra
-- Purpose: Technology selection wrapper to instantiate
-- JESD204b interface for ADCs and DACs
-- Description:
--
-- Select g_direction = RX_ONLY for ADC
-- IP settings are for the AD9683 ADC
--- Technology currently supported: Intel Arria 10 (e1sg), unb2b, unb2c
+-- Technology currently supported: Intel Arria 10 (e1sg, e2sg), unb2b, unb2c
--
-- . For c_tech_arria10_e1sg:
--
@@ -73,6 +73,7 @@ entity tech_jesd204b_v2 is
-- Data to fabric
dp_clk : in std_logic;
dp_rst : in std_logic;
+ dp_sysref : out std_logic; -- = dp_sosi_arr(0).sync, all dp_sosi_arr().sync carry the dp_sysref
dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
-- MM Control
@@ -91,7 +92,7 @@ end tech_jesd204b_v2;
architecture str of tech_jesd204b_v2 is
begin
gen_ip_arria10_e1sg_v2 : if g_technology = c_tech_arria10_e1sg generate
- u0 : entity work.tech_jesd204b_arria10_e2sg_v2
+ u0 : entity work.tech_jesd204b_arria10_e1sg_v2
generic map(
g_sim => g_sim,
g_nof_streams => g_nof_streams,
@@ -108,6 +109,7 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
+ dp_sysref => dp_sysref,
dp_sosi_arr => dp_sosi_arr,
-- MM
@@ -141,6 +143,7 @@ begin
dp_clk => dp_clk,
dp_rst => dp_rst,
+ dp_sysref => dp_sysref,
dp_sosi_arr => dp_sosi_arr,
-- MM