diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index dda363b40a7b4c6c92aecfa6ed1c6b4cdcf378ab..b4b591c923ec32c6ddbfbcdb67deae31d4f2fcae 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -123,7 +123,6 @@ ARCHITECTURE rtl OF dp_fifo_fill_eop IS
SIGNAL hold_src_in : t_dp_siso;
SIGNAL pend_src_out : t_dp_sosi;
-<<<<<<< HEAD
SIGNAL reg_wr_eop_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL reg_rd_eop_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL wr_eop_done : STD_LOGIC;
@@ -135,16 +134,6 @@ ARCHITECTURE rtl OF dp_fifo_fill_eop IS
SIGNAL rd_eop_cnt : NATURAL := 0;
SIGNAL eop_cnt : INTEGER := 0;
SIGNAL nxt_eop_cnt : INTEGER := 0;
-=======
- SIGNAL received_eop : BOOLEAN := FALSE;
- SIGNAL nxt_received_eop : BOOLEAN := FALSE;
- SIGNAL expecting_eop : BOOLEAN := FALSE;
- SIGNAL nxt_expecting_eop : BOOLEAN := FALSE;
- SIGNAL common_spulse_clken : STD_LOGIC_VECTOR(c_nof_spulse DOWNTO 0) := (OTHERS => '1');
- SIGNAL common_spulse_out_pulse : STD_LOGIC_VECTOR(c_nof_spulse-1 DOWNTO 0);
- SIGNAL common_spulse_busy : STD_LOGIC_VECTOR(c_nof_spulse-1 DOWNTO 0);
- SIGNAL crossed_domain_snk_in_eop : STD_LOGIC := '0';
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
BEGIN
-- Output monitor FIFO filling
@@ -158,10 +147,6 @@ BEGIN
rd_fill_ctrl <= rd_fill_32b(c_fifo_size_w-1 DOWNTO 0);
gen_dp_fifo_sc : IF g_use_dual_clock=FALSE GENERATE
-<<<<<<< HEAD
-=======
- crossed_domain_snk_in_eop <= snk_in.eop; -- No need to transfer eop across clock domains
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
u_dp_fifo_sc : ENTITY work.dp_fifo_sc
GENERIC MAP (
g_technology => g_technology,
@@ -218,26 +203,6 @@ BEGIN
END GENERATE;
gen_dp_fifo_dc : IF g_use_dual_clock=TRUE GENERATE
-<<<<<<< HEAD
-=======
- -- Transfer eop across clock domain
- crossed_domain_snk_in_eop <= vector_or(common_spulse_out_pulse);
- gen_spulse : FOR I IN 0 TO c_nof_spulse-1 GENERATE
- common_spulse_clken(I+1) <= vector_and(common_spulse_busy(I DOWNTO 0));
- u_common_spulse : ENTITY common_lib.common_spulse
- PORT MAP (
- in_rst => wr_rst,
- in_clk => wr_clk,
- in_clken => common_spulse_clken(I),
- in_pulse => snk_in.eop,
- in_busy => common_spulse_busy(I),
- out_rst => rd_rst,
- out_clk => rd_clk,
- out_pulse => common_spulse_out_pulse(I)
- );
- END GENERATE;
-
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
u_dp_fifo_dc : ENTITY work.dp_fifo_dc
GENERIC MAP (
g_technology => g_technology,
@@ -337,46 +302,20 @@ BEGIN
xon_reg <= '0';
state <= s_idle;
i_src_out <= c_dp_sosi_rst;
-<<<<<<< HEAD
-=======
- received_eop <= FALSE;
- expecting_eop <= FALSE;
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
ELSIF rising_edge(rd_clk) THEN
xon_reg <= nxt_xon_reg;
state <= nxt_state;
i_src_out <= nxt_src_out;
-<<<<<<< HEAD
eop_cnt <= nxt_eop_cnt;
-=======
- IF crossed_domain_snk_in_eop = '1' THEN
- IF expecting_eop THEN
- expecting_eop <= FALSE;
- ELSE
- received_eop <= TRUE;
- END IF;
- ELSE
- expecting_eop <= nxt_expecting_eop;
- received_eop <= nxt_received_eop;
- END IF;
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
END IF;
END PROCESS;
nxt_xon_reg <= src_in.xon; -- register xon to easy timing closure
gen_rl_0 : IF g_fifo_rl=0 GENERATE
-<<<<<<< HEAD
p_state : PROCESS(state, rd_sosi, src_in, xon_reg, rd_fifo_usedw, rd_fill_ctrl, rd_eop_cnt, eop_cnt, rd_eop_new)
BEGIN
nxt_state <= state;
-=======
- p_state : PROCESS(state, rd_sosi, src_in, xon_reg, rd_fifo_usedw, rd_fill_ctrl, received_eop, expecting_eop)
- BEGIN
- nxt_state <= state;
- nxt_received_eop <= received_eop;
- nxt_expecting_eop <= expecting_eop;
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
rd_siso <= src_in; -- default acknowledge (RL=1) this input when output is ready
-- The output register stage increase RL=0 to 1, so it matches RL = 1 for src_in.ready
@@ -415,17 +354,10 @@ BEGIN
IF src_in.ready='1' THEN
nxt_src_out <= rd_sosi; -- output sop that is still at FIFO output (RL=0)
nxt_state <= s_output;
-<<<<<<< HEAD
IF rd_eop_new = '1' THEN
nxt_eop_cnt <= eop_cnt + rd_eop_cnt - 1;
ELSE
nxt_eop_cnt <= eop_cnt -1;
-=======
- IF received_eop THEN
- nxt_received_eop <= FALSE;
- ELSE
- nxt_expecting_eop <= TRUE;
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
END IF;
END IF;
END IF;
@@ -469,17 +401,9 @@ BEGIN
src_out_reg => i_src_out
);
-<<<<<<< HEAD
p_state : PROCESS(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl, rd_eop_cnt, eop_cnt, rd_eop_new)
BEGIN
nxt_state <= state;
-=======
- p_state : PROCESS(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl, received_eop, expecting_eop)
- BEGIN
- nxt_state <= state;
- nxt_received_eop <= received_eop;
- nxt_expecting_eop <= expecting_eop;
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
hold_src_in <= src_in; -- default request (RL=1) new input when output is ready
@@ -519,17 +443,10 @@ BEGIN
IF src_in.ready='1' THEN
nxt_src_out <= pend_src_out; -- output sop that is still pending in dp_hold_input
nxt_state <= s_output;
-<<<<<<< HEAD
IF rd_eop_new = '1' THEN
nxt_eop_cnt <= eop_cnt + rd_eop_cnt - 1;
ELSE
nxt_eop_cnt <= eop_cnt -1;
-=======
- IF received_eop THEN
- nxt_received_eop <= FALSE;
- ELSE
- nxt_expecting_eop <= TRUE;
->>>>>>> a9f29c033d05b5f8f9e623b894e59e7abd43b4c3
END IF;
END IF;
END IF;