diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index 679b432484442b5b03dc6b8e31ca4cfa1c06b4a4..70304b7a4e2cca27c71682e6110ad25253a48409 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -45,7 +45,9 @@
 --   got errors.
 --   The diag_sample keeps the last valid in_dat value. When diag_en='0' it is
 --   reset to 0. Reading diag_sample via MM gives an impression of the valid
---   in_dat activity.
+--   in_dat activity. The diag_sample_diff shows the difference of the last and
+--   the previous in_dat value. The diag_sample_diff can be useful to determine
+--   or debug the values that are needed for diag_steps_arr.
 --
 -- . g_use_steps = TRUE
 --   The test data is fixed to COUNTER and diag_sel is ignored. The rx_seq can
@@ -116,7 +118,9 @@ ENTITY diag_rx_seq IS
     diag_steps_arr : t_integer_arr(g_nof_steps-1 DOWNTO 0) := (OTHERS=>1);
     diag_res       : OUT STD_LOGIC_VECTOR(g_diag_res_w-1 DOWNTO 0);  -- diag_res valid indication bits & aggregate diff of in_dat during diag_en
     diag_res_val   : OUT STD_LOGIC;
-    diag_sample    : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);  -- monitor last valid in_dat
+    diag_sample      : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);  -- monitor last valid in_dat
+    diag_sample_diff : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);  -- monitor difference between last valid in_dat and previous valid in_dat
+    diag_sample_val  : OUT STD_LOGIC;
     
     -- ST input
     in_cnt         : OUT STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0);  -- count valid input test sequence data
@@ -170,8 +174,11 @@ ARCHITECTURE rtl OF diag_rx_seq IS
   
   SIGNAL diag_res_int    : STD_LOGIC_VECTOR(diag_res'RANGE) := c_diag_res_invalid;
   
-  SIGNAL i_diag_sample   : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-  SIGNAL nxt_diag_sample : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+  SIGNAL i_diag_sample        : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+  SIGNAL nxt_diag_sample      : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+  SIGNAL i_diag_sample_diff   : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+  SIGNAL nxt_diag_sample_diff : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+  SIGNAL nxt_diag_sample_val  : STD_LOGIC;
 
   TYPE t_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
   
@@ -187,6 +194,7 @@ BEGIN
 
   diag_dis <= NOT diag_en;
   diag_sample <= i_diag_sample;
+  diag_sample_diff <= i_diag_sample_diff;
   
   gen_input_reg : IF g_input_reg=TRUE GENERATE
     p_reg : PROCESS (clk)
@@ -245,7 +253,9 @@ BEGIN
         diff_arr     <= nxt_diff_arr;
         diff_detect  <= nxt_diff_detect;
         -- Outputs.
-        i_diag_sample <= nxt_diag_sample;
+        i_diag_sample      <= nxt_diag_sample;
+        i_diag_sample_diff <= nxt_diag_sample_diff;
+        diag_sample_val    <= nxt_diag_sample_val;
       END IF;
     END IF;
   END PROCESS;
@@ -253,7 +263,9 @@ BEGIN
   ------------------------------------------------------------------------------
   -- Keep last valid in_dat value for MM monitoring
   ------------------------------------------------------------------------------
-  nxt_diag_sample <= (OTHERS=>'0') WHEN diag_en='0' ELSE in_dat WHEN in_val='1' ELSE i_diag_sample;
+  nxt_diag_sample      <= (OTHERS=>'0') WHEN diag_en='0' ELSE in_dat_reg                          WHEN in_val_reg='1' ELSE i_diag_sample;
+  nxt_diag_sample_diff <= (OTHERS=>'0') WHEN diag_en='0' ELSE SUB_UVEC(in_dat_reg, i_diag_sample) WHEN in_val_reg='1' ELSE i_diag_sample_diff;
+  nxt_diag_sample_val  <=          '0'  WHEN diag_en='0' ELSE in_val_reg;
   
   ------------------------------------------------------------------------------
   -- Detect that there has been valid input data for at least two clock cycles
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index 2c52ecbd942dcf8b6d6332a8da848807501a7a35..7e54bf5a3a775404bd0dc26b403fe074c6011611 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -170,6 +170,8 @@ ARCHITECTURE str OF mms_diag_rx_seq IS
   
   SIGNAL rx_cnt_arr          : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);  -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
   SIGNAL rx_sample_arr       : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL rx_sample_diff_arr  : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL rx_sample_val_arr   : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
   SIGNAL rx_seq_arr          : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
   SIGNAL rx_seq_val_arr      : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
   SIGNAL rx_data_arr         : t_data_arr(g_nof_streams-1 DOWNTO 0);
@@ -235,6 +237,8 @@ BEGIN
       diag_res          => diag_res_arr(I),
       diag_res_val      => diag_res_val_arr(I),
       diag_sample       => rx_sample_arr(I),
+      diag_sample_diff  => rx_sample_diff_arr(I),
+      diag_sample_val   => rx_sample_val_arr(I),
 
       -- Streaming
       in_cnt            => rx_cnt_arr(I),