From 9a9fba3d3f3319bc86b7be0bc5253040eecef990 Mon Sep 17 00:00:00 2001 From: donker <donker@astron.nl> Date: Thu, 15 Jun 2023 08:23:46 +0200 Subject: [PATCH] RTSD-93, review comment 1 --- .../lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd | 8 ++++---- .../lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd | 8 ++++---- .../RSP/pft2/src/vhdl/pft_separate(rtl).vhd | 4 ++-- .../lofar1/RSP/pft2/src/vhdl/pft_separate.vhd | 4 ++-- .../lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd | 4 ++-- .../lofar1/RSP/pft2/src/vhdl/pft_switch.vhd | 4 ++-- .../RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd | 4 ++-- .../lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd | 4 ++-- applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd | 2 +- .../lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd | 2 +- ...l_timer_0_altera_avalon_timer_180_5qqtsby.vhd | 4 ++-- ...l_timer_0_altera_avalon_timer_180_5qqtsby.vhd | 4 ++-- libraries/base/common/src/vhdl/common_clip.vhd | 2 +- libraries/base/common/src/vhdl/common_pkg.vhd | 4 ++-- .../base/common/tb/vhdl/tb_common_transpose.vhd | 2 +- .../tb/vhdl/tb_common_complex_mult.vhd | 16 ++++++++-------- .../tb/vhdl/tb_mmf_fringe_stop_unit.vhd | 8 ++++---- libraries/dsp/iquv/src/vhdl/iquv.vhd | 2 +- libraries/technology/mult/tech_complex_mult.vhd | 14 +++++++------- 19 files changed, 50 insertions(+), 50 deletions(-) diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd index 8ff5e6d54a..d98e112537 100644 --- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd +++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd @@ -128,11 +128,11 @@ begin -- yr <= xr(n-k) - xr(n) nxt_yr_add <= '0'; - nxt_yr_a <= xr(- c_dist); + nxt_yr_a <= xr(-c_dist); nxt_yr_b <= xr(0); -- yi <= xi(n-k) - xi(n) nxt_yi_add <= '0'; - nxt_yi_a <= xi(- c_dist); + nxt_yi_a <= xi(-c_dist); nxt_yi_b <= xi(0); when "10" => @@ -151,11 +151,11 @@ begin -- y <= x(n-k) + i*x(n) -- yr(n) <= xr(n-k) - xi(n); nxt_yr_add <= '0'; - nxt_yr_a <= xr(- c_dist); + nxt_yr_a <= xr(-c_dist); nxt_yr_b <= xi(0); -- yi(n) <= xi(n-k) + xr(n); nxt_yi_add <= '1'; - nxt_yi_a <= xi(- c_dist); + nxt_yi_a <= xi(-c_dist); nxt_yi_b <= xr(0); end case; diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd index 25581058fd..707029cf75 100644 --- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd +++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd @@ -177,11 +177,11 @@ begin -- yr <= xr(n-k) - xr(n) nxt_yr_add <= '0'; - nxt_yr_a <= xr(- c_dist); + nxt_yr_a <= xr(-c_dist); nxt_yr_b <= xr(0); -- yi <= xi(n-k) - xi(n) nxt_yi_add <= '0'; - nxt_yi_a <= xi(- c_dist); + nxt_yi_a <= xi(-c_dist); nxt_yi_b <= xi(0); when "10" => @@ -200,11 +200,11 @@ begin -- y <= x(n-k) + i*x(n) -- yr(n) <= xr(n-k) - xi(n); nxt_yr_add <= '0'; - nxt_yr_a <= xr(- c_dist); + nxt_yr_a <= xr(-c_dist); nxt_yr_b <= xi(0); -- yi(n) <= xi(n-k) + xr(n); nxt_yi_add <= '1'; - nxt_yi_a <= xi(- c_dist); + nxt_yi_a <= xi(-c_dist); nxt_yi_b <= xr(0); end case; diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd index 992c4708dc..fb1990b020 100644 --- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd +++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd @@ -145,12 +145,12 @@ begin nxt_add0 <= rddata_re_dly(0); nxt_add1 <= rddata_re_dly(0); nxt_sub0 <= rddata_re_dly(1); - nxt_sub1 <= std_logic_vector(- signed(rddata_re_dly(1))); + nxt_sub1 <= std_logic_vector(-signed(rddata_re_dly(1))); elsif unsigned(rd_cnt) = 1 then nxt_add0 <= rddata_im_dly(1); nxt_add1 <= rddata_im_dly(1); nxt_sub0 <= rddata_im_dly(2); - nxt_sub1 <= std_logic_vector(- signed(rddata_im_dly(2))); + nxt_sub1 <= std_logic_vector(-signed(rddata_im_dly(2))); elsif rd_cnt(0) = '0' then nxt_add0 <= rddata_re_dly(0); nxt_add1 <= rddata_re_dly(1); diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd index debba277f5..21ae81944a 100644 --- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd +++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd @@ -193,12 +193,12 @@ begin nxt_add0 <= rddata_re_dly(0); nxt_add1 <= rddata_re_dly(0); nxt_sub0 <= rddata_re_dly(1); - nxt_sub1 <= std_logic_vector(- signed(rddata_re_dly(1))); + nxt_sub1 <= std_logic_vector(-signed(rddata_re_dly(1))); elsif unsigned(rd_cnt) = 1 then nxt_add0 <= rddata_im_dly(1); nxt_add1 <= rddata_im_dly(1); nxt_sub0 <= rddata_im_dly(2); - nxt_sub1 <= std_logic_vector(- signed(rddata_im_dly(2))); + nxt_sub1 <= std_logic_vector(-signed(rddata_im_dly(2))); elsif rd_cnt(0) = '0' then nxt_add0 <= rddata_re_dly(0); nxt_add1 <= rddata_re_dly(1); diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd index 4e713e02d7..978b68cb3f 100644 --- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd +++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd @@ -63,13 +63,13 @@ begin nxt_out_sync <= in_sync and in_val; if lfsr_bit1 = cnt(cnt'high) and switch_en = '1' then - nxt_out_re <= std_logic_vector(- signed(in_re)); + nxt_out_re <= std_logic_vector(-signed(in_re)); else nxt_out_re <= in_re; end if; if lfsr_bit2 = cnt(cnt'high) and switch_en = '1' then - nxt_out_im <= std_logic_vector(- signed(in_im)); + nxt_out_im <= std_logic_vector(-signed(in_im)); else nxt_out_im <= in_im; end if; diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd index d6406f384d..dc0573854a 100644 --- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd +++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd @@ -108,13 +108,13 @@ begin nxt_out_sync <= in_sync and in_val; if lfsr_bit1 = cnt(cnt'high) and switch_en = '1' then - nxt_out_re <= std_logic_vector(- signed(in_re)); + nxt_out_re <= std_logic_vector(-signed(in_re)); else nxt_out_re <= in_re; end if; if lfsr_bit2 = cnt(cnt'high) and switch_en = '1' then - nxt_out_im <= std_logic_vector(- signed(in_im)); + nxt_out_im <= std_logic_vector(-signed(in_im)); else nxt_out_im <= in_im; end if; diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd index 129ed03ec5..e965007495 100644 --- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd +++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd @@ -66,8 +66,8 @@ begin nxt_out_im <= in_im; if ((cnt(0) = '0' and cnt(cnt'high) = lfsr_bit1) or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then - nxt_out_re <= std_logic_vector(- signed(in_re)); - nxt_out_im <= std_logic_vector(- signed(in_im)); + nxt_out_re <= std_logic_vector(-signed(in_re)); + nxt_out_im <= std_logic_vector(-signed(in_im)); end if; end process; diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd index 9d3750da90..b4d481800a 100644 --- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd +++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd @@ -111,8 +111,8 @@ begin nxt_out_im <= in_im; if ((cnt(0) = '0' and cnt(cnt'high) = lfsr_bit1) or (cnt(0) = '1' and cnt(cnt'high) = lfsr_bit2)) and (switch_en = '1') then - nxt_out_re <= std_logic_vector(- signed(in_re)); - nxt_out_im <= std_logic_vector(- signed(in_im)); + nxt_out_re <= std_logic_vector(-signed(in_re)); + nxt_out_im <= std_logic_vector(-signed(in_im)); end if; end process; diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd index 5e1c351a5a..3fbd80e15a 100644 --- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd +++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd @@ -284,7 +284,7 @@ architecture tb of tb_pft2 is for i in 1 to N / 2 - 1 loop lo := im(i); hi := im(N - i); - sr(i) <= (- hi + lo) / N; + sr(i) <= (-hi + lo) / N; end loop; end if; end proc_fft_real2_im; diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd index fa858d4061..7e4f250ff4 100644 --- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd +++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd @@ -153,7 +153,7 @@ begin elsif rising_edge(clk) then if cnt(0) = '1' then if in_val = '1' then - in_x <= std_logic_vector(- signed(in_x)); + in_x <= std_logic_vector(-signed(in_x)); in_y <= std_logic_vector(signed(in_y)); end if; end if; diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd index aad5977f48..8b3e6b4cf8 100644 --- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd +++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd @@ -105,7 +105,7 @@ begin elsif clk'event and clk = '1' then if std_logic'(clk_en) = '1' then if std_logic'(do_start_counter) = '1' then - counter_is_running <= Vector_To_Std_Logic(- signed(std_logic_vector'("00000000000000000000000000000001"))); + counter_is_running <= Vector_To_Std_Logic(-signed(std_logic_vector'("00000000000000000000000000000001"))); elsif std_logic'(do_stop_counter) = '1' then counter_is_running <= std_logic'('0'); end if; @@ -137,7 +137,7 @@ begin if std_logic'(status_wr_strobe) = '1' then timeout_occurred <= std_logic'('0'); elsif std_logic'(timeout_event) = '1' then - timeout_occurred <= Vector_To_Std_Logic(- signed(std_logic_vector'("00000000000000000000000000000001"))); + timeout_occurred <= Vector_To_Std_Logic(-signed(std_logic_vector'("00000000000000000000000000000001"))); end if; end if; end if; diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd index aad5977f48..8b3e6b4cf8 100644 --- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd +++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd @@ -105,7 +105,7 @@ begin elsif clk'event and clk = '1' then if std_logic'(clk_en) = '1' then if std_logic'(do_start_counter) = '1' then - counter_is_running <= Vector_To_Std_Logic(- signed(std_logic_vector'("00000000000000000000000000000001"))); + counter_is_running <= Vector_To_Std_Logic(-signed(std_logic_vector'("00000000000000000000000000000001"))); elsif std_logic'(do_stop_counter) = '1' then counter_is_running <= std_logic'('0'); end if; @@ -137,7 +137,7 @@ begin if std_logic'(status_wr_strobe) = '1' then timeout_occurred <= std_logic'('0'); elsif std_logic'(timeout_event) = '1' then - timeout_occurred <= Vector_To_Std_Logic(- signed(std_logic_vector'("00000000000000000000000000000001"))); + timeout_occurred <= Vector_To_Std_Logic(-signed(std_logic_vector'("00000000000000000000000000000001"))); end if; end if; end if; diff --git a/libraries/base/common/src/vhdl/common_clip.vhd b/libraries/base/common/src/vhdl/common_clip.vhd index c68abbd6de..67bff34b13 100644 --- a/libraries/base/common/src/vhdl/common_clip.vhd +++ b/libraries/base/common/src/vhdl/common_clip.vhd @@ -86,7 +86,7 @@ begin nxt_clip_dat <= std_logic_vector(RESIZE_NUM( c_s_full_scale, c_dat_w)); nxt_clip_ovr <= '1'; elsif signed(in_dat) < - c_s_full_scale then - nxt_clip_dat <= std_logic_vector(RESIZE_NUM(- c_s_full_scale, c_dat_w)); + nxt_clip_dat <= std_logic_vector(RESIZE_NUM(-c_s_full_scale, c_dat_w)); nxt_clip_ovr <= '1'; end if; else diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd index 5a96c55922..1c54724dc4 100644 --- a/libraries/base/common/src/vhdl/common_pkg.vhd +++ b/libraries/base/common/src/vhdl/common_pkg.vhd @@ -2195,7 +2195,7 @@ package body common_pkg is begin -- use NUMERIC_STD to avoid range limitation of 32b INTEGER -- default approach - return std_logic_vector(- signed(vec)); -- negate by multiplying by -1 + return std_logic_vector(-signed(vec)); -- negate by multiplying by -1 -- alternative equivalent approach -- RETURN INCR_UVEC(NOT vec, 1); -- negate by using two complement negate end; @@ -2213,7 +2213,7 @@ package body common_pkg is if signed(v_val) = c_min then return std_logic_vector(to_signed(c_max, c_vec_w)); -- most negative becomes most positive else - return std_logic_vector(RESIZE_NUM(- signed(v_val), c_vec_w)); -- negate by multiplying by -1 + return std_logic_vector(RESIZE_NUM(-signed(v_val), c_vec_w)); -- negate by multiplying by -1 end if; end; diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd index ad1477c061..842c6e7de1 100644 --- a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd +++ b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd @@ -88,7 +88,7 @@ architecture tb of tb_common_transpose is signal in_eop : std_logic; -- DUT output - signal trans_offset : std_logic_vector(g_addr_w - 1 downto 0) := TO_SVEC(- g_addr_offset, g_addr_w); -- use -g_addr_offset as inverse operation + signal trans_offset : std_logic_vector(g_addr_w - 1 downto 0) := TO_SVEC(-g_addr_offset, g_addr_w); -- use -g_addr_offset as inverse operation signal trans_addr : std_logic_vector(g_addr_w - 1 downto 0); signal trans_data : std_logic_vector(g_data_w - 1 downto 0); signal trans_val : std_logic; diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd index 20dd830d46..45a7f60398 100644 --- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd +++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd @@ -147,13 +147,13 @@ begin wait until rising_edge(clk); in_ar <= TO_SVEC( c_max, g_in_dat_w); in_ai <= TO_SVEC( c_max, g_in_dat_w); - in_br <= TO_SVEC(- c_max, g_in_dat_w); - in_bi <= TO_SVEC(- c_max, g_in_dat_w); + in_br <= TO_SVEC(-c_max, g_in_dat_w); + in_bi <= TO_SVEC(-c_max, g_in_dat_w); wait until rising_edge(clk); in_ar <= TO_SVEC( c_min, g_in_dat_w); in_ai <= TO_SVEC( c_min, g_in_dat_w); - in_br <= TO_SVEC(- c_max, g_in_dat_w); - in_bi <= TO_SVEC(- c_max, g_in_dat_w); + in_br <= TO_SVEC(-c_max, g_in_dat_w); + in_bi <= TO_SVEC(-c_max, g_in_dat_w); wait until rising_edge(clk); in_ar <= TO_SVEC(0, g_in_dat_w); in_br <= TO_SVEC(0, g_in_dat_w); @@ -180,13 +180,13 @@ begin wait until rising_edge(clk); in_ar <= TO_SVEC( c_max, g_in_dat_w); in_ai <= TO_SVEC( c_max - 1, g_in_dat_w); - in_br <= TO_SVEC(- c_max + 2, g_in_dat_w); - in_bi <= TO_SVEC(- c_max + 3, g_in_dat_w); + in_br <= TO_SVEC(-c_max + 2, g_in_dat_w); + in_bi <= TO_SVEC(-c_max + 3, g_in_dat_w); wait until rising_edge(clk); in_ar <= TO_SVEC( c_min, g_in_dat_w); in_ai <= TO_SVEC( c_min + 1, g_in_dat_w); - in_br <= TO_SVEC(- c_max + 2, g_in_dat_w); - in_bi <= TO_SVEC(- c_max + 3, g_in_dat_w); + in_br <= TO_SVEC(-c_max + 2, g_in_dat_w); + in_bi <= TO_SVEC(-c_max + 3, g_in_dat_w); wait until rising_edge(clk); in_ar <= TO_SVEC(0, g_in_dat_w); in_br <= TO_SVEC(0, g_in_dat_w); diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd index 950ea6bc7a..5cc3974777 100644 --- a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd +++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd @@ -371,13 +371,13 @@ begin -- Measure verify_sum_en <= '0'; -- Initial (out_re, out_im) = (-c_in_amplitude, 0) - proc_common_wait_until_value(- c_in_amplitude, dp_clk, out_re); -- wait until out_re=-c_in_amplitude - proc_common_wait_until_value(- c_in_amplitude+1, dp_clk, out_re); -- wait until out_re=-c_in_amplitude+1 + proc_common_wait_until_value(-c_in_amplitude, dp_clk, out_re); -- wait until out_re=-c_in_amplitude + proc_common_wait_until_value(-c_in_amplitude+1, dp_clk, out_re); -- wait until out_re=-c_in_amplitude+1 proc_common_wait_until_evt(dp_clk, out_re); -- wait until out_re changes vBegin := NOW / c_dp_clk_period; verify_sum_en <= '1'; - proc_common_wait_until_value(- c_in_amplitude, dp_clk, out_re); -- wait until out_re=-c_in_amplitude again - proc_common_wait_until_value(- c_in_amplitude+1, dp_clk, out_re); -- wait until out_re=-c_in_amplitude+1 again + proc_common_wait_until_value(-c_in_amplitude, dp_clk, out_re); -- wait until out_re=-c_in_amplitude again + proc_common_wait_until_value(-c_in_amplitude+1, dp_clk, out_re); -- wait until out_re=-c_in_amplitude+1 again proc_common_wait_until_evt(dp_clk, out_re); -- wait until out_re changes vEnd := NOW / c_dp_clk_period; vPeriod := vEnd - vBegin; diff --git a/libraries/dsp/iquv/src/vhdl/iquv.vhd b/libraries/dsp/iquv/src/vhdl/iquv.vhd index 6f609d2e78..09bd9053ba 100644 --- a/libraries/dsp/iquv/src/vhdl/iquv.vhd +++ b/libraries/dsp/iquv/src/vhdl/iquv.vhd @@ -323,7 +323,7 @@ begin out_dat => product_xy_re_dly ); - product_xy_im_neg <= TO_SVEC(- TO_SINT(product_xy_im), c_multprod_w); + product_xy_im_neg <= TO_SVEC(-TO_SINT(product_xy_im), c_multprod_w); u_delay_xy_imag : entity common_lib.common_pipeline generic map ( diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd index 29b65e2238..d895f83f36 100644 --- a/libraries/technology/mult/tech_complex_mult.vhd +++ b/libraries/technology/mult/tech_complex_mult.vhd @@ -120,7 +120,7 @@ begin ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w); ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w); br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w); - bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(- TO_SINT(in_bi), c_dsp_mult_18_w); + bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w); u0 : ip_stratixiv_complex_mult port map ( @@ -145,7 +145,7 @@ begin ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w); ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w); br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w); - bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(- TO_SINT(in_bi), c_dsp_mult_18_w); + bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w); u0 : ip_arria10_complex_mult port map ( @@ -170,7 +170,7 @@ begin ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w); ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w); br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w); - bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(- TO_SINT(in_bi), c_dsp_mult_18_w); + bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w); u0 : ip_arria10_e1sg_complex_mult port map ( @@ -195,7 +195,7 @@ begin ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w); ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w); br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w); - bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(- TO_SINT(in_bi), c_dsp_mult_18_w); + bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w); u0 : ip_arria10_e2sg_complex_mult port map ( @@ -225,7 +225,7 @@ begin ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w); ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w); br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w); - bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) when g_conjugate_b = false else TO_SVEC(- TO_SINT(in_bi), c_dsp_mult_27_w); + bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w); u0 : ip_arria10_e1sg_complex_mult_27b port map ( @@ -250,7 +250,7 @@ begin ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w); ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w); br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w); - bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) when g_conjugate_b = false else TO_SVEC(- TO_SINT(in_bi), c_dsp_mult_27_w); + bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w); u0 : ip_arria10_e2sg_complex_mult_27b port map ( @@ -333,7 +333,7 @@ begin g_technology = c_tech_arria10_e1sg or g_technology = c_tech_arria10_e2sg) generate -- support g_conjugate_b - bi <= in_bi when g_conjugate_b = false else TO_SVEC(- TO_SINT(in_bi), g_in_b_w); + bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w); u0 : ip_arria10_complex_mult_rtl_canonical generic map ( -- GitLab