From 99a2ef6edb48d001ede83aa54fb2e1b17f0844c5 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 10 Apr 2015 09:58:15 +0000
Subject: [PATCH] Use phy records from tech_ddr_lib.tech_ddr_pkg. Use
tech_ddr_lib.tech_ddr_memory_model.
---
.../tb/vhdl/tb_unb1_ddr3_transpose.vhd | 75 ++++---------------
1 file changed, 15 insertions(+), 60 deletions(-)
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
index fedabeda98..5c16297a26 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
@@ -25,12 +25,13 @@
-- that are used on hardware.
-LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, ddr3_lib;
+LIBRARY IEEE, tech_ddr_lib, common_lib, unb1_board_lib, i2c_lib, ddr3_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
USE ddr3_lib.ddr3_pkg.ALL;
ENTITY tb_unb1_ddr3_transpose IS
@@ -52,8 +53,8 @@ ARCHITECTURE tb OF tb_unb1_ddr3_transpose IS
CONSTANT c_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
- CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
-
+ CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
+
-- DUT
SIGNAL clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
@@ -75,14 +76,10 @@ ARCHITECTURE tb OF tb_unb1_ddr3_transpose IS
SIGNAL sens_sda : STD_LOGIC;
-- Signals to interface with the DDR3 memory model.
- SIGNAL phy_in : t_ddr3_phy_in_arr(0 DOWNTO 0);
- SIGNAL phy_io : t_ddr3_phy_io_arr(0 DOWNTO 0);
- SIGNAL phy_ou : t_ddr3_phy_ou_arr(0 DOWNTO 0);
+ SIGNAL phy_in : t_tech_ddr3_phy_in;
+ SIGNAL phy_io : t_tech_ddr3_phy_io;
+ SIGNAL phy_ou : t_tech_ddr3_phy_ou;
- SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
- SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
- SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
-
-- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
CONSTANT c_fpga_temp : INTEGER := 60;
@@ -194,56 +191,14 @@ BEGIN
);
-- DDR3 Model
- u_4gb_800_ddr3_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
- GENERIC MAP (
- MEM_IF_ADDR_WIDTH => 15,
- MEM_IF_ROW_ADDR_WIDTH => 15,
- MEM_IF_COL_ADDR_WIDTH => 10,
- MEM_IF_CS_PER_RANK => 1,
- MEM_IF_CONTROL_WIDTH => 1,
- MEM_IF_DQS_WIDTH => 8,
- MEM_IF_CS_WIDTH => 2,
- MEM_IF_BANKADDR_WIDTH => 3,
- MEM_IF_DQ_WIDTH => 64,
- MEM_IF_CK_WIDTH => 2,
- MEM_IF_CLK_EN_WIDTH => 2,
- DEVICE_WIDTH => 1,
- MEM_TRCD => 6,
- MEM_TRTP => 3,
- MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
- MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
- MEM_IF_ODT_WIDTH => 2,
- MEM_MIRROR_ADDRESSING_DEC => 0,
- MEM_REGDIMM_ENABLED => false,
- DEVICE_DEPTH => 1,
- MEM_GUARANTEED_WRITE_INIT => false,
- MEM_VERBOSE => true,
- MEM_INIT_EN => false,
- MEM_INIT_FILE => "",
- DAT_DATA_WIDTH => 32
- )
+ u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+ GENERIC MAP (
+ g_tech_ddr => c_tech_ddr
+ )
PORT MAP (
- mem_a => phy_ou(0).a(c_ddr.a_w-1 DOWNTO 0),
- mem_ba => phy_ou(0).ba,
- mem_ck => phy_io(0).clk,
- mem_ck_n => phy_io(0).clk_n,
- mem_cke => phy_ou(0).cke(c_ddr.cs_w-1 DOWNTO 0),
- mem_cs_n => phy_ou(0).cs_n(c_ddr.cs_w-1 DOWNTO 0),
- mem_dm => phy_ou(0).dm,
- mem_ras_n => ras_n,
- mem_cas_n => cas_n,
- mem_we_n => we_n,
- mem_reset_n => phy_ou(0).reset_n,
- mem_dq => phy_io(0).dq,
- mem_dqs => phy_io(0).dqs,
- mem_dqs_n => phy_io(0).dqs_n,
- mem_odt => phy_ou(0).odt
- );
-
- ras_n(0) <= phy_ou(0).ras_n;
- cas_n(0) <= phy_ou(0).cas_n;
- we_n(0) <= phy_ou(0).we_n;
-
+ -- DDR3 PHY interface
+ mem3_in => phy_ou,
+ mem3_io => phy_io
+ );
-
END tb;
--
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