From 996114aa83c8ce9e57438cd12776ba448163bda4 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Thu, 9 Apr 2015 11:41:23 +0000
Subject: [PATCH] - Added fifo used words to the register for both rd and wr
fifo - Switched fail and ok in reg map - Removed comments
---
libraries/io/ddr/src/vhdl/io_ddr.vhd | 48 ++++++++++++++++------------
1 file changed, 28 insertions(+), 20 deletions(-)
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 31e17b4b0c..35a0f996a9 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -238,7 +238,11 @@ ARCHITECTURE str OF io_ddr IS
CONSTANT c_wr_fifo_depth : NATURAL := g_wr_fifo_depth * (c_ctlr_data_w/g_wr_data_w); -- get FIFO depth at write side
CONSTANT c_wr_fifo_af_margin : NATURAL := 4 + 1; -- use +1 to compensate for latency introduced by registering wr_siso.ready due to RL=0
- CONSTANT c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, 1 , 32 , 1, 'X');
+
+ CONSTANT c_mem_reg_adr_w : NATURAL := 2;
+ CONSTANT c_mem_reg_dat_w : NATURAL := 32;
+ CONSTANT c_mem_reg_nof_data : NATURAL := 3;
+ CONSTANT c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_adr_w , c_mem_reg_dat_w , c_mem_reg_nof_data, 'X');
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
@@ -268,7 +272,7 @@ ARCHITECTURE str OF io_ddr IS
SIGNAL dp_flush_snk_in : t_dp_sosi := c_dp_sosi_rst;
SIGNAL ctlr_rst_out_i : STD_LOGIC;
- SIGNAL mm_reg_io_ddr : STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL mm_reg_io_ddr : STD_LOGIC_VECTOR(c_mem_reg_nof_data*c_mem_reg_dat_w-1 DOWNTO 0);
BEGIN
@@ -468,34 +472,38 @@ BEGIN
phy4_ou => phy4_ou
);
- ctlr_rst_out <= ctlr_rst_out_i;
- mm_reg_io_ddr <= RESIZE_UVEC(ctlr_tech_miso.cal_ok & ctlr_tech_miso.cal_fail & ctlr_rst_out_i & ctlr_tech_mosi.flush & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done, 32);
+ ctlr_rst_out <= ctlr_rst_out_i;
+
+
+ mm_reg_io_ddr <= RESIZE_UVEC(ctlr_wr_fifo_usedw, c_mem_reg_dat_w) &
+ RESIZE_UVEC(ctlr_rd_fifo_usedw, c_mem_reg_dat_w) &
+ RESIZE_UVEC(ctlr_tech_miso.cal_fail & ctlr_tech_miso.cal_ok & ctlr_rst_out_i & ctlr_wr_flush_en & ctlr_tech_miso.waitrequest_n & ctlr_tech_miso.done, c_mem_reg_dat_w);
u_reg_map : ENTITY common_lib. common_reg_r_w_dc
GENERIC MAP (
- g_cross_clock_domain => TRUE, -- : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
- g_in_new_latency => 0, -- : NATURAL := 0; -- >= 0
- g_readback => FALSE, -- : BOOLEAN := FALSE; -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
- g_reg => c_mem_reg_io_ddr, -- : t_c_mem := c_mem_reg;
- g_init_reg => (OTHERS => '0') -- : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
+ g_cross_clock_domain => TRUE,
+ g_in_new_latency => 0,
+ g_readback => FALSE,
+ g_reg => c_mem_reg_io_ddr,
+ g_init_reg => (OTHERS => '0')
)
PORT MAP (
-- Clocks and reset
- mm_rst => mm_rst, --: IN STD_LOGIC; -- reset synchronous with mm_clk
- mm_clk => mm_clk, --: IN STD_LOGIC; -- memory-mapped bus clock
- st_rst => ctlr_rst_in, --: IN STD_LOGIC; -- reset synchronous with st_clk
- st_clk => ctlr_clk_in, --: IN STD_LOGIC; -- other clock domain clock
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ st_rst => ctlr_rst_in,
+ st_clk => ctlr_clk_in,
-- Memory Mapped Slave in mm_clk domain
- sla_in => reg_io_ddr_mosi, --: IN t_mem_mosi; -- actual ranges defined by g_reg
- sla_out => reg_io_ddr_miso, --: OUT t_mem_miso; -- actual ranges defined by g_reg
+ sla_in => reg_io_ddr_mosi,
+ sla_out => reg_io_ddr_miso,
-- MM registers in st_clk domain
- reg_wr_arr => OPEN, -- : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
- reg_rd_arr => OPEN, -- : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
- in_new => '1', -- : IN STD_LOGIC := '1';
- in_reg => mm_reg_io_ddr, -- : IN STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
- out_reg => OPEN -- : OUT STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0)
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => '1',
+ in_reg => mm_reg_io_ddr,
+ out_reg => OPEN
);
END str;
--
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