From 97e37f98c6ccb5799850248ef7bff77266575512 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 21 Feb 2024 13:53:42 +0100
Subject: [PATCH] Clarified how sync is poassed on through the FIFO.
---
.../jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd | 15 ++++++++++++---
.../jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd | 15 ++++++++++++---
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
index 8766f1130d..06e7aa9824 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_v2.vhd
@@ -537,13 +537,22 @@ begin
-- dp_index. This is because reading ab, cd, ef, ... is equivalent to reading
-- bc, de, fg, ... However the phase of dp_ready with respect to dp_index is
-- important for reading the sync, because if dp_ready has the wrong phase,
- -- then the sync is missed at the FIFO output.
+ -- then the sync is missed at the FIFO output. The reason that the sync can be
+ -- missed is that it is passed on via the sosi.sync, which means that it is
+ -- forced to '0' when sosi.valid = '0' due to dp_ready = '0'. If the sync would
+ -- be passed on as a sosi.data bit, then it would hold its '1' value also during
+ -- sosi.valid = '0'.
-- . If dp_index = '0' or '1' initialy, then in both cases use dp_ready <= not
-- dp_index, and then in both cases the latency dp_sosi.sync and data = 1000 is
-- then 340 ns
- -- . Do not use dp_ready <= dp_index, because then the dp_sosi.sync gets missed.
+ -- . Do not use dp_ready <= dp_index, because then they have opposite phase
+ -- and then dp_sosi.sync gets missed.
-- Therefore choose to use dp_index = '0' initially, because then dp_ready =
- -- dp_index always.
+ -- dp_index always. Then in the dp_clk cycle after dp_ready = '1' the high part
+ -- data is read (because dp_index = '0') and the sync is available (because
+ -- then valid = '1'). In the next dp_clk cycle the low part is read (because
+ -- dp_index = '1') and the dp_ready = '1', to prepare for the next data word
+ -- read from the FIFO.
p_fsm_dp_index : process(dp_rst, dp_clk)
begin
if dp_rst = '1' then
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
index 35fbecd22b..a21f86e148 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_v2.vhd
@@ -537,13 +537,22 @@ begin
-- dp_index. This is because reading ab, cd, ef, ... is equivalent to reading
-- bc, de, fg, ... However the phase of dp_ready with respect to dp_index is
-- important for reading the sync, because if dp_ready has the wrong phase,
- -- then the sync is missed at the FIFO output.
+ -- then the sync is missed at the FIFO output. The reason that the sync can be
+ -- missed is that it is passed on via the sosi.sync, which means that it is
+ -- forced to '0' when sosi.valid = '0' due to dp_ready = '0'. If the sync would
+ -- be passed on as a sosi.data bit, then it would hold its '1' value also during
+ -- sosi.valid = '0'.
-- . If dp_index = '0' or '1' initialy, then in both cases use dp_ready <= not
-- dp_index, and then in both cases the latency dp_sosi.sync and data = 1000 is
-- then 340 ns
- -- . Do not use dp_ready <= dp_index, because then the dp_sosi.sync gets missed.
+ -- . Do not use dp_ready <= dp_index, because then they have opposite phase
+ -- and then dp_sosi.sync gets missed.
-- Therefore choose to use dp_index = '0' initially, because then dp_ready =
- -- dp_index always.
+ -- dp_index always. Then in the dp_clk cycle after dp_ready = '1' the high part
+ -- data is read (because dp_index = '0') and the sync is available (because
+ -- then valid = '1'). In the next dp_clk cycle the low part is read (because
+ -- dp_index = '1') and the dp_ready = '1', to prepare for the next data word
+ -- read from the FIFO.
p_fsm_dp_index : process(dp_rst, dp_clk)
begin
if dp_rst = '1' then
--
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