diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f161025c11587c25930a82124daf46b42d42cdfb
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
@@ -0,0 +1,40 @@
+# ------------------------------------------------------------------------------
+#
+# Copyright 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# ------------------------------------------------------------------------------
+#
+# Author: D.F. Brouwer
+# Description:
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult/sim"
+
+vmap altmult_complex_1910 ./work/
+
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_agi027_xxxx_complex_mult_altmult_complex_1910_mvkwxpy.vhd" -work altmult_complex_1910
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult_27b/sim"
+
+ vcom "$IP_DIR/../altmult_complex_1910/sim/ip_agi027_xxxx_complex_mult_27b_altmult_complex_1910_fuab2ya.vhd" -work altmult_complex_1910
diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0cf2e102e6c8b637e39ed0bee55eab956528598a
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_agi027_xxxx_altmult_complex_1910
+hdl_library_clause_name = altmult_complex_1910
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/compile_ip.tcl
+
+
+
diff --git a/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt
new file mode 100644
index 0000000000000000000000000000000000000000..404094477eaadc47132663a8e9349ffcb66561f9
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/altera_libraries/altmult_complex_1910/liborder.txt
@@ -0,0 +1,3 @@
+common: n_libs=9 lib_order=['technology', 'ip_agi027_xxxx_ram', 'tech_memory', 'ip_agi027_xxxx_fifo', 'tech_fifo', 'ip_agi027_xxxx_ddio', 'tech_iobuf', 'tst', 'common']
+
+New test order: []
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/README.txt b/libraries/technology/ip_agi027_xxxx/complex_mult/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..a2afb13ea0e244df9b2ac0b9c724e50231fd2126
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/README.txt
@@ -0,0 +1,62 @@
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/complex_mult
+
+1) Porting
+2) IP component
+3) Compilation, simulation and verification
+4) Synthesis
+5) Remarks
+
+
+1) Porting
+
+The complex_mult IP was ported manually from Quartus v19.4 for Arria10_e2sg to Quartus 23.2 for Agi027_xxxx by creating it in Quartus (Qsys) using
+the same parameter settings.
+
+
+2) IP component
+
+The generated IPs are not kept in git repository, only the ip source files:
+
+ ip_agi027_xxxx_complex_mult.ip
+ ip_agi027_xxxx_complex_mult_27b.ip
+
+Therefore first the IP needs to be generated using:
+
+ generate_ip_libs iwave
+
+
+3) Compilation, simulation and verification
+
+The generated IP also contains a msim_setup.tcl file that was used to manually create:
+
+ compile_ip.tcl
+
+This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
+
+
+4) Synthesis
+
+No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
+
+ ip_agi027_xxxx_complex_mult.qip
+ ip_agi027_xxxx_complex_mult_27b.qip
+
+is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+5) Remarks
+
+a) Use generated IP specific library clause name and IP specific lib uses sim
+
+ The generated ip_agi027_xxxx_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
+ specific library as library clause name and, in addition, uses lib uses sim to make it known:
+
+ hdl_lib_name = ip_agi027_xxxx_<lib_name>
+ hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_<ip_specific>
+ hdl_lib_uses_sim = ip_agi027_xxxx_<ip_specific>
+
+b) When multiple IPs are generated, each utilizing the same IP function but with different settings, it results in the generation of the same
+ library name, containing a different .vhd file, as opposed to the previously used unique library names. This leads to issues. To address
+ this, shared libraries are combined within a single library with the IP-specific library name in the build directory when 'generate_ip_libs'
+ is used. Therefore, a directory is manually created in 'altera_libraries' with the IP-specific library name, containing three files:
+ 'compile_ip.tcl', 'hdllib.cfg' and 'liborder'.
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl b/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..dd0ade513a25242deaf1c05d565ea6ac319da0bd
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
@@ -0,0 +1,37 @@
+# ------------------------------------------------------------------------------
+#
+# Copyright 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# ------------------------------------------------------------------------------
+#
+# Author: D.F. Brouwer
+# Description:
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult/sim"
+ vcom "$IP_DIR/ip_agi027_xxxx_complex_mult.vhd"
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_complex_mult_27b/sim"
+ vcom "$IP_DIR/ip_agi027_xxxx_complex_mult_27b.vhd"
+
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..abeabd8feafd1d4a4ec05e31afc3843523377c24
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_agi027_xxxx_complex_mult
+hdl_library_clause_name = ip_agi027_xxxx_complex_mult_altmult_complex_1910
+hdl_lib_uses_synth =
+hdl_lib_uses_sim = ip_agi027_xxxx_altmult_complex_1910
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_xxxx/complex_mult/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_complex_mult/ip_agi027_xxxx_complex_mult.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_complex_mult_27b/ip_agi027_xxxx_complex_mult_27b.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_xxxx_complex_mult.ip
+ ip_agi027_xxxx_complex_mult_27b.ip
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip b/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip
new file mode 100644
index 0000000000000000000000000000000000000000..3d685fe000c22b63e4cd32b7088ca86eba7b8850
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult.ip
@@ -0,0 +1,769 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_complex_mult</ipxact:library>
+ <ipxact:name>altmult_complex_0</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result_real</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result_real</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result_imag</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result_imag</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="reset" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>clock</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>ena</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>ena</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>altmult_complex</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>dataa_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>35</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>35</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_complex_mult</ipxact:library>
+ <ipxact:name>altmult_complex</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="CBX_AUTO_BLACKBOX" type="string">
+ <ipxact:name>CBX_AUTO_BLACKBOX</ipxact:name>
+ <ipxact:displayName>CBX_AUTO_BLACKBOX</ipxact:displayName>
+ <ipxact:value>ALL</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_A" type="int">
+ <ipxact:name>WIDTH_A</ipxact:name>
+ <ipxact:displayName>How wide should the A input buses be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_B" type="int">
+ <ipxact:name>WIDTH_B</ipxact:name>
+ <ipxact:displayName>How wide should the B input buses be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_RESULT" type="int">
+ <ipxact:name>WIDTH_RESULT</ipxact:name>
+ <ipxact:displayName>How wide should the 'result' output bus be?</ipxact:displayName>
+ <ipxact:value>36</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_A" type="int">
+ <ipxact:name>REPRESENTATION_A</ipxact:name>
+ <ipxact:displayName>What is the representation format for A inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_B" type="int">
+ <ipxact:name>REPRESENTATION_B</ipxact:name>
+ <ipxact:displayName>What is the representation format for B inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DYNAMIC_COMPLEX" type="bit">
+ <ipxact:name>GUI_DYNAMIC_COMPLEX</ipxact:name>
+ <ipxact:displayName>Dynamic Complex Mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="IMPLEMENTATION_STYLE" type="string">
+ <ipxact:name>IMPLEMENTATION_STYLE</ipxact:name>
+ <ipxact:displayName>Which implementation style should be used?</ipxact:displayName>
+ <ipxact:value>AUTO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="PIPELINE" type="int">
+ <ipxact:name>PIPELINE</ipxact:name>
+ <ipxact:displayName>Output latency</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLEAR_TYPE" type="string">
+ <ipxact:name>GUI_CLEAR_TYPE</ipxact:name>
+ <ipxact:displayName>Clear Signal Type</ipxact:displayName>
+ <ipxact:value>ACLR</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_USE_CLKEN" type="bit">
+ <ipxact:name>GUI_USE_CLKEN</ipxact:name>
+ <ipxact:displayName>Create a Clock Enable input?</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element altmult_complex_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="aclr" altera:internal="altmult_complex_0.aclr" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="altmult_complex_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_imag" altera:internal="altmult_complex_0.dataa_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_imag" altera:internal="dataa_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_real" altera:internal="altmult_complex_0.dataa_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_real" altera:internal="dataa_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_imag" altera:internal="altmult_complex_0.datab_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_imag" altera:internal="datab_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_real" altera:internal="altmult_complex_0.datab_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_real" altera:internal="datab_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="ena" altera:internal="altmult_complex_0.ena" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="ena" altera:internal="ena"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_imag" altera:internal="altmult_complex_0.result_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_imag" altera:internal="result_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_real" altera:internal="altmult_complex_0.result_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_real" altera:internal="result_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip b/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip
new file mode 100644
index 0000000000000000000000000000000000000000..e14c33f7db0df2922c66e5326649b668fc90de1e
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult/ip_agi027_xxxx_complex_mult_27b.ip
@@ -0,0 +1,769 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_complex_mult_27b</ipxact:library>
+ <ipxact:name>altmult_complex_0</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
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+ <ipxact:parameters>
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+ <ipxact:value></ipxact:value>
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+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
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+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>26</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_real</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>53</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result_imag</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>53</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>ena</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_complex_mult_27b</ipxact:library>
+ <ipxact:name>altmult_complex</ipxact:name>
+ <ipxact:version>19.1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="CBX_AUTO_BLACKBOX" type="string">
+ <ipxact:name>CBX_AUTO_BLACKBOX</ipxact:name>
+ <ipxact:displayName>CBX_AUTO_BLACKBOX</ipxact:displayName>
+ <ipxact:value>ALL</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_A" type="int">
+ <ipxact:name>WIDTH_A</ipxact:name>
+ <ipxact:displayName>How wide should the A input buses be?</ipxact:displayName>
+ <ipxact:value>27</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_B" type="int">
+ <ipxact:name>WIDTH_B</ipxact:name>
+ <ipxact:displayName>How wide should the B input buses be?</ipxact:displayName>
+ <ipxact:value>27</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="WIDTH_RESULT" type="int">
+ <ipxact:name>WIDTH_RESULT</ipxact:name>
+ <ipxact:displayName>How wide should the 'result' output bus be?</ipxact:displayName>
+ <ipxact:value>54</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_A" type="int">
+ <ipxact:name>REPRESENTATION_A</ipxact:name>
+ <ipxact:displayName>What is the representation format for A inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="REPRESENTATION_B" type="int">
+ <ipxact:name>REPRESENTATION_B</ipxact:name>
+ <ipxact:displayName>What is the representation format for B inputs?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_DYNAMIC_COMPLEX" type="bit">
+ <ipxact:name>GUI_DYNAMIC_COMPLEX</ipxact:name>
+ <ipxact:displayName>Dynamic Complex Mode</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="IMPLEMENTATION_STYLE" type="string">
+ <ipxact:name>IMPLEMENTATION_STYLE</ipxact:name>
+ <ipxact:displayName>Which implementation style should be used?</ipxact:displayName>
+ <ipxact:value>AUTO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="PIPELINE" type="int">
+ <ipxact:name>PIPELINE</ipxact:name>
+ <ipxact:displayName>Output latency</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLEAR_TYPE" type="string">
+ <ipxact:name>GUI_CLEAR_TYPE</ipxact:name>
+ <ipxact:displayName>Clear Signal Type</ipxact:displayName>
+ <ipxact:value>ACLR</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_USE_CLKEN" type="bit">
+ <ipxact:name>GUI_USE_CLKEN</ipxact:name>
+ <ipxact:displayName>Create a Clock Enable input?</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element altmult_complex_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="aclr" altera:internal="altmult_complex_0.aclr" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="aclr" altera:internal="aclr"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="altmult_complex_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_imag" altera:internal="altmult_complex_0.dataa_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_imag" altera:internal="dataa_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_real" altera:internal="altmult_complex_0.dataa_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_real" altera:internal="dataa_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_imag" altera:internal="altmult_complex_0.datab_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_imag" altera:internal="datab_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_real" altera:internal="altmult_complex_0.datab_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_real" altera:internal="datab_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="ena" altera:internal="altmult_complex_0.ena" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="ena" altera:internal="ena"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_imag" altera:internal="altmult_complex_0.result_imag" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_imag" altera:internal="result_imag"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result_real" altera:internal="altmult_complex_0.result_real" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result_real" altera:internal="result_real"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..93f2eb999ce93259e77d464a2dc33236911739ef
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_agi027_xxxx_complex_mult_rtl
+hdl_library_clause_name = ip_agi027_xxxx_complex_mult_rtl_lib
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = #Similar to the complex_mult_rtl hdllib of arria10_e1sg, e2sg, e3sge3
+
+synth_files =
+ ip_agi027_xxxx_complex_mult_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..21af4e3cbe536a207cf2359159eabbb0b7ebd85a
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl/ip_agi027_xxxx_complex_mult_rtl.vhd
@@ -0,0 +1,258 @@
+-- --------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Reference:
+-- Copied from */technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--
+-- Function: Signed complex multiply
+-- p = a * b when g_conjugate_b = FALSE
+-- = (ar + j ai) * (br + j bi)
+-- = ar*br - ai*bi + j ( ar*bi + ai*br)
+--
+-- p = a * conj(b) when g_conjugate_b = TRUE
+-- = (ar + j ai) * (br - j bi)
+-- = ar*br + ai*bi + j (-ar*bi + ai*br)
+--
+-- Architectures:
+-- . rtl : uses RTL to have all registers in one clocked process
+--
+
+entity ip_agi027_xxxx_complex_mult_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+ g_conjugate_b : boolean := false;
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_ar : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_ai : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_br : in std_logic_vector(g_in_b_w - 1 downto 0);
+ in_bi : in std_logic_vector(g_in_b_w - 1 downto 0);
+ result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
+ result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_complex_mult_rtl;
+
+architecture str of ip_agi027_xxxx_complex_mult_rtl is
+ function RESIZE_NUM(s : signed; w : natural) return signed is
+ begin
+ -- extend sign bit or keep LS part
+ if w > s'length then
+ return resize(s, w); -- extend sign bit
+ else
+ return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ end if;
+ end;
+
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+ constant c_sum_w : natural := c_prod_w + 1;
+
+-- CONSTANT c_re_add_sub : STRING := sel_a_b(g_conjugate_b, "ADD", "SUB");
+-- CONSTANT c_im_add_sub : STRING := sel_a_b(g_conjugate_b, "SUB", "ADD");
+
+ -- registers
+ signal reg_ar : signed(g_in_a_w - 1 downto 0);
+ signal reg_ai : signed(g_in_a_w - 1 downto 0);
+ signal reg_br : signed(g_in_b_w - 1 downto 0);
+ signal reg_bi : signed(g_in_b_w - 1 downto 0);
+ signal reg_prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ signal reg_prod_ai_bi : signed(c_prod_w - 1 downto 0);
+ signal reg_prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ signal reg_prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal reg_sum_re : signed(c_sum_w - 1 downto 0);
+ signal reg_sum_im : signed(c_sum_w - 1 downto 0);
+ signal reg_result_re : signed(g_out_p_w - 1 downto 0);
+ signal reg_result_im : signed(g_out_p_w - 1 downto 0);
+
+ -- combinatorial
+ signal nxt_ar : signed(g_in_a_w - 1 downto 0);
+ signal nxt_ai : signed(g_in_a_w - 1 downto 0);
+ signal nxt_br : signed(g_in_b_w - 1 downto 0);
+ signal nxt_bi : signed(g_in_b_w - 1 downto 0);
+ signal nxt_prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ signal nxt_prod_ai_bi : signed(c_prod_w - 1 downto 0);
+ signal nxt_prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ signal nxt_prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal nxt_sum_re : signed(c_sum_w - 1 downto 0);
+ signal nxt_sum_im : signed(c_sum_w - 1 downto 0);
+ signal nxt_result_re : signed(g_out_p_w - 1 downto 0);
+ signal nxt_result_im : signed(g_out_p_w - 1 downto 0);
+
+ -- the active signals
+ signal ar : signed(g_in_a_w - 1 downto 0);
+ signal ai : signed(g_in_a_w - 1 downto 0);
+ signal br : signed(g_in_b_w - 1 downto 0);
+ signal bi : signed(g_in_b_w - 1 downto 0);
+ signal prod_ar_br : signed(c_prod_w - 1 downto 0); -- re
+ signal prod_ai_bi : signed(c_prod_w - 1 downto 0);
+ signal prod_ai_br : signed(c_prod_w - 1 downto 0); -- im
+ signal prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal sum_re : signed(c_sum_w - 1 downto 0);
+ signal sum_im : signed(c_sum_w - 1 downto 0);
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ reg_ar <= (others => '0');
+ reg_ai <= (others => '0');
+ reg_br <= (others => '0');
+ reg_bi <= (others => '0');
+ reg_prod_ar_br <= (others => '0');
+ reg_prod_ai_bi <= (others => '0');
+ reg_prod_ai_br <= (others => '0');
+ reg_prod_ar_bi <= (others => '0');
+ reg_sum_re <= (others => '0');
+ reg_sum_im <= (others => '0');
+ reg_result_re <= (others => '0');
+ reg_result_im <= (others => '0');
+ elsif clken = '1' then
+ reg_ar <= nxt_ar; -- inputs
+ reg_ai <= nxt_ai;
+ reg_br <= nxt_br;
+ reg_bi <= nxt_bi;
+ reg_prod_ar_br <= nxt_prod_ar_br; -- products for re
+ reg_prod_ai_bi <= nxt_prod_ai_bi;
+ reg_prod_ai_br <= nxt_prod_ai_br; -- products for im
+ reg_prod_ar_bi <= nxt_prod_ar_bi;
+ reg_sum_re <= nxt_sum_re; -- sum
+ reg_sum_im <= nxt_sum_im;
+ reg_result_re <= nxt_result_re; -- result sum after optional register stage
+ reg_result_im <= nxt_result_im;
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_ar <= signed(in_ar);
+ nxt_ai <= signed(in_ai);
+ nxt_br <= signed(in_br);
+ nxt_bi <= signed(in_bi);
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ ar <= nxt_ar;
+ ai <= nxt_ai;
+ br <= nxt_br;
+ bi <= nxt_bi;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ ar <= reg_ar;
+ ai <= reg_ai;
+ br <= reg_br;
+ bi <= reg_bi;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod_ar_br <= ar * br; -- products for re
+ nxt_prod_ai_bi <= ai * bi;
+ nxt_prod_ai_br <= ai * br; -- products for im
+ nxt_prod_ar_bi <= ar * bi;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod_ar_br <= nxt_prod_ar_br;
+ prod_ai_bi <= nxt_prod_ai_bi;
+ prod_ai_br <= nxt_prod_ai_br;
+ prod_ar_bi <= nxt_prod_ar_bi;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod_ar_br <= reg_prod_ar_br;
+ prod_ai_bi <= reg_prod_ai_bi;
+ prod_ai_br <= reg_prod_ai_br;
+ prod_ar_bi <= reg_prod_ar_bi;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Sum
+ ------------------------------------------------------------------------------
+
+ -- Re
+ -- . "ADD" for a*conj(b) : ar*br + ai*bi
+ -- . "SUB" for a*b : ar*br - ai*bi
+ gen_re_add : if g_conjugate_b generate
+ nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) + prod_ai_bi;
+ end generate;
+
+ gen_re_sub : if not g_conjugate_b generate
+ nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) - prod_ai_bi;
+ end generate;
+
+ -- Im
+ -- . "ADD" for a*b : ai*br + ar*bi
+ -- . "SUB" for a*conj(b) : ai*br - ar*bi
+ gen_im_add : if not g_conjugate_b generate
+ nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) + prod_ar_bi;
+ end generate;
+
+ gen_im_sub : if g_conjugate_b generate
+ nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) - prod_ar_bi;
+ end generate;
+
+ no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ sum_re <= nxt_sum_re;
+ sum_im <= nxt_sum_im;
+ end generate;
+ gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ sum_re <= reg_sum_re;
+ sum_im <= reg_sum_im;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result_re <= RESIZE_NUM(sum_re, g_out_p_w);
+ nxt_result_im <= RESIZE_NUM(sum_im, g_out_p_w);
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result_re <= std_logic_vector(nxt_result_re);
+ result_im <= std_logic_vector(nxt_result_im);
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result_re <= std_logic_vector(reg_result_re);
+ result_im <= std_logic_vector(reg_result_im);
+ end generate;
+end architecture;
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..62325a9ea818bfd48e4d3e9f2a54e7dd0ea7a906
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_agi027_xxxx_complex_mult_rtl_canonical
+hdl_library_clause_name = ip_agi027_xxxx_complex_mult_rtl_canonical_lib
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = #Similar to the complex_mult_rtl_canonical hdllib of arria10_e1sg, e2sg, e3sge3
+synth_files =
+ ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b5c614401604866a7d2b4d6f1af781eab36080f2
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/complex_mult_rtl_canonical/ip_agi027_xxxx_complex_mult_rtl_canonical.vhd
@@ -0,0 +1,270 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author :
+-- . D.F. Brouwer
+-- Purpose:
+-- . RTL complex multiplier, canonical version (3 simple multipliers).
+-- Description:
+-- . re = ((ar+ai)*(br-bi))+(ar*bi-ai*br)
+-- im = ar*bi+ai*br
+-- Remark:
+-- . g_conjugate_b is not supported!
+-- Reference:
+-- . Copied from */technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd, authored by Daniel van der Schuur
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity ip_agi027_xxxx_complex_mult_rtl_canonical is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+-- g_conjugate_b : BOOLEAN := FALSE;
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_ar : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_ai : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_br : in std_logic_vector(g_in_b_w - 1 downto 0);
+ in_bi : in std_logic_vector(g_in_b_w - 1 downto 0);
+ result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
+ result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_complex_mult_rtl_canonical;
+
+architecture str of ip_agi027_xxxx_complex_mult_rtl_canonical is
+ function RESIZE_NUM(s : signed; w : natural) return signed is
+ begin
+ -- extend sign bit or keep LS part
+ if w > s'length then
+ return resize(s, w); -- extend sign bit
+ else
+ return signed(resize(unsigned(s), w)); -- keep LSbits (= vec[w-1:0])
+ end if;
+ end;
+
+ function largest(n, m : integer) return integer is
+ begin
+ if n > m then
+ return n;
+ else
+ return m;
+ end if;
+ end;
+
+ -----------------------------------------------------------------------------
+ -- Multiply / add output signals
+ -- . re = ((ar+ai)*(br-bi))+(ar*bi-ai*br)
+ -- im = ar*bi+ai*br
+ -----------------------------------------------------------------------------
+ constant c_sum_ar_ai_w : natural := g_in_a_w + 1; -- sum_ar_ai
+ constant c_sum_br_bi_w : natural := g_in_b_w + 1; -- sum_br_bi
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w; -- prod_ar_bi, prod_ai_br
+ constant c_sum_prod_w : natural := c_prod_w + 1; -- sum_prod_ar_bi_prod_ai_br
+ constant c_prod_sum_w : natural := c_sum_ar_ai_w + c_sum_br_bi_w; -- prod_sum_ar_ai_sum_br_bi
+ constant c_sum_im_w : natural := c_prod_w + 1; -- sum_im
+ constant c_sum_re_w : natural := largest(c_sum_prod_w, c_prod_sum_w) + 1; -- sum_re
+
+ signal sum_ar_ai : signed(c_sum_ar_ai_w - 1 downto 0); -- ar+ai : used in re
+ signal sum_br_bi : signed(c_sum_br_bi_w - 1 downto 0); -- br-bi : used in re
+ signal sum_prod_ar_bi_prod_ai_br : signed(c_sum_prod_w - 1 downto 0); -- ar*bi-ai*br : used in re
+ signal sum_im : signed(c_sum_im_w - 1 downto 0); -- ar*bi+ai*br : im
+ signal sum_re : signed(c_sum_re_w - 1 downto 0); -- ((ar+ai)*(br-bi))+(ar*bi-ai*br) : re
+
+ signal prod_ar_bi : signed(c_prod_w - 1 downto 0); -- ar*bi : used in re and im
+ signal prod_ai_br : signed(c_prod_w - 1 downto 0); -- ai*br : used in re and im
+ signal prod_sum_ar_ai_sum_br_bi : signed(c_prod_sum_w - 1 downto 0); -- (ar+ai)*(br-bi) : used in re
+
+ -----------------------------------------------------------------------------
+ -- register signals
+ -----------------------------------------------------------------------------
+ signal ar : signed(g_in_a_w - 1 downto 0);
+ signal ai : signed(g_in_a_w - 1 downto 0);
+ signal br : signed(g_in_b_w - 1 downto 0);
+ signal bi : signed(g_in_b_w - 1 downto 0);
+
+ signal nxt_ar : signed(g_in_a_w - 1 downto 0);
+ signal nxt_ai : signed(g_in_a_w - 1 downto 0);
+ signal nxt_br : signed(g_in_b_w - 1 downto 0);
+ signal nxt_bi : signed(g_in_b_w - 1 downto 0);
+
+ signal reg_ar : signed(g_in_a_w - 1 downto 0);
+ signal reg_ai : signed(g_in_a_w - 1 downto 0);
+ signal reg_br : signed(g_in_b_w - 1 downto 0);
+ signal reg_bi : signed(g_in_b_w - 1 downto 0);
+
+ signal nxt_sum_ar_ai : signed(c_sum_ar_ai_w - 1 downto 0);
+ signal nxt_sum_br_bi : signed(c_sum_br_bi_w - 1 downto 0);
+ signal nxt_sum_prod_ar_bi_prod_ai_br : signed(c_sum_prod_w - 1 downto 0);
+ signal nxt_sum_im : signed(c_sum_im_w - 1 downto 0);
+ signal nxt_sum_re : signed(c_sum_re_w - 1 downto 0);
+
+ signal nxt_prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal nxt_prod_ai_br : signed(c_prod_w - 1 downto 0);
+ signal nxt_prod_sum_ar_ai_sum_br_bi : signed(c_prod_sum_w - 1 downto 0);
+
+ signal reg_sum_ar_ai : signed(c_sum_ar_ai_w - 1 downto 0);
+ signal reg_sum_br_bi : signed(c_sum_br_bi_w - 1 downto 0);
+ signal reg_sum_prod_ar_bi_prod_ai_br : signed(c_sum_prod_w - 1 downto 0);
+ signal reg_sum_im : signed(c_sum_im_w - 1 downto 0);
+ signal reg_sum_re : signed(c_sum_re_w - 1 downto 0);
+
+ signal reg_prod_ar_bi : signed(c_prod_w - 1 downto 0);
+ signal reg_prod_ai_br : signed(c_prod_w - 1 downto 0);
+ signal reg_prod_sum_ar_ai_sum_br_bi : signed(c_prod_sum_w - 1 downto 0);
+
+ signal nxt_result_re : signed(g_out_p_w - 1 downto 0);
+ signal nxt_result_im : signed(g_out_p_w - 1 downto 0);
+
+ signal reg_result_re : signed(g_out_p_w - 1 downto 0);
+ signal reg_result_im : signed(g_out_p_w - 1 downto 0);
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ reg_ar <= (others => '0');
+ reg_ai <= (others => '0');
+ reg_br <= (others => '0');
+ reg_bi <= (others => '0');
+
+ reg_sum_ar_ai <= (others => '0');
+ reg_sum_br_bi <= (others => '0');
+ reg_sum_prod_ar_bi_prod_ai_br <= (others => '0');
+ reg_sum_im <= (others => '0');
+ reg_sum_re <= (others => '0');
+
+ reg_prod_ar_bi <= (others => '0');
+ reg_prod_ai_br <= (others => '0');
+ reg_prod_sum_ar_ai_sum_br_bi <= (others => '0');
+ elsif clken = '1' then
+ reg_ar <= nxt_ar;
+ reg_ai <= nxt_ai;
+ reg_br <= nxt_br;
+ reg_bi <= nxt_bi;
+
+ reg_sum_ar_ai <= nxt_sum_ar_ai;
+ reg_sum_br_bi <= nxt_sum_br_bi;
+ reg_sum_prod_ar_bi_prod_ai_br <= nxt_sum_prod_ar_bi_prod_ai_br;
+ reg_sum_im <= nxt_sum_im;
+ reg_sum_re <= nxt_sum_re;
+
+ reg_prod_ar_bi <= nxt_prod_ar_bi;
+ reg_prod_ai_br <= nxt_prod_ai_br;
+ reg_prod_sum_ar_ai_sum_br_bi <= nxt_prod_sum_ar_ai_sum_br_bi;
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+ nxt_ar <= signed(in_ar);
+ nxt_ai <= signed(in_ai);
+ nxt_br <= signed(in_br);
+ nxt_bi <= signed(in_bi);
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ ar <= nxt_ar;
+ ai <= nxt_ai;
+ br <= nxt_br;
+ bi <= nxt_bi;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ ar <= reg_ar;
+ ai <= reg_ai;
+ br <= reg_br;
+ bi <= reg_bi;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Sums
+ ------------------------------------------------------------------------------
+ nxt_sum_ar_ai <= RESIZE_NUM(ar, c_sum_ar_ai_w) + ai;
+ nxt_sum_br_bi <= RESIZE_NUM(br, c_sum_br_bi_w) + bi;
+ nxt_sum_prod_ar_bi_prod_ai_br <= RESIZE_NUM(prod_ar_bi, c_prod_sum_w) + prod_ai_br;
+ nxt_sum_re <= RESIZE_NUM(prod_sum_ar_ai_sum_br_bi, c_prod_sum_w), sum_prod_ar_bi_prod_ai_br;
+ nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_im_w) + prod_ar_bi;
+
+ no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ sum_ar_ai <= nxt_sum_ar_ai;
+ sum_br_bi <= nxt_sum_br_bi;
+ sum_prod_ar_bi_prod_ai_br <= nxt_sum_prod_ar_bi_prod_ai_br;
+ sum_re <= nxt_sum_re;
+ sum_im <= nxt_sum_im;
+ end generate;
+ gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ sum_ar_ai <= reg_sum_ar_ai;
+ sum_br_bi <= reg_sum_br_bi;
+ sum_prod_ar_bi_prod_ai_br <= reg_sum_prod_ar_bi_prod_ai_br;
+ sum_re <= reg_sum_re;
+ sum_im <= reg_sum_im;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+ nxt_prod_ar_bi <= ar * bi;
+ nxt_prod_ai_br <= ai * br;
+ nxt_prod_sum_ar_ai_sum_br_bi <= sum_ar_ai * sum_br_bi;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod_ar_bi <= nxt_prod_ar_bi;
+ prod_ai_br <= nxt_prod_ai_br;
+ prod_sum_ar_ai_sum_br_bi <= nxt_prod_sum_ar_ai_sum_br_bi;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod_ar_bi <= reg_prod_ar_bi;
+ prod_ai_br <= reg_prod_ai_br;
+ prod_sum_ar_ai_sum_br_bi <= reg_prod_sum_ar_ai_sum_br_bi;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result_re <= RESIZE_NUM(sum_re, g_out_p_w);
+ nxt_result_im <= RESIZE_NUM(sum_im, g_out_p_w);
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result_re <= std_logic_vector(nxt_result_re);
+ result_im <= std_logic_vector(nxt_result_im);
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result_re <= std_logic_vector(reg_result_re);
+ result_im <= std_logic_vector(reg_result_im);
+ end generate;
+end architecture;
diff --git a/libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c3fee94e62efa14bd0d9dbda4e779bef03ec1338
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = ip_agi027_xxxx_mult
+hdl_library_clause_name = ip_agi027_xxxx_mult_lib
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = #Similar to the mult hdllib of arria10_e1sg, e2sg, e3sge3
+
+synth_files =
+ ip_agi027_xxxx_mult.vhd
+ ip_agi027_xxxx_mult_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip
new file mode 100644
index 0000000000000000000000000000000000000000..9572d6da95176a10e3750a013786484330bfd6ba
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_lpm_mult.ip
@@ -0,0 +1,523 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_lpm_mult</ipxact:library>
+ <ipxact:name>lpm_mult_0</ipxact:name>
+ <ipxact:version>19.2.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>dataa</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>result</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clken</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clken</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clken</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>lpm_mult</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>dataa</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>result</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>35</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clken</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_lpm_mult</ipxact:library>
+ <ipxact:name>lpm_mult</ipxact:name>
+ <ipxact:version>19.2.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device Family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_A" type="int">
+ <ipxact:name>GUI_WIDTH_A</ipxact:name>
+ <ipxact:displayName>Dataa width</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_B" type="int">
+ <ipxact:name>GUI_WIDTH_B</ipxact:name>
+ <ipxact:displayName>Datab width</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_WIDTH_P" type="int">
+ <ipxact:name>GUI_WIDTH_P</ipxact:name>
+ <ipxact:displayName>Value</ipxact:displayName>
+ <ipxact:value>36</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CONSTANT_B" type="int">
+ <ipxact:name>GUI_CONSTANT_B</ipxact:name>
+ <ipxact:displayName>Value</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_LATENCY" type="int">
+ <ipxact:name>GUI_LATENCY</ipxact:name>
+ <ipxact:displayName>Latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLEAR_TYPE" type="string">
+ <ipxact:name>GUI_CLEAR_TYPE</ipxact:name>
+ <ipxact:displayName>Clear Signal Type</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_CLKEN" type="bit">
+ <ipxact:name>GUI_CLKEN</ipxact:name>
+ <ipxact:displayName>Create a 'clken' clock enable clock</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_USE_MULT" type="int">
+ <ipxact:name>GUI_USE_MULT</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_AUTO_SIZE_RESULT" type="int">
+ <ipxact:name>GUI_AUTO_SIZE_RESULT</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_B_IS_CONSTANT" type="int">
+ <ipxact:name>GUI_B_IS_CONSTANT</ipxact:name>
+ <ipxact:displayName>Does the 'datab' input bus have a constant value?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_SIGNED_MULT" type="int">
+ <ipxact:name>GUI_SIGNED_MULT</ipxact:name>
+ <ipxact:displayName>Which type of multiplication do you want?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_IMPLEMENTATION" type="int">
+ <ipxact:name>GUI_IMPLEMENTATION</ipxact:name>
+ <ipxact:displayName>Which multiplier implementation should be used?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_PIPELINE" type="int">
+ <ipxact:name>GUI_PIPELINE</ipxact:name>
+ <ipxact:displayName>Pipeline</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="GUI_OPTIMIZE" type="int">
+ <ipxact:name>GUI_OPTIMIZE</ipxact:name>
+ <ipxact:displayName>Type</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element lpm_mult_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="clken" altera:internal="lpm_mult_0.clken" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="clken" altera:internal="clken"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock" altera:internal="lpm_mult_0.clock" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock" altera:internal="clock"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa" altera:internal="lpm_mult_0.dataa" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa" altera:internal="dataa"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab" altera:internal="lpm_mult_0.datab" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab" altera:internal="datab"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result" altera:internal="lpm_mult_0.result" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result" altera:internal="result"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..57521504991262d3080b830b266a0c50db9ec394
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult.vhd
@@ -0,0 +1,122 @@
+-- --------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper / Instantiate MULTiplier IP with generics
+-- Reference:
+-- Copied from */technology/ip_arria10/mult/ip_arria10_mult.vhd and add component declaration lpm_mult from
+-- generated/lpm_mult_1920/sim/ip_agi027_xxxx_lpm_mult_lpm_mult_1920_sphm57q.vhd
+-- Remark:
+-- Directly instantiate LPM component.
+-- The Agilex 7 (agi027_xxxx) supports the lpm library, so the copied file can be reused.
+-- This is checked by making the IP files on the basis of the generic and port of the entity, and also the generic and port map.
+-- The IP file will also remain present in the folder, so that the settings can be reproduced later.
+
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library lpm;
+use lpm.lpm_components.all;
+
+ entity ip_agi027_xxxx_mult is
+ generic (
+ g_in_a_w : positive := 18; -- Width of the data A port
+ g_in_b_w : positive := 18; -- Width of the data B port
+ g_out_p_w : positive := 36; -- Width of the result port
+-- g_out_s_w : POSITIVE := 1; -- Width of the sum port (not used in current designs)
+ g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1; -- >= 0
+ g_representation : string := "SIGNED" -- or "UNSIGNED"
+ );
+ port (
+ clk : in std_logic;
+ clken : in std_logic := '1';
+-- aclr : IN STD_LOGIC := '0'; (not used in current designs)
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+-- sum : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_s_w-1 DOWNTO 0) := (OTHERS => '0'); (not used in current designs)
+ out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end ip_agi027_xxxx_mult;
+
+architecture str of ip_agi027_xxxx_mult is
+ constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
+
+ -- When g_out_p_w < g_in_a_w+g_in_b_w then the LPM_MULT truncates the LSbits of the product. Therefore
+ -- define c_prod_w to be able to let common_mult truncate the LSBits of the product.
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+
+ component lpm_mult
+ generic (
+ lpm_hint : string;
+ lpm_pipeline : natural;
+ lpm_representation : string;
+ lpm_type : string;
+ lpm_widtha : natural;
+ lpm_widthb : natural;
+ -- lpm_widths : natural;
+ lpm_widthp : natural
+ );
+ port (
+ dataa : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ datab : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ -- sum : in STD_LOGIC_VECTOR((g_nof_mult*g_in_s_w-1 DOWNTO 0) := (OTHERS => '0'); (not used in current designs)
+ -- aclr : in STD_LOGIC; (not used in current designs)
+ clock : in std_logic;
+ clken : in std_logic;
+ result : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end component;
+
+ signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
+begin
+ gen_mult : for I in 0 to g_nof_mult - 1 generate
+ m : lpm_mult
+ generic map (
+ lpm_hint => "MAXIMIZE_SPEED=5", -- default "UNUSED"
+ lpm_pipeline => c_pipeline,
+ lpm_representation => g_representation,
+ lpm_type => "LPM_MULT",
+ lpm_widtha => g_in_a_w,
+ lpm_widthb => g_in_b_w,
+-- lpm_widths => g_in_s_w, (Partial sum input with not used in current designs)
+ lpm_widthp => c_prod_w
+ )
+ port map (
+ dataa => in_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w),
+ datab => in_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w),
+ -- sum => sum((I+1)*g_in_s_w-1 DOWNTO I*g_in_s_w), -- partial sum input is not used in current designs
+ -- aclr => aclr, -- async clear input is not used in current designs
+ clock => clk,
+ clken => clken,
+ result => prod((I + 1) * c_prod_w - 1 downto I * c_prod_w)
+ );
+
+ out_p <= prod;
+---- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
+-- out_p((I+1)*g_out_p_w-1 DOWNTO I*g_out_p_w) <= RESIZE_SVEC(prod((I+1)*c_prod_w-1 DOWNTO I*c_prod_w), g_out_p_w) WHEN g_representation="SIGNED" ELSE
+-- RESIZE_UVEC(prod((I+1)*c_prod_w-1 DOWNTO I*c_prod_w), g_out_p_w);
+ end generate;
+
+end str;
diff --git a/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c9a49693fffeb60693a373a586c834e5179b99b7
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult/ip_agi027_xxxx_mult_rtl.vhd
@@ -0,0 +1,144 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Reference:
+-- Copied from */technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+-- no support for rounding in this RTL architecture
+ entity ip_agi027_xxxx_mult_rtl is
+ generic (
+ g_in_a_w : positive := 18;
+ g_in_b_w : positive := 18;
+ g_out_p_w : positive := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+ g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1; -- >= 0
+ g_representation : string := "SIGNED" -- or "UNSIGNED"
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end ip_agi027_xxxx_mult_rtl;
+
+architecture str of ip_agi027_xxxx_mult_rtl is
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+
+ -- registers
+ signal reg_a : std_logic_vector(in_a'range);
+ signal reg_b : std_logic_vector(in_b'range);
+ signal reg_prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
+ signal reg_result : std_logic_vector(out_p'range);
+
+ -- combinatorial
+ signal nxt_a : std_logic_vector(in_a'range);
+ signal nxt_b : std_logic_vector(in_b'range);
+ signal nxt_prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
+ signal nxt_result : std_logic_vector(out_p'range);
+
+ -- the active signals
+ signal inp_a : std_logic_vector(in_a'range);
+ signal inp_b : std_logic_vector(in_b'range);
+ signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0); -- stage dependent on g_pipeline_product being 0 or 1
+ signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rst = '1' then
+ reg_a <= (others => '0');
+ reg_b <= (others => '0');
+ reg_prod <= (others => '0');
+ reg_result <= (others => '0');
+ elsif rising_edge(clk) then
+ if clken = '1' then
+ reg_a <= nxt_a;
+ reg_b <= nxt_b;
+ reg_prod <= nxt_prod;
+ reg_result <= nxt_result;
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a <= in_a;
+ nxt_b <= in_b;
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ inp_a <= nxt_a;
+ inp_b <= nxt_b;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ inp_a <= reg_a;
+ inp_b <= reg_b;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ gen_mult : for I in 0 to g_nof_mult - 1 generate
+ nxt_prod((I + 1) * c_prod_w - 1 downto I * c_prod_w) <=
+ std_logic_vector( signed(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * signed(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w))) when g_representation = "SIGNED" else
+ std_logic_vector(unsigned(inp_a((I + 1) * g_in_a_w - 1 downto I * g_in_a_w)) * unsigned(inp_b((I + 1) * g_in_b_w - 1 downto I * g_in_b_w)));
+ end generate;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod <= nxt_prod;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod <= reg_prod;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Results
+ ------------------------------------------------------------------------------
+ nxt_result <= prod;
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result <= nxt_result;
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result <= reg_result;
+ end generate;
+
+out_p <= result;
+end str;
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..10de323cf0dba3baf8f4687065085848bbb2f75c
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add2/hdllib.cfg
@@ -0,0 +1,17 @@
+hdl_lib_name = ip_agi027_xxxx_mult_add2
+hdl_library_clause_name = ip_agi027_xxxx_mult_add2_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+ ip_agi027_xxxx_mult_add2_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd b/libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6a3bcf3cab6b2d1f2e20d17f2d46bcd517adc46d
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add2/ip_agi027_xxxx_mult_add2_rtl.vhd
@@ -0,0 +1,201 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Reference:
+-- Copied from */technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2.vhd,
+-- that is based on ip_stratixiv_mult_add2_rtl
+
+library IEEE, common_lib;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use common_lib.common_pkg.all;
+
+------------------------------------------------------------------------------
+-- Function:
+-- . res = a0 * b0 + a1 * b1
+-- . res = a0 * b0 - a1 * b1
+------------------------------------------------------------------------------
+
+entity ip_agi027_xxxx_mult_add2_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
+ g_add_sub : string := "ADD"; -- or "SUB"
+ g_nof_mult : integer := 2; -- fixed
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ res : out std_logic_vector(g_res_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_mult_add2_rtl;
+
+architecture str of ip_agi027_xxxx_mult_add2_rtl is
+ -- Extra output pipelining is only needed when g_pipeline_output > 1
+ constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
+
+ constant c_prod_w : natural := g_in_a_w + g_in_b_w;
+ constant c_sum_w : natural := c_prod_w + 1;
+
+ -- registers
+ signal reg_a0 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b0 : signed(g_in_b_w - 1 downto 0);
+ signal reg_a1 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b1 : signed(g_in_b_w - 1 downto 0);
+ signal reg_prod0 : signed(c_prod_w - 1 downto 0);
+ signal reg_prod1 : signed(c_prod_w - 1 downto 0);
+ signal reg_sum : signed(c_sum_w - 1 downto 0);
+ signal reg_result : signed(g_res_w - 1 downto 0);
+
+ -- combinatorial
+ signal nxt_a0 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b0 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_a1 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b1 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_prod0 : signed(c_prod_w - 1 downto 0);
+ signal nxt_prod1 : signed(c_prod_w - 1 downto 0);
+ signal nxt_sum : signed(c_sum_w - 1 downto 0);
+ signal nxt_result : signed(g_res_w - 1 downto 0);
+
+ -- the active signals
+ signal a0 : signed(g_in_a_w - 1 downto 0);
+ signal b0 : signed(g_in_b_w - 1 downto 0);
+ signal a1 : signed(g_in_a_w - 1 downto 0);
+ signal b1 : signed(g_in_b_w - 1 downto 0);
+ signal prod0 : signed(c_prod_w - 1 downto 0);
+ signal prod1 : signed(c_prod_w - 1 downto 0);
+ signal sum : signed(c_sum_w - 1 downto 0);
+ signal result : signed(g_res_w - 1 downto 0);
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ reg_a0 <= (others => '0');
+ reg_b0 <= (others => '0');
+ reg_a1 <= (others => '0');
+ reg_b1 <= (others => '0');
+ reg_prod0 <= (others => '0');
+ reg_prod1 <= (others => '0');
+ reg_sum <= (others => '0');
+ reg_result <= (others => '0');
+ elsif clken = '1' then
+ reg_a0 <= nxt_a0; -- inputs
+ reg_b0 <= nxt_b0;
+ reg_a1 <= nxt_a1;
+ reg_b1 <= nxt_b1;
+ reg_prod0 <= nxt_prod0; -- products
+ reg_prod1 <= nxt_prod1;
+ reg_sum <= nxt_sum; -- sum
+ reg_result <= nxt_result; -- result sum after optional rounding
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a0 <= signed(in_a( g_in_a_w - 1 downto 0));
+ nxt_b0 <= signed(in_b( g_in_b_w - 1 downto 0));
+ nxt_a1 <= signed(in_a(2 * g_in_a_w - 1 downto g_in_a_w));
+ nxt_b1 <= signed(in_b(2 * g_in_b_w - 1 downto g_in_b_w));
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ a0 <= nxt_a0;
+ b0 <= nxt_b0;
+ a1 <= nxt_a1;
+ b1 <= nxt_b1;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ a0 <= reg_a0;
+ b0 <= reg_b0;
+ a1 <= reg_a1;
+ b1 <= reg_b1;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod0 <= a0 * b0;
+ nxt_prod1 <= a1 * b1;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod0 <= nxt_prod0;
+ prod1 <= nxt_prod1;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod0 <= reg_prod0;
+ prod1 <= reg_prod1;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Sum
+ ------------------------------------------------------------------------------
+ gen_add : if g_add_sub = "ADD" generate
+ nxt_sum <= RESIZE_NUM(prod0, c_sum_w) + prod1;
+ end generate;
+
+ gen_sub : if g_add_sub = "SUB" generate
+ nxt_sum <= RESIZE_NUM(prod0, c_sum_w) - prod1;
+ end generate;
+
+ no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ sum <= nxt_sum;
+ end generate;
+ gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ sum <= reg_sum;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result <= RESIZE_NUM(sum, g_res_w);
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result <= nxt_result;
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result <= reg_result;
+ end generate;
+
+ res <= std_logic_vector(result);
+end str;
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl b/libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..111fd4da2b3c2c649ae7091d1381cf9beb99b82c
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add4/compile_ip.tcl
@@ -0,0 +1,38 @@
+# ------------------------------------------------------------------------------
+#
+# Copyright (C) 2023
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# ------------------------------------------------------------------------------
+# Author: D.F. Brouwer
+# Description:
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/ ;# Assume library work already exist
+
+
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_mult_add4/sim"
+
+vmap ip_agi027_xxxx_mult_add4 ./work/
+vmap altera_mult_add_1920 ./work/
+
+
+ vcom "$IP_DIR/../altera_mult_add_1920/sim/ip_agi027_xxxx_mult_add4_altera_mult_add_1920_ljq3huq.vhd" -work altera_mult_add_1920
+ vcom "$IP_DIR/ip_agi027_xxxx_mult_add4.vhd" -work ip_agi027_xxxx_mult_add4
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e4bc0f9bac292993339fceabc984dbc5ea265ec3
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add4/hdllib.cfg
@@ -0,0 +1,21 @@
+hdl_lib_name = ip_agi027_xxxx_mult_add4
+hdl_library_clause_name = ip_agi027_xxxx_mult_add4_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+ ip_agi027_xxxx_mult_add4_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_xxxx_mult_add4.ip
+
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip b/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip
new file mode 100644
index 0000000000000000000000000000000000000000..8b6eb98f7206626a9a2954a385ec3beee08e5f97
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4.ip
@@ -0,0 +1,1508 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_mult_add4</ipxact:library>
+ <ipxact:name>mult_add_0</ipxact:name>
+ <ipxact:version>19.2.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>result</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>result</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>result</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>output</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_0</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_1</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_1</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_1</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_2</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_2</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_2</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>dataa_3</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>dataa_3</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>dataa_3</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_0</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_1</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_1</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_1</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_2</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_2</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_2</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>datab_3</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>datab_3</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>datab_3</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clock0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="clock" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="clock" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>clock0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>ena0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>ena0</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>ena0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>aclr0</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="reset" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>aclr0</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>clock0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
+ <ipxact:name>ui.blockdiagram.direction</ipxact:name>
+ <ipxact:value>input</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>altera_mult_add</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>result</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>37</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_1</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_2</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>dataa_3</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_1</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_2</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>datab_3</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>17</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>clock0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>ena0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>aclr0</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_mult_add4</ipxact:library>
+ <ipxact:name>altera_mult_add</ipxact:name>
+ <ipxact:version>19.2.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="number_of_multipliers" type="int">
+ <ipxact:name>number_of_multipliers</ipxact:name>
+ <ipxact:displayName>What is the number of multipliers?</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_a" type="int">
+ <ipxact:name>width_a</ipxact:name>
+ <ipxact:displayName>How wide should the A input buses be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_b" type="int">
+ <ipxact:name>width_b</ipxact:name>
+ <ipxact:displayName>How wide should the B input buses be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_result" type="int">
+ <ipxact:name>width_result</ipxact:name>
+ <ipxact:displayName>How wide should the 'result' output bus be?</ipxact:displayName>
+ <ipxact:value>38</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_4th_asynchronous_clear" type="bit">
+ <ipxact:name>gui_4th_asynchronous_clear</ipxact:name>
+ <ipxact:displayName>Create a 4th asynchronous clear input option</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_associated_clock_enable" type="bit">
+ <ipxact:name>gui_associated_clock_enable</ipxact:name>
+ <ipxact:displayName>Create an associated clock enable for each clock</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_output_register" type="bit">
+ <ipxact:name>gui_output_register</ipxact:name>
+ <ipxact:displayName>Register output of the adder unit</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_output_register_clock" type="string">
+ <ipxact:name>gui_output_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_output_register_aclr" type="string">
+ <ipxact:name>gui_output_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_output_register_sclr" type="string">
+ <ipxact:name>gui_output_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier1_direction" type="string">
+ <ipxact:name>gui_multiplier1_direction</ipxact:name>
+ <ipxact:displayName>What operation should be perfomed on outputs of the first pair of multipliers</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_register1" type="bit">
+ <ipxact:name>gui_addnsub_multiplier_register1</ipxact:name>
+ <ipxact:displayName>Register 'addnsub1' input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_register1_clock" type="string">
+ <ipxact:name>gui_addnsub_multiplier_register1_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_aclr1" type="string">
+ <ipxact:name>gui_addnsub_multiplier_aclr1</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_sclr1" type="string">
+ <ipxact:name>gui_addnsub_multiplier_sclr1</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier3_direction" type="string">
+ <ipxact:name>gui_multiplier3_direction</ipxact:name>
+ <ipxact:displayName>What operation should be perfomed on outputs of the second pair of multipliers</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_register3" type="bit">
+ <ipxact:name>gui_addnsub_multiplier_register3</ipxact:name>
+ <ipxact:displayName>Register 'addnsub3' input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_register3_clock" type="string">
+ <ipxact:name>gui_addnsub_multiplier_register3_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_aclr3" type="string">
+ <ipxact:name>gui_addnsub_multiplier_aclr3</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_addnsub_multiplier_sclr3" type="string">
+ <ipxact:name>gui_addnsub_multiplier_sclr3</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_use_subnadd" type="bit">
+ <ipxact:name>gui_use_subnadd</ipxact:name>
+ <ipxact:displayName>Enable 'use_subnadd'</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_representation_a" type="string">
+ <ipxact:name>gui_representation_a</ipxact:name>
+ <ipxact:displayName>What is the representation format for Multipliers A inputs?</ipxact:displayName>
+ <ipxact:value>SIGNED</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signa" type="bit">
+ <ipxact:name>gui_register_signa</ipxact:name>
+ <ipxact:displayName>Register 'signa' input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signa_clock" type="string">
+ <ipxact:name>gui_register_signa_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signa_aclr" type="string">
+ <ipxact:name>gui_register_signa_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signa_sclr" type="string">
+ <ipxact:name>gui_register_signa_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_representation_b" type="string">
+ <ipxact:name>gui_representation_b</ipxact:name>
+ <ipxact:displayName>What is the representation format for Multipliers B inputs?</ipxact:displayName>
+ <ipxact:value>SIGNED</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signb" type="bit">
+ <ipxact:name>gui_register_signb</ipxact:name>
+ <ipxact:displayName>Register 'signb' input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signb_clock" type="string">
+ <ipxact:name>gui_register_signb_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signb_aclr" type="string">
+ <ipxact:name>gui_register_signb_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_register_signb_sclr" type="string">
+ <ipxact:name>gui_register_signb_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_a" type="bit">
+ <ipxact:name>gui_input_register_a</ipxact:name>
+ <ipxact:displayName>Register input A of the multiplier</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_a_clock" type="string">
+ <ipxact:name>gui_input_register_a_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_a_aclr" type="string">
+ <ipxact:name>gui_input_register_a_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_a_sclr" type="string">
+ <ipxact:name>gui_input_register_a_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_b" type="bit">
+ <ipxact:name>gui_input_register_b</ipxact:name>
+ <ipxact:displayName>Register input B of the multiplier</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_b_clock" type="string">
+ <ipxact:name>gui_input_register_b_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_b_aclr" type="string">
+ <ipxact:name>gui_input_register_b_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_register_b_sclr" type="string">
+ <ipxact:name>gui_input_register_b_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_a_input" type="string">
+ <ipxact:name>gui_multiplier_a_input</ipxact:name>
+ <ipxact:displayName>What is the input A of the multiplier connected to?</ipxact:displayName>
+ <ipxact:value>Multiplier input</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_scanouta_register" type="bit">
+ <ipxact:name>gui_scanouta_register</ipxact:name>
+ <ipxact:displayName>Register output of the scan chain</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_scanouta_register_clock" type="string">
+ <ipxact:name>gui_scanouta_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_scanouta_register_aclr" type="string">
+ <ipxact:name>gui_scanouta_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_scanouta_register_sclr" type="string">
+ <ipxact:name>gui_scanouta_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_b_input" type="string">
+ <ipxact:name>gui_multiplier_b_input</ipxact:name>
+ <ipxact:displayName>What is the input B of the multiplier connected to?</ipxact:displayName>
+ <ipxact:value>Multiplier input</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_register" type="bit">
+ <ipxact:name>gui_multiplier_register</ipxact:name>
+ <ipxact:displayName>Register output of the multiplier</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_register_clock" type="string">
+ <ipxact:name>gui_multiplier_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_register_aclr" type="string">
+ <ipxact:name>gui_multiplier_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_multiplier_register_sclr" type="string">
+ <ipxact:name>gui_multiplier_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="preadder_mode" type="string">
+ <ipxact:name>preadder_mode</ipxact:name>
+ <ipxact:displayName>Select preadder mode</ipxact:displayName>
+ <ipxact:value>SIMPLE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_preadder_direction" type="string">
+ <ipxact:name>gui_preadder_direction</ipxact:name>
+ <ipxact:displayName>Select preadder direction</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_c" type="int">
+ <ipxact:name>width_c</ipxact:name>
+ <ipxact:displayName>How wide should the C input buses be?</ipxact:displayName>
+ <ipxact:value>16</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_datac_input_register" type="bit">
+ <ipxact:name>gui_datac_input_register</ipxact:name>
+ <ipxact:displayName>Register datac input</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_datac_input_register_clock" type="string">
+ <ipxact:name>gui_datac_input_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_datac_input_register_aclr" type="string">
+ <ipxact:name>gui_datac_input_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_datac_input_register_sclr" type="string">
+ <ipxact:name>gui_datac_input_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="width_coef" type="int">
+ <ipxact:name>width_coef</ipxact:name>
+ <ipxact:displayName>How wide should the coef width be?</ipxact:displayName>
+ <ipxact:value>18</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_coef_register" type="bit">
+ <ipxact:name>gui_coef_register</ipxact:name>
+ <ipxact:displayName>Register the coefsel inputs</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_coef_register_clock" type="string">
+ <ipxact:name>gui_coef_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_coef_register_aclr" type="string">
+ <ipxact:name>gui_coef_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_coef_register_sclr" type="string">
+ <ipxact:name>gui_coef_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_0" type="int">
+ <ipxact:name>coef0_0</ipxact:name>
+ <ipxact:displayName>Coef0_0</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_1" type="int">
+ <ipxact:name>coef0_1</ipxact:name>
+ <ipxact:displayName>Coef0_1</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_2" type="int">
+ <ipxact:name>coef0_2</ipxact:name>
+ <ipxact:displayName>Coef0_2</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_3" type="int">
+ <ipxact:name>coef0_3</ipxact:name>
+ <ipxact:displayName>Coef0_3</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_4" type="int">
+ <ipxact:name>coef0_4</ipxact:name>
+ <ipxact:displayName>Coef0_4</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_5" type="int">
+ <ipxact:name>coef0_5</ipxact:name>
+ <ipxact:displayName>Coef0_5</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_6" type="int">
+ <ipxact:name>coef0_6</ipxact:name>
+ <ipxact:displayName>Coef0_6</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef0_7" type="int">
+ <ipxact:name>coef0_7</ipxact:name>
+ <ipxact:displayName>Coef0_7</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_0" type="int">
+ <ipxact:name>coef1_0</ipxact:name>
+ <ipxact:displayName>Coef1_0</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_1" type="int">
+ <ipxact:name>coef1_1</ipxact:name>
+ <ipxact:displayName>Coef1_1</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_2" type="int">
+ <ipxact:name>coef1_2</ipxact:name>
+ <ipxact:displayName>Coef1_2</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_3" type="int">
+ <ipxact:name>coef1_3</ipxact:name>
+ <ipxact:displayName>Coef1_3</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_4" type="int">
+ <ipxact:name>coef1_4</ipxact:name>
+ <ipxact:displayName>Coef1_4</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_5" type="int">
+ <ipxact:name>coef1_5</ipxact:name>
+ <ipxact:displayName>Coef1_5</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_6" type="int">
+ <ipxact:name>coef1_6</ipxact:name>
+ <ipxact:displayName>Coef1_6</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef1_7" type="int">
+ <ipxact:name>coef1_7</ipxact:name>
+ <ipxact:displayName>Coef1_7</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_0" type="int">
+ <ipxact:name>coef2_0</ipxact:name>
+ <ipxact:displayName>Coef2_0</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_1" type="int">
+ <ipxact:name>coef2_1</ipxact:name>
+ <ipxact:displayName>Coef2_1</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_2" type="int">
+ <ipxact:name>coef2_2</ipxact:name>
+ <ipxact:displayName>Coef2_2</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_3" type="int">
+ <ipxact:name>coef2_3</ipxact:name>
+ <ipxact:displayName>Coef2_3</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_4" type="int">
+ <ipxact:name>coef2_4</ipxact:name>
+ <ipxact:displayName>Coef2_4</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_5" type="int">
+ <ipxact:name>coef2_5</ipxact:name>
+ <ipxact:displayName>Coef2_5</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_6" type="int">
+ <ipxact:name>coef2_6</ipxact:name>
+ <ipxact:displayName>Coef2_6</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef2_7" type="int">
+ <ipxact:name>coef2_7</ipxact:name>
+ <ipxact:displayName>Coef2_7</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_0" type="int">
+ <ipxact:name>coef3_0</ipxact:name>
+ <ipxact:displayName>Coef3_0</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_1" type="int">
+ <ipxact:name>coef3_1</ipxact:name>
+ <ipxact:displayName>Coef3_1</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_2" type="int">
+ <ipxact:name>coef3_2</ipxact:name>
+ <ipxact:displayName>Coef3_2</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_3" type="int">
+ <ipxact:name>coef3_3</ipxact:name>
+ <ipxact:displayName>Coef3_3</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_4" type="int">
+ <ipxact:name>coef3_4</ipxact:name>
+ <ipxact:displayName>Coef3_4</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_5" type="int">
+ <ipxact:name>coef3_5</ipxact:name>
+ <ipxact:displayName>Coef3_5</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_6" type="int">
+ <ipxact:name>coef3_6</ipxact:name>
+ <ipxact:displayName>Coef3_6</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="coef3_7" type="int">
+ <ipxact:name>coef3_7</ipxact:name>
+ <ipxact:displayName>Coef3_7</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="accumulator" type="string">
+ <ipxact:name>accumulator</ipxact:name>
+ <ipxact:displayName>Enable accumulator?</ipxact:displayName>
+ <ipxact:value>NO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="accum_direction" type="string">
+ <ipxact:name>accum_direction</ipxact:name>
+ <ipxact:displayName>What is the accumulator operation type?</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_ena_preload_const" type="bit">
+ <ipxact:name>gui_ena_preload_const</ipxact:name>
+ <ipxact:displayName>Enable preload constant</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_accumulate_port_select" type="int">
+ <ipxact:name>gui_accumulate_port_select</ipxact:name>
+ <ipxact:displayName>What is the input of accumulate port connected to?</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="loadconst_value" type="int">
+ <ipxact:name>loadconst_value</ipxact:name>
+ <ipxact:displayName>Select value for preload constant</ipxact:displayName>
+ <ipxact:value>64</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_accum_sload_register_clock" type="string">
+ <ipxact:name>gui_accum_sload_register_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_accum_sload_register_aclr" type="string">
+ <ipxact:name>gui_accum_sload_register_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_accum_sload_register_sclr" type="string">
+ <ipxact:name>gui_accum_sload_register_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_double_accum" type="bit">
+ <ipxact:name>gui_double_accum</ipxact:name>
+ <ipxact:displayName>Enable double accumulator</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="chainout_adder" type="string">
+ <ipxact:name>chainout_adder</ipxact:name>
+ <ipxact:displayName>Enable chainout adder</ipxact:displayName>
+ <ipxact:value>NO</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="chainout_adder_direction" type="string">
+ <ipxact:name>chainout_adder_direction</ipxact:name>
+ <ipxact:displayName>What is the chainout adder operation type?</ipxact:displayName>
+ <ipxact:value>ADD</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="port_negate" type="string">
+ <ipxact:name>port_negate</ipxact:name>
+ <ipxact:displayName>Enable 'negate' input for chainout adder?</ipxact:displayName>
+ <ipxact:value>PORT_UNUSED</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="negate_register" type="string">
+ <ipxact:name>negate_register</ipxact:name>
+ <ipxact:displayName>Register 'negate' input?</ipxact:displayName>
+ <ipxact:value>UNREGISTERED</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="negate_aclr" type="string">
+ <ipxact:name>negate_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="negate_sclr" type="string">
+ <ipxact:name>negate_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_systolic_delay" type="bit">
+ <ipxact:name>gui_systolic_delay</ipxact:name>
+ <ipxact:displayName>Enable systolic delay registers</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_systolic_delay_clock" type="string">
+ <ipxact:name>gui_systolic_delay_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_systolic_delay_aclr" type="string">
+ <ipxact:name>gui_systolic_delay_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_systolic_delay_sclr" type="string">
+ <ipxact:name>gui_systolic_delay_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_pipelining" type="int">
+ <ipxact:name>gui_pipelining</ipxact:name>
+ <ipxact:displayName>Do you want to add pipeline register to the input?</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="latency" type="int">
+ <ipxact:name>latency</ipxact:name>
+ <ipxact:displayName>Please specify the number of latency clock cycles</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_latency_clock" type="string">
+ <ipxact:name>gui_input_latency_clock</ipxact:name>
+ <ipxact:displayName>What is the source for clock input?</ipxact:displayName>
+ <ipxact:value>CLOCK0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_latency_aclr" type="string">
+ <ipxact:name>gui_input_latency_aclr</ipxact:name>
+ <ipxact:displayName>What is the source for asynchronous clear input?</ipxact:displayName>
+ <ipxact:value>ACLR0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="gui_input_latency_sclr" type="string">
+ <ipxact:name>gui_input_latency_sclr</ipxact:name>
+ <ipxact:displayName>What is the source for synchronous clear input?</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="selected_device_family" type="string">
+ <ipxact:name>selected_device_family</ipxact:name>
+ <ipxact:displayName>selected_device_family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="reg_autovec_sim" type="bit">
+ <ipxact:name>reg_autovec_sim</ipxact:name>
+ <ipxact:displayName>reg_autovec_sim</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31A1I1VB</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element mult_add_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="aclr0" altera:internal="mult_add_0.aclr0" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="aclr0" altera:internal="aclr0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clock0" altera:internal="mult_add_0.clock0" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="clock0" altera:internal="clock0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_0" altera:internal="mult_add_0.dataa_0" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_0" altera:internal="dataa_0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_1" altera:internal="mult_add_0.dataa_1" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_1" altera:internal="dataa_1"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_2" altera:internal="mult_add_0.dataa_2" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_2" altera:internal="dataa_2"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="dataa_3" altera:internal="mult_add_0.dataa_3" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="dataa_3" altera:internal="dataa_3"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_0" altera:internal="mult_add_0.datab_0" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_0" altera:internal="datab_0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_1" altera:internal="mult_add_0.datab_1" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_1" altera:internal="datab_1"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_2" altera:internal="mult_add_0.datab_2" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_2" altera:internal="datab_2"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="datab_3" altera:internal="mult_add_0.datab_3" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="datab_3" altera:internal="datab_3"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="ena0" altera:internal="mult_add_0.ena0" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="ena0" altera:internal="ena0"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="result" altera:internal="mult_add_0.result" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="result" altera:internal="result"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd b/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..da79fb61756bc0a4a08fc46e942d2731f2033ce7
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/mult_add4/ip_agi027_xxxx_mult_add4_rtl.vhd
@@ -0,0 +1,274 @@
+-- -----------------------------------------------------------------------------
+--
+-- Copyright 2023
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-- -----------------------------------------------------------------------------
+--
+-- Author : D.F. Brouwer
+-- Purpose:
+-- RadioHDL wrapper
+-- Reference:
+-- Copied from */technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add2.vhd
+
+library IEEE, common_lib;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use common_lib.common_pkg.all;
+
+-- Function:
+-- . res = (a0 * b0 +- a1 * b1) +- (a2 * b2 +- a3 * b3)
+
+entity ip_agi027_xxxx_mult_add4_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(4)
+ g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
+ g_add_sub0 : string := "ADD"; -- or "SUB"
+ g_add_sub1 : string := "ADD"; -- or "SUB"
+ g_add_sub : string := "ADD"; -- or "SUB" only available with rtl architecture
+ g_nof_mult : integer := 4; -- fixed
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1, first sum
+ g_pipeline_output : natural := 1 -- >= 0, second sum and optional rounding
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ res : out std_logic_vector(g_res_w - 1 downto 0)
+ );
+end ip_agi027_xxxx_mult_add4_rtl;
+
+architecture str of ip_agi027_xxxx_mult_add4_rtl is
+ -- Extra output pipelining is only needed when g_pipeline_output > 1
+ constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
+
+ -- registers
+ signal reg_a0 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b0 : signed(g_in_b_w - 1 downto 0);
+ signal reg_a1 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b1 : signed(g_in_b_w - 1 downto 0);
+ signal reg_a2 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b2 : signed(g_in_b_w - 1 downto 0);
+ signal reg_a3 : signed(g_in_a_w - 1 downto 0);
+ signal reg_b3 : signed(g_in_b_w - 1 downto 0);
+ signal reg_prod0 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal reg_prod1 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal reg_prod2 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal reg_prod3 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal reg_sum0 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal reg_sum1 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal reg_result : signed(res'range);
+
+ -- combinatorial
+ signal nxt_a0 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b0 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_a1 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b1 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_a2 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b2 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_a3 : signed(g_in_a_w - 1 downto 0);
+ signal nxt_b3 : signed(g_in_b_w - 1 downto 0);
+ signal nxt_prod0 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal nxt_prod1 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal nxt_prod2 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal nxt_prod3 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal nxt_sum0 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal nxt_sum1 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal nxt_result : signed(res'range);
+
+ -- the active signals
+ signal a0 : signed(g_in_a_w - 1 downto 0);
+ signal b0 : signed(g_in_b_w - 1 downto 0);
+ signal a1 : signed(g_in_a_w - 1 downto 0);
+ signal b1 : signed(g_in_b_w - 1 downto 0);
+ signal a2 : signed(g_in_a_w - 1 downto 0);
+ signal b2 : signed(g_in_b_w - 1 downto 0);
+ signal a3 : signed(g_in_a_w - 1 downto 0);
+ signal b3 : signed(g_in_b_w - 1 downto 0);
+ signal prod0 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal prod1 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal prod2 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal prod3 : signed(g_in_a_w + g_in_b_w - 1 downto 0);
+ signal sum0 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal sum1 : signed(g_in_a_w + g_in_b_w downto 0);
+ signal sum : signed(g_in_a_w + g_in_b_w + 1 downto 0);
+ signal result : signed(res'range);
+begin
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : process (rst, clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' then
+ reg_a0 <= (others => '0');
+ reg_b0 <= (others => '0');
+ reg_a1 <= (others => '0');
+ reg_b1 <= (others => '0');
+ reg_a2 <= (others => '0');
+ reg_b2 <= (others => '0');
+ reg_a3 <= (others => '0');
+ reg_b3 <= (others => '0');
+ reg_prod0 <= (others => '0');
+ reg_prod1 <= (others => '0');
+ reg_prod2 <= (others => '0');
+ reg_prod3 <= (others => '0');
+ reg_sum0 <= (others => '0');
+ reg_sum1 <= (others => '0');
+ reg_result <= (others => '0');
+ elsif clken = '1' then
+ reg_a0 <= nxt_a0; -- inputs
+ reg_b0 <= nxt_b0;
+ reg_a1 <= nxt_a1;
+ reg_b1 <= nxt_b1;
+ reg_a2 <= nxt_a2;
+ reg_b2 <= nxt_b2;
+ reg_a3 <= nxt_a3;
+ reg_b3 <= nxt_b3;
+ reg_prod0 <= nxt_prod0; -- products
+ reg_prod1 <= nxt_prod1;
+ reg_prod2 <= nxt_prod2;
+ reg_prod3 <= nxt_prod3;
+ reg_sum0 <= nxt_sum0; -- first sum
+ reg_sum1 <= nxt_sum1;
+ reg_result <= nxt_result; -- result second sum after optional rounding
+ end if;
+ end if;
+ end process;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a0 <= signed(in_a( g_in_a_w - 1 downto 0));
+ nxt_b0 <= signed(in_b( g_in_b_w - 1 downto 0));
+ nxt_a1 <= signed(in_a(2 * g_in_a_w - 1 downto g_in_a_w));
+ nxt_b1 <= signed(in_b(2 * g_in_b_w - 1 downto g_in_b_w));
+ nxt_a2 <= signed(in_a(3 * g_in_a_w - 1 downto 2 * g_in_a_w));
+ nxt_b2 <= signed(in_b(3 * g_in_b_w - 1 downto 2 * g_in_b_w));
+ nxt_a3 <= signed(in_a(4 * g_in_a_w - 1 downto 3 * g_in_a_w));
+ nxt_b3 <= signed(in_b(4 * g_in_b_w - 1 downto 3 * g_in_b_w));
+
+ no_input_reg : if g_pipeline_input = 0 generate -- wired
+ a0 <= nxt_a0;
+ b0 <= nxt_b0;
+ a1 <= nxt_a1;
+ b1 <= nxt_b1;
+ a2 <= nxt_a2;
+ b2 <= nxt_b2;
+ a3 <= nxt_a3;
+ b3 <= nxt_b3;
+ end generate;
+
+ gen_input_reg : if g_pipeline_input > 0 generate -- register input
+ a0 <= reg_a0;
+ b0 <= reg_b0;
+ a1 <= reg_a1;
+ b1 <= reg_b1;
+ a2 <= reg_a2;
+ b2 <= reg_b2;
+ a3 <= reg_a3;
+ b3 <= reg_b3;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod0 <= a0 * b0;
+ nxt_prod1 <= a1 * b1;
+ nxt_prod2 <= a2 * b2;
+ nxt_prod3 <= a3 * b3;
+
+ no_product_reg : if g_pipeline_product = 0 generate -- wired
+ prod0 <= nxt_prod0;
+ prod1 <= nxt_prod1;
+ prod2 <= nxt_prod2;
+ prod3 <= nxt_prod3;
+ end generate;
+ gen_product_reg : if g_pipeline_product > 0 generate -- register
+ prod0 <= reg_prod0;
+ prod1 <= reg_prod1;
+ prod2 <= reg_prod2;
+ prod3 <= reg_prod3;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- First sum
+ ------------------------------------------------------------------------------
+ gen_add0 : if g_add_sub0 = "ADD" generate
+ nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) + prod1;
+ end generate;
+
+ gen_sub0 : if g_add_sub0 = "SUB" generate
+ nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) - prod1;
+ end generate;
+
+ gen_add1 : if g_add_sub1 = "ADD" generate
+ nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) + prod3;
+ end generate;
+
+ gen_sub1 : if g_add_sub1 = "SUB" generate
+ nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) - prod3;
+ end generate;
+
+ -- Optinal first sum register
+ no_adder_reg : if g_pipeline_adder = 0 generate -- wired
+ sum0 <= nxt_sum0;
+ sum1 <= nxt_sum1;
+ end generate;
+ gen_adder_reg : if g_pipeline_adder > 0 generate -- register
+ sum0 <= reg_sum0;
+ sum1 <= reg_sum1;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Second sum
+ ------------------------------------------------------------------------------
+
+ -- No register for second sum, gets combined with result register
+ gen_add : if g_add_sub = "ADD" generate
+ sum <= RESIZE_NUM(sum0, sum'length) + sum1;
+ end generate;
+
+ gen_sub : if g_add_sub = "SUB" generate
+ sum <= RESIZE_NUM(sum0, sum'length) - sum1;
+ end generate;
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result <= RESIZE_NUM(sum, res'length);
+
+ no_result_reg : if g_pipeline_output = 0 generate -- wired
+ result <= nxt_result;
+ end generate;
+ gen_result_reg : if g_pipeline_output > 0 generate -- register
+ result <= reg_result;
+ end generate;
+
+ res <= std_logic_vector(result);
+end str;
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
index c117b1a36852672fbeab89e222e6d6bade9f6414..772a81cadece2b7b5fec0eece6c64ca8afb7e032 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult_rtl/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = ip_arria10_complex_mult_rtl
hdl_library_clause_name = ip_arria10_complex_mult_rtl_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3 and arria10_e1sg
+hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3, arria10_e1sg and arria10_e2sg. It can be used for other (new) technologies. Leave hdl_lib_technology empty.
synth_files =
ip_arria10_complex_mult_rtl.vhd
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl_canonical/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult_rtl_canonical/hdllib.cfg
index a8446b153d87f2590f26bcbd290c5f7a78143d8c..bb6e480fe3d45b596e127c6411d62e7040141fc4 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl_canonical/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult_rtl_canonical/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = ip_arria10_complex_mult_rtl_canonical
hdl_library_clause_name = ip_arria10_complex_mult_rtl_canonical_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3 and arria10_e1sg
+hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3, arria10_e1sg and arria10_e2sg. It can be used for other (new) technologies. Leave hdl_lib_technology empty.
synth_files =
ip_arria10_complex_mult_rtl_canonical.vhd
diff --git a/libraries/technology/ip_arria10/mult/hdllib.cfg b/libraries/technology/ip_arria10/mult/hdllib.cfg
index 261e2d6efcfec39cbc60d57a4f2cb1cb01301ea2..75ed0b9a50eac50f8c3d59522a54d38a4e9ff83e 100644
--- a/libraries/technology/ip_arria10/mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mult/hdllib.cfg
@@ -2,7 +2,7 @@ hdl_lib_name = ip_arria10_mult
hdl_library_clause_name = ip_arria10_mult_lib
hdl_lib_uses_synth =
hdl_lib_uses_sim =
-hdl_lib_technology =
+hdl_lib_technology = #ip_arria10 This file is also used for arria10_e3sge3, arria10_e1sg and arria10_e2sg. It can be used for other (new) technologies. Leave hdl_lib_technology empty.
synth_files =
ip_arria10_mult.vhd
diff --git a/libraries/technology/mult/hdllib.cfg b/libraries/technology/mult/hdllib.cfg
index 6cec72909f1987c343efe91bf4226b69ef007453..1febdded2e79c181d0a9437ff1a00ce6ec36d014 100644
--- a/libraries/technology/mult/hdllib.cfg
+++ b/libraries/technology/mult/hdllib.cfg
@@ -6,13 +6,20 @@ hdl_lib_uses_synth = common technology
ip_arria10_complex_mult
ip_arria10_complex_mult_rtl
ip_arria10_complex_mult_rtl_canonical
- ip_arria10_e1sg_complex_mult
ip_arria10_e3sge3_mult_add4
+ ip_arria10_e1sg_complex_mult
ip_arria10_e1sg_mult_add4
ip_arria10_e1sg_mult_add2
+ ip_arria10_e2sg_complex_mult
ip_arria10_e2sg_mult_add4
ip_arria10_e2sg_mult_add2
- ip_arria10_e2sg_complex_mult
+ ip_agi027_xxxx_complex_mult
+ ip_agi027_xxxx_complex_mult_rtl
+ ip_agi027_xxxx_complex_mult_rtl_canonical
+ ip_agi027_xxxx_mult
+ ip_agi027_xxxx_mult_add4
+ ip_agi027_xxxx_mult_add2
+
hdl_lib_uses_sim =
hdl_lib_technology =
@@ -21,13 +28,19 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_mult ip_arria10_mult_lib
ip_arria10_complex_mult ip_arria10_complex_mult_altmult_complex_150
ip_arria10_complex_mult_rtl ip_arria10_complex_mult_rtl_lib
- ip_arria10_e1sg_complex_mult ip_arria10_e1sg_complex_mult_altmult_complex_180
ip_arria10_e3sge3_mult_add4 ip_arria10_e3sge3_mult_add4_lib
+ ip_arria10_e1sg_complex_mult ip_arria10_e1sg_complex_mult_altmult_complex_180
ip_arria10_e1sg_mult_add4 ip_arria10_e1sg_mult_add4_lib
ip_arria10_e1sg_mult_add2 ip_arria10_e1sg_mult_add2_lib
+ ip_arria10_e2sg_complex_mult ip_arria10_e2sg_complex_mult_altmult_complex_1910
ip_arria10_e2sg_mult_add4 ip_arria10_e2sg_mult_add4_lib
ip_arria10_e2sg_mult_add2 ip_arria10_e2sg_mult_add2_lib
- ip_arria10_e2sg_complex_mult ip_arria10_e2sg_complex_mult_altmult_complex_1910
+ ip_agi027_xxxx_complex_mult ip_agi027_xxxx_complex_mult_altmult_complex_1910
+ ip_agi027_xxxx_complex_mult_rtl ip_agi027_xxxx_complex_mult_rtl_lib
+ ip_agi027_xxxx_mult ip_agi027_xxxx_mult_lib
+ ip_agi027_xxxx_mult_add4 ip_agi027_xxxx_mult_add4_lib
+ ip_agi027_xxxx_mult_add2 ip_agi027_xxxx_mult_add2_lib
+
synth_files =
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index d11e36bb05a80b51423d6641bf2b06f5d2859735..168d165e910e62c27e7b80f5fd8ed747e2e194e1 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -1,25 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
-- Author : E. Kooistra
+-- Changed by : D.F. Brouwer
-- Purpose : Wrapper for complex multiplier IP
-- Decription :
--
@@ -42,7 +42,7 @@
-- The largest value for pi = min**2 + min**2.
-- The largest value for pr = min**2 - min*max < largest pi.
--
--- The largest pi = 2 * min**2 = 2**(c_dsp_dat_w-1), so it just does not
+-- The largest pi = 2 * min**2 = 2**(c_dsp_prod_w-1), so it just does not
-- fit in c_dsp_prod_w, but largest pi - 1 = 2**(c_dsp_dat_w-1) - 1 does
-- fit, so all other input values fit. In DSP systems the input value
-- (min + j*min) typically never occurs.
@@ -63,13 +63,14 @@ use work.tech_mult_component_pkg.all;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
library ip_stratixiv_mult_lib;
---LIBRARY ip_arria10_mult_lib;
---LIBRARY ip_arria10_mult_rtl_lib;
library ip_arria10_complex_mult_altmult_complex_150;
library ip_arria10_e1sg_complex_mult_altmult_complex_180;
library ip_arria10_e2sg_complex_mult_altmult_complex_1910;
+library ip_agi027_xxxx_complex_mult_altmult_complex_1910;
library ip_arria10_complex_mult_rtl_lib;
+library ip_agi027_xxxx_complex_mult_rtl_lib;
library ip_arria10_complex_mult_rtl_canonical_lib;
+library ip_agi027_xxxx_complex_mult_rtl_canonical_lib;
entity tech_complex_mult is
generic (
@@ -212,6 +213,31 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
+ gen_ip_agi027_xxxx_ip : if g_variant = "IP" and g_technology = c_tech_agi027_xxxx and c_dsp_dat_w <= c_dsp_mult_18_w generate
+ -- Adapt DSP input widths
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_18_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_18_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_18_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_18_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_18_w);
+
+ u0 : ip_agi027_xxxx_complex_mult
+ port map (
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
+
+ -- Back to true input widths and then resize for output width
+ result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+ result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+ end generate;
+
-----------------------------------------------------------------------------
-- IP variants for > 18 bit and <= 27 bit
-----------------------------------------------------------------------------
@@ -266,6 +292,31 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
+ gen_ip_agi027_xxxx_ip_27b : if g_variant = "IP" and g_technology = c_tech_agi027_xxxx and c_dsp_dat_w > c_dsp_mult_18_w and c_dsp_dat_w <= c_dsp_mult_27_w generate
+ -- Adapt DSP input widths
+ ar <= RESIZE_SVEC(in_ar, c_dsp_mult_27_w);
+ ai <= RESIZE_SVEC(in_ai, c_dsp_mult_27_w);
+ br <= RESIZE_SVEC(in_br, c_dsp_mult_27_w);
+ bi <= RESIZE_SVEC(in_bi, c_dsp_mult_27_w) when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), c_dsp_mult_27_w);
+
+ u0 : ip_agi027_xxxx_complex_mult_27b
+ port map (
+ aclr => rst,
+ clock => clk,
+ dataa_imag => ai,
+ dataa_real => ar,
+ datab_imag => bi,
+ datab_real => br,
+ ena => clken,
+ result_imag => mult_im,
+ result_real => mult_re
+ );
+
+ -- Back to true input widths and then resize for output width
+ result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
+ result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
+ end generate;
+
-----------------------------------------------------------------------------
-- RTL variants that can infer multipliers for a technology, fits all widths
-----------------------------------------------------------------------------
@@ -328,7 +379,6 @@ begin
gen_ip_arria10_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_arria10_proto or
g_technology = c_tech_arria10_e3sge3 or
g_technology = c_tech_arria10_e1sg or
-
g_technology = c_tech_arria10_e2sg) generate
-- support g_conjugate_b
bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
@@ -356,4 +406,58 @@ begin
);
end generate;
+ -- RTL variant is for iwave
+ gen_ip_agi027_xxxx_rtl : if g_variant = "RTL" and (g_technology = c_tech_agi027_xxxx) generate
+ u0 : ip_agi027_xxxx_complex_mult_rtl
+ generic map (
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_conjugate_b => g_conjugate_b,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => in_bi,
+ result_re => result_re,
+ result_im => result_im
+ );
+ end generate;
+
+ -- RTL variant is for iwave
+ gen_ip_agi027_xxxx_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_agi027_xxxx) generate
+ -- support g_conjugate_b
+ bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
+
+ u0 : ip_agi027_xxxx_complex_mult_rtl_canonical
+ generic map (
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_ar => in_ar,
+ in_ai => in_ai,
+ in_br => in_br,
+ in_bi => bi,
+ result_re => result_re,
+ result_im => result_im
+ );
+ end generate;
+
end str;
diff --git a/libraries/technology/mult/tech_mult.vhd b/libraries/technology/mult/tech_mult.vhd
index 02302d50192a9aa4cdf39b42eb9214238e82a9e8..340909990f2383f7021d32c1f645d8085ed290aa 100644
--- a/libraries/technology/mult/tech_mult.vhd
+++ b/libraries/technology/mult/tech_mult.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
@@ -29,6 +31,7 @@ use work.tech_mult_component_pkg.all;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
library ip_stratixiv_mult_lib;
library ip_arria10_mult_lib;
+library ip_agi027_xxxx_mult_lib;
entity tech_mult is
generic (
@@ -146,6 +149,49 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx_ip : if (g_technology = c_tech_agi027_xxxx and g_variant = "IP") generate
+ u0 : ip_agi027_xxxx_mult
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => prod
+ );
+ end generate;
+
+ gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
+ u0 : ip_agi027_xxxx_mult_rtl
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_out_p_w => g_out_p_w,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_output => g_pipeline_output,
+ g_representation => g_representation
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ out_p => prod
+ );
+ end generate;
+
gen_trunk : for I in 0 to g_nof_mult - 1 generate
-- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
out_p((I + 1) * g_out_p_w - 1 downto I * g_out_p_w) <= RESIZE_SVEC(prod((I + 1) * c_prod_w - 1 downto I * c_prod_w), g_out_p_w) when g_representation = "SIGNED" else
diff --git a/libraries/technology/mult/tech_mult_add2.vhd b/libraries/technology/mult/tech_mult_add2.vhd
index 59504b2139122a8bcd6ea3fc182460d1b59b3df7..caabbb03d31aa08a858c5e133167c390361dc632 100644
--- a/libraries/technology/mult/tech_mult_add2.vhd
+++ b/libraries/technology/mult/tech_mult_add2.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
@@ -30,6 +32,7 @@ use work.tech_mult_component_pkg.all;
library ip_stratixiv_mult_lib;
library ip_arria10_e1sg_mult_add2_lib;
library ip_arria10_e2sg_mult_add2_lib;
+library ip_agi027_xxxx_mult_add2_lib;
entity tech_mult_add2 is
generic (
@@ -130,4 +133,28 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
+ u0 : ip_agi027_xxxx_mult_add2_rtl
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => res
+ );
+ end generate;
+
end str;
diff --git a/libraries/technology/mult/tech_mult_add4.vhd b/libraries/technology/mult/tech_mult_add4.vhd
index bc2e5da25b59eb3e1acbb873bf9617eecea20c3b..effb07e3de72b451223763422c7ad12bd0b5b80f 100644
--- a/libraries/technology/mult/tech_mult_add4.vhd
+++ b/libraries/technology/mult/tech_mult_add4.vhd
@@ -1,23 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2009
+-- Copyright 2009-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
@@ -31,6 +33,7 @@ library ip_stratixiv_mult_lib;
library ip_arria10_e3sge3_mult_add4_lib;
library ip_arria10_e1sg_mult_add4_lib;
library ip_arria10_e2sg_mult_add4_lib;
+library ip_agi027_xxxx_mult_add4_lib;
entity tech_mult_add4 is
generic (
@@ -165,4 +168,30 @@ begin
);
end generate;
+ gen_ip_agi027_xxxx_rtl : if (g_technology = c_tech_agi027_xxxx and g_variant = "RTL") generate
+ u0 : ip_agi027_xxxx_mult_add4_rtl
+ generic map(
+ g_in_a_w => g_in_a_w,
+ g_in_b_w => g_in_b_w,
+ g_res_w => g_res_w,
+ g_force_dsp => g_force_dsp,
+ g_add_sub0 => g_add_sub0,
+ g_add_sub1 => g_add_sub1,
+ g_add_sub => g_add_sub,
+ g_nof_mult => g_nof_mult,
+ g_pipeline_input => g_pipeline_input,
+ g_pipeline_product => g_pipeline_product,
+ g_pipeline_adder => g_pipeline_adder,
+ g_pipeline_output => g_pipeline_output
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ in_a => in_a,
+ in_b => in_b,
+ res => res
+ );
+ end generate;
+
end str;
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index 8d9668897ba9d69109eff6079f39ab095adb39d1..9e12d7f58eb29bfb3406e55a62b86c79bb440d7a 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -1,25 +1,27 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
-
--- Purpose: IP components declarations for various devices that get wrapped by the tech components
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
+-- Purpose:
+-- IP components declarations for various devices that get wrapped by the tech components
library IEEE;
use IEEE.std_logic_1164.all;
@@ -296,6 +298,7 @@ package tech_mult_component_pkg is
-----------------------------------------------------------------------------
-- Arria 10 e1sg components
-----------------------------------------------------------------------------
+
component ip_arria10_e1sg_mult_add2_rtl is
generic (
g_in_a_w : positive;
@@ -371,9 +374,11 @@ package tech_mult_component_pkg is
result_imag : out std_logic_vector(53 downto 0) -- .result_imag
);
end component;
+
-----------------------------------------------------------------------------
-- Arria 10 e2sg components
-----------------------------------------------------------------------------
+
component ip_arria10_e2sg_mult_add2_rtl is
generic (
g_in_a_w : positive;
@@ -449,4 +454,175 @@ package tech_mult_component_pkg is
result_imag : out std_logic_vector(53 downto 0) -- .result_imag
);
end component;
+
+ -----------------------------------------------------------------------------
+ -- Agilex 7 (agi027) xxxx components
+ -----------------------------------------------------------------------------
+
+ component ip_agi027_xxxx_mult is
+ generic (
+ g_in_a_w : positive := 18; -- Width of the data A port
+ g_in_b_w : positive := 18; -- Width of the data B port
+ g_out_p_w : positive := 36; -- Width of the result port
+ g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1; -- >= 0
+ g_representation : string := "SIGNED" -- or "UNSIGNED"
+ );
+ port (
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_mult_rtl is
+ generic (
+ g_in_a_w : positive := 18;
+ g_in_b_w : positive := 18;
+ g_out_p_w : positive := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
+ g_nof_mult : positive := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1; -- >= 0
+ g_representation : string := "SIGNED" -- or "UNSIGNED"
+ );
+ port (
+ rst : in std_logic;
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ out_p : out std_logic_vector(g_nof_mult * (g_in_a_w + g_in_b_w) - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_mult_add2_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(2)
+ g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
+ g_add_sub : string := "ADD"; -- or "SUB"
+ g_nof_mult : integer := 2; -- fixed
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ res : out std_logic_vector(g_res_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_mult_add4_rtl is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_res_w : positive; -- g_in_a_w + g_in_b_w + log2(4)
+ g_force_dsp : boolean := true; -- when TRUE resize input width to >= 18
+ g_add_sub0 : string := "ADD"; -- or "SUB"
+ g_add_sub1 : string := "ADD"; -- or "SUB"
+ g_add_sub : string := "ADD"; -- or "SUB" only available with rtl architecture
+ g_nof_mult : integer := 4; -- fixed
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1, first sum
+ g_pipeline_output : natural := 1 -- >= 0, second sum and optional rounding
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_a : in std_logic_vector(g_nof_mult * g_in_a_w - 1 downto 0);
+ in_b : in std_logic_vector(g_nof_mult * g_in_b_w - 1 downto 0);
+ res : out std_logic_vector(g_res_w - 1 downto 0)
+ );
+ end component;
+
+
+ component ip_agi027_xxxx_complex_mult_rtl is
+ generic (
+ g_in_a_w : positive := 18;
+ g_in_b_w : positive := 18;
+ g_out_p_w : positive := 36;
+ g_conjugate_b : boolean := false;
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_ar : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_ai : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_br : in std_logic_vector(g_in_b_w - 1 downto 0);
+ in_bi : in std_logic_vector(g_in_b_w - 1 downto 0);
+ result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
+ result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_complex_mult_rtl_canonical is
+ generic (
+ g_in_a_w : positive;
+ g_in_b_w : positive;
+ g_out_p_w : positive; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
+-- g_conjugate_b : BOOLEAN := FALSE;
+ g_pipeline_input : natural := 1; -- 0 or 1
+ g_pipeline_product : natural := 0; -- 0 or 1
+ g_pipeline_adder : natural := 1; -- 0 or 1
+ g_pipeline_output : natural := 1 -- >= 0
+ );
+ port (
+ rst : in std_logic := '0';
+ clk : in std_logic;
+ clken : in std_logic := '1';
+ in_ar : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_ai : in std_logic_vector(g_in_a_w - 1 downto 0);
+ in_br : in std_logic_vector(g_in_b_w - 1 downto 0);
+ in_bi : in std_logic_vector(g_in_b_w - 1 downto 0);
+ result_re : out std_logic_vector(g_out_p_w - 1 downto 0);
+ result_im : out std_logic_vector(g_out_p_w - 1 downto 0)
+ );
+ end component;
+
+ component ip_agi027_xxxx_complex_mult is
+ port (
+ dataa_real : in std_logic_vector(17 downto 0) := (others => '0'); -- complex_input.dataa_real
+ dataa_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .dataa_imag
+ datab_real : in std_logic_vector(17 downto 0) := (others => '0'); -- .datab_real
+ datab_imag : in std_logic_vector(17 downto 0) := (others => '0'); -- .datab_imag
+ clock : in std_logic := '0'; -- .clk
+ aclr : in std_logic := '0'; -- .aclr
+ ena : in std_logic := '0'; -- .ena
+ result_real : out std_logic_vector(35 downto 0); -- complex_output.result_real
+ result_imag : out std_logic_vector(35 downto 0) -- .result_imag
+ );
+ end component;
+
+ component ip_agi027_xxxx_complex_mult_27b is
+ port (
+ dataa_real : in std_logic_vector(26 downto 0) := (others => '0'); -- complex_input.dataa_real
+ dataa_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .dataa_imag
+ datab_real : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_real
+ datab_imag : in std_logic_vector(26 downto 0) := (others => '0'); -- .datab_imag
+ clock : in std_logic := '0'; -- .clk
+ aclr : in std_logic := '0'; -- .aclr
+ ena : in std_logic := '0'; -- .ena
+ result_real : out std_logic_vector(53 downto 0); -- complex_output.result_real
+ result_imag : out std_logic_vector(53 downto 0) -- .result_imag
+ );
+ end component;
+
end tech_mult_component_pkg;
diff --git a/libraries/technology/mult/tech_mult_pkg.vhd b/libraries/technology/mult/tech_mult_pkg.vhd
index 093a503af280e3ae167d8312b6ce3315a3cecc41..b86a07117932d2b59d163ee0bd28401711697f27 100644
--- a/libraries/technology/mult/tech_mult_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_pkg.vhd
@@ -1,24 +1,25 @@
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright 2014-2023
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
--
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
+-- http://www.apache.org/licenses/LICENSE-2.0
--
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
--
--------------------------------------------------------------------------------
+-- -----------------------------------------------------------------------------
+--
+-- Author : -
+-- Changed by : D.F. Brouwer
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
@@ -36,5 +37,7 @@ package tech_mult_pkg is
constant c_tech_mult_stratixiv_ip : t_c_tech_mult_variant := (" IP", true);
constant c_tech_mult_arria10_rtl : t_c_tech_mult_variant := ("RTL", false);
constant c_tech_mult_arria10_ip : t_c_tech_mult_variant := (" IP", true);
+ constant c_tech_mult_agi027_xxxx_rtl : t_c_tech_mult_variant := ("RTL", false);
+ constant c_tech_mult_agi027_xxxx_ip : t_c_tech_mult_variant := (" IP", true);
end tech_mult_pkg;