From 963f4f8e4716bcb6922ac330d8bfa5d1625210eb Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 11 Jun 2014 12:36:15 +0000
Subject: [PATCH] Use tech_hton() from technology_pkg.vhd instead of from
common_pkg.vhd. Similar for tech_ceil_div().
---
.../vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd | 22 +++++++++---------
libraries/technology/technology_pkg.vhd | 23 +++++++++++++++++++
2 files changed, 34 insertions(+), 11 deletions(-)
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd
index 3e52d14989..4a8642d220 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd
@@ -30,10 +30,10 @@
-- > as 10
-- > run 50 us
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
ENTITY tb_ip_stratixiv_tse_sgmii_lvds IS
@@ -258,15 +258,15 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
-- DST MAC
dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
dp_src_out.data <= (OTHERS=>'0');
- dp_src_out.data(15 DOWNTO 0) <= hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
+ dp_src_out.data(15 DOWNTO 0) <= tech_hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
- dp_src_out.data <= hton(dst_mac_addr(47 DOWNTO 16));
+ dp_src_out.data <= tech_hton(dst_mac_addr(47 DOWNTO 16));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
-- SRC MAC
- dp_src_out.data <= hton(src_mac_addr(31 DOWNTO 0));
+ dp_src_out.data <= tech_hton(src_mac_addr(31 DOWNTO 0));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
-- SRC MAC & ETHERTYPE
- dp_src_out.data <= hton(src_mac_addr(47 DOWNTO 32)) & hton(c_eth_ethertype);
+ dp_src_out.data <= tech_hton(src_mac_addr(47 DOWNTO 32)) & tech_hton(c_eth_ethertype);
-- DATA
FOR I IN 0 TO c_nof_data_beats-1 LOOP
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
@@ -344,16 +344,16 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
- ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = tech_hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = tech_hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = tech_hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 16) = hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
- ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = tech_hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = tech_hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
-- Verify DATA
v_first := TRUE;
proc_valid(dp_clk, dp_snk_in.valid);
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index 8a8d0299b0..53d62326c5 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -40,6 +40,10 @@ PACKAGE technology_pkg IS
FUNCTION tech_true_log2(n : NATURAL) RETURN NATURAL; -- tech_true_log2(n) = log2(n)
FUNCTION tech_ceil_log2(n : NATURAL) RETURN NATURAL; -- tech_ceil_log2(n) = log2(n), but force tech_ceil_log2(1) = 1
+ FUNCTION tech_ceil_div(n, d : NATURAL) RETURN NATURAL; -- tech_ceil_div = n/d + (n MOD d)/=0
+
+ FUNCTION tech_hton(a :IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- convert endianity from host to network byte order or vice versa
+
FUNCTION tech_nat_to_mbps_str( n : IN NATURAL ) RETURN STRING;
END technology_pkg;
@@ -84,6 +88,25 @@ PACKAGE BODY technology_pkg IS
END IF;
END;
+ FUNCTION tech_ceil_div(n, d : NATURAL) RETURN NATURAL IS
+ BEGIN
+ RETURN n/d + sel_a_b(n MOD d = 0, 0, 1);
+ END;
+
+ FUNCTION tech_hton(a :IN STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
+ CONSTANT c_sz : NATURAL := a'LENGTH/c_byte_w;
+ VARIABLE vA : STD_LOGIC_VECTOR(a'LENGTH-1 DOWNTO 0) := a; -- map a to range [h:0]
+ BEGIN
+ CASE c_sz IS
+ WHEN 1 => NULL;
+ WHEN 2 => vA := a(7 DOWNTO 0) & a(15 DOWNTO 8);
+ WHEN 4 => vA := a(7 DOWNTO 0) & a(15 DOWNTO 8) & a(23 DOWNTO 16) & a(31 DOWNTO 24);
+ WHEN OTHERS =>
+ REPORT "tech_hton only supports size of 1, 2 or 4 bytes" SEVERITY FAILURE;
+ END CASE;
+ RETURN vA;
+ END;
+
FUNCTION tech_nat_to_mbps_str( n : IN NATURAL ) RETURN STRING IS -- Converts a selection of naturals to Mbps strings, used for edited MegaWizard file in ip_stratixiv_hssi_*_generic.vhd
VARIABLE r : STRING(1 TO 9);
BEGIN
--
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