diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/hdllib.cfg
index 6304d41c05de9cd7a6c8fc24952489dac5a9e5b1..22a6542cf4b65b73ee2cd1e1c1916d463928b6a6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/hdllib.cfg
@@ -17,9 +17,11 @@ synth_files =
src/vhdl/lofar2_unb2b_ring.vhd
test_bench_files =
-# tb/vhdl/tb_lofar2_unb2b_ring.vhd
+ tb/vhdl/tb_lofar2_unb2b_ring.vhd
+ tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
regression_test_vhdl =
+ tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
[modelsim_project_file]
modelsim_copy_files =
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
index 21089dce5a11b69ebc9405e6b4e416c197f19b6a..3d25e3f64b9aa2aa947629257ebcab46761ca750 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='timer_0.s1' start='0x3440' end='0x3460' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_epcs.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_remu.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34C0' end='0x34D0' datawidth='32' /><slave name='pio_pps.mem' start='0x34D0' end='0x34E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34E8' end='0x34F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34F0' end='0x34F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34F8' end='0x3500' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3500' end='0x3508' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x600' end='0x700' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x700' end='0x740' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x740' end='0x780' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x780' end='0x7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x7C0' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_diag_bg.mem' start='0x3040' end='0x3060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x30C0' end='0x30D0' datawidth='32' /><slave name='pio_pps.mem' start='0x30D0' end='0x30E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30E8' end='0x30F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30F0' end='0x30F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30F8' end='0x3100' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3100' end='0x3108' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x4000' end='0x5000' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x5000' end='0x6000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='timer_0.s1' start='0x3440' end='0x3460' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_epcs.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_remu.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34C0' end='0x34D0' datawidth='32' /><slave name='pio_pps.mem' start='0x34D0' end='0x34E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34E8' end='0x34F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34F0' end='0x34F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34F8' end='0x3500' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3500' end='0x3508' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x600' end='0x700' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x700' end='0x740' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x740' end='0x780' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x780' end='0x7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x7C0' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_diag_bg.mem' start='0x3040' end='0x3060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x30C0' end='0x30D0' datawidth='32' /><slave name='pio_pps.mem' start='0x30D0' end='0x30E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30E8' end='0x30F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30F0' end='0x30F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30F8' end='0x3100' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3100' end='0x3108' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x4000' end='0x5000' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x5000' end='0x6000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
index 09388c20125191dbe9cffded649c0d3102382db2..7b98016cd2037e9f2ff27dde6a7d5422bc911fa5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">512</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>6</spirit:right>
+ <spirit:right>9</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>6</spirit:right>
+ <spirit:right>9</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">7</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">10</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
index b37475205f99f0a7059e2f102eec7c535389c11e..fdcaae55801538b901a49cb2363349c028c30c7f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">512</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>6</spirit:right>
+ <spirit:right>9</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>6</spirit:right>
+ <spirit:right>9</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">7</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">10</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -846,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -910,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -979,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1374,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys
index ed28393abeccadf6702dafb6ea2281382a73ca83..80c202e281ffd2530c691dbc1d00202312a2a323 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/qsys_lofar2_unb2b_ring.qsys
@@ -83,7 +83,7 @@
{
datum baseAddress
{
- value = "13568";
+ value = "12544";
type = "String";
}
}
@@ -133,7 +133,7 @@
{
datum baseAddress
{
- value = "13520";
+ value = "12496";
type = "String";
}
}
@@ -218,7 +218,7 @@
{
datum baseAddress
{
- value = "12800";
+ value = "20480";
type = "String";
}
}
@@ -234,7 +234,7 @@
{
datum baseAddress
{
- value = "1536";
+ value = "16384";
type = "String";
}
}
@@ -250,7 +250,7 @@
{
datum baseAddress
{
- value = "12320";
+ value = "12352";
type = "String";
}
}
@@ -266,7 +266,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "1792";
type = "String";
}
}
@@ -298,7 +298,7 @@
{
datum baseAddress
{
- value = "12480";
+ value = "1920";
type = "String";
}
}
@@ -314,7 +314,7 @@
{
datum baseAddress
{
- value = "12416";
+ value = "1856";
type = "String";
}
}
@@ -335,7 +335,7 @@
{
datum baseAddress
{
- value = "13560";
+ value = "12536";
type = "String";
}
}
@@ -356,7 +356,7 @@
{
datum baseAddress
{
- value = "13552";
+ value = "12528";
type = "String";
}
}
@@ -377,7 +377,7 @@
{
datum baseAddress
{
- value = "13440";
+ value = "12416";
type = "String";
}
}
@@ -393,7 +393,7 @@
{
datum baseAddress
{
- value = "13408";
+ value = "12384";
type = "String";
}
}
@@ -414,7 +414,7 @@
{
datum baseAddress
{
- value = "13312";
+ value = "1984";
type = "String";
}
}
@@ -435,7 +435,7 @@
{
datum baseAddress
{
- value = "13544";
+ value = "12520";
type = "String";
}
}
@@ -456,7 +456,7 @@
{
datum baseAddress
{
- value = "13536";
+ value = "12512";
type = "String";
}
}
@@ -477,7 +477,7 @@
{
datum baseAddress
{
- value = "13472";
+ value = "12448";
type = "String";
}
}
@@ -493,7 +493,7 @@
{
datum baseAddress
{
- value = "13504";
+ value = "12480";
type = "String";
}
}
@@ -573,7 +573,7 @@
{
datum baseAddress
{
- value = "12544";
+ value = "1536";
type = "String";
}
}
@@ -641,7 +641,7 @@
{
datum baseAddress
{
- value = "13376";
+ value = "12320";
type = "String";
}
}
@@ -4684,7 +4684,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x600' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_diag_bg.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x3080' end='0x30C0' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x30C0' end='0x3100' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='timer_0.s1' start='0x3440' end='0x3460' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x3460' end='0x3480' datawidth='32' /><slave name='reg_epcs.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_remu.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x34C0' end='0x34D0' datawidth='32' /><slave name='pio_pps.mem' start='0x34D0' end='0x34E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x34E0' end='0x34E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x34E8' end='0x34F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x34F0' end='0x34F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x34F8' end='0x3500' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3500' end='0x3508' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_ring_lane_info.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='ram_diag_bg.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_dp_block_validate_err.mem' start='0x400' end='0x600' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x600' end='0x700' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync.mem' start='0x700' end='0x740' datawidth='32' /><slave name='reg_dp_xonoff_local.mem' start='0x740' end='0x780' datawidth='32' /><slave name='reg_dp_xonoff_lane.mem' start='0x780' end='0x7C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x7C0' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_diag_bg.mem' start='0x3040' end='0x3060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x3060' end='0x3080' datawidth='32' /><slave name='reg_epcs.mem' start='0x3080' end='0x30A0' datawidth='32' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x30C0' end='0x30D0' datawidth='32' /><slave name='pio_pps.mem' start='0x30D0' end='0x30E0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x30E0' end='0x30E8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x30E8' end='0x30F0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x30F0' end='0x30F8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x30F8' end='0x3100' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3100' end='0x3108' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx.mem' start='0x4000' end='0x5000' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx.mem' start='0x5000' end='0x6000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -9187,7 +9187,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9251,7 +9251,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9320,7 +9320,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -9726,11 +9726,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -9803,7 +9803,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9867,7 +9867,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9936,7 +9936,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -10342,11 +10342,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24067,7 +24067,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x3500" />
+ <parameter name="baseAddress" value="0x3100" />
</connection>
<connection
kind="avalon"
@@ -24081,7 +24081,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x3100" />
+ <parameter name="baseAddress" value="0x0600" />
</connection>
<connection
kind="avalon"
@@ -24102,7 +24102,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x34d0" />
+ <parameter name="baseAddress" value="0x30d0" />
</connection>
<connection
kind="avalon"
@@ -24116,49 +24116,49 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x34a0" />
+ <parameter name="baseAddress" value="0x30a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x3480" />
+ <parameter name="baseAddress" value="0x3080" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x34f8" />
+ <parameter name="baseAddress" value="0x30f8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x34f0" />
+ <parameter name="baseAddress" value="0x30f0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x34e8" />
+ <parameter name="baseAddress" value="0x30e8" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x34e0" />
+ <parameter name="baseAddress" value="0x30e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x3460" />
+ <parameter name="baseAddress" value="0x3060" />
</connection>
<connection
kind="avalon"
@@ -24172,7 +24172,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x07c0" />
</connection>
<connection
kind="avalon"
@@ -24186,28 +24186,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx.mem">
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x5000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_tx.mem">
- <parameter name="baseAddress" value="0x0600" />
+ <parameter name="baseAddress" value="0x4000" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff_lane.mem">
- <parameter name="baseAddress" value="0x30c0" />
+ <parameter name="baseAddress" value="0x0780" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff_local.mem">
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x0740" />
</connection>
<connection
kind="avalon"
@@ -24221,14 +24221,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync.mem">
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x0700" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_info.mem">
- <parameter name="baseAddress" value="0x34c0" />
+ <parameter name="baseAddress" value="0x30c0" />
</connection>
<connection
kind="avalon"
@@ -24256,7 +24256,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_diag_bg.mem">
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x3040" />
</connection>
<connection
kind="avalon"
@@ -24305,7 +24305,7 @@
version="18.0"
start="cpu_0.data_master"
end="timer_0.s1">
- <parameter name="baseAddress" value="0x3440" />
+ <parameter name="baseAddress" value="0x3020" />
</connection>
<connection
kind="avalon"
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index a49266604eea6edbb357f3a052c731f96e46d6dc..5891567b0adc6e12c3d8b24f0a934a632da0d264 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -51,6 +51,7 @@ ENTITY lofar2_unb2b_ring IS
g_design_note : STRING := "UNUSED";
g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_sync_timeout : NATURAL := 3*1024;
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
@@ -108,7 +109,7 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
-- Revision parameters
CONSTANT c_revision_select : t_lofar2_unb2b_ring_config := func_sel_revision_rec(g_design_name);
- CONSTANT c_nof_lanes : c_revision_select.N_ring_lanes;
+ CONSTANT c_nof_lanes : NATURAL := c_revision_select.N_ring_lanes;
-- Firmware version x.y
CONSTANT c_fw_version : t_unb2b_board_fw_version := (2, 0);
CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_100M;
@@ -129,18 +130,24 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
CONSTANT c_nof_mac : NATURAL := 3 * c_nof_even_lanes; -- must match one of the MAC IP variations, e.g. 3, 12, 24, 48
CONSTANT c_lane_data_w : NATURAL := 64;
- CONSTANT c_lane_packet_length : NATURAL := 1024;
+ CONSTANT c_lane_packet_length : NATURAL := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size; -- = 48 longwords per packet, so the maximum data rate with a packetrate of 195312.5 and all 16 nodes combined = 16 * 48 / 1024 * 64 * 200M = 9.6 Gb/s
CONSTANT c_use_dp_layer : BOOLEAN := TRUE;
- CONSTANT c_nof_rx_monitors : NATURAL := 1;
- CONSTANT c_nof_tx_monitors : NATURAL := 1;
+ CONSTANT c_nof_rx_monitors : NATURAL := c_sdp_N_pn_max;
+ CONSTANT c_nof_tx_monitors : NATURAL := c_sdp_N_pn_max;
CONSTANT c_err_bi : NATURAL := 0;
CONSTANT c_nof_err_counts : NATURAL := 8;
CONSTANT c_validate_err_fifo_size : NATURAL := 1536;
CONSTANT c_bsn_at_sync_check_channel : NATURAL := 1;
CONSTANT c_validate_channel : BOOLEAN := TRUE;
CONSTANT c_validate_channel_mode : STRING := "=";
- CONSTANT c_fifo_tx_fill : NATURAL := c_lane_packet_length;
- CONSTANT c_fifo_tx_size : NATURAL := 2 * c_lane_packet_length;
+ CONSTANT c_fifo_tx_fill : NATURAL := c_lane_packet_length + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); --total packet length
+ CONSTANT c_fifo_tx_size : NATURAL := 2 * c_lane_packet_length;
+ CONSTANT c_lofar2_sync_timeout : NATURAL := c_lofar2_sample_clk_freq + c_lofar2_sample_clk_freq / 10; -- 10% margin.
+ CONSTANT c_sync_timeout : NATURAL := sel_a_b(g_sim, g_sim_sync_timeout, c_lofar2_sync_timeout );
+ CONSTANT c_nof_if : NATURAL := 3; -- 3 different interfaces, QSFP, RING_0 and RING_1
+ CONSTANT c_qsfp_if_offset : NATURAL := 0; -- QSFP signals are indexed at c_nof_if * I.
+ CONSTANT c_ring_0_if_offset : NATURAL := 1; -- RING_0 signals are indexed at c_nof_if * I + 1.
+ CONSTANT c_ring_1_if_offset : NATURAL := 2; -- RING_1 signals are indexed at c_nof_if * I + 2.
CONSTANT c_addr_w_reg_ring_lane_info : NATURAL := 1;
CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_rx : NATURAL := ceil_log2(c_nof_rx_monitors) + 3;
@@ -148,6 +155,13 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
CONSTANT c_addr_w_reg_dp_block_validate_err : NATURAL := ceil_log2(c_nof_err_counts + 3);
CONSTANT c_addr_w_reg_dp_block_validate_bsn_at_sync : NATURAL := ceil_log2(3);
+
+ CONSTANT c_reg_ring_input_select : t_c_mem := (latency => 1,
+ adr_w => ceil_log2(c_nof_lanes),
+ dat_w => 1,
+ nof_dat => c_nof_lanes,
+ init_sl => '0'); -- default use lane input = 0, 1 = local input.
+
SIGNAL this_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
-- System
@@ -322,8 +336,8 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
SIGNAL tr_10gbe_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_mac-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tr_10gbe_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_mac-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_even_lanes-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => '0');
SIGNAL this_bck_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_uniboard_w-1 DOWNTO 0);
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb2b_board_nof_chip_w-1 DOWNTO 0);
@@ -332,9 +346,7 @@ ARCHITECTURE str OF lofar2_unb2b_ring IS
SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL unb2_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
- SIGNAL unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
- SIGNAL unb2_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w -1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
BEGIN
@@ -633,13 +645,14 @@ BEGIN
);
bs_sosi <= local_sosi;
+
-----------------------------------------------------------------------------
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
u_mmp_dp_xonoff_lane : ENTITY dp_lib.mms_dp_xonoff
GENERIC MAP (
g_nof_streams => c_nof_lanes,
- g_default_value => '0'
+ g_default_value => '1' --default enabled, because standard behaviour is to only pass on packets from lane.
)
PORT MAP (
mm_rst => mm_rst,
@@ -668,7 +681,7 @@ BEGIN
u_mmp_dp_xonoff_local : ENTITY dp_lib.mms_dp_xonoff
GENERIC MAP (
g_nof_streams => c_nof_lanes,
- g_default_value => '0'
+ g_default_value => '0' -- default disabled, because standard behaviour is to only pass on packets from lane.
)
PORT MAP (
mm_rst => mm_rst,
@@ -700,7 +713,17 @@ BEGIN
u_dp_mux : ENTITY dp_lib.dp_mux
GENERIC MAP (
g_append_channel_lo => FALSE,
- g_sel_ctrl_invert => TRUE
+ g_sel_ctrl_invert => TRUE,
+ g_use_fifo => TRUE,
+ g_bsn_w => c_longword_w,
+ g_data_w => c_lane_data_w,
+ g_in_channel_w => c_byte_w,
+ g_error_w => c_nof_err_counts,
+ g_use_bsn => TRUE,
+ g_use_in_channel => TRUE,
+ g_use_error => TRUE,
+ g_use_sync => TRUE,
+ g_fifo_size => array_init(2*c_lane_packet_length, 2)
)
PORT MAP (
rst => dp_rst,
@@ -730,6 +753,7 @@ BEGIN
ring_info => ring_info
);
+
this_rn <= TO_UVEC(TO_UINT(ID) - TO_UINT(ring_info.O_rn), c_byte_w);
-----------------------------------------------------------------------------
@@ -749,7 +773,8 @@ BEGIN
g_validate_err_fifo_size => c_validate_err_fifo_size,
g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
)
PORT MAP (
mm_rst => mm_rst,
@@ -778,8 +803,8 @@ BEGIN
this_rn => this_rn,
N_rn => ring_info.N_rn,
- rx_select => ring_info.rx_select,
- tx_select => ring_info.tx_select
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
);
END GENERATE;
@@ -800,7 +825,8 @@ BEGIN
g_validate_err_fifo_size => c_validate_err_fifo_size,
g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
)
PORT MAP (
mm_rst => mm_rst,
@@ -827,10 +853,10 @@ BEGIN
reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_copi_arr(2*I +1),
reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_cipo_arr(2*I +1),
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.tx_select, -- reverse tx/rx select for odd indices
- tx_select => ring_info.rx_select
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_next_rn, -- reverse tx/rx select for odd indices.
+ tx_select => ring_info.use_cable_to_previous_rn
);
END GENERATE;
@@ -839,21 +865,21 @@ BEGIN
-----------------------------------------------------------------------------
gen_combine: FOR I IN 0 TO c_nof_even_lanes-1 GENERATE
-- QSFP_RX
- lane_rx_cable_even_sosi_arr(I) <= tr_10gbe_src_out_arr(3*I) WHEN ring_info.rx_select = '1' ELSE c_dp_sosi_rst; -- rx_select=1 -> even lanes receive from cable
- lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(3*I) WHEN ring_info.tx_select = '1' ELSE c_dp_sosi_rst; -- tx_select=1 -> odd lanes receive from cable
+ lane_rx_cable_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> even lanes receive from cable
+ lane_rx_cable_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> odd lanes receive from cable
-- QSFP_TX
- tr_10gbe_snk_in_arr(3*I) <= lane_tx_cable_even_sosi_arr(I) WHEN ring_info.tx_select = '1' ELSE -- tx_select=1 -> even lanes transmit to cable
- lane_tx_cable_odd_sosi_arr(I) WHEN ring_info.rx_select = '1' ELSE c_dp_sosi_rst; -- rx_select=1 -> odd lanes transmit to cable
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_even_sosi_arr(I) WHEN ring_info.use_cable_to_next_rn = '1' ELSE -- use_cable_to_next_rn=1 -> even lanes transmit to cable
+ lane_tx_cable_odd_sosi_arr(I) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> odd lanes transmit to cable
-- RING_0_RX even lanes receive from RING_0 (from the left)
- lane_rx_board_even_sosi_arr(I) <= tr_10gbe_src_out_arr(3*I +1);
+ lane_rx_board_even_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_ring_0_if_offset);
-- RING_0_TX odd lanes transmit to RING_0 (to the left)
- tr_10gbe_snk_in_arr(3*I +1) <= lane_tx_board_odd_sosi_arr(I);
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_ring_0_if_offset) <= lane_tx_board_odd_sosi_arr(I);
-- RING_1_RX odd lanes receive from RING_1 (from the right)
- lane_rx_board_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(3*I +2);
+ lane_rx_board_odd_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_ring_1_if_offset);
-- RING_1_TX even lanes transmit to RING_1 (to the right)
- tr_10gbe_snk_in_arr(3*I +2) <= lane_tx_board_odd_sosi_arr(I);
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_ring_1_if_offset) <= lane_tx_board_even_sosi_arr(I);
END GENERATE;
-----------------------------------------------------------------------------
@@ -908,19 +934,19 @@ BEGIN
-- QSFP port, RING_0 port and RING_1 port.
gen_seperate: FOR I IN 0 TO c_nof_even_lanes-1 GENERATE
-- QSFP_TX
- unb2_board_front_io_serial_tx_arr(I) <= tr_10gbe_serial_tx_arr(3*I);
+ unb2_board_front_io_serial_tx_arr(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_qsfp_if_offset);
-- QSFP_RX
- tr_10gbe_serial_rx_arr(3*I) <= unb2_board_front_io_serial_rx_arr(I);
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_qsfp_if_offset) <= unb2_board_front_io_serial_rx_arr(I);
-- RING_0_TX
- i_RING_TX(0)(I) <= tr_10gbe_serial_tx_arr(3*I +1);
+ i_RING_TX(0)(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_ring_0_if_offset);
-- RING_0_RX
- tr_10gbe_serial_rx_arr(3*I +1) <= i_RING_RX(0)(I);
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_ring_0_if_offset) <= i_RING_RX(0)(I);
-- RING_1_TX
- i_RING_TX(1)(I) <= tr_10gbe_serial_tx_arr(3*I +2);
+ i_RING_TX(1)(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_ring_1_if_offset);
-- RING_1_RX
- tr_10gbe_serial_rx_arr(3*I +2) <= i_RING_RX(1)(I);
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_ring_1_if_offset) <= i_RING_RX(1)(I);
END GENERATE;
---------
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
index a29810f9731648d6064292ef758d2777479a1bc3..d13d70eaddae164d72b41ed1d7dc8877316fe959 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
@@ -33,10 +33,11 @@ PACKAGE lofar2_unb2b_ring_pkg IS
TYPE t_lofar2_unb2b_ring_config IS RECORD
N_ring_lanes : NATURAL;
+ reserved : NATURAL; -- adding reserved field as records with 1 field must be intialized differently.
END RECORD;
- CONSTANT c_one : t_lofar2_unb2b_ring_config := (1);
- CONSTANT c_full : t_lofar2_unb2b_ring_config := (8);
+ CONSTANT c_one : t_lofar2_unb2b_ring_config := (1, 0);
+ CONSTANT c_full : t_lofar2_unb2b_ring_config := (8, 0);
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_ring_config;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index 93ac9db79e3f1c1e2d99536b408fc06886a75ec7..349a444c0fca8b442ebebd80404b7bfa4a9c54e8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -78,14 +78,14 @@ PACKAGE qsys_lofar2_unb2b_ring_pkg IS
ram_scrap_reset_export : out std_logic; -- export
ram_scrap_write_export : out std_logic; -- export
ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_address_export : out std_logic_vector(9 downto 0); -- export
reg_bsn_monitor_v2_ring_rx_clk_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_read_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_monitor_v2_ring_rx_reset_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_write_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_rx_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_address_export : out std_logic_vector(9 downto 0); -- export
reg_bsn_monitor_v2_ring_tx_clk_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_tx_read_export : out std_logic; -- export
reg_bsn_monitor_v2_ring_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..66d78fa1775e61531aed243175b985f57b563b96
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -0,0 +1,378 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Self-checking testbench for simulating lofar2_unb2b_ring using BG data.
+--
+-- Description:
+-- See, https://support.astron.nl/confluence/x/jyu7Ag
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, ring_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+USE ring_lib.ring_pkg.ALL;
+USE work.lofar2_unb2b_ring_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_ring IS
+ GENERIC (
+ g_unb_nr : NATURAL := 0;
+ g_design_name : STRING := "lofar2_unb2b_ring_full";
+ g_nof_rn : NATURAL := 3;
+ g_access_scheme : INTEGER RANGE 1 TO 3 := 1
+ );
+END tb_lofar2_unb2b_ring;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_ring IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(g_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(0, c_unb2b_board_nof_chip_w);
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+ CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+ CONSTANT c_cable_delay : TIME := 12 ns;
+
+ CONSTANT c_revision_select : t_lofar2_unb2b_ring_config := func_sel_revision_rec(g_design_name);
+ CONSTANT c_nof_lanes : NATURAL := c_revision_select.N_ring_lanes;
+
+ CONSTANT c_block_period : NATURAL := 1024;
+ CONSTANT c_blocksize : NATURAL := c_sdp_V_ring_pkt_len_max - c_ring_dp_hdr_field_size;
+ CONSTANT c_gapsize : NATURAL := c_block_period - c_blocksize;
+ CONSTANT c_nof_block_per_sync : NATURAL := 3;
+ CONSTANT c_sync_timeout : NATURAL := c_block_period * c_nof_block_per_sync + 10; -- +10 for extra slack
+ CONSTANT c_exp_bsn_at_sync : NATURAL := c_nof_block_per_sync;
+ CONSTANT c_exp_nof_sop : NATURAL := c_nof_block_per_sync;
+ CONSTANT c_exp_nof_valid : NATURAL := c_nof_block_per_sync * c_blocksize;
+
+
+ -- MM
+ CONSTANT c_mm_file_reg_ring_info : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_RING_INFO";
+ CONSTANT c_mm_file_reg_ring_lane_info : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_RING_LANE_INFO";
+ CONSTANT c_mm_file_reg_diag_bg : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_DIAG_BG";
+ CONSTANT c_mm_file_ram_diag_bg : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "RAM_DIAG_BG";
+ CONSTANT c_mm_file_reg_dp_xonoff_lane : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_DP_XONOFF_LANE";
+ CONSTANT c_mm_file_reg_dp_xonoff_local : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_DP_XONOFF_LOCAL";
+ CONSTANT c_mm_file_reg_bsn_monitor_v2_ring_rx : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RING_RX";
+ CONSTANT c_mm_file_reg_bsn_monitor_v2_ring_tx : STRING := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_BSN_MONITOR_V2_RING_TX";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+ SIGNAL i_QSFP_0_TX : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_QSFP_0_RX : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_0_TX : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_0_RX : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_1_TX : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_1_RX : t_unb2b_board_qsfp_bus_2arr(g_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '1';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ SIGNAL SA_CLK : STD_LOGIC := '1';
+
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+ pps_rst <= '0' AFTER c_ext_clk_period*2;
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, pps);
+ ext_pps <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUTs
+ ------------------------------------------------------------------------------
+ gen_dut : FOR I IN 0 TO g_nof_rn -1 GENERATE
+ u_lofar_unb2b_ring : ENTITY work.lofar2_unb2b_ring
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => g_unb_nr,
+ g_sim_node_nr => I,
+ g_sim_sync_timeout => c_sync_timeout
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(g_unb_nr, c_unb2b_board_nof_uniboard_w) & TO_UVEC(I, c_unb2b_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers
+ QSFP_0_RX => i_QSFP_0_RX(I),
+ QSFP_0_TX => i_QSFP_0_TX(I),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(I),
+ RING_0_TX => i_RING_0_TX(I),
+ RING_1_RX => i_RING_1_RX(I),
+ RING_1_TX => i_RING_1_TX(I),
+ -- LEDs
+ QSFP_LED => open
+
+ );
+ END GENERATE;
+
+ -- Ring connections
+ gen_ring : FOR I IN 0 TO g_nof_rn -2 GENERATE
+ -- Connect consecutive nodes with RING interfaces (PCB)
+ i_RING_0_RX(I+1) <= i_RING_1_TX(I);
+ i_RING_1_RX(I) <= i_RING_0_TX(I+1);
+ END GENERATE;
+ -- Connect first and last nodes with QSFP interface.
+ i_QSFP_0_RX(0) <= i_QSFP_0_TX(g_nof_rn-1);
+ i_QSFP_0_RX(g_nof_rn-1) <= i_QSFP_0_TX(0);
+
+
+
+ ------------------------------------------------------------------------------
+ -- MM peripeheral accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ proc_common_wait_until_hi_lo(ext_clk, ext_pps);
+
+ -- Write ring configuration to all nodes.
+ FOR RN IN 0 TO g_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_INFO", 2, g_nof_rn, tb_clk); -- N_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
+ END LOOP;
+
+ -- Start node specific settings
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk); -- use_ring_to_previous_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
+
+ -- End node specific settings
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
+
+ ----------------------------------------------------------------------------
+ -- Access scheme 1. A source RN creates the packets and sends them along the ring.
+ ----------------------------------------------------------------------------
+ IF g_access_scheme = 1 THEN
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ -- Select local input (= 1) on start node on all lanes.
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_lane, I*2, 0, tb_clk); -- Disable input from lane
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_local, I*2, 1, tb_clk); -- Enable local input
+
+ -- Set transport_nof_hops to N_rn on start node for a full transfer around the ring.
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, 0) & "REG_RING_LANE_INFO", I*2+1, g_nof_rn, tb_clk);
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- Access scheme 2, 3. Each RN creates packets and sends them along the ring.
+ ----------------------------------------------------------------------------
+ ELSE
+ FOR RN IN 0 TO g_nof_rn-1 LOOP
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ -- Select both local and remote input on all nodes on all lanes.
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DP_XONOFF_LANE", I*2, 1, tb_clk); -- Enable input from lane
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DP_XONOFF_LOCAL", I*2, 1, tb_clk); -- Enable local input
+
+ -- Set transport_nof_hops to N_rn-1 on all nodes.
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_RING_LANE_INFO", I*2+1, g_nof_rn-1, tb_clk);
+ END LOOP;
+ END LOOP;
+ END IF;
+ ----------------------------------------------------------------------------
+ -- Enable BG on all nodes (for bs_sosi)
+ ----------------------------------------------------------------------------
+ FOR RN IN 0 TO g_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 1, c_blocksize, tb_clk); -- samples per packet
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 2, c_nof_block_per_sync, tb_clk); -- blocks per sync
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 3, c_gapsize, tb_clk); -- gapsize
+ mmf_mm_bus_wr(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_DIAG_BG", 0, 3, tb_clk); -- enable at sync
+ END LOOP;
+ ----------------------------------------------------------------------------
+ -- Verify Access scheme 1 by reading rx / tx monitors on source RN
+ ----------------------------------------------------------------------------
+ IF g_access_scheme = 1 THEN
+ -- Wait for bsn monitor to have received a sync period.
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_monitor_v2_ring_rx, 4, -- read nof valid
+ "SIGNED", rd_data, ">", 0, -- this is the wait until condition
+ 1 us, tb_clk); -- read every 1 us
+
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I*c_sdp_N_pn_max*8+1, rd_data, tb_clk); --bsn at sync
+ ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on source node in access scheme 1." SEVERITY ERROR;
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I*c_sdp_N_pn_max*8+3, rd_data, tb_clk); --nof_sop
+ ASSERT TO_UINT(rd_data) = c_exp_nof_sop REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_tx on source node in access scheme 1." SEVERITY ERROR;
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I*c_sdp_N_pn_max*8+4, rd_data, tb_clk); --nof_valid
+ ASSERT TO_UINT(rd_data) = c_exp_nof_valid REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_tx on source node in access scheme 1." SEVERITY ERROR;
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_tx, I*c_sdp_N_pn_max*8+5, rd_data, tb_clk); --nof_err
+ ASSERT TO_UINT(rd_data) = 0 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_tx on source node in access scheme 1." SEVERITY ERROR;
+
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I*c_sdp_N_pn_max*8+1, rd_data, tb_clk); --bsn at sync
+ ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on source node in access scheme 1." SEVERITY ERROR;
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I*c_sdp_N_pn_max*8+3, rd_data, tb_clk); --nof_sop
+ ASSERT TO_UINT(rd_data) = c_exp_nof_sop REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_rx on source node in access scheme 1." SEVERITY ERROR;
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I*c_sdp_N_pn_max*8+4, rd_data, tb_clk); --nof_valid
+ ASSERT TO_UINT(rd_data) = c_exp_nof_valid REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_rx on source node in access scheme 1." SEVERITY ERROR;
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_v2_ring_rx, I*c_sdp_N_pn_max*8+5, rd_data, tb_clk); --nof_err
+ ASSERT TO_UINT(rd_data) = 0 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_rx on source node in access scheme 1." SEVERITY ERROR;
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- Verify Access scheme 2,3 by reading rx / tx monitors on all RN
+ ----------------------------------------------------------------------------
+ ELSE
+ -- Wait for bsn monitor to have received a sync period.
+ mmf_mm_wait_until_value(mmf_unb_file_prefix(g_unb_nr, g_nof_rn-1) & "REG_BSN_MONITOR_V2_RING_RX", 4, -- read nof valid
+ "SIGNED", rd_data, ">", 0, -- this is the wait until condition
+ 1 us, tb_clk); -- read every 1 us
+
+ FOR RN IN 0 TO g_nof_rn-1 LOOP
+ FOR I IN 0 TO c_nof_lanes-1 LOOP -- lane index
+ FOR J IN 0 TO g_nof_rn-1 LOOP -- bsn_monitor index
+ -- No packets transmitted from next RN (this_rn + 1 for even lanes, this_rn - 1 for odd lanes) as this RN should have removed it from the ring.
+ IF (I MOD 2 = 0 AND (RN + 1) MOD g_nof_rn = J) OR (I MOD 2 = 1 AND (RN + g_nof_rn-1) MOD g_nof_rn = J) THEN
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
+ ASSERT rd_data(2) = '1' REPORT "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ ELSE
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
+ ASSERT rd_data(2) = '0' REPORT "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
+ ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
+ ASSERT TO_UINT(rd_data) = c_exp_nof_sop REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
+ ASSERT TO_UINT(rd_data) = c_exp_nof_valid REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_TX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
+ ASSERT TO_UINT(rd_data) = 0 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_tx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ END IF;
+ IF RN = J THEN -- No packets received from itself as the previous RN should have removed it from the ring.
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
+ ASSERT rd_data(2) = '1' REPORT "Wrong sync_timout, expected 1, got 0. From bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ ELSE
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+0, rd_data, tb_clk); --status bits
+ ASSERT rd_data(2) = '0' REPORT "Wrong sync_timout, expected 0, got 1. From bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+1, rd_data, tb_clk); --bsn at sync
+ ASSERT TO_UINT(rd_data) = c_exp_bsn_at_sync REPORT "Wrong bsn_at_sync value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+3, rd_data, tb_clk); --nof_sop
+ ASSERT TO_UINT(rd_data) = c_exp_nof_sop REPORT "Wrong nof_sop value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+4, rd_data, tb_clk); --nof_valid
+ ASSERT TO_UINT(rd_data) = c_exp_nof_valid REPORT "Wrong nof_valid value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(g_unb_nr, RN) & "REG_BSN_MONITOR_V2_RING_RX", (I*c_sdp_N_pn_max + J) * 8+5, rd_data, tb_clk); --nof_err
+ ASSERT TO_UINT(rd_data) = 0 REPORT "Wrong nof_err value from bsn_monitor_v2_ring_rx on RN_" & INTEGER'IMAGE(RN) & " in access scheme 2/3." SEVERITY ERROR;
+ END IF;
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ END IF;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cc5ea3b82ba95a847162f09ee376614ddc763085
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
@@ -0,0 +1,50 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- Author : R vd Walle
+-- Purpose: Verify multiple variations of tb_lofar2_unb2b_ring
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY tb_tb_lofar2_unb2b_ring IS
+END tb_tb_lofar2_unb2b_ring;
+
+ARCHITECTURE tb OF tb_tb_lofar2_unb2b_ring IS
+ CONSTANT c_nof_rn : NATURAL := 3;
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+BEGIN
+-- g_unb_nr : NATURAL := 0;
+-- g_design_name : STRING := "lofar2_unb2b_ring_full";
+-- g_nof_rn : NATURAL := 3;
+-- g_access_scheme : INTEGER RANGE 1 TO 3 := 1
+
+-- using different g_unb_nr to avoid MM file clashing.
+ u_one_1 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(0, "lofar2_unb2b_ring_one", c_nof_rn, 1); -- access scheme 1.
+ u_one_2_3 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(1, "lofar2_unb2b_ring_one", c_nof_rn, 2); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
+ u_full_1 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(2, "lofar2_unb2b_ring_full", c_nof_rn, 1); -- access scheme 1.
+ u_full_2_3 : ENTITY work.tb_lofar2_unb2b_ring GENERIC MAP(3, "lofar2_unb2b_ring_full", c_nof_rn, 2); -- access scheme 2/3. Tb for access scheme 2 is same tb for 3
+END tb;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index aeaa4b503ef02754561922705d2f9803c9444a18..32abb324a2812acfbe6e082727431fcc0e99f819 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -67,34 +67,36 @@ PACKAGE sdp_pkg is
-------------------------------------------------
-- SDP specific parameters as defined in:
-- L3 SDP Decision: SDP Parameter definitions
- CONSTANT c_sdp_f_adc_MHz : NATURAL := 200;
- CONSTANT c_sdp_N_beamsets : NATURAL := 2;
- CONSTANT c_sdp_N_crosslets_max : NATURAL := 7;
- CONSTANT c_sdp_N_fft : NATURAL := 1024;
- CONSTANT c_sdp_N_pn_lb : NATURAL := 16;
- CONSTANT c_sdp_N_pol : NATURAL := 2;
- CONSTANT c_sdp_N_pol_bf : NATURAL := 2;
- CONSTANT c_sdp_N_ring_lanes_max: NATURAL := 8;
- CONSTANT c_sdp_N_sub : NATURAL := 512;
- CONSTANT c_sdp_N_taps : NATURAL := 16;
- CONSTANT c_sdp_P_sq : NATURAL := 9;
- CONSTANT c_sdp_Q_fft : NATURAL := 2;
- CONSTANT c_sdp_S_pn : NATURAL := 12;
- CONSTANT c_sdp_S_rcu : NATURAL := 3;
- CONSTANT c_sdp_S_sub_bf : NATURAL := 488;
- CONSTANT c_sdp_V_sample_delay : NATURAL := 4096;
- CONSTANT c_sdp_V_si_db : NATURAL := 1024;
- CONSTANT c_sdp_V_si_db_large : NATURAL := 131072;
- CONSTANT c_sdp_V_si_histogram : NATURAL := 512;
- CONSTANT c_sdp_W_adc : NATURAL := 14;
- CONSTANT c_sdp_W_adc_jesd : NATURAL := 16;
- CONSTANT c_sdp_W_fir_coef : NATURAL := 16;
- CONSTANT c_sdp_W_subband : NATURAL := 18;
- CONSTANT c_sdp_W_crosslet : NATURAL := 16;
- CONSTANT c_sdp_W_beamlet_sum : NATURAL := 18;
- CONSTANT c_sdp_W_beamlet : NATURAL := 8;
- CONSTANT c_sdp_W_gn_id : NATURAL := 5;
- CONSTANT c_sdp_W_statistic : NATURAL := 64;
+ CONSTANT c_sdp_f_adc_MHz : NATURAL := 200;
+ CONSTANT c_sdp_N_beamsets : NATURAL := 2;
+ CONSTANT c_sdp_N_crosslets_max : NATURAL := 7;
+ CONSTANT c_sdp_N_fft : NATURAL := 1024;
+ CONSTANT c_sdp_N_pn_lb : NATURAL := 16;
+ CONSTANT c_sdp_N_pn_max : NATURAL := 16;
+ CONSTANT c_sdp_N_pol : NATURAL := 2;
+ CONSTANT c_sdp_N_pol_bf : NATURAL := 2;
+ CONSTANT c_sdp_N_ring_lanes_max : NATURAL := 8;
+ CONSTANT c_sdp_N_sub : NATURAL := 512;
+ CONSTANT c_sdp_N_taps : NATURAL := 16;
+ CONSTANT c_sdp_P_sq : NATURAL := 9;
+ CONSTANT c_sdp_Q_fft : NATURAL := 2;
+ CONSTANT c_sdp_S_pn : NATURAL := 12;
+ CONSTANT c_sdp_S_rcu : NATURAL := 3;
+ CONSTANT c_sdp_S_sub_bf : NATURAL := 488;
+ CONSTANT c_sdp_V_ring_pkt_len_max : NATURAL := 48; -- for 16 nodes
+ CONSTANT c_sdp_V_sample_delay : NATURAL := 4096;
+ CONSTANT c_sdp_V_si_db : NATURAL := 1024;
+ CONSTANT c_sdp_V_si_db_large : NATURAL := 131072;
+ CONSTANT c_sdp_V_si_histogram : NATURAL := 512;
+ CONSTANT c_sdp_W_adc : NATURAL := 14;
+ CONSTANT c_sdp_W_adc_jesd : NATURAL := 16;
+ CONSTANT c_sdp_W_fir_coef : NATURAL := 16;
+ CONSTANT c_sdp_W_subband : NATURAL := 18;
+ CONSTANT c_sdp_W_crosslet : NATURAL := 16;
+ CONSTANT c_sdp_W_beamlet_sum : NATURAL := 18;
+ CONSTANT c_sdp_W_beamlet : NATURAL := 8;
+ CONSTANT c_sdp_W_gn_id : NATURAL := 5;
+ CONSTANT c_sdp_W_statistic : NATURAL := 64;
CONSTANT c_sdp_W_sub_weight : NATURAL := 16; -- = w in s(w, p), s = signed
CONSTANT c_sdp_W_sub_weight_fraction : NATURAL := 13; -- = p in s(w, p)
CONSTANT c_sdp_W_sub_weight_magnitude : NATURAL := c_sdp_W_sub_weight - c_sdp_W_sub_weight_fraction - 1; -- = 2
@@ -346,8 +348,8 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
-- RING MM address widths
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4;
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 4;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
CONSTANT c_sdp_reg_ring_lane_info_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
CONSTANT c_sdp_reg_dp_xonoff_lane_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
CONSTANT c_sdp_reg_dp_xonoff_local_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
index b71ce78bc5cdfcf2bbfbee099bbde6ea961265e9..c21ef65e507057dd120d32a1d9a0f4629863e52a 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
@@ -49,6 +49,7 @@
-- dp_block_validate_bsn_at_sync.vhd on other PN. In this way it is
-- suffiicent to have one instance of dp_block_validate_bsn_at_sync.vhd per
-- PN.
+-- . See, https://support.astron.nl/confluence/x/jyu7Ag
-------------------------------------------------------------------------------
-- REGMAP
-------------------------------------------------------------------------------
@@ -110,6 +111,7 @@ ARCHITECTURE rtl OF dp_block_validate_bsn_at_sync IS
SIGNAL cnt_discarded_en : STD_LOGIC;
SIGNAL out_valid : STD_LOGIC;
+ SIGNAL out_valid_reg : STD_LOGIC;
SIGNAL bsn_ok : STD_LOGIC;
SIGNAL bsn_ok_reg : STD_LOGIC;
SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
@@ -191,15 +193,19 @@ BEGIN
bsn_at_sync <= bs_sosi.bsn WHEN bs_sosi.sync = '1' ELSE bsn_at_sync_reg;
bsn_ok <= bsn_ok_reg WHEN in_sosi.sync = '0' ELSE '1' WHEN in_sosi.bsn = bsn_at_sync ELSE '0';
- out_valid <= bsn_ok WHEN TO_UINT(in_sosi.channel) = g_check_channel ELSE '1';
+ out_valid <= '1' WHEN in_sosi.sop = '1' AND TO_UINT(in_sosi.channel) /= g_check_channel ELSE
+ bsn_ok WHEN in_sosi.sop = '1' AND TO_UINT(in_sosi.channel) = g_check_channel ELSE
+ out_valid_reg;
p_dp_clk : PROCESS(dp_rst, dp_clk)
BEGIN
IF dp_rst='1' THEN
bsn_ok_reg <= '1';
+ out_valid_reg <= '1';
bsn_at_sync_reg <= (OTHERS => '0');
ELSIF rising_edge(dp_clk) THEN
bsn_ok_reg <= bsn_ok;
+ out_valid_reg <= out_valid;
bsn_at_sync_reg <= bsn_at_sync;
END IF;
END PROCESS;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
index fb11b08d928086630b22b7f35b1fd95b9644a950..ead0038c65910aa3c063387457d08300ec968cde 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
@@ -163,9 +163,9 @@ BEGIN
nxt_mon_nof_valid <= nof_valid WHEN sync='1' ELSE i_mon_nof_valid;
nxt_mon_latency <= latency WHEN sync='1' ELSE i_mon_latency;
- nof_sop <= INCR_UVEC(cnt_sop, 1); -- +1 because the sop at the sync also counts
+ nof_sop <= cnt_sop;
nof_err <= cnt_err;
- nof_valid <= INCR_UVEC(cnt_valid, 1); -- +1 because the valid at the sync also counts
+ nof_valid <= cnt_valid;
latency <= cnt_latency;
u_sync_timeout_cnt : ENTITY common_lib.common_counter
@@ -285,8 +285,9 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
- cnt_clr => sync,
+ cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the sop at the sync counts too.
cnt_en => sop,
+ load => TO_SVEC(1, c_cnt_sop_w),
count => cnt_sop
);
@@ -309,8 +310,9 @@ BEGIN
PORT MAP (
rst => rst,
clk => clk,
- cnt_clr => sync,
+ cnt_ld => sync, -- using cnt_ld instead of cnt clr to reset to 1 as the valid at the sync counts too.
cnt_en => valid,
+ load => TO_SVEC(1, c_cnt_valid_w),
count => cnt_valid
);
diff --git a/libraries/base/ring/src/vhdl/ring_info.vhd b/libraries/base/ring/src/vhdl/ring_info.vhd
index 7bf41c8d6e2edf745627030bef40bca86b9e3b20..47e8cdb9fdfbe4e9ea069b85f3067817bf23a863 100644
--- a/libraries/base/ring/src/vhdl/ring_info.vhd
+++ b/libraries/base/ring/src/vhdl/ring_info.vhd
@@ -81,10 +81,10 @@ BEGIN
);
-- get "RW" fields from mm_fields
- ring_info.O_rn <= mm_fields_out(field_hi(c_ring_info_field_arr, "O_rn") DOWNTO field_lo(c_ring_info_field_arr, "O_rn"));
- ring_info.N_rn <= mm_fields_out(field_hi(c_ring_info_field_arr, "N_rn") DOWNTO field_lo(c_ring_info_field_arr, "N_rn"));
- ring_info.rx_select <= mm_fields_out(field_hi(c_ring_info_field_arr, "rx_select") DOWNTO field_lo(c_ring_info_field_arr, "rx_select"))(0);
- ring_info.tx_select <= mm_fields_out(field_hi(c_ring_info_field_arr, "tx_select") DOWNTO field_lo(c_ring_info_field_arr, "tx_select"))(0);
+ ring_info.O_rn <= mm_fields_out(field_hi(c_ring_info_field_arr, "O_rn") DOWNTO field_lo(c_ring_info_field_arr, "O_rn"));
+ ring_info.N_rn <= mm_fields_out(field_hi(c_ring_info_field_arr, "N_rn") DOWNTO field_lo(c_ring_info_field_arr, "N_rn"));
+ ring_info.use_cable_to_previous_rn <= sl(mm_fields_out(field_hi(c_ring_info_field_arr, "use_cable_to_previous_rn") DOWNTO field_lo(c_ring_info_field_arr, "use_cable_to_previous_rn")));
+ ring_info.use_cable_to_next_rn <= sl(mm_fields_out(field_hi(c_ring_info_field_arr, "use_cable_to_next_rn") DOWNTO field_lo(c_ring_info_field_arr, "use_cable_to_next_rn")));
END str;
diff --git a/libraries/base/ring/src/vhdl/ring_lane.vhd b/libraries/base/ring/src/vhdl/ring_lane.vhd
index 3295e70d67e60cd721360dd7402b8c8048cb602e..bf2ba0fe87e0f08e2103f347f725ae8a8a18223b 100644
--- a/libraries/base/ring/src/vhdl/ring_lane.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane.vhd
@@ -53,7 +53,8 @@ ENTITY ring_lane IS
g_validate_err_fifo_size : NATURAL := 1536; -- should be >= g_lane_packet_length
g_bsn_at_sync_check_channel : NATURAL := 1; -- on which channel should the bsn be checked
g_validate_channel : BOOLEAN := TRUE;
- g_validate_channel_mode : STRING := ">"
+ g_validate_channel_mode : STRING := ">";
+ g_sync_timeout : NATURAL := 220*10**6 -- 10% margin
);
PORT (
-- Clocks and reset
@@ -122,7 +123,8 @@ BEGIN
g_block_size => g_lane_packet_length,
g_nof_err_counts => g_nof_err_counts,
g_fifo_size => g_validate_err_fifo_size,
- g_check_channel => g_bsn_at_sync_check_channel
+ g_check_channel => g_bsn_at_sync_check_channel,
+ g_sync_timeout => g_sync_timeout
)
PORT MAP (
mm_rst => mm_rst,
@@ -155,7 +157,8 @@ BEGIN
g_data_w => g_lane_data_w,
g_nof_tx_monitors => g_nof_tx_monitors,
g_validate_channel=> g_validate_channel,
- g_mode => g_validate_channel_mode
+ g_mode => g_validate_channel_mode,
+ g_sync_timeout => g_sync_timeout
)
PORT MAP (
mm_rst => mm_rst,
diff --git a/libraries/base/ring/src/vhdl/ring_pkg.vhd b/libraries/base/ring/src/vhdl/ring_pkg.vhd
index 5af05ebbbe88845840e3b9dfc33fc559ac8d338e..8a41f1b36dc65cc56eee281556e053a713a9957c 100644
--- a/libraries/base/ring/src/vhdl/ring_pkg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_pkg.vhd
@@ -35,24 +35,6 @@ USE common_lib.common_network_layers_pkg.ALL;
PACKAGE ring_pkg is
-- lane info, see https://support.astron.nl/confluence/x/jyu7Ag
--- +====================+========+==============================================================================+===========================+
--- | Field | Access | Description | Remark |
--- +====================+========+==============================================================================+===========================+
--- | transport_nof_hops | RW | Number of hops (N_transport_hops) to transport a packet. The RN will remove | Same setting for all RN |
--- | | | packets that have traveled N_transport_hops hops. If | |
--- | | | N_transport_hops >= N_rn, then the ring cannot remove the packet, because | |
--- | | | then it cannot distinguish between a packet that just starts or that has | |
--- | | | has already been transported along the entire ring, so then the application | |
--- | | | has to take care of removing the packet from the ring (or let it cycle along | |
--- | | | the ring 'forever'). | |
--- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+
--- | lane_direction | RO | 1 = transport in positive RN index direction on lanes with even lane index. 0| Same setting for all RN |
--- | | | = transport in negative RN index direction on lanes with odd lane index. | |
--- | | | Hence for N_lanes = 8, lanes 0, 2, 4, and 6 will transport in positive | |
--- | | | direction, and lanes 1, 3, 5, 7 will transport in opposite (= negative) | |
--- | | | direction. The lane direction is fixed per lane and therefore read only. | |
--- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+
-
TYPE t_lane_info IS RECORD
transport_nof_hops : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
lane_direction : STD_LOGIC;
@@ -66,38 +48,21 @@ PACKAGE ring_pkg is
(field_name_pad("lane_direction"), "RO", 1, field_default(0)) );
-- ring info, see https://support.astron.nl/confluence/x/jyu7Ag
--- +====================+========+==============================================================================+===========================+
--- | Field | Access | Description | Remark |
--- +====================+========+==============================================================================+===========================+
--- | O_rn | RW | Offset index of the first global node (GN) in the ring. | Same setting for all RN |
--- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+
--- | N_rn | RW | The number of ring nodes (RN) in the closed ring. | Same setting for all RN |
--- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+
--- | tx_select | RW | 0 = transmit via on board port, 1 = transmit via cable (QSFP) port. Default | Individual setting per RN |
--- | | | in firmware assume cable between RN on different UniBoard2 and assume cable | |
--- | | | to close the ring defined by ring_info. The programmable tx_select allows | |
--- | | | using cables between other RN in the ring. | |
--- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+
--- | rx_select | RW | 0 = receive via on board port, 1 = receive via cable (QSFP) port. Default in | Individual setting per RN |
--- | | | firmware assume cable between RN on different UniBoard2 and assume cable to | |
--- | | | close the ring defined by ring_info. The programmable rx_select allows using | |
--- | | | cables between other RN in the ring. | |
--- +--------------------+--------+------------------------------------------------------------------------------+---------------------------+
TYPE t_ring_info IS RECORD
- O_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
- N_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
- tx_select : STD_LOGIC;
- rx_select : STD_LOGIC;
+ O_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ N_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+ use_cable_to_next_rn : STD_LOGIC;
+ use_cable_to_previous_rn : STD_LOGIC;
END RECORD;
CONSTANT c_ring_info_rst : t_ring_info :=
( (OTHERS => '0'), (OTHERS => '0'), '0', '0' );
CONSTANT c_ring_info_field_arr : t_common_field_arr(3 DOWNTO 0) :=
- ( (field_name_pad("O_rn"), "RW", 8, field_default( 0)),
- (field_name_pad("N_rn"), "RW", 8, field_default(16)),
- (field_name_pad("tx_select"), "RW", 1, field_default( 0)),
- (field_name_pad("rx_select"), "RW", 1, field_default( 0)) );
+ ( (field_name_pad("O_rn"), "RW", 8, field_default( 0)),
+ (field_name_pad("N_rn"), "RW", 8, field_default(16)),
+ (field_name_pad("use_cable_to_next_rn"), "RW", 1, field_default( 0)),
+ (field_name_pad("use_cable_to_previous_rn"), "RW", 1, field_default( 0)) );
CONSTANT c_ring_eth_dst_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := x"FFFFFFFFFFFF";
CONSTANT c_ring_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0) := x"002286080000";
@@ -113,6 +78,8 @@ PACKAGE ring_pkg is
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(c_ring_eth_src_mac) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(0) )
);
+ CONSTANT c_ring_eth_hdr_field_size : NATURAL := ceil_div(field_slv_len(c_ring_eth_hdr_field_arr), c_longword_w);
+
CONSTANT c_ring_dp_nof_hdr_fields : NATURAL := 6;
CONSTANT c_ring_dp_hdr_field_sel : STD_LOGIC_VECTOR(c_ring_dp_nof_hdr_fields-1 DOWNTO 0) := "000"&"000";
@@ -124,6 +91,7 @@ PACKAGE ring_pkg is
( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
( field_name_pad("dp_bsn" ), "RW", 63, field_default(0) )
);
+ CONSTANT c_ring_dp_hdr_field_size : NATURAL := ceil_div(field_slv_len(c_ring_dp_hdr_field_arr), c_longword_w);
FUNCTION func_nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : NATURAL) RETURN NATURAL;
FUNCTION func_nof_hops_to_source_rn(hops, this_rn, N_rn : STD_LOGIC_VECTOR; lane_dir : NATURAL) RETURN STD_LOGIC_VECTOR; -- return vector length is same as hops vector length
@@ -137,9 +105,9 @@ PACKAGE BODY ring_pkg IS
VARIABLE v_source_rn_nat : NATURAL;
BEGIN
- IF lane_dir > 0 THEN
+ IF lane_dir > 0 THEN --transport in positive direction (even lanes)
v_source_rn := this_rn - hops;
- ELSE
+ ELSE --transport in negative direction (odd lanes)
v_source_rn := this_rn + hops;
END IF;
@@ -147,7 +115,7 @@ PACKAGE BODY ring_pkg IS
v_source_rn := v_source_rn + N_rn;
END IF;
- IF v_source_rn > N_rn THEN
+ IF v_source_rn >= N_rn THEN
v_source_rn := v_source_rn - N_rn;
END IF;
@@ -157,7 +125,7 @@ PACKAGE BODY ring_pkg IS
FUNCTION func_nof_hops_to_source_rn(hops, this_rn, N_rn : STD_LOGIC_VECTOR; lane_dir : NATURAL) RETURN STD_LOGIC_VECTOR IS
BEGIN
- RETURN TO_UVEC(func_nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(N_rn), TO_UINT(N_rn), lane_dir),hops'LENGTH);
+ RETURN TO_UVEC(func_nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(this_rn), TO_UINT(N_rn), lane_dir),hops'LENGTH);
END;
END ring_pkg;
diff --git a/libraries/base/ring/src/vhdl/ring_rx.vhd b/libraries/base/ring/src/vhdl/ring_rx.vhd
index 369cc84298942f58dbad751e5cd4a23cc7eba795..7ac8a4a6e774bad9889adf4aef24d82c972b852d 100644
--- a/libraries/base/ring/src/vhdl/ring_rx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_rx.vhd
@@ -50,7 +50,8 @@ ENTITY ring_rx IS
g_block_size : NATURAL := 1024;
g_nof_err_counts : NATURAL := 1;
g_fifo_size : NATURAL := 1536;
- g_check_channel : NATURAL := 1
+ g_check_channel : NATURAL := 1;
+ g_sync_timeout : NATURAL := 220*10**6 -- 10% margin
);
PORT (
-- Clocks and reset
@@ -83,6 +84,8 @@ ARCHITECTURE str OF ring_rx IS
CONSTANT c_nof_hdr_fields : NATURAL := sel_a_b(g_use_dp_layer, c_ring_dp_nof_hdr_fields, c_ring_eth_nof_hdr_fields);
CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_arr, c_ring_eth_hdr_field_arr);
+ CONSTANT c_hdr_field_size : NATURAL := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size);
+ CONSTANT c_packet_size : NATURAL := g_block_size + c_hdr_field_size;
SIGNAL lane_rx_sosi : t_dp_sosi;
SIGNAL packet_sosi : t_dp_sosi;
@@ -90,9 +93,11 @@ ARCHITECTURE str OF ring_rx IS
SIGNAL offload_rx_sosi : t_dp_sosi;
SIGNAL decoded_sosi : t_dp_sosi;
SIGNAL monitor_sosi : t_dp_sosi;
- SIGNAL monitor_sosi_arr : t_dp_sosi_arr(g_nof_rx_monitors-1 DOWNTO 0);
+ SIGNAL demux_sosi_arr : t_dp_sosi_arr(0 TO g_nof_rx_monitors-1); -- using 0 TO ... as that is the output of the demux
+ SIGNAL monitor_sosi_arr : t_dp_sosi_arr(g_nof_rx_monitors-1 DOWNTO 0);
SIGNAL hdr_fields_out : STD_LOGIC_VECTOR(1023 DOWNTO 0);
+ SIGNAL hdr_fields_raw : STD_LOGIC_VECTOR(1023 DOWNTO 0);
BEGIN
@@ -103,7 +108,7 @@ BEGIN
u_dp_block_validate_length : ENTITY dp_lib.dp_block_validate_length
GENERIC MAP (
g_err_bi => g_err_bi,
- g_expected_length => g_block_size
+ g_expected_length => c_packet_size
)
PORT MAP (
rst => dp_rst,
@@ -116,8 +121,8 @@ BEGIN
-- Validate error field
u_dp_block_validate_err : ENTITY dp_lib.dp_block_validate_err
GENERIC MAP (
- g_max_block_size => g_block_size,
- g_min_block_size => g_block_size,
+ g_max_block_size => c_packet_size,
+ g_min_block_size => c_packet_size,
g_nof_err_counts => g_nof_err_counts,
g_fifo_size => g_fifo_size,
g_data_w => g_data_w
@@ -153,17 +158,18 @@ BEGIN
snk_in_arr(0) => validated_sosi,
src_out_arr(0) => offload_rx_sosi,
- hdr_fields_out_arr(0) => hdr_fields_out
+ hdr_fields_out_arr(0) => hdr_fields_out,
+ hdr_fields_raw_arr(0) => hdr_fields_raw
);
-- Use dp layer
gen_dp_layer : IF g_use_dp_layer GENERATE
- p_set_meta: PROCESS(offload_rx_sosi, hdr_fields_out)
+ p_set_meta: PROCESS(offload_rx_sosi, hdr_fields_out, hdr_fields_raw)
BEGIN
decoded_sosi <= offload_rx_sosi;
- decoded_sosi.sync <= hdr_fields_out(field_hi(c_hdr_field_arr, "dp_sync" ) DOWNTO field_lo(c_hdr_field_arr, "dp_sync" ))(0);
- decoded_sosi.channel <= RESIZE_DP_CHANNEL(hdr_fields_out(field_hi(c_hdr_field_arr, "dp_channel" ) DOWNTO field_lo(c_hdr_field_arr, "dp_channel" )));
- decoded_sosi.bsn <= RESIZE_DP_BSN( hdr_fields_out(field_hi(c_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "dp_bsn" )));
+ decoded_sosi.sync <= sl(hdr_fields_out(field_hi(c_hdr_field_arr, "dp_sync" ) DOWNTO field_lo(c_hdr_field_arr, "dp_sync" )));
+ decoded_sosi.bsn <= RESIZE_DP_BSN( hdr_fields_raw(field_hi(c_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "dp_bsn" )));
+ decoded_sosi.channel <= RESIZE_DP_CHANNEL(hdr_fields_raw(field_hi(c_hdr_field_arr, "dp_channel" ) DOWNTO field_lo(c_hdr_field_arr, "dp_channel" )));
END PROCESS;
-- Validate bsn at sync
@@ -187,7 +193,7 @@ BEGIN
);
-- Convert nof_hops to source RN
- p_hop_to_src_rn: PROCESS(validated_sosi, this_rn, N_rn)
+ p_hop_to_src_rn: PROCESS(decoded_sosi, this_rn, N_rn)
BEGIN
monitor_sosi <= decoded_sosi;
monitor_sosi.channel <= func_nof_hops_to_source_rn(decoded_sosi.channel, this_rn, N_rn, g_lane_direction);
@@ -195,20 +201,21 @@ BEGIN
u_dp_demux : ENTITY dp_lib.dp_demux
GENERIC MAP (
- g_nof_output => g_nof_rx_monitors,
- g_sel_ctrl_invert => TRUE
+ g_nof_output => g_nof_rx_monitors
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => monitor_sosi,
- src_out_arr => monitor_sosi_arr
+ src_out_arr => demux_sosi_arr
);
+ monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr); -- Fix reversed bus.
-- BSN Monitors
u_mms_dp_bsn_monitor_v2 : ENTITY dp_lib.mms_dp_bsn_monitor_v2
GENERIC MAP (
- g_nof_streams => g_nof_rx_monitors
+ g_nof_streams => g_nof_rx_monitors,
+ g_sync_timeout => g_sync_timeout
)
PORT MAP (
mm_rst => mm_rst,
diff --git a/libraries/base/ring/src/vhdl/ring_tx.vhd b/libraries/base/ring/src/vhdl/ring_tx.vhd
index deded34423aa5708da279a613f3b9239497d63ec..3c5b9df0b81f6cd4db1fe75d19bf1cf73bbf3eff 100644
--- a/libraries/base/ring/src/vhdl/ring_tx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_tx.vhd
@@ -45,7 +45,8 @@ ENTITY ring_tx IS
g_ring_pkt_type : STD_LOGIC_VECTOR(c_halfword_w-1 DOWNTO 0) := c_ring_pkt_type_bf;
g_validate_channel : BOOLEAN := TRUE;
g_mode : STRING := ">";
- g_nof_tx_monitors : NATURAL := 1
+ g_nof_tx_monitors : NATURAL := 1;
+ g_sync_timeout : NATURAL := 220*10**6 -- 10% margin
);
PORT (
-- Clocks and reset
@@ -76,7 +77,7 @@ ARCHITECTURE str OF ring_tx IS
CONSTANT c_nof_hdr_fields : NATURAL := sel_a_b(g_use_dp_layer, c_ring_dp_nof_hdr_fields, c_ring_eth_nof_hdr_fields);
CONSTANT c_hdr_field_sel : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_sel, c_ring_eth_hdr_field_sel);
CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_arr, c_ring_eth_hdr_field_arr);
- CONSTANT c_fifo_size : NATURAL := 5; -- Large enough to fit ETH/DP header.
+ CONSTANT c_fifo_size : NATURAL := 8; -- Large enough to fit ETH/DP header (choose power of 2).
SIGNAL validated_sosi : t_dp_sosi;
SIGNAL tx_sosi : t_dp_sosi;
@@ -84,6 +85,7 @@ ARCHITECTURE str OF ring_tx IS
SIGNAL tx_fifo_siso : t_dp_siso;
SIGNAL lane_tx_sosi : t_dp_sosi;
SIGNAL monitor_sosi : t_dp_sosi;
+ SIGNAL demux_sosi_arr : t_dp_sosi_arr(0 TO g_nof_tx_monitors-1); -- using 0 TO ... as that is the output of the demux
SIGNAL monitor_sosi_arr : t_dp_sosi_arr(g_nof_tx_monitors-1 DOWNTO 0);
SIGNAL hdr_fields_in : STD_LOGIC_VECTOR(1023 DOWNTO 0);
@@ -199,19 +201,20 @@ BEGIN
u_dp_demux : ENTITY dp_lib.dp_demux
GENERIC MAP (
- g_nof_output => g_nof_tx_monitors,
- g_sel_ctrl_invert => TRUE
+ g_nof_output => g_nof_tx_monitors
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
snk_in => monitor_sosi,
- src_out_arr => monitor_sosi_arr
+ src_out_arr => demux_sosi_arr
);
+ monitor_sosi_arr <= func_dp_stream_arr_reverse_range(demux_sosi_arr); -- Fix reversed bus.
u_mms_dp_bsn_monitor_v2 : ENTITY dp_lib.mms_dp_bsn_monitor_v2
GENERIC MAP (
- g_nof_streams => g_nof_tx_monitors
+ g_nof_streams => g_nof_tx_monitors,
+ g_sync_timeout => g_sync_timeout
)
PORT MAP (
mm_rst => mm_rst,