From 9502bf9aa65e9a1e49997c160cf5e58301ffd823 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 6 Jan 2022 12:00:40 +0100
Subject: [PATCH] Use technology wrapper of DAC tech_jesd204b_tx in tb.
---
.../technology/jesd204b/tb_tech_jesd204b.vhd | 142 ++++++++++--------
.../jesd204b/tech_jesd204b_component_pkg.vhd | 117 ++++++++++++++-
2 files changed, 198 insertions(+), 61 deletions(-)
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index 7b5bffd1a0..fa72add31a 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -18,26 +18,27 @@
--
-------------------------------------------------------------------------------
--- Author: J Hargreaves
+-- Author: J Hargreaves, E. Kooistra
-- Purpose: Tb for tech_jesd204b IP
-- Description:
-- Includes 3 JESD transmit sources to test multichannel syncronization
-- Relative delays between TX and RX channels can be varied by editing c_delay_*
-- Used default technology e1sg
--- ToDo: Make a tb_tb to run several test cases automatically
+-- TODO:
+-- Make a tb_tb to run several test cases automatically
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 3 # check that the hierarchy for g_design_name is complete (or use do wave_tb_tech_jesd204b.do)
-- > run 120us # enough time to reset and syncronize the JESD IP
-LIBRARY IEEE, common_lib, ip_arria10_e1sg_jesd204b_lib, dp_lib; --, tech_jesd204b_lib;
+LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
+USE work.tech_jesd204b_component_pkg.ALL;
ENTITY tb_tech_jesd204b IS
END tb_tech_jesd204b;
@@ -54,6 +55,10 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- number of jesd204b input sources to instantiate
CONSTANT c_nof_streams_jesd204b : NATURAL := 12; -- number of jesd204b receiver channels
+ CONSTANT c_jesd204b_rx_data_w : NATURAL :=32;
+ CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_jesd204b_rx_somf_w : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
+
-- Transport delays
TYPE t_time_arr IS ARRAY (0 TO c_nof_streams_jesd204b-1) OF TIME;
CONSTANT c_delay_data_arr : t_time_arr := (4000 ps,
@@ -126,6 +131,14 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
SIGNAL rx_sysref : STD_LOGIC := '0';
SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ SIGNAL rx_sosi : t_dp_sosi;
+ SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_jesd204b_rx_framer_data_w-1 DOWNTO 0); -- 16 bit samples
+ SIGNAL rx_sosi_channel : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w-1 DOWNTO 0);
+ SIGNAL rx_sosi_valid : STD_LOGIC;
+ SIGNAL rx_sosi_sync : STD_LOGIC;
+ SIGNAL rx_sosi_sop : STD_LOGIC;
+ SIGNAL rx_sosi_eop : STD_LOGIC;
+
SIGNAL jesd204b_sampclk_fpga : STD_LOGIC := '1';
SIGNAL jesd204b_sampclk_adc : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL jesd204b_sysref_fpga : STD_LOGIC;
@@ -165,7 +178,7 @@ BEGIN
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
- u_jesd204b: ENTITY work.tech_jesd204b
+ u_jesd204b : ENTITY work.tech_jesd204b
GENERIC MAP(
g_sim => c_sim,
g_nof_streams => c_nof_streams_jesd204b,
@@ -218,60 +231,59 @@ BEGIN
-----------------------------------------------------------------------------
gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
- u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
- PORT MAP
- (
- csr_cf => OPEN,
- csr_cs => OPEN,
- csr_f => OPEN,
- csr_hd => OPEN,
- csr_k => OPEN,
- csr_l => OPEN,
- csr_lane_powerdown => open, --out
- csr_m => OPEN,
- csr_n => OPEN,
- csr_np => OPEN,
- csr_tx_testmode => OPEN,
- csr_tx_testpattern_a => OPEN,
- csr_tx_testpattern_b => OPEN,
- csr_tx_testpattern_c => OPEN,
- csr_tx_testpattern_d => OPEN,
- csr_s => OPEN,
- dev_sync_n => dev_sync_n(i), --out
- jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
- jesd204_tx_avs_address => avs_address(i),
- jesd204_tx_avs_read => avs_read(i),
- jesd204_tx_avs_readdata => avs_readdata(i),
- jesd204_tx_avs_waitrequest => open,
- jesd204_tx_avs_write => '0',
- jesd204_tx_avs_writedata => (others => '0'),
- jesd204_tx_avs_clk => mm_clk,
- jesd204_tx_avs_rst_n => avs_rst_n,
- jesd204_tx_dlb_data => open, -- debug/loopback testing
- jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
- jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
- jesd204_tx_frame_error => '0',
- jesd204_tx_int => OPEN, -- Connected to status IO in example design
- jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
- jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
- jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
- mdev_sync_n => dev_sync_n(i), --in
- pll_locked => pll_locked, --in
- sync_n => jesd204b_sync_n_adc(i), --in
- tx_analogreset => tx_analogreset,
- tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
- tx_cal_busy => open,
- tx_digitalreset => tx_digitalreset,
- tx_serial_data => serial_tx(i downto i),
- txlink_clk => txlink_clk(i),
- txlink_rst_n_reset_n => txlink_rst_n,
- txphy_clk => txphy_clk(i downto i),
- somf => OPEN,
- sysref => jesd204b_sysref_adc(i)
- );
+ -- Tb DAC
+ u_tech_jesd204b_tx : ENTITY work.tech_jesd204b_tx
+ PORT MAP (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, --out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), --out
+ jesd204_tx_avs_chipselect => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
+ jesd204_tx_avs_address => avs_address(i),
+ jesd204_tx_avs_read => avs_read(i),
+ jesd204_tx_avs_readdata => avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => mm_clk,
+ jesd204_tx_avs_rst_n => avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
+ mdev_sync_n => dev_sync_n(i), --in
+ pll_locked => pll_locked, --in
+ sync_n => jesd204b_sync_n_adc(i), --in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => serial_tx(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => jesd204b_sysref_adc(i)
+ );
-- Generate test pattern at each ADC
-
proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
VARIABLE data : INTEGER := 0;
VARIABLE even_sample : BOOLEAN := TRUE;
@@ -315,8 +327,6 @@ BEGIN
END IF;
END PROCESS;
-
-
END GENERATE;
@@ -463,6 +473,20 @@ BEGIN
END LOOP;
END PROCESS;
+ ------------------------------------------------------------------------------
+ -- Debug signals
+ ------------------------------------------------------------------------------
+
+ -- Wire rx_sosi_arr(0), because for some reason rx_sosi_arr does not show with as in wave window
+ rx_sosi <= rx_sosi_arr(0);
+ rx_sosi_data <= rx_sosi.data(rx_sosi_data'RANGE);
+ rx_sosi_channel <= rx_sosi.channel(rx_sosi_channel'RANGE);
+ rx_sosi_valid <= rx_sosi.valid;
+ rx_sosi_sync <= rx_sosi.sync;
+ rx_sosi_sop <= rx_sosi.sop;
+ rx_sosi_eop <= rx_sosi.eop;
+
+
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 7b109077f7..b3eeb7fd74 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -35,6 +35,9 @@ PACKAGE tech_jesd204b_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
+ ------------------------------------------------------------------------------
+ -- RX ONLY
+ ------------------------------------------------------------------------------
COMPONENT ip_arria10_e1sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
@@ -43,7 +46,7 @@ PACKAGE tech_jesd204b_component_pkg IS
g_direction : STRING := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_jesd_freq : STRING := "200MHz"
);
- PORT (
+ PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
@@ -70,10 +73,67 @@ PACKAGE tech_jesd204b_component_pkg IS
);
END COMPONENT;
+ ------------------------------------------------------------------------------
+ -- TX ONLY, 1 channel
+ ------------------------------------------------------------------------------
+ component ip_arria10_e1sg_jesd204b_tx is
+ port (
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_tx_avs_read : in std_logic := 'X'; -- read
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_tx_avs_write : in std_logic := 'X'; -- write
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
+ jesd204_tx_frame_error : in std_logic := 'X'; -- export
+ jesd204_tx_frame_ready : out std_logic; -- export
+ jesd204_tx_int : out std_logic; -- irq
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ jesd204_tx_link_valid : in std_logic := 'X'; -- valid
+ jesd204_tx_link_ready : out std_logic; -- ready
+ mdev_sync_n : in std_logic := 'X'; -- export
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ somf : out std_logic_vector(3 downto 0); -- export
+ sync_n : in std_logic := 'X'; -- export
+ sysref : in std_logic := 'X'; -- export
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
+ txlink_clk : in std_logic := 'X'; -- clk
+ txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ txphy_clk : out std_logic_vector(0 downto 0) -- export
+ );
+ end component;
+
+
------------------------------------------------------------------------------
-- ip_arria10_e2sg
------------------------------------------------------------------------------
+ -- RX ONLY
COMPONENT ip_arria10_e2sg_jesd204b IS
GENERIC (
g_sim : BOOLEAN := FALSE;
@@ -81,7 +141,7 @@ PACKAGE tech_jesd204b_component_pkg IS
g_nof_sync_n : NATURAL := 1;
g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
);
- PORT (
+ PORT (
-- JESD204B external signals
jesd204b_refclk : IN STD_LOGIC := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
@@ -106,6 +166,59 @@ PACKAGE tech_jesd204b_component_pkg IS
);
END COMPONENT;
+ -- TX ONLY, 1 channel
+ component ip_arria10_e2sg_jesd204b_tx is
+ port (
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ csr_tx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_tx_testpattern_a : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_b : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_c : out std_logic_vector(31 downto 0); -- export
+ csr_tx_testpattern_d : out std_logic_vector(31 downto 0); -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_tx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_tx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_tx_avs_read : in std_logic := 'X'; -- read
+ jesd204_tx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_tx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_tx_avs_write : in std_logic := 'X'; -- write
+ jesd204_tx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_tx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_tx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_tx_dlb_data : out std_logic_vector(31 downto 0); -- export
+ jesd204_tx_dlb_kchar_data : out std_logic_vector(3 downto 0); -- export
+ jesd204_tx_frame_error : in std_logic := 'X'; -- export
+ jesd204_tx_frame_ready : out std_logic; -- export
+ jesd204_tx_int : out std_logic; -- irq
+ jesd204_tx_link_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
+ jesd204_tx_link_valid : in std_logic := 'X'; -- valid
+ jesd204_tx_link_ready : out std_logic; -- ready
+ mdev_sync_n : in std_logic := 'X'; -- export
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ somf : out std_logic_vector(3 downto 0); -- export
+ sync_n : in std_logic := 'X'; -- export
+ sysref : in std_logic := 'X'; -- export
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_analogreset
+ tx_bonding_clocks : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- tx_digitalreset
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data
+ txlink_clk : in std_logic := 'X'; -- clk
+ txlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ txphy_clk : out std_logic_vector(0 downto 0) -- export
+ );
+ end component;
+
END tech_jesd204b_component_pkg;
PACKAGE BODY tech_jesd204b_component_pkg IS
--
GitLab