diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index c0d6cb97a15dbad02393806ad24f7e19c246fd1f..0ca8a448057a7ebe6079ec8965bd59b5469abd86 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -83,19 +83,20 @@ synth-check-programming-files:
###############################################################################
-# Hardware stage
-# . for some reason we cannot use tags + trigger together. So this will be
-# run on the shared Gitlab runner - which is fine.
+# Trigger hardware test only on merge request
###############################################################################
+
trigger-opc-ua-test:
stage: hardware
+ variables:
+ HDL_BRANCH: '$CI_COMMIT_BRANCH'
only:
changes:
- applications/lofar2/images/lofar2_unb2b_sdp_station_full.tar.gz
-# script:
-# - echo "Found updated programming file. Triggering OPC UA test in SDPTR repo."
+# - merge_requests
+
trigger:
- project: DESP/UPEgear
- branch: L2SDP-535
+ project: LOFAR2.0/sdptr
+ branch: L2SDP-658 #Point to specific branch when needed. Otherwise comment this out to trigger test in downstream master repo.
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
index 80806efb43bcce15c07ffad7edb9687ba4f0cc64..ed1a182056b30b5066dfc16fff58922795a68c6e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/lofar2_unb2b_beamformer.mmap.gold
@@ -162,7 +162,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x0004a008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x0004a009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0004a00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0004a00b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0004a00c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0004a00d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0004a00e 1 RW uint32 b[11:11] - - -
@@ -258,7 +258,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00062008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00062009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0006200a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0006200b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0006200b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0006200c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0006200d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0006200e 1 RW uint32 b[11:11] - - -
@@ -469,4 +469,4 @@ number_of_columns = 13
- - - - - 0x00065c3d - - - b[31:0] b[31:0] - -
REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00066000 1 RO uint32 b[0:0] - - -
- - - - xgmii_tx_ready 0x00066000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00066000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ - - - - xgmii_link_status 0x00066000 1 RO uint32 b[3:2] - - -
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
index 06ef74274b9d1dea1c90fc2eb73d8d9bf0ff6499..1a1c6d657bb44f3a38ef9b3a84c0337d71e53755 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/hdllib.cfg
@@ -8,9 +8,9 @@ hdl_lib_include_ip =
ip_arria10_e1sg_pll_xgmii_mac_clocks
ip_arria10_e1sg_transceiver_pll_10g
ip_arria10_e1sg_phy_10gbase_r
- ip_arria10_e1sg_phy_10gbase_r_3
+ ip_arria10_e1sg_phy_10gbase_r_12
ip_arria10_e1sg_transceiver_reset_controller_1
- ip_arria10_e1sg_transceiver_reset_controller_3
+ ip_arria10_e1sg_transceiver_reset_controller_12
synth_files =
src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index d712c37ea97368476c54d55bfe2a21a23b3517ce..d81af35df4ab5f3cefa898b3df8664bbc1f4f821 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -234,7 +234,14 @@ peripherals:
peripheral_group: sst
mm_port_names:
- REG_STAT_HDR_DAT_SST
-
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: sst_udp
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_SST_OFFLOAD
+
#############################################################################
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
@@ -274,21 +281,21 @@ peripherals:
parameter_overrides:
- { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- - REG_BSN_ALIGN_V2
+ - REG_BSN_ALIGN_V2_XSUB
- peripheral_name: dp/dp_bsn_monitor_v2
- peripheral_group: bsn_align_input
+ peripheral_group: rx_align_xsub
parameter_overrides:
- { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- - REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT
+ - REG_BSN_MONITOR_V2_RX_ALIGN_XSUB
- peripheral_name: dp/dp_bsn_monitor_v2
- peripheral_group: bsn_align_output
+ peripheral_group: aligned_xsub
parameter_overrides:
- { name: g_nof_streams, value: 1 }
mm_port_names:
- - REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT
+ - REG_BSN_MONITOR_V2_ALIGNED_XSUB
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: xst_udp
@@ -358,6 +365,66 @@ peripherals:
mm_port_names:
- RAM_BF_WEIGHTS
+ - peripheral_name: dp/dp_bsn_align_v2
+ peripheral_group: bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 2 }
+ mm_port_names:
+ - REG_BSN_ALIGN_V2_BF
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: rx_align_bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 2 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_RX_ALIGN_BF
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: aligned_bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_ALIGNED_BF
+
+ - peripheral_name: ring/ring_lane_info
+ peripheral_group: bf
+ number_of_peripherals: c_N_beamsets
+ mm_port_names:
+ - REG_RING_LANE_INFO_BF
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: ring_rx_bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_lane_nof_rx_monitors }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_RING_RX_BF
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: ring_tx_bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_lane_nof_tx_monitors }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_RING_TX_BF
+
+ - peripheral_name: dp/dp_block_validate_err
+ peripheral_group: bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_err_counts, value: c_lane_nof_err_counts }
+ mm_port_names:
+ - REG_DP_BLOCK_VALIDATE_ERR_BF
+
+ - peripheral_name: dp/dp_block_validate_bsn_at_sync
+ peripheral_group: bf
+ number_of_peripherals: c_N_beamsets
+ mm_port_names:
+ - REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF
+
- peripheral_name: sdp/sdp_bf_scale
number_of_peripherals: c_N_beamsets
peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
@@ -402,6 +469,22 @@ peripherals:
mm_port_names:
- REG_STAT_HDR_DAT_BST
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: bst_udp
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_BST_OFFLOAD
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: beamlet_output
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_BEAMLET_OUTPUT
+
- peripheral_name: nw_10GbE/nw_10GbE_unb2legacy # For beamlet output
peripheral_group: beamlet_output
parameter_overrides:
@@ -415,6 +498,3 @@ peripherals:
- { name: g_nof_macs, value: 1 }
mm_port_names:
- REG_NW_10GBE_ETH10G
-
-
-
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
index 8b5129a2b8e78b28ab7b7d3045ec87b3b390da04..000138c5c188f46e1979d9d6ca447d8076b6f60f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
@@ -48,7 +48,7 @@ number_of_columns = 13
- - - - expected_cnt 0x00030001 1 RW uint32 b[27:0] - - -
- - - - edge 0x00030001 1 RW uint32 b[31:31] - - -
- - - - offset_cnt 0x00030002 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x00038000 1 WO uint32 b[23:0] - - -
+ REG_EPCS 1 1 REG addr 0x00038000 1 WO uint32 b[31:0] - - -
- - - - rden 0x00038001 1 WO uint32 b[0:0] - - -
- - - - read_bit 0x00038002 1 WO uint32 b[0:0] - - -
- - - - write_bit 0x00038003 1 WO uint32 b[0:0] - - -
@@ -64,8 +64,8 @@ number_of_columns = 13
- - - - param 0x00050001 1 WO uint32 b[2:0] - - -
- - - - read_param 0x00050002 1 WO uint32 b[0:0] - - -
- - - - write_param 0x00050003 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x00050004 1 RO uint32 b[23:0] - - -
- - - - - data_in 0x00050005 1 WO uint32 b[23:0] - - -
+ - - - - data_out 0x00050004 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x00050005 1 WO uint32 b[31:0] - - -
- - - - busy 0x00050006 1 RO uint32 b[0:0] - - -
REG_SDP_INFO 1 1 REG block_period 0x00058000 1 RO uint32 b[15:0] - - -
- - - - beam_repositioning_flag 0x00058001 1 RW uint32 b[0:0] - - -
@@ -172,7 +172,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x000e8008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x000e8009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x000e800a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x000e800b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x000e800b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x000e800c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x000e800d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x000e800e 1 RW uint32 b[11:11] - - -
@@ -205,18 +205,27 @@ number_of_columns = 13
- - - - eth_destination_mac 0x000e8029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x000e802a - - - b[15:0] b[47:32] - -
- - - - word_align 0x000e802b 1 RW uint32 b[15:0] - - -
- REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000f0000 1 RW uint32 b[0:0] - - -
- - - - - ctrl_interval_size 0x000f0001 1 RW uint32 b[30:0] - - -
- - - - - ctrl_start_bsn 0x000f0002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000f0003 - - - b[31:0] b[63:32] - -
- - - - - mon_current_input_bsn 0x000f0004 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000f0005 - - - b[31:0] b[63:32] - -
- - - - - mon_input_bsn_at_sync 0x000f0006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000f0007 - - - b[31:0] b[63:32] - -
- - - - - mon_output_enable 0x000f0008 1 RO uint32 b[0:0] - - -
- - - - - mon_output_sync_bsn 0x000f0009 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000f000a - - - b[31:0] b[63:32] - -
- - - - - block_size 0x000f000b 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x000f0000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x000f0000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000f0000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000f0001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f0002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000f0003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000f0004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000f0005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000f0008 1 RO uint32 b[31:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000f8000 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x000f8001 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x000f8002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f8003 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x000f8004 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f8005 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x000f8006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f8007 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x000f8008 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x000f8009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f800a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x000f800b 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00100000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00100001 - - - b[31:0] b[63:32] - -
- - - - - 0x00100002 - - - b[31:0] b[95:64] - -
@@ -241,7 +250,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00128008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00128009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0012800a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0012800b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0012800b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0012800c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0012800d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0012800e 1 RW uint32 b[11:11] - - -
@@ -274,8 +283,9 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00128029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0012802a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0012802b 1 RW uint32 b[15:0] - - -
- REG_BSN_ALIGN 1 9 REG enable 0x00130000 1 RW uint32 b[0:0] - - 1
- REG_BSN_MONITOR_V2_BSN_ALIGN_INPUT 1 9 REG xon_stable 0x00138000 1 RO uint32 b[0:0] - - 8
+ REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00130000 1 RW uint32 b[0:0] - - 2
+ - - - - replaced_pkt_cnt 0x00130001 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00138000 1 RO uint32 b[0:0] - - 8
- - - - ready_stable 0x00138000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00138000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00138001 1 RO uint64 b[31:0] b[31:0] - -
@@ -284,7 +294,7 @@ number_of_columns = 13
- - - - nof_valid 0x00138004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00138005 1 RO uint32 b[31:0] - - -
- - - - latency 0x00138008 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_BSN_ALIGN_OUTPUT 1 1 REG xon_stable 0x00140000 1 RO uint32 b[0:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00140000 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00140000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00140000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00140001 1 RO uint64 b[31:0] b[31:0] - -
@@ -293,7 +303,7 @@ number_of_columns = 13
- - - - nof_valid 0x00140004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00140005 1 RO uint32 b[31:0] - - -
- - - - latency 0x00140008 1 RO uint32 b[31:0] - - -
- REG_XST_UDP_MONITOR 1 1 REG xon_stable 0x00148000 1 RO uint32 b[0:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00148000 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00148000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00148000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00148001 1 RO uint64 b[31:0] b[31:0] - -
@@ -510,276 +520,341 @@ number_of_columns = 13
- - - - xgmii_link_status 0x00180000 1 RO uint32 b[3:2] - - -
RAM_SS_SS_WIDE 2 6 RAM data 0x00188000 976 RW uint32 b[9:0] - 8192 1024
RAM_BF_WEIGHTS 2 12 RAM data 0x00190000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x00198000 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x00198001 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x001a0000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x001a0001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x001a0002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x001a0003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x001a0004 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x001a0005 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x001a0006 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x001a0007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x001a0008 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x001a0009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x001a000a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x001a000b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x001a000c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x001a000d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x001a000e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x001a000f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x001a0010 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x001a0011 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x001a0012 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x001a0013 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x001a0014 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x001a0015 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x001a0016 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x001a0017 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x001a0018 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x001a0019 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x001a001a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x001a001b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x001a001c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x001a001d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x001a001e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x001a001f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x001a0020 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x001a0021 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x001a0022 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x001a0023 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x001a0024 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x001a0025 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x001a0026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x001a0027 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x001a0028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x001a0029 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x001a8000 1 RW uint32 b[0:0] - 2 2
- RAM_ST_BST 2 1 RAM data 0x001b0000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - - 0x001b0001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x001b8000 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x001c0000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x001c0001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x001c0002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x001c0003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x001c0004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x001c0005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x001c0006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x001c0006 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x001c0006 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x001c0007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x001c0008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x001c0009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x001c000a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x001c000b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x001c000c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x001c000d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x001c000e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x001c000f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x001c0010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x001c0011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x001c0012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x001c0013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x001c0014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x001c0015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x001c0016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x001c0017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x001c0018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x001c0019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x001c001a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x001c001b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x001c001c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x001c001d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x001c001e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x001c001f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x001c0020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x001c0021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x001c0022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x001c0023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x001c0024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x001c0025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x001c0026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x001c0027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x001c0028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x001c0029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x001c002a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x001c002b 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x001c8000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x001c8001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x001c8002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x001c8040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x001c8080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x001c80c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c80c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x001c80c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c80c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x001c8100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x001c8140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x001c8800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x001c8801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x001c8802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x001c8803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x001c8804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x001c8805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x001c8806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x001c8807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x001c8808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x001c8809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x001c880a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x001c880b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x001c8818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x001c8c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x001c8c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x001c8c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x001c8c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x001c8c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x001c8c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x001c8c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x001c8c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x001c8c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x001c8c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x001c8c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x001c8c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x001c8c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x001c8c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x001c8c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x001c8c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x001c8c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x001c8c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x001c8c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x001c8c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x001c8c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x001c8c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x001c8c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x001c8c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x001c8c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x001c8c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x001c8c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x001c8c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x001c8c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x001c8c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x001c8c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c8c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x001c9001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x001c9040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x001c9080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x001c90c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c90c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x001c9100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x001c9140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x001c9141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x001c9142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x001c9180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x001c9181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x001c9182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x001c9183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x001c9184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x001c9185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x001c9186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x001c9187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x001c9190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x001c9191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x001c9192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x001c9193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x001c9194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x001c9195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x001c9196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x001c9197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x001c91a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x001c9200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x001c9201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x001c9202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x001c9801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x001c9c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x001c9c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x001c9c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x001c9c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x001c9c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x001c9c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x001c9c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x001c9c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x001c9c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x001c9c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x001c9c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x001c9c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x001c9c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x001c9c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x001c9c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x001c9c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x001c9c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x001c9c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x001c9c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x001c9c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x001c9c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x001c9c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x001c9c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x001c9c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x001c9c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x001c9c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x001c9c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x001c9c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x001c9c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x001c9c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x001c9c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x001c9c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x001d0000 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x001d0000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x001d0000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00198000 1 RW uint32 b[0:0] - 1 2
+ - - - - replaced_pkt_cnt 0x00198001 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x001a0000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x001a0000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x001a0000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x001a0001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001a0002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x001a0003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x001a0004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x001a0005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x001a0008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x001a8000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x001a8000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x001a8000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x001a8001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001a8002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x001a8003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x001a8004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x001a8005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
+ - - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001b8002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x001b8003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001c0002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x001c0003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x001c0004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x001c0005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x001c0008 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x001c8000 8 RO uint32 b[31:0] - 1 16
+ - - - - total_discarded_blocks 0x001c8008 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x001c8009 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x001c800a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x001d0000 1 RO uint32 b[31:0] - 1 4
+ - - - - nof_sync 0x001d0001 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x001d0002 1 RW uint32 b[31:0] - - -
+ REG_BF_SCALE 2 1 REG scale 0x001d8000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x001d8001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x001e0000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x001e0001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x001e0002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x001e0003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x001e0004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x001e0005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x001e0006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x001e0007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001e0008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x001e0009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x001e000a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x001e000b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x001e000c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x001e000d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x001e000e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x001e000f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x001e0010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x001e0011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x001e0012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x001e0013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x001e0014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x001e0015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x001e0016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x001e0017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x001e0018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x001e0019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x001e001a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x001e001b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x001e001c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x001e001d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x001e001e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x001e001f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x001e0020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x001e0021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x001e0022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x001e0023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x001e0024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x001e0025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x001e0026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001e0027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x001e0028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001e0029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x001e8000 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x001f0000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x001f0001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x001f8000 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00200000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00200001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00200002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00200003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00200004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00200005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00200006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00200006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00200006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00200007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00200008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00200009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0020000a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0020000b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0020000c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0020000d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0020000e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0020000f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00200010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00200011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00200012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00200013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00200014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00200015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00200016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00200017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00200018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00200019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0020001a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0020001b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0020001c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0020001d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0020001e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0020001f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00200020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00200021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00200022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00200023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00200024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00200025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00200026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00200027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00200028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00200029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0020002a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0020002b 1 RW uint32 b[15:0] - - -
+ REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00208000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00208000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00208000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00208001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00208002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00208003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00208004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00208005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00208008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00210000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00210000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00210000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00210001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00210002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00210003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00210004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00210005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00210008 1 RO uint32 b[31:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00218000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00218001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00218002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00218040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00218080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x002180c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x002180c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x002180c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x002180c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00218100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00218140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00218800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00218801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00218802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00218803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00218804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00218805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00218806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00218807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00218808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00218809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0021880a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0021880b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00218818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00218c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00218c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00218c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00218c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00218c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00218c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00218c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00218c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00218c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00218c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00218c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00218c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00218c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00218c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00218c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00218c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00218c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00218c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00218c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00218c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00218c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00218c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00218c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00218c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00218c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00218c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00218c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00218c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00218c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00218c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00218c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00219001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00219040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00219080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x002190c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x002190c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00219100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00219140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00219141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00219142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00219180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00219181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00219182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00219183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00219184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00219185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00219186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00219187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00219190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00219191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00219192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00219193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00219194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00219195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00219196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00219197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x002191a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00219200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00219201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00219202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00219801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00219c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00219c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00219c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00219c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00219c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00219c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00219c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00219c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00219c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00219c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00219c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00219c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00219c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00219c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00219c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00219c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00219c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00219c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00219c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00219c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00219c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00219c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00219c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00219c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00219c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00219c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00219c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00219c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00219c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00219c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00219c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00220000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00220000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00220000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
index 3c27ce464b71aa6706fd57f98d98d7a74d415cea..bfc94ce8760a37cf31647ac9bbcaa952a8208549 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.qsys.gold
@@ -36,51 +36,51 @@ number_of_columns = 13
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043210 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x000431e0 6 RO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043498 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00043450 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x00000c10 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x000433e0 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x0004323c 1 RO uint32 b[29:0] - - -
- - - - - stable 0x0004323c 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x0004323c 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x0004323d 1 RW uint32 b[27:0] - - -
- - - - - edge 0x0004323d 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x0004323e 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x00043218 1 WO uint32 b[31:0] - - -
- - - - - rden 0x00043219 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x0004321a 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x0004321b 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x0004321c 1 WO uint32 b[0:0] - - -
- - - - - busy 0x0004321d 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x0004321e 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043256 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x00043254 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x00043252 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x00043253 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x00043250 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x00043220 1 WO uint32 b[31:0] - - -
- - - - - param 0x00043221 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x00043222 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x00043223 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x00043224 1 RO uint32 b[31:0] - - -
- - - - - data_in 0x00043225 1 WO uint32 b[31:0] - - -
- - - - - busy 0x00043226 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x000431d0 1 RO uint32 b[15:0] - - -
- - - - - beam_repositioning_flag 0x000431d1 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x000431d2 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x000431d3 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x000431d4 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x000431d5 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x000431d6 1 RW uint32 b[0:0] - - -
- - - - - station_id 0x000431d7 1 RW uint32 b[15:0] - - -
- REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x00043228 1 RW uint32 b[0:0] - - -
- - - - - use_cable_to_next_rn 0x00043229 1 RW uint32 b[0:0] - - -
- - - - - n_rn 0x0004322a 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x0004322b 1 RW uint32 b[7:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x00043246 1 RW uint32 b[30:0] - - -
- - - - - reset 0x00043246 1 RW uint32 b[31:31] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x000434c8 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x000434c8 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x000434c8 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x000434c9 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x000434c9 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x000434ca 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x000434a0 1 WO uint32 b[31:0] - - -
+ - - - - rden 0x000434a1 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x000434a2 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x000434a3 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x000434a4 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x000434a5 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x000434a6 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x000434e2 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x000434e0 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x000434de 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x000434df 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x000434dc 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x000434a8 1 WO uint32 b[31:0] - - -
+ - - - - param 0x000434a9 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x000434aa 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x000434ab 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x000434ac 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x000434ad 1 WO uint32 b[31:0] - - -
+ - - - - busy 0x000434ae 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x00043440 1 RO uint32 b[15:0] - - -
+ - - - - beam_repositioning_flag 0x00043441 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x00043442 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x00043443 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x00043444 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x00043445 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x00043446 1 RW uint32 b[0:0] - - -
+ - - - - station_id 0x00043447 1 RW uint32 b[15:0] - - -
+ REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x000434b4 1 RW uint32 b[0:0] - - -
+ - - - - use_cable_to_next_rn 0x000434b5 1 RW uint32 b[0:0] - - -
+ - - - - n_rn 0x000434b6 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x000434b7 1 RW uint32 b[7:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x000434d2 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x000434d2 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
- - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
- - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
@@ -118,47 +118,47 @@ number_of_columns = 13
- - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00043180 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043208 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00043208 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x00043209 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x0004320a 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004320b - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x0004320c 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0004324c 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004324d - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x00043080 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x00043080 1 RW uint32 b[31:16] - - -
- - - - - phase 0x00043081 1 RW uint32 b[15:0] - - -
- - - - - freq 0x00043082 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x00043083 1 RW uint32 b[16:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x000433c0 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043490 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00043490 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00043491 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00043492 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043493 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00043494 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x000434d8 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000434d9 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00043000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00043006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00043008 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00043280 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x00043280 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00043281 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00043282 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00043283 1 RW uint32 b[16:0] - - -
RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024
RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x000430c0 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x000430c1 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x000430c2 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x000430c3 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000c20 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x00000c21 1 RO uint32 b[31:0] - - -
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x000432c0 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x000432c1 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x000432c2 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x000432c3 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x000433a0 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x000433a1 1 RO uint32 b[31:0] - - -
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
- REG_SI 1 1 REG enable 0x0004324e 1 RW uint32 b[0:0] - - -
+ REG_SI 1 1 REG enable 0x000434da 1 RW uint32 b[0:0] - - -
RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x0004324a 1 RW uint32 b[0:0] - - -
+ REG_DP_SELECTOR 1 1 REG input_select 0x000434d6 1 RW uint32 b[0:0] - - -
RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x00043244 1 RW uint32 b[0:0] - - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x000434d0 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
@@ -172,7 +172,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
@@ -205,27 +205,36 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
- REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000431b0 1 RW uint32 b[0:0] - - -
- - - - - ctrl_interval_size 0x000431b1 1 RW uint32 b[30:0] - - -
- - - - - ctrl_start_bsn 0x000431b2 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431b3 - - - b[31:0] b[63:32] - -
- - - - - mon_current_input_bsn 0x000431b4 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431b5 - - - b[31:0] b[63:32] - -
- - - - - mon_input_bsn_at_sync 0x000431b6 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431b7 - - - b[31:0] b[63:32] - -
- - - - - mon_output_enable 0x000431b8 1 RO uint32 b[0:0] - - -
- - - - - mon_output_sync_bsn 0x000431b9 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431ba - - - b[31:0] b[63:32] - -
- - - - - block_size 0x000431bb 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x00043470 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043470 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043470 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043471 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043472 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043473 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043474 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043475 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043478 1 RO uint32 b[31:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00043420 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x00043421 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x00043422 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043423 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x00043424 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043425 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x00043426 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043427 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x00043428 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x00043429 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004342a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x0004342b 1 RO uint32 b[31:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - 0x00010001 - - - b[31:0] b[63:32] - -
- - - - - 0x00010002 - - - b[31:0] b[95:64] - -
- - - - - 0x00010003 - - - b[31:0] b[127:96] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x000431c0 15 RW uint32 b[31:0] - - -
- - - - - step 0x000431cf 1 RW uint32 b[31:0] - - -
- REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00043240 1 RW uint32 b[31:0] - - -
- - - - - unused 0x00043241 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x00043242 1 RW uint32 b[0:0] - - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00043430 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0004343f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x000434cc 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x000434cd 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x000434ce 1 RW uint32 b[0:0] - - -
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
@@ -241,7 +250,7 @@ number_of_columns = 13
- - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0000004b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
@@ -274,35 +283,35 @@ number_of_columns = 13
- - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
- REG_BSN_ALIGN_V2 1 9 REG enable 0x00000020 1 RW uint32 b[0:0] - - 2
- - - - - replaced_pkt_cnt 0x00000021 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT 1 9 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - - 8
- - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT 1 1 REG xon_stable 0x00043200 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00043200 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00043200 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00043201 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043202 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00043203 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00043204 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00043205 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043208 1 RO uint32 b[31:0] - - -
- REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x000431f8 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x000431f8 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x000431f8 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x000431f9 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000431fa - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x000431fb 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x000431fc 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x000431fd 1 RO uint32 b[31:0] - - -
- - - - - latency 0x00043200 1 RO uint32 b[31:0] - - -
+ REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043380 1 RW uint32 b[0:0] - - 2
+ - - - - replaced_pkt_cnt 0x00043381 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00043100 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00043100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043105 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043108 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00043488 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043488 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043488 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043489 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004348a - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004348b 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004348c 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004348d 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043490 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043480 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043480 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043480 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043481 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043482 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043483 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043484 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043485 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043488 1 RO uint32 b[31:0] - - -
REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
- - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8
@@ -323,13 +332,13 @@ number_of_columns = 13
- - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
- - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x000431a0 8 RO uint32 b[31:0] - - -
- - - - - total_discarded_blocks 0x000431a8 1 RO uint32 b[31:0] - - -
- - - - - total_block_count 0x000431a9 1 RO uint32 b[31:0] - - -
- - - - - clear 0x000431aa 1 RW uint32 b[31:0] - - -
- REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x0004322c 1 RO uint32 b[31:0] - - -
- - - - - nof_sync 0x0004322d 1 RO uint32 b[31:0] - - -
- - - - - clear 0x0004322e 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043410 8 RO uint32 b[31:0] - - -
+ - - - - total_discarded_blocks 0x00043418 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x00043419 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004341a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x000434b8 1 RO uint32 b[31:0] - - -
+ - - - - nof_sync 0x000434b9 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x000434ba 1 RW uint32 b[31:0] - - -
REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
- - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
@@ -506,105 +515,170 @@ number_of_columns = 13
- - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
- REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x000431f0 1 RO uint32 b[0:0] - - 1
- - - - - xgmii_tx_ready 0x000431f0 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x000431f0 1 RO uint32 b[3:2] - - -
+ REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00043478 1 RO uint32 b[0:0] - - 1
+ - - - - xgmii_tx_ready 0x00043478 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00043478 1 RO uint32 b[3:2] - - -
RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x00043238 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x00043239 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00043000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00043001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00043002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00043003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00043004 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00043005 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00043006 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00043007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043008 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00043009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0004300a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0004300b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004300c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004300d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004300e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0004300f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00043010 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00043011 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00043012 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00043013 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00043014 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00043015 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00043016 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00043017 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00043018 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00043019 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004301a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004301b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004301c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004301d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004301e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0004301f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00043020 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00043021 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00043022 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00043023 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00043024 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00043025 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00043026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043027 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00043028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00043029 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x00043234 1 RW uint32 b[0:0] - 2 2
+ REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00043460 1 RW uint32 b[0:0] - 1 2
+ - - - - replaced_pkt_cnt 0x00043461 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000c21 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c22 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000c23 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000c28 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00000c10 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00000c10 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000c10 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000c11 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c12 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000c13 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000c14 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000c15 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000c18 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x00000c04 1 RO uint32 b[0:0] - 1 2
+ - - - - transport_nof_hops 0x00000c05 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16
+ - - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0000002a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00000c08 1 RO uint32 b[31:0] - 1 4
+ - - - - nof_sync 0x00000c09 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x00000c0a 1 RW uint32 b[31:0] - - -
+ REG_BF_SCALE 2 1 REG scale 0x000434c4 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x000434c5 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00043200 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00043201 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00043202 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00043203 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00043204 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00043205 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00043206 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00043207 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043208 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00043209 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0004320a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0004320b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004320c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004320d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004320e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004320f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00043210 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00043211 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00043212 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00043213 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00043214 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00043215 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00043216 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00043217 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00043218 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00043219 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004321a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004321b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004321c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004321d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004321e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004321f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00043220 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00043221 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00043222 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00043223 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00043224 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00043225 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00043226 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043227 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00043228 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043229 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x000434c0 1 RW uint32 b[0:0] - 2 2
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00001001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x00043230 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000d80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00000d81 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00000d82 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00000d83 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00000d84 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00000d85 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000d86 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00000d86 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00000d86 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x00000d87 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000d88 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000d89 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x00000d8a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x00000d8b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x00000d8c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x00000d8d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x00000d8e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x00000d8f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000d90 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000d91 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000d92 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000d93 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000d94 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000d95 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000d96 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000d97 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000d98 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000d99 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00000d9a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x00000d9b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x00000d9c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x00000d9d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x00000d9e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x00000d9f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000da0 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000da1 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000da2 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000da3 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000da4 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000da5 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000da6 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000da7 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000da8 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000da9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000daa - - - b[15:0] b[47:32] - -
- - - - - word_align 0x00000dab 1 RW uint32 b[15:0] - - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x000434bc 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00043180 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00043181 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00043182 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00043183 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00043184 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00043185 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00043186 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00043186 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00043186 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00043187 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00043188 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00043189 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0004318a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0004318b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0004318c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004318d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004318e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004318f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00043190 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00043191 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00043192 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00043193 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00043194 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00043195 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00043196 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00043197 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00043198 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00043199 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0004319a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004319b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004319c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004319d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004319e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004319f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x000431a0 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x000431a1 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x000431a2 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x000431a3 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x000431a4 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x000431a5 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x000431a6 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x000431a7 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431a8 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x000431a9 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431aa - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x000431ab 1 RW uint32 b[15:0] - - -
+ REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043400 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043400 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043400 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043401 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043402 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043403 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043404 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043405 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043408 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x000433f0 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x000433f0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000433f0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000433f1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000433f2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000433f3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000433f4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000433f5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000433f8 1 RO uint32 b[31:0] - - -
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
@@ -781,6 +855,6 @@ number_of_columns = 13
- - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00043248 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x00043248 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00043248 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x000434d4 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x000434d4 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x000434d4 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
index f2de5dfb644c030a75c8548817026f755675bdf9..f1f05baafbd66243f24abbd85ec4da4299f1c00c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C7C0' end='0x10C7E0' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C7E0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_remu.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C8A0' end='0x10C8B0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C8B0' end='0x10C8C0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C8C0' end='0x10C8D0' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C8D0' end='0x10C8E0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C8E0' end='0x10C8F0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C8F0' end='0x10C900' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C900' end='0x10C908' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C908' end='0x10C910' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C910' end='0x10C918' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C918' end='0x10C920' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C920' end='0x10C928' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C928' end='0x10C930' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C930' end='0x10C938' datawidth='32' /><slave name='reg_si.mem' start='0x10C938' end='0x10C940' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C940' end='0x10C948' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C948' end='0x10C950' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10C950' end='0x10C958' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10C958' end='0x10C960' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C960' end='0x10C968' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10CC00' end='0x10CD00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10CD00' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CE00' end='0x10CE80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CE80' end='0x10CF00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CF00' end='0x10CF80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CF80' end='0x10CFC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CFC0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10D000' end='0x10D040' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10D040' end='0x10D080' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10D080' end='0x10D0C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10D0C0' end='0x10D100' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10D100' end='0x10D140' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10D140' end='0x10D180' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10D180' end='0x10D1A0' datawidth='32' /><slave name='timer_0.s1' start='0x10D1A0' end='0x10D1C0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10D1C0' end='0x10D1E0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10D1E0' end='0x10D200' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D200' end='0x10D220' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D220' end='0x10D240' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D240' end='0x10D260' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D260' end='0x10D280' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D280' end='0x10D2A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D2A0' end='0x10D2C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D2C0' end='0x10D2D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D2D0' end='0x10D2E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D2E0' end='0x10D2F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D2F0' end='0x10D300' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D300' end='0x10D310' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D310' end='0x10D320' datawidth='32' /><slave name='pio_pps.mem' start='0x10D320' end='0x10D330' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D330' end='0x10D338' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D338' end='0x10D340' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D340' end='0x10D348' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D348' end='0x10D350' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D350' end='0x10D358' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D358' end='0x10D360' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D360' end='0x10D368' datawidth='32' /><slave name='reg_si.mem' start='0x10D368' end='0x10D370' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D370' end='0x10D378' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D378' end='0x10D380' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D380' end='0x10D388' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D388' end='0x10D390' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D390' end='0x10D398' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C7C0' end='0x10C7E0' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C7E0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_remu.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C8A0' end='0x10C8B0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C8B0' end='0x10C8C0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C8C0' end='0x10C8D0' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C8D0' end='0x10C8E0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C8E0' end='0x10C8F0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C8F0' end='0x10C900' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C900' end='0x10C908' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C908' end='0x10C910' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C910' end='0x10C918' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C918' end='0x10C920' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C920' end='0x10C928' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C928' end='0x10C930' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C930' end='0x10C938' datawidth='32' /><slave name='reg_si.mem' start='0x10C938' end='0x10C940' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C940' end='0x10C948' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C948' end='0x10C950' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10C950' end='0x10C958' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10C958' end='0x10C960' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C960' end='0x10C968' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10CC00' end='0x10CD00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10CD00' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CE00' end='0x10CE80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CE80' end='0x10CF00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CF00' end='0x10CF80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CF80' end='0x10CFC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CFC0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10D000' end='0x10D040' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10D040' end='0x10D080' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10D080' end='0x10D0C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10D0C0' end='0x10D100' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10D100' end='0x10D140' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10D140' end='0x10D180' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10D180' end='0x10D1A0' datawidth='32' /><slave name='timer_0.s1' start='0x10D1A0' end='0x10D1C0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10D1C0' end='0x10D1E0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10D1E0' end='0x10D200' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D200' end='0x10D220' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D220' end='0x10D240' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D240' end='0x10D260' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D260' end='0x10D280' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D280' end='0x10D2A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D2A0' end='0x10D2C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D2C0' end='0x10D2D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D2D0' end='0x10D2E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D2E0' end='0x10D2F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D2F0' end='0x10D300' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D300' end='0x10D310' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D310' end='0x10D320' datawidth='32' /><slave name='pio_pps.mem' start='0x10D320' end='0x10D330' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D330' end='0x10D338' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D338' end='0x10D340' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D340' end='0x10D348' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D348' end='0x10D350' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D350' end='0x10D358' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D358' end='0x10D360' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D360' end='0x10D368' datawidth='32' /><slave name='reg_si.mem' start='0x10D368' end='0x10D370' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D370' end='0x10D378' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D378' end='0x10D380' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D380' end='0x10D388' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D388' end='0x10D390' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D390' end='0x10D398' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..76d1efff147c48dd25ee577b1c9d9e475f0809ff
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>2</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>2</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
index 04f98e5482cf16a99885fe4325448bc1dcf36840..0991715aa4440ec3362fafcfc7ed0a299814f647 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..09ad95c7748768eadc77b404878324e54757ee31
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
index 7dc82c1611c7596e8f79093353edfa6de67b0d3a..2744e22ae95c2057b9b721d8ae40c5c3855a9615 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
new file mode 100644
index 0000000000000000000000000000000000000000..344dd3d1571e2f8abcf8e0e34e9f322b4c47a0ce
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
new file mode 100644
index 0000000000000000000000000000000000000000..8deeae71ff41cc54ca1c1ec4c9eddf4c3de003ed
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>3</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..9a7f8d8df10e5068ef1d11ad2d442e8d2d12433c
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">1024</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>7</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>7</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>1024</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..8e01451caf0cf229c34d10c1bd3b4530611e30a2
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">1024</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>7</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>7</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>1024</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..8bc1beccbea92185b28330bc70894d3eb248f583
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>4</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>4</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
index edb81ad4367c27004dbc9670b4147d42df9c1c08..7c8e9587796a55963004aaa110afc7ac4772ed7f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -1406,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
new file mode 100644
index 0000000000000000000000000000000000000000..d0f8d11be14c224118455be58a5f0b86052086a4
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>2</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>2</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..0dbd6add72473c4736d67b099fac231047bce433
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>2</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>2</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..880603d5da0672e42d7aa09227399c3732dd420c
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>4</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>4</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..d4804c56a11a42b3798c59cad358eab412f221ba
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">16</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
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+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>1</spirit:right>
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+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
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+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
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+ <spirit:direction>in</spirit:direction>
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+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
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+ <spirit:direction>in</spirit:direction>
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+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
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+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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+ </spirit:port>
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+ <spirit:name>avs_mem_read</spirit:name>
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+ <spirit:typeName>STD_LOGIC</spirit:typeName>
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+ <spirit:direction>out</spirit:direction>
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+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
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+ <spirit:name>coe_reset_export</spirit:name>
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+ <spirit:typeName>STD_LOGIC</spirit:typeName>
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+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
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+ <spirit:direction>out</spirit:direction>
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+ <spirit:left>0</spirit:left>
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+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
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+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
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+ <spirit:direction>out</spirit:direction>
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+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
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+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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+ <spirit:name>coe_read_export</spirit:name>
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+ <spirit:direction>out</spirit:direction>
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+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
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+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</spirit:library>
+ <spirit:name>avs_common_mm</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">100000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>4</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c154beb86c5b3d3352bd65adc62e83311d02f6d9
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
@@ -0,0 +1,43 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+#
+### QSFP_1_0 For BF
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cc6ee17b2bfac613b91c40f8f5a4ba3641fc1665
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
@@ -0,0 +1,444 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+#=====================
+# JESD pins
+# ====================
+# Pins needed for the 12 channel JESD204B interface to the ADCs
+set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
+set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[8]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[9]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[10]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[11]
+
+#set_location_assignment PIN_B9 -to BCK_RX[0]
+set_location_assignment PIN_D9 -to BCK_RX[1]
+set_location_assignment PIN_C11 -to BCK_RX[2]
+set_location_assignment PIN_F9 -to BCK_RX[3]
+set_location_assignment PIN_C7 -to BCK_RX[4]
+set_location_assignment PIN_E11 -to BCK_RX[5]
+set_location_assignment PIN_E7 -to BCK_RX[6]
+set_location_assignment PIN_D5 -to BCK_RX[7]
+set_location_assignment PIN_G7 -to BCK_RX[8]
+set_location_assignment PIN_F5 -to BCK_RX[9]
+set_location_assignment PIN_J7 -to BCK_RX[10]
+set_location_assignment PIN_H5 -to BCK_RX[11]
+set_location_assignment PIN_L7 -to BCK_RX[12]
+set_location_assignment PIN_K5 -to BCK_RX[13]
+set_location_assignment PIN_N7 -to BCK_RX[14]
+set_location_assignment PIN_M5 -to BCK_RX[15]
+set_location_assignment PIN_R7 -to BCK_RX[16]
+set_location_assignment PIN_P5 -to BCK_RX[17]
+set_location_assignment PIN_U7 -to BCK_RX[18]
+set_location_assignment PIN_T5 -to BCK_RX[19]
+set_location_assignment PIN_W7 -to BCK_RX[20]
+set_location_assignment PIN_V5 -to BCK_RX[21]
+set_location_assignment PIN_AA7 -to BCK_RX[22]
+set_location_assignment PIN_Y5 -to BCK_RX[23]
+set_location_assignment PIN_AC7 -to BCK_RX[24]
+set_location_assignment PIN_AB5 -to BCK_RX[25]
+set_location_assignment PIN_AE7 -to BCK_RX[26]
+set_location_assignment PIN_AD5 -to BCK_RX[27]
+set_location_assignment PIN_AG7 -to BCK_RX[28]
+set_location_assignment PIN_AF5 -to BCK_RX[29]
+set_location_assignment PIN_AJ7 -to BCK_RX[30]
+set_location_assignment PIN_AH5 -to BCK_RX[31]
+set_location_assignment PIN_AL7 -to BCK_RX[32]
+set_location_assignment PIN_AK5 -to BCK_RX[33]
+set_location_assignment PIN_AN7 -to BCK_RX[34]
+set_location_assignment PIN_AM5 -to BCK_RX[35]
+set_location_assignment PIN_AR7 -to BCK_RX[36]
+set_location_assignment PIN_AP5 -to BCK_RX[37]
+set_location_assignment PIN_AU7 -to BCK_RX[38]
+set_location_assignment PIN_AT5 -to BCK_RX[39]
+set_location_assignment PIN_AW7 -to BCK_RX[40]
+set_location_assignment PIN_AV5 -to BCK_RX[41]
+set_location_assignment PIN_BA7 -to BCK_RX[42]
+set_location_assignment PIN_AY5 -to BCK_RX[43]
+set_location_assignment PIN_BC7 -to BCK_RX[44]
+set_location_assignment PIN_BB5 -to BCK_RX[45]
+set_location_assignment PIN_AY9 -to BCK_RX[46]
+set_location_assignment PIN_BB9 -to BCK_RX[47]
+
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[12]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[13]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[13]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[14]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[14]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[15]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[15]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[16]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[16]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[17]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[17]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[18]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[18]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[19]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[19]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[20]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[20]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[21]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[21]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[22]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[22]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[23]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[24]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[24]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[24]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[24]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[24]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[24]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[25]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[25]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[25]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[25]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[25]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[25]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[26]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[26]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[26]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[26]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[26]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[26]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[27]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[27]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[27]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[27]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[27]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[27]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[28]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[28]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[28]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[28]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[28]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[28]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[29]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[29]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[29]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[29]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[29]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[29]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[30]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[30]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[30]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[30]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[30]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[30]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[31]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[31]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[31]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[31]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[31]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[31]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[32]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[32]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[32]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[32]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[32]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[32]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[33]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[33]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[33]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[33]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[33]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[33]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[34]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[34]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[34]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[34]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[34]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[34]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[35]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[35]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[35]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[35]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[35]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[35]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[36]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[36]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[36]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[36]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[36]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[36]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[37]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[37]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[37]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[37]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[37]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[37]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[38]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[38]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[38]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[38]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[38]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[38]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[39]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[39]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[39]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[39]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[39]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[39]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[40]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[40]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[40]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[40]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[40]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[40]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[41]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[41]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[41]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[41]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[41]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[41]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[42]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[42]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[42]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[42]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[42]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[42]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[43]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[43]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[43]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[43]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[43]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[43]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[44]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[44]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[44]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[44]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[44]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[44]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[45]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[45]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[45]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[45]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[45]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[45]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[46]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[46]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[46]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[46]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[46]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[46]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[47]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[47]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[47]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[47]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[47]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[47]
+
+
+# Substitute new signal names from the jesd_simple design
+#set_location_assignment PIN_BA7 -to BCK_RX[0]
+
+set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_REF_CLK
+set_location_assignment PIN_V9 -to BCK_REF_CLK
+set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+
+set_location_assignment PIN_V12 -to JESD204B_SYSREF
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYSREF
+
+set_location_assignment PIN_U12 -to JESD204B_SYNC_N[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
+set_location_assignment PIN_U14 -to JESD204B_SYNC_N[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
index ca2240dd710c3cd72cb96c527b84752e1561757b..736d08b812885002ead951ef1fd37bdfec638982 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
@@ -72,53 +72,6 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
-
-### QSFP_0_0
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
-
-### QSFP_1_0
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
-
# QSFP_0_RX
set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
@@ -162,476 +115,5 @@ set_location_assignment PIN_J42 -to RING_1_TX[1]
set_location_assignment PIN_G42 -to RING_1_TX[2]
set_location_assignment PIN_F44 -to RING_1_TX[3]
-#RING_0 RX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
-
-#RING_1 RX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
-
-#RING_0 TX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
-
-#RING_1 TX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
-
-
-#=====================
-# JESD pins
-# ====================
-# Pins needed for the 12 channel JESD204B interface to the ADCs
-set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
-set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[8]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[9]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[10]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[11]
-
-#set_location_assignment PIN_B9 -to BCK_RX[0]
-set_location_assignment PIN_D9 -to BCK_RX[1]
-set_location_assignment PIN_C11 -to BCK_RX[2]
-set_location_assignment PIN_F9 -to BCK_RX[3]
-set_location_assignment PIN_C7 -to BCK_RX[4]
-set_location_assignment PIN_E11 -to BCK_RX[5]
-set_location_assignment PIN_E7 -to BCK_RX[6]
-set_location_assignment PIN_D5 -to BCK_RX[7]
-set_location_assignment PIN_G7 -to BCK_RX[8]
-set_location_assignment PIN_F5 -to BCK_RX[9]
-set_location_assignment PIN_J7 -to BCK_RX[10]
-set_location_assignment PIN_H5 -to BCK_RX[11]
-set_location_assignment PIN_L7 -to BCK_RX[12]
-set_location_assignment PIN_K5 -to BCK_RX[13]
-set_location_assignment PIN_N7 -to BCK_RX[14]
-set_location_assignment PIN_M5 -to BCK_RX[15]
-set_location_assignment PIN_R7 -to BCK_RX[16]
-set_location_assignment PIN_P5 -to BCK_RX[17]
-set_location_assignment PIN_U7 -to BCK_RX[18]
-set_location_assignment PIN_T5 -to BCK_RX[19]
-set_location_assignment PIN_W7 -to BCK_RX[20]
-set_location_assignment PIN_V5 -to BCK_RX[21]
-set_location_assignment PIN_AA7 -to BCK_RX[22]
-set_location_assignment PIN_Y5 -to BCK_RX[23]
-set_location_assignment PIN_AC7 -to BCK_RX[24]
-set_location_assignment PIN_AB5 -to BCK_RX[25]
-set_location_assignment PIN_AE7 -to BCK_RX[26]
-set_location_assignment PIN_AD5 -to BCK_RX[27]
-set_location_assignment PIN_AG7 -to BCK_RX[28]
-set_location_assignment PIN_AF5 -to BCK_RX[29]
-set_location_assignment PIN_AJ7 -to BCK_RX[30]
-set_location_assignment PIN_AH5 -to BCK_RX[31]
-set_location_assignment PIN_AL7 -to BCK_RX[32]
-set_location_assignment PIN_AK5 -to BCK_RX[33]
-set_location_assignment PIN_AN7 -to BCK_RX[34]
-set_location_assignment PIN_AM5 -to BCK_RX[35]
-set_location_assignment PIN_AR7 -to BCK_RX[36]
-set_location_assignment PIN_AP5 -to BCK_RX[37]
-set_location_assignment PIN_AU7 -to BCK_RX[38]
-set_location_assignment PIN_AT5 -to BCK_RX[39]
-set_location_assignment PIN_AW7 -to BCK_RX[40]
-set_location_assignment PIN_AV5 -to BCK_RX[41]
-set_location_assignment PIN_BA7 -to BCK_RX[42]
-set_location_assignment PIN_AY5 -to BCK_RX[43]
-set_location_assignment PIN_BC7 -to BCK_RX[44]
-set_location_assignment PIN_BB5 -to BCK_RX[45]
-set_location_assignment PIN_AY9 -to BCK_RX[46]
-set_location_assignment PIN_BB9 -to BCK_RX[47]
-
-
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
-#
-#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
-#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
-#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[12]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[12]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[12]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[12]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[13]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[13]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[13]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[13]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[13]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[13]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[14]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[14]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[14]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[14]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[14]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[14]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[15]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[15]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[15]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[15]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[15]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[15]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[16]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[16]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[16]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[16]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[16]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[16]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[17]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[17]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[17]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[17]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[17]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[17]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[18]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[18]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[18]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[18]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[18]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[18]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[19]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[19]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[19]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[19]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[19]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[19]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[20]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[20]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[20]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[20]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[20]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[20]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[21]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[21]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[21]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[21]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[21]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[21]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[22]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[22]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[22]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[22]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[22]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[22]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[23]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[23]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[23]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[23]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[24]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[24]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[24]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[25]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[25]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[25]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[26]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[26]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[26]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[27]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[27]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[27]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[28]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[28]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[28]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[29]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[29]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[29]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[30]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[30]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[30]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[31]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[31]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[31]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[32]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[32]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[32]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[33]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[33]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[33]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[34]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[34]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[34]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[35]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[35]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[35]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[36]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[36]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[36]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[37]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[37]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[37]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[38]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[38]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[38]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[39]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[39]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[39]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[40]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[40]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[40]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[41]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[41]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[41]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[42]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[42]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[42]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[43]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[43]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[43]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[44]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[44]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[44]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[45]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[45]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[45]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[46]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[46]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[46]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[47]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[47]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[47]
-
-
-# Substitute new signal names from the jesd_simple design
-#set_location_assignment PIN_BA7 -to BCK_RX[0]
-
-set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
-set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_REF_CLK
-set_location_assignment PIN_V9 -to BCK_REF_CLK
-set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
-
-set_location_assignment PIN_V12 -to JESD204B_SYSREF
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYSREF
-
-set_location_assignment PIN_U12 -to JESD204B_SYNC_N[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
-set_location_assignment PIN_U14 -to JESD204B_SYNC_N[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4501f2eb662068aa7a8d5bb523615787d5b4c6fe
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
@@ -0,0 +1,297 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+#
+### QSFP_0_0 For ring
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
+
+### QSFP_0_1 For ring
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
+
+### QSFP_0_2 For ring
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
+
+### QSFP_0_3 For ring
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3]
+#
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
+
+#RING_0 RX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
+
+
+#RING_1 RX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
+
+
+#RING_0 TX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
+
+
+#RING_1 TX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index 7f3ecf426d32288f5910133db21f2158238071ce..c1ca3431cd546ea3828beb71d0d9d948b6cb7487 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "1101696";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1100128";
+ value = "1102736";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1100056";
+ value = "1102664";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1100016";
+ value = "1102624";
type = "String";
}
}
@@ -202,7 +202,7 @@
{
datum baseAddress
{
- value = "12304";
+ value = "1102528";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "1098496";
+ value = "1100544";
type = "String";
}
}
@@ -410,11 +410,27 @@
{
datum baseAddress
{
- value = "1100000";
+ value = "1102608";
type = "String";
}
}
- element reg_bsn_align_v2
+ element reg_bsn_align_v2_bf
+ {
+ datum _sortIndex
+ {
+ value = "73";
+ type = "int";
+ }
+ }
+ element reg_bsn_align_v2_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "1102208";
+ type = "String";
+ }
+ }
+ element reg_bsn_align_v2_xsub
{
datum _sortIndex
{
@@ -422,11 +438,11 @@
type = "int";
}
}
- element reg_bsn_align_v2.mem
+ element reg_bsn_align_v2_xsub.mem
{
datum baseAddress
{
- value = "128";
+ value = "1101312";
type = "String";
}
}
@@ -442,27 +458,27 @@
{
datum baseAddress
{
- value = "1024";
+ value = "1097728";
type = "String";
}
}
- element reg_bsn_monitor_v2_bsn_align_v2_input
+ element reg_bsn_monitor_v2_aligned_bf
{
datum _sortIndex
{
- value = "59";
+ value = "75";
type = "int";
}
}
- element reg_bsn_monitor_v2_bsn_align_v2_input.mem
+ element reg_bsn_monitor_v2_aligned_bf.mem
{
datum baseAddress
{
- value = "13312";
+ value = "12352";
type = "String";
}
}
- element reg_bsn_monitor_v2_bsn_align_v2_output
+ element reg_bsn_monitor_v2_aligned_xsub
{
datum _sortIndex
{
@@ -470,11 +486,59 @@
type = "int";
}
}
- element reg_bsn_monitor_v2_bsn_align_v2_output.mem
+ element reg_bsn_monitor_v2_aligned_xsub.mem
{
datum baseAddress
{
- value = "1099776";
+ value = "1102368";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_beamlet_output
+ {
+ datum _sortIndex
+ {
+ value = "72";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_beamlet_output.mem
+ {
+ datum baseAddress
+ {
+ value = "1101760";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_bst_offload
+ {
+ datum _sortIndex
+ {
+ value = "71";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_bst_offload.mem
+ {
+ datum baseAddress
+ {
+ value = "1101824";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_ring_rx_bf
+ {
+ datum _sortIndex
+ {
+ value = "77";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_ring_rx_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "13312";
type = "String";
}
}
@@ -482,7 +546,7 @@
{
datum _sortIndex
{
- value = "63";
+ value = "62";
type = "int";
}
}
@@ -494,11 +558,27 @@
type = "String";
}
}
+ element reg_bsn_monitor_v2_ring_tx_bf
+ {
+ datum _sortIndex
+ {
+ value = "78";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_ring_tx_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
+ type = "String";
+ }
+ }
element reg_bsn_monitor_v2_ring_tx_xst
{
datum _sortIndex
{
- value = "64";
+ value = "63";
type = "int";
}
}
@@ -510,11 +590,59 @@
type = "String";
}
}
+ element reg_bsn_monitor_v2_rx_align_bf
+ {
+ datum _sortIndex
+ {
+ value = "74";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_align_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_align_xsub
+ {
+ datum _sortIndex
+ {
+ value = "59";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_align_xsub.mem
+ {
+ datum baseAddress
+ {
+ value = "1098752";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_sst_offload
+ {
+ datum _sortIndex
+ {
+ value = "70";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_sst_offload.mem
+ {
+ datum baseAddress
+ {
+ value = "1102272";
+ type = "String";
+ }
+ }
element reg_bsn_monitor_v2_xst_offload
{
datum _sortIndex
{
- value = "61";
+ value = "69";
type = "int";
}
}
@@ -522,7 +650,7 @@
{
datum baseAddress
{
- value = "1099744";
+ value = "1102336";
type = "String";
}
}
@@ -538,7 +666,7 @@
{
datum baseAddress
{
- value = "1100080";
+ value = "1102688";
type = "String";
}
}
@@ -554,7 +682,7 @@
{
datum baseAddress
{
- value = "1099808";
+ value = "1102400";
type = "String";
}
}
@@ -570,7 +698,7 @@
{
datum baseAddress
{
- value = "1099456";
+ value = "1101952";
type = "String";
}
}
@@ -586,7 +714,7 @@
{
datum baseAddress
{
- value = "1099520";
+ value = "1102016";
type = "String";
}
}
@@ -602,7 +730,23 @@
{
datum baseAddress
{
- value = "12416";
+ value = "1101440";
+ type = "String";
+ }
+ }
+ element reg_dp_block_validate_bsn_at_sync_bf
+ {
+ datum _sortIndex
+ {
+ value = "80";
+ type = "int";
+ }
+ }
+ element reg_dp_block_validate_bsn_at_sync_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "12320";
type = "String";
}
}
@@ -610,7 +754,7 @@
{
datum _sortIndex
{
- value = "66";
+ value = "65";
type = "int";
}
}
@@ -618,7 +762,23 @@
{
datum baseAddress
{
- value = "1099952";
+ value = "1102560";
+ type = "String";
+ }
+ }
+ element reg_dp_block_validate_err_bf
+ {
+ datum _sortIndex
+ {
+ value = "79";
+ type = "int";
+ }
+ }
+ element reg_dp_block_validate_err_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
type = "String";
}
}
@@ -626,7 +786,7 @@
{
datum _sortIndex
{
- value = "65";
+ value = "64";
type = "int";
}
}
@@ -634,7 +794,7 @@
{
datum baseAddress
{
- value = "1099392";
+ value = "1101888";
type = "String";
}
}
@@ -650,7 +810,7 @@
{
datum baseAddress
{
- value = "1100072";
+ value = "1102680";
type = "String";
}
}
@@ -666,7 +826,7 @@
{
datum baseAddress
{
- value = "1099264";
+ value = "1101568";
type = "String";
}
}
@@ -682,7 +842,7 @@
{
datum baseAddress
{
- value = "1099984";
+ value = "1102592";
type = "String";
}
}
@@ -703,7 +863,7 @@
{
datum baseAddress
{
- value = "1100120";
+ value = "1102728";
type = "String";
}
}
@@ -724,7 +884,7 @@
{
datum baseAddress
{
- value = "1100112";
+ value = "1102720";
type = "String";
}
}
@@ -745,7 +905,7 @@
{
datum baseAddress
{
- value = "1099872";
+ value = "1102464";
type = "String";
}
}
@@ -761,7 +921,7 @@
{
datum baseAddress
{
- value = "1099840";
+ value = "1102432";
type = "String";
}
}
@@ -782,7 +942,7 @@
{
datum baseAddress
{
- value = "1099648";
+ value = "1102144";
type = "String";
}
}
@@ -798,7 +958,7 @@
{
datum baseAddress
{
- value = "1097728";
+ value = "1099776";
type = "String";
}
}
@@ -819,7 +979,7 @@
{
datum baseAddress
{
- value = "1100104";
+ value = "1102712";
type = "String";
}
}
@@ -840,7 +1000,7 @@
{
datum baseAddress
{
- value = "1100096";
+ value = "1102704";
type = "String";
}
}
@@ -856,7 +1016,7 @@
{
datum baseAddress
{
- value = "1100032";
+ value = "1102640";
type = "String";
}
}
@@ -872,7 +1032,7 @@
{
datum baseAddress
{
- value = "1100064";
+ value = "1102672";
type = "String";
}
}
@@ -909,7 +1069,7 @@
{
datum baseAddress
{
- value = "1099904";
+ value = "1102496";
type = "String";
}
}
@@ -917,7 +1077,7 @@
{
datum _sortIndex
{
- value = "67";
+ value = "66";
type = "int";
}
}
@@ -925,7 +1085,23 @@
{
datum baseAddress
{
- value = "1099936";
+ value = "1102544";
+ type = "String";
+ }
+ }
+ element reg_ring_lane_info_bf
+ {
+ datum _sortIndex
+ {
+ value = "76";
+ type = "int";
+ }
+ }
+ element reg_ring_lane_info_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "12304";
type = "String";
}
}
@@ -933,7 +1109,7 @@
{
datum _sortIndex
{
- value = "62";
+ value = "61";
type = "int";
}
}
@@ -957,7 +1133,7 @@
{
datum baseAddress
{
- value = "1099584";
+ value = "1102080";
type = "String";
}
}
@@ -973,7 +1149,7 @@
{
datum baseAddress
{
- value = "1100088";
+ value = "1102696";
type = "String";
}
}
@@ -989,7 +1165,7 @@
{
datum baseAddress
{
- value = "1099968";
+ value = "1102576";
type = "String";
}
}
@@ -1005,7 +1181,7 @@
{
datum baseAddress
{
- value = "1100048";
+ value = "1102656";
type = "String";
}
}
@@ -1021,7 +1197,7 @@
{
datum baseAddress
{
- value = "1100040";
+ value = "1102648";
type = "String";
}
}
@@ -1037,7 +1213,7 @@
{
datum baseAddress
{
- value = "13824";
+ value = "1099264";
type = "String";
}
}
@@ -1077,7 +1253,7 @@
{
datum _sortIndex
{
- value = "68";
+ value = "67";
type = "int";
}
}
@@ -1085,7 +1261,7 @@
{
datum baseAddress
{
- value = "1099712";
+ value = "1102304";
type = "String";
}
}
@@ -1093,7 +1269,7 @@
{
datum _sortIndex
{
- value = "69";
+ value = "68";
type = "int";
}
}
@@ -1117,7 +1293,7 @@
{
datum baseAddress
{
- value = "1098752";
+ value = "1100800";
type = "String";
}
}
@@ -1133,7 +1309,7 @@
{
datum baseAddress
{
- value = "1099008";
+ value = "1101056";
type = "String";
}
}
@@ -1175,7 +1351,7 @@
{
datum baseAddress
{
- value = "1098240";
+ value = "1100288";
type = "String";
}
}
@@ -1217,7 +1393,7 @@
{
datum baseAddress
{
- value = "12320";
+ value = "1102240";
type = "String";
}
}
@@ -1939,38 +2115,73 @@
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_address"
- internal="reg_bsn_align_v2.address"
+ name="reg_bsn_align_v2_bf_address"
+ internal="reg_bsn_align_v2_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_bf_clk"
+ internal="reg_bsn_align_v2_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_bf_read"
+ internal="reg_bsn_align_v2_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_bf_readdata"
+ internal="reg_bsn_align_v2_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_bf_reset"
+ internal="reg_bsn_align_v2_bf.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_clk"
- internal="reg_bsn_align_v2.clk"
+ name="reg_bsn_align_v2_bf_write"
+ internal="reg_bsn_align_v2_bf.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_read"
- internal="reg_bsn_align_v2.read"
+ name="reg_bsn_align_v2_bf_writedata"
+ internal="reg_bsn_align_v2_bf.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_readdata"
- internal="reg_bsn_align_v2.readdata"
+ name="reg_bsn_align_v2_xsub_address"
+ internal="reg_bsn_align_v2_xsub.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_reset"
- internal="reg_bsn_align_v2.reset"
+ name="reg_bsn_align_v2_xsub_clk"
+ internal="reg_bsn_align_v2_xsub.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_write"
- internal="reg_bsn_align_v2.write"
+ name="reg_bsn_align_v2_xsub_read"
+ internal="reg_bsn_align_v2_xsub.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_writedata"
- internal="reg_bsn_align_v2.writedata"
+ name="reg_bsn_align_v2_xsub_readdata"
+ internal="reg_bsn_align_v2_xsub.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_xsub_reset"
+ internal="reg_bsn_align_v2_xsub.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_xsub_write"
+ internal="reg_bsn_align_v2_xsub.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_xsub_writedata"
+ internal="reg_bsn_align_v2_xsub.writedata"
type="conduit"
dir="end" />
<interface
@@ -2009,73 +2220,178 @@
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_address"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.address"
+ name="reg_bsn_monitor_v2_aligned_bf_address"
+ internal="reg_bsn_monitor_v2_aligned_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_clk"
+ internal="reg_bsn_monitor_v2_aligned_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_read"
+ internal="reg_bsn_monitor_v2_aligned_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_readdata"
+ internal="reg_bsn_monitor_v2_aligned_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_reset"
+ internal="reg_bsn_monitor_v2_aligned_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_write"
+ internal="reg_bsn_monitor_v2_aligned_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_writedata"
+ internal="reg_bsn_monitor_v2_aligned_bf.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_address"
+ internal="reg_bsn_monitor_v2_aligned_xsub.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_clk"
+ internal="reg_bsn_monitor_v2_aligned_xsub.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_read"
+ internal="reg_bsn_monitor_v2_aligned_xsub.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_readdata"
+ internal="reg_bsn_monitor_v2_aligned_xsub.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_reset"
+ internal="reg_bsn_monitor_v2_aligned_xsub.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_write"
+ internal="reg_bsn_monitor_v2_aligned_xsub.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_writedata"
+ internal="reg_bsn_monitor_v2_aligned_xsub.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_address"
+ internal="reg_bsn_monitor_v2_beamlet_output.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_clk"
+ internal="reg_bsn_monitor_v2_beamlet_output.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_read"
+ internal="reg_bsn_monitor_v2_beamlet_output.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_readdata"
+ internal="reg_bsn_monitor_v2_beamlet_output.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_reset"
+ internal="reg_bsn_monitor_v2_beamlet_output.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_write"
+ internal="reg_bsn_monitor_v2_beamlet_output.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_writedata"
+ internal="reg_bsn_monitor_v2_beamlet_output.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bst_offload_address"
+ internal="reg_bsn_monitor_v2_bst_offload.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_clk"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.clk"
+ name="reg_bsn_monitor_v2_bst_offload_clk"
+ internal="reg_bsn_monitor_v2_bst_offload.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_read"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.read"
+ name="reg_bsn_monitor_v2_bst_offload_read"
+ internal="reg_bsn_monitor_v2_bst_offload.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_readdata"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.readdata"
+ name="reg_bsn_monitor_v2_bst_offload_readdata"
+ internal="reg_bsn_monitor_v2_bst_offload.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_reset"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.reset"
+ name="reg_bsn_monitor_v2_bst_offload_reset"
+ internal="reg_bsn_monitor_v2_bst_offload.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_write"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.write"
+ name="reg_bsn_monitor_v2_bst_offload_write"
+ internal="reg_bsn_monitor_v2_bst_offload.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_writedata"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.writedata"
+ name="reg_bsn_monitor_v2_bst_offload_writedata"
+ internal="reg_bsn_monitor_v2_bst_offload.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_address"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.address"
+ name="reg_bsn_monitor_v2_ring_rx_bf_address"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_clk"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.clk"
+ name="reg_bsn_monitor_v2_ring_rx_bf_clk"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_read"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.read"
+ name="reg_bsn_monitor_v2_ring_rx_bf_read"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_readdata"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.readdata"
+ name="reg_bsn_monitor_v2_ring_rx_bf_readdata"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_reset"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.reset"
+ name="reg_bsn_monitor_v2_ring_rx_bf_reset"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_write"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.write"
+ name="reg_bsn_monitor_v2_ring_rx_bf_write"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_writedata"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.writedata"
+ name="reg_bsn_monitor_v2_ring_rx_bf_writedata"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.writedata"
type="conduit"
dir="end" />
<interface
@@ -2113,6 +2429,41 @@
internal="reg_bsn_monitor_v2_ring_rx_xst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_address"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_clk"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_read"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_readdata"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_reset"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_write"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_writedata"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_monitor_v2_ring_tx_xst_address"
internal="reg_bsn_monitor_v2_ring_tx_xst.address"
@@ -2148,6 +2499,111 @@
internal="reg_bsn_monitor_v2_ring_tx_xst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_address"
+ internal="reg_bsn_monitor_v2_rx_align_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_clk"
+ internal="reg_bsn_monitor_v2_rx_align_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_read"
+ internal="reg_bsn_monitor_v2_rx_align_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_readdata"
+ internal="reg_bsn_monitor_v2_rx_align_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_reset"
+ internal="reg_bsn_monitor_v2_rx_align_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_write"
+ internal="reg_bsn_monitor_v2_rx_align_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_writedata"
+ internal="reg_bsn_monitor_v2_rx_align_bf.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_address"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_clk"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_read"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_readdata"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_reset"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_write"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_writedata"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_address"
+ internal="reg_bsn_monitor_v2_sst_offload.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_clk"
+ internal="reg_bsn_monitor_v2_sst_offload.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_read"
+ internal="reg_bsn_monitor_v2_sst_offload.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_readdata"
+ internal="reg_bsn_monitor_v2_sst_offload.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_reset"
+ internal="reg_bsn_monitor_v2_sst_offload.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_write"
+ internal="reg_bsn_monitor_v2_sst_offload.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_writedata"
+ internal="reg_bsn_monitor_v2_sst_offload.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_monitor_v2_xst_offload_address"
internal="reg_bsn_monitor_v2_xst_offload.address"
@@ -2358,6 +2814,41 @@
internal="reg_diag_data_buffer_bsn.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_address"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_clk"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_read"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_readdata"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_reset"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_write"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_writedata"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dp_block_validate_bsn_at_sync_xst_address"
internal="reg_dp_block_validate_bsn_at_sync_xst.address"
@@ -2393,6 +2884,41 @@
internal="reg_dp_block_validate_bsn_at_sync_xst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_address"
+ internal="reg_dp_block_validate_err_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_clk"
+ internal="reg_dp_block_validate_err_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_read"
+ internal="reg_dp_block_validate_err_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_readdata"
+ internal="reg_dp_block_validate_err_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_reset"
+ internal="reg_dp_block_validate_err_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_write"
+ internal="reg_dp_block_validate_err_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_writedata"
+ internal="reg_dp_block_validate_err_bf.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dp_block_validate_err_xst_address"
internal="reg_dp_block_validate_err_xst.address"
@@ -2980,6 +3506,41 @@
internal="reg_ring_info.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_address"
+ internal="reg_ring_lane_info_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_clk"
+ internal="reg_ring_lane_info_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_read"
+ internal="reg_ring_lane_info_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_readdata"
+ internal="reg_ring_lane_info_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_reset"
+ internal="reg_ring_lane_info_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_write"
+ internal="reg_ring_lane_info_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_writedata"
+ internal="reg_ring_lane_info_bf.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_ring_lane_info_xst_address"
internal="reg_ring_lane_info_xst.address"
@@ -6468,7 +7029,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10C400' end='0x10C500' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10C500' end='0x10C600' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C600' end='0x10C680' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C680' end='0x10C6C0' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C6C0' end='0x10C700' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C700' end='0x10C740' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C740' end='0x10C780' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C780' end='0x10C7C0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C7C0' end='0x10C7E0' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C7E0' end='0x10C800' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C800' end='0x10C820' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C820' end='0x10C840' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C840' end='0x10C860' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C860' end='0x10C880' datawidth='32' /><slave name='reg_remu.mem' start='0x10C880' end='0x10C8A0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C8A0' end='0x10C8B0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C8B0' end='0x10C8C0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C8C0' end='0x10C8D0' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C8D0' end='0x10C8E0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C8E0' end='0x10C8F0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C8F0' end='0x10C900' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C900' end='0x10C908' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C908' end='0x10C910' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C910' end='0x10C918' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C918' end='0x10C920' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C920' end='0x10C928' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C928' end='0x10C930' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C930' end='0x10C938' datawidth='32' /><slave name='reg_si.mem' start='0x10C938' end='0x10C940' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C940' end='0x10C948' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C948' end='0x10C950' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10C950' end='0x10C958' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10C958' end='0x10C960' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C960' end='0x10C968' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x10CC00' end='0x10CD00' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x10CD00' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CE00' end='0x10CE80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CE80' end='0x10CF00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CF00' end='0x10CF80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CF80' end='0x10CFC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CFC0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10D000' end='0x10D040' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10D040' end='0x10D080' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10D080' end='0x10D0C0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10D0C0' end='0x10D100' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10D100' end='0x10D140' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10D140' end='0x10D180' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10D180' end='0x10D1A0' datawidth='32' /><slave name='timer_0.s1' start='0x10D1A0' end='0x10D1C0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10D1C0' end='0x10D1E0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10D1E0' end='0x10D200' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D200' end='0x10D220' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D220' end='0x10D240' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D240' end='0x10D260' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D260' end='0x10D280' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D280' end='0x10D2A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D2A0' end='0x10D2C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D2C0' end='0x10D2D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D2D0' end='0x10D2E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D2E0' end='0x10D2F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D2F0' end='0x10D300' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D300' end='0x10D310' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D310' end='0x10D320' datawidth='32' /><slave name='pio_pps.mem' start='0x10D320' end='0x10D330' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D330' end='0x10D338' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D338' end='0x10D340' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D340' end='0x10D348' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D348' end='0x10D350' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D350' end='0x10D358' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D358' end='0x10D360' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D360' end='0x10D368' datawidth='32' /><slave name='reg_si.mem' start='0x10D368' end='0x10D370' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D370' end='0x10D378' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D378' end='0x10D380' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D380' end='0x10D388' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D388' end='0x10D390' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D390' end='0x10D398' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -18963,7 +19524,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_align_v2"
+ name="reg_bsn_align_v2_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18979,7 +19540,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19043,7 +19604,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19112,7 +19673,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -19518,11 +20079,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19549,37 +20110,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bsn_align_v2_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -19595,7 +20156,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19659,7 +20220,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -19728,7 +20289,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20134,11 +20695,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20165,37 +20726,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_bsn_align_v2_input"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20211,7 +20772,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20275,7 +20836,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20344,7 +20905,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -20750,11 +21311,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20781,37 +21342,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_bsn_align_v2_output"
+ name="reg_bsn_monitor_v2_aligned_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -20827,7 +21388,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20891,7 +21452,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -20960,7 +21521,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21366,11 +21927,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21397,37 +21958,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_rx_xst"
+ name="reg_bsn_monitor_v2_aligned_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -21443,7 +22004,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21507,7 +22068,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -21576,7 +22137,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -21982,11 +22543,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22013,37 +22574,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_tx_xst"
+ name="reg_bsn_monitor_v2_beamlet_output"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22059,7 +22620,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22123,7 +22684,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22192,7 +22753,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -22598,11 +23159,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22629,37 +23190,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_xst_offload"
+ name="reg_bsn_monitor_v2_bst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -22675,7 +23236,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22739,7 +23300,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -22808,7 +23369,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23214,11 +23775,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23245,37 +23806,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_v2_ring_rx_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23291,7 +23852,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23355,7 +23916,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23424,7 +23985,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -23830,11 +24391,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23861,37 +24422,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source_v2"
+ name="reg_bsn_monitor_v2_ring_rx_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -23907,7 +24468,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -23971,7 +24532,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24040,7 +24601,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -24446,11 +25007,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24477,37 +25038,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_sync_scheduler_xsub"
+ name="reg_bsn_monitor_v2_ring_tx_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -24523,7 +25084,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24587,7 +25148,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -24656,7 +25217,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25062,11 +25623,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25093,37 +25654,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_crosslets_info"
+ name="reg_bsn_monitor_v2_ring_tx_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -25139,7 +25700,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25203,7 +25764,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -25272,7 +25833,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -25678,11 +26239,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -25709,37 +26270,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_bsn_monitor_v2_rx_align_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26325,37 +26886,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_bsn_at_sync_xst"
+ name="reg_bsn_monitor_v2_rx_align_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26371,7 +26932,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26435,7 +26996,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -26504,7 +27065,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -26910,11 +27471,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26941,37 +27502,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_err_xst"
+ name="reg_bsn_monitor_v2_sst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -26987,7 +27548,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27051,7 +27612,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27120,7 +27681,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -27526,11 +28087,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27557,37 +28118,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_bsn_monitor_v2_xst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -27603,7 +28164,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27667,7 +28228,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -27736,7 +28297,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28142,11 +28703,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28173,37 +28734,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28219,7 +28780,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28283,7 +28844,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28352,7 +28913,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -28758,11 +29319,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28789,37 +29350,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_xonoff"
+ name="reg_bsn_source_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -28835,7 +29396,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28899,7 +29460,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -28968,7 +29529,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29374,11 +29935,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -29405,37 +29966,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_bsn_sync_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -29451,7 +30012,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29515,7 +30076,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -29584,7 +30145,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -29990,11 +30551,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30021,37 +30582,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30067,7 +30628,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30131,7 +30692,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30200,7 +30761,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -30606,11 +31167,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -30637,37 +31198,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -30683,7 +31244,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30747,7 +31308,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -30816,7 +31377,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31222,11 +31783,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -31253,37 +31814,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_dp_block_validate_bsn_at_sync_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31869,37 +32430,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_dp_block_validate_bsn_at_sync_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31915,7 +32476,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31979,7 +32540,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32048,7 +32609,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32454,11 +33015,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32485,37 +33046,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_hdr_dat"
+ name="reg_dp_block_validate_err_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32531,7 +33092,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32595,7 +33156,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32664,7 +33225,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33070,11 +33631,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33101,37 +33662,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_dp_block_validate_err_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33147,7 +33708,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33211,7 +33772,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33280,7 +33841,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33686,11 +34247,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33717,37 +34278,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34333,37 +34894,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nof_crosslets"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34379,7 +34940,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34443,7 +35004,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34512,7 +35073,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34918,11 +35479,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34949,37 +35510,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_dp_xonoff"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34995,7 +35556,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35059,7 +35620,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35128,7 +35689,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35534,11 +36095,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -35565,37 +36126,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -35611,7 +36172,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35675,7 +36236,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35744,7 +36305,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36150,11 +36711,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36181,37 +36742,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36227,7 +36788,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36291,7 +36852,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36360,7 +36921,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36766,11 +37327,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36797,37 +37358,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_info"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36843,7 +37404,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36907,7 +37468,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36976,7 +37537,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37382,11 +37943,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -37413,37 +37974,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_lane_info_xst"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37459,7 +38020,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37523,7 +38084,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37592,7 +38153,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37998,11 +38559,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -38029,37 +38590,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38645,37 +39206,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38691,7 +39252,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38755,7 +39316,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38824,7 +39385,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39230,11 +39791,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39261,37 +39822,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -39307,7 +39868,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39371,7 +39932,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39440,7 +40001,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39846,11 +40407,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -39877,37 +40438,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_sst"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -40493,37 +41054,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_xst"
+ name="reg_nof_crosslets"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41109,37 +41670,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41155,7 +41716,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41219,7 +41780,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41288,7 +41849,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -41694,11 +42255,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -41725,37 +42286,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_sst"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41771,7 +42332,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41835,7 +42396,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41904,7 +42465,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42310,11 +42871,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -42341,37 +42902,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_xst"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -42387,7 +42948,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42451,7 +43012,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42520,7 +43081,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42926,11 +43487,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -42957,37 +43518,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10gbe_eth10g"
+ name="reg_ring_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -43003,7 +43564,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43067,7 +43628,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43136,7 +43697,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43542,11 +44103,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -43573,37 +44134,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10gbe_mac"
+ name="reg_ring_lane_info_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -43619,7 +44180,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>15</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43683,7 +44244,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>15</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43752,7 +44313,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>131072</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -44158,11 +44719,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>17</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -44189,37 +44750,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_pmbus"
+ name="reg_ring_lane_info_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -44235,7 +44796,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44299,7 +44860,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44368,7 +44929,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -44774,11 +45335,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -44805,37 +45366,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_sens"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -44851,7 +45412,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44915,7 +45476,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -44984,7 +45545,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -45390,11 +45951,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -45421,37 +45982,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wdi"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46037,37 +46598,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wg"
+ name="reg_stat_enable_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46083,7 +46644,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46147,7 +46708,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46216,7 +46777,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -46622,11 +47183,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -46653,37 +47214,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="rom_system_info"
+ name="reg_stat_enable_sst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46699,7 +47260,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46763,7 +47324,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46832,7 +47393,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47238,11 +47799,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -47269,37 +47830,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_rom_system_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="timer_0"
+ name="reg_stat_enable_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -47307,17 +47868,17 @@
<boundary>
<interfaces>
<interface>
- <name>clk</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -47326,27 +47887,26 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>irq</name>
- <type>interrupt</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>irq</name>
- <role>irq</role>
+ <name>coe_clk_export</name>
+ <role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
@@ -47358,106 +47918,63 @@
</assignments>
<parameters>
<parameterValueMap>
- <entry>
- <key>associatedAddressablePoint</key>
- <value>timer_0.s1</value>
- </entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
- </entry>
- <entry>
- <key>bridgedReceiverOffset</key>
- <value>0</value>
- </entry>
- <entry>
- <key>bridgesToReceiver</key>
- </entry>
- <entry>
- <key>irqScheme</key>
- <value>NONE</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>clk</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>s1</name>
+ <name>mem</name>
<type>avalon</type>
<isStart>false</isStart>
<ports>
<port>
- <name>address</name>
+ <name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>writedata</name>
- <role>writedata</role>
+ <name>avs_mem_write</name>
+ <role>write</role>
<direction>Input</direction>
- <width>16</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>readdata</name>
- <role>readdata</role>
- <direction>Output</direction>
- <width>16</width>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
<port>
- <name>chipselect</name>
- <role>chipselect</role>
+ <name>avs_mem_read</name>
+ <role>read</role>
<direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
</port>
<port>
- <name>write_n</name>
- <role>write_n</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -47478,17 +47995,13 @@
<key>embeddedsw.configuration.isPrintableDevice</key>
<value>0</value>
</entry>
- <entry>
- <key>embeddedsw.configuration.isTimerDevice</key>
- <value>1</value>
- </entry>
</assignmentValueMap>
</assignments>
<parameters>
<parameterValueMap>
<entry>
<key>addressAlignment</key>
- <value>NATIVE</value>
+ <value>DYNAMIC</value>
</entry>
<entry>
<key>addressGroup</key>
@@ -47508,11 +48021,6835 @@
</entry>
<entry>
<key>associatedClock</key>
- <value>clk</value>
+ <value>system</value>
</entry>
<entry>
<key>associatedReset</key>
- <value>reset</value>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_hdr_dat_bst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>512</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>9</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_hdr_dat_sst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_hdr_dat_xst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_tr_10gbe_eth10g"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_tr_10gbe_mac"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>15</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>15</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>131072</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>17</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_unb_pmbus"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_unb_sens"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_wdi"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wdi</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_wg"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wg</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="rom_system_info"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32768</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>15</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_rom_system_info</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="timer_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>irq</name>
+ <type>interrupt</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>irq</name>
+ <role>irq</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedAddressablePoint</key>
+ <value>timer_0.s1</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
+ </entry>
+ <entry>
+ <key>bridgedReceiverOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToReceiver</key>
+ </entry>
+ <entry>
+ <key>irqScheme</key>
+ <value>NONE</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>reset_n</name>
+ <role>reset_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>s1</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>16</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>chipselect</name>
+ <role>chipselect</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>write_n</name>
+ <role>write_n</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isTimerDevice</key>
+ <value>1</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>NATIVE</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>clk</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>reset</value>
</entry>
<entry>
<key>bitsPerSymbol</key>
@@ -48027,7 +55364,7 @@
version="18.0"
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
- <parameter name="baseAddress" value="0x0010c960" />
+ <parameter name="baseAddress" value="0x0010d390" />
</connection>
<connection
kind="avalon"
@@ -48041,7 +55378,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_unb_sens.mem">
- <parameter name="baseAddress" value="0x0010c500" />
+ <parameter name="baseAddress" value="0x0010cd00" />
</connection>
<connection
kind="avalon"
@@ -48062,7 +55399,7 @@
version="18.0"
start="cpu_0.data_master"
end="pio_pps.mem">
- <parameter name="baseAddress" value="0x0010c8f0" />
+ <parameter name="baseAddress" value="0x0010d320" />
</connection>
<connection
kind="avalon"
@@ -48076,63 +55413,63 @@
version="18.0"
start="cpu_0.data_master"
end="reg_remu.mem">
- <parameter name="baseAddress" value="0x0010c880" />
+ <parameter name="baseAddress" value="0x0010d2a0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_epcs.mem">
- <parameter name="baseAddress" value="0x0010c860" />
+ <parameter name="baseAddress" value="0x0010d280" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
- <parameter name="baseAddress" value="0x0010c958" />
+ <parameter name="baseAddress" value="0x0010d388" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
- <parameter name="baseAddress" value="0x0010c950" />
+ <parameter name="baseAddress" value="0x0010d380" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
- <parameter name="baseAddress" value="0x0010c948" />
+ <parameter name="baseAddress" value="0x0010d378" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
- <parameter name="baseAddress" value="0x0010c940" />
+ <parameter name="baseAddress" value="0x0010d370" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
- <parameter name="baseAddress" value="0x0010c840" />
+ <parameter name="baseAddress" value="0x0010d260" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_unb_pmbus.mem">
- <parameter name="baseAddress" value="0x0010c400" />
+ <parameter name="baseAddress" value="0x0010cc00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
- <parameter name="baseAddress" value="0x0010c780" />
+ <parameter name="baseAddress" value="0x0010d140" />
</connection>
<connection
kind="avalon"
@@ -48146,7 +55483,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_si.mem">
- <parameter name="baseAddress" value="0x0010c938" />
+ <parameter name="baseAddress" value="0x0010d368" />
</connection>
<connection
kind="avalon"
@@ -48167,7 +55504,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
- <parameter name="baseAddress" value="0x0010c300" />
+ <parameter name="baseAddress" value="0x0010cb00" />
</connection>
<connection
kind="avalon"
@@ -48181,35 +55518,35 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
- <parameter name="baseAddress" value="0x0010c600" />
+ <parameter name="baseAddress" value="0x0010cf00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
- <parameter name="baseAddress" value="0x0010c930" />
+ <parameter name="baseAddress" value="0x0010d360" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
- <parameter name="baseAddress" value="0x0010c820" />
+ <parameter name="baseAddress" value="0x0010d240" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_wg.mem">
- <parameter name="baseAddress" value="0x0010c200" />
+ <parameter name="baseAddress" value="0x0010ca00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_input.mem">
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x0010c000" />
</connection>
<connection
kind="avalon"
@@ -48223,7 +55560,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_selector.mem">
- <parameter name="baseAddress" value="0x0010c928" />
+ <parameter name="baseAddress" value="0x0010d358" />
</connection>
<connection
kind="avalon"
@@ -48251,21 +55588,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bf_scale.mem">
- <parameter name="baseAddress" value="0x0010c8e0" />
+ <parameter name="baseAddress" value="0x0010d310" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
- <parameter name="baseAddress" value="0x0010c000" />
+ <parameter name="baseAddress" value="0x0010c800" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
- <parameter name="baseAddress" value="0x0010c8d0" />
+ <parameter name="baseAddress" value="0x0010d300" />
</connection>
<connection
kind="avalon"
@@ -48279,14 +55616,14 @@
version="18.0"
start="cpu_0.data_master"
end="reg_sdp_info.mem">
- <parameter name="baseAddress" value="0x0010c740" />
+ <parameter name="baseAddress" value="0x0010d100" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x0010c920" />
+ <parameter name="baseAddress" value="0x0010d350" />
</connection>
<connection
kind="avalon"
@@ -48300,7 +55637,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x0010ce80" />
</connection>
<connection
kind="avalon"
@@ -48314,14 +55651,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
- <parameter name="baseAddress" value="0x0010c918" />
+ <parameter name="baseAddress" value="0x0010d348" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
- <parameter name="baseAddress" value="0x0010c910" />
+ <parameter name="baseAddress" value="0x0010d340" />
</connection>
<connection
kind="avalon"
@@ -48335,21 +55672,21 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
- <parameter name="baseAddress" value="0x0010c8c0" />
+ <parameter name="baseAddress" value="0x0010d2f0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_stat_hdr_dat_bst.mem">
- <parameter name="baseAddress" value="0x3600" />
+ <parameter name="baseAddress" value="0x0010c600" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
- <parameter name="baseAddress" value="0x0010c700" />
+ <parameter name="baseAddress" value="0x0010d0c0" />
</connection>
<connection
kind="avalon"
@@ -48363,7 +55700,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
- <parameter name="baseAddress" value="0x0010c908" />
+ <parameter name="baseAddress" value="0x0010d338" />
</connection>
<connection
kind="avalon"
@@ -48377,7 +55714,7 @@
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
- <parameter name="baseAddress" value="0x0010c6c0" />
+ <parameter name="baseAddress" value="0x0010d080" />
</connection>
<connection
kind="avalon"
@@ -48391,35 +55728,35 @@
version="18.0"
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
- <parameter name="baseAddress" value="0x0010c900" />
+ <parameter name="baseAddress" value="0x0010d330" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_bsn_align_v2.mem">
- <parameter name="baseAddress" value="0x0080" />
+ end="reg_bsn_align_v2_xsub.mem">
+ <parameter name="baseAddress" value="0x0010ce00" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_bsn_monitor_v2_bsn_align_v2_input.mem">
- <parameter name="baseAddress" value="0x3400" />
+ end="reg_bsn_monitor_v2_rx_align_xsub.mem">
+ <parameter name="baseAddress" value="0x0010c400" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_bsn_monitor_v2_bsn_align_v2_output.mem">
- <parameter name="baseAddress" value="0x0010c800" />
+ end="reg_bsn_monitor_v2_aligned_xsub.mem">
+ <parameter name="baseAddress" value="0x0010d220" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_xst_offload.mem">
- <parameter name="baseAddress" value="0x0010c7e0" />
+ <parameter name="baseAddress" value="0x0010d200" />
</connection>
<connection
kind="avalon"
@@ -48447,28 +55784,28 @@
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
- <parameter name="baseAddress" value="0x0010c680" />
+ <parameter name="baseAddress" value="0x0010d040" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
- <parameter name="baseAddress" value="0x0010c8b0" />
+ <parameter name="baseAddress" value="0x0010d2e0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_ring_info.mem">
- <parameter name="baseAddress" value="0x0010c8a0" />
+ <parameter name="baseAddress" value="0x0010d2d0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
- <parameter name="baseAddress" value="0x0010c7c0" />
+ <parameter name="baseAddress" value="0x0010d1e0" />
</connection>
<connection
kind="avalon"
@@ -48477,6 +55814,83 @@
end="reg_tr_10gbe_mac.mem">
<parameter name="baseAddress" value="0x00080000" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_sst_offload.mem">
+ <parameter name="baseAddress" value="0x0010d1c0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_bst_offload.mem">
+ <parameter name="baseAddress" value="0x0010d000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_beamlet_output.mem">
+ <parameter name="baseAddress" value="0x0010cfc0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_align_v2_bf.mem">
+ <parameter name="baseAddress" value="0x0010d180" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_rx_align_bf.mem">
+ <parameter name="baseAddress" value="0x3080" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_aligned_bf.mem">
+ <parameter name="baseAddress" value="0x3040" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_ring_lane_info_bf.mem">
+ <parameter name="baseAddress" value="0x3010" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_ring_rx_bf.mem">
+ <parameter name="baseAddress" value="0x3400" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_ring_tx_bf.mem">
+ <parameter name="baseAddress" value="0x0400" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_dp_block_validate_err_bf.mem">
+ <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="reg_dp_block_validate_bsn_at_sync_bf.mem">
+ <parameter name="baseAddress" value="0x3020" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -48489,7 +55903,7 @@
version="18.0"
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x0010cf80" />
</connection>
<connection
kind="avalon"
@@ -48510,14 +55924,14 @@
version="18.0"
start="cpu_0.data_master"
end="pio_wdi.s1">
- <parameter name="baseAddress" value="0x3010" />
+ <parameter name="baseAddress" value="0x0010d2c0" />
</connection>
<connection
kind="avalon"
version="18.0"
start="cpu_0.data_master"
end="timer_0.s1">
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x0010d1a0" />
</connection>
<connection
kind="avalon"
@@ -48754,17 +56168,17 @@
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_bsn_align_v2.system" />
+ end="reg_bsn_align_v2_xsub.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_bsn_monitor_v2_bsn_align_v2_input.system" />
+ end="reg_bsn_monitor_v2_rx_align_xsub.system" />
<connection
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_bsn_monitor_v2_bsn_align_v2_output.system" />
+ end="reg_bsn_monitor_v2_aligned_xsub.system" />
<connection
kind="clock"
version="18.0"
@@ -48810,6 +56224,61 @@
version="18.0"
start="clk_0.clk"
end="reg_tr_10gbe_mac.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_sst_offload.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_bst_offload.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_beamlet_output.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bsn_align_v2_bf.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_rx_align_bf.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_aligned_bf.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_ring_lane_info_bf.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_ring_rx_bf.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_ring_tx_bf.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_dp_block_validate_err_bf.system" />
+ <connection
+ kind="clock"
+ version="18.0"
+ start="clk_0.clk"
+ end="reg_dp_block_validate_bsn_at_sync_bf.system" />
<connection
kind="interrupt"
version="18.0"
@@ -49110,17 +56579,17 @@
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_bsn_align_v2.system_reset" />
+ end="reg_bsn_align_v2_xsub.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_bsn_monitor_v2_bsn_align_v2_input.system_reset" />
+ end="reg_bsn_monitor_v2_rx_align_xsub.system_reset" />
<connection
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_bsn_monitor_v2_bsn_align_v2_output.system_reset" />
+ end="reg_bsn_monitor_v2_aligned_xsub.system_reset" />
<connection
kind="reset"
version="18.0"
@@ -49166,6 +56635,61 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_tr_10gbe_mac.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_sst_offload.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_bst_offload.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_beamlet_output.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_align_v2_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_rx_align_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_aligned_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_ring_lane_info_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_ring_rx_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_ring_tx_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_dp_block_validate_err_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="reg_dp_block_validate_bsn_at_sync_bf.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 6bd0a8873ced50bf960b8b6be09c4a251ec681cc..47e72aafd1e3ef6d7f7527541f4cecfea6e7f821 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -32,7 +32,7 @@ quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+ lofar2_unb2b_sdp_station_adc_pins.tcl
quartus_vhdl_files =
@@ -65,19 +65,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
@@ -95,6 +105,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1951a9467db81c29743ddc496672c7fb0f0e6b41
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl
@@ -0,0 +1,24 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 229a1dda6281640f822ac03e42da3fa8aedc6d2b..cbc98f7daa43b7ab93f6e49718261afbee5402df 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -40,12 +40,13 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+ lofar2_unb2b_sdp_station_bf_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_bf/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
@@ -72,19 +73,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
@@ -102,6 +113,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4c0efdf4ecb475bea47c7efdb0cd104a1ffaadcd
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl
@@ -0,0 +1,25 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index ee26002cd772de8b1afc75c4c45694a9276e402b..a44d4c512bf8c128077ea7ac257068af6286b2a2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -39,7 +39,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+ lofar2_unb2b_sdp_station_fsub_pins.tcl
quartus_vhdl_files =
@@ -72,19 +72,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
@@ -102,6 +112,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1951a9467db81c29743ddc496672c7fb0f0e6b41
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl
@@ -0,0 +1,24 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
index 7ed67af400ce7498546ef818afe90ff33e3c04e2..d42226b8521136d8b3d131652da99f6ef8a14edf 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -36,7 +36,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+ lofar2_unb2b_sdp_station_full_pins.tcl
quartus_vhdl_files =
@@ -69,19 +69,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
@@ -99,6 +109,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
index 43623ac2bc174a5aaa9ff1106c4315e37ff26849..e89d875b7b5b62e35fc228473a088f0da4017afd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -23,7 +23,7 @@
-- Wrapper for Lofar2 SDP Station full design
-- Description:
-- Unb2b version for lab testing
--- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB and BF
+-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
@@ -76,13 +76,22 @@ ENTITY lofar2_unb2b_sdp_station_full IS
-- Transceiver clocks
SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
- -- front transceivers
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
-
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
-- back transceivers (note only 6 are used in unb2b)
BCK_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_tr_jesd204b + c_unb2b_board_start_tr_jesd204b-1 downto c_unb2b_board_nof_tr_jesd204b); -- c_unb2b_board_nof_tr_jesd204b = 6, c_sdp_S_pn = 12
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
@@ -159,13 +168,22 @@ BEGIN
-- Transceiver clocks
SA_CLK => SA_CLK,
- -- front transceivers
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
QSFP_1_RX => QSFP_1_RX,
QSFP_1_TX => QSFP_1_TX,
-
-- LEDs
QSFP_LED => QSFP_LED,
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
-- back transceivers
JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
JESD204B_REFCLK => JESD204B_REFCLK,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b85bc78b08035457af0eed4a6fae25007a1f4bef
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl
@@ -0,0 +1,26 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..8c6453b5bb4a43f992e2397e5e589081dc3fe6fd
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg
@@ -0,0 +1,131 @@
+hdl_lib_name = lofar2_unb2b_sdp_station_full_wg
+hdl_library_clause_name = lofar2_unb2b_sdp_station_full_wg_lib
+hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e1sg
+
+ synth_files =
+ lofar2_unb2b_sdp_station_full_wg.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2b_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ lofar2_unb2b_sdp_station_full_wg_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9b7c7ae3d0e55821d966ba9473b214ea0407fde2
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
@@ -0,0 +1,158 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station full design.
+-- Description:
+-- Unb2b version for lab testing of SDP using the WG.
+-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
+
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2b_sdp_station_full_wg IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2b_sdp_station_full_wg";
+ g_design_note : STRING := "Lofar2 SDP station full design WG";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- front transceivers
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0)
+ );
+END lofar2_unb2b_sdp_station_full_wg;
+
+ARCHITECTURE str OF lofar2_unb2b_sdp_station_full_wg IS
+
+BEGIN
+
+ u_revision : ENTITY lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..689b010fb83a0f4df276dd070b6e8cc383755595
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl
@@ -0,0 +1,25 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index fed2e8b3d27bd1e91b75b1b772ad6b976d1eaf97..b1e3cfd9e4be1250ed1ab05ddee127de07c10ad1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -39,7 +39,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+ lofar2_unb2b_sdp_station_xsub_one_pins.tcl
quartus_vhdl_files =
@@ -72,19 +72,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
@@ -102,6 +112,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1951a9467db81c29743ddc496672c7fb0f0e6b41
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl
@@ -0,0 +1,24 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
index 395e76106e502dc0219b3655a4c1f67d9f5de88f..84b35008e1ead3ca8f609fb50ca80ea295fc43ec 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
@@ -37,7 +37,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2b_sdp_station_pins.tcl
+ lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
quartus_vhdl_files =
@@ -70,19 +70,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
@@ -100,6 +110,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..29347861db580a487457a4c698ccfec42f264ec0
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
@@ -0,0 +1,25 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index ba5e595a6216fdf42f9df375a5a4f510d567fd31..cc9fab9fcd06ae09302aee6c241b78a2968c75e3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -328,7 +328,7 @@ BEGIN
----------------------------------------------------------------------------
FOR I IN 0 TO c_sdp_P_sq-1 LOOP
IF I >= c_P_sq THEN
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_ALIGN_V2", I, 0, tb_clk);
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_ALIGN_V2_XSUB", I, 0, tb_clk);
END IF;
END LOOP;
@@ -452,31 +452,31 @@ BEGIN
----------------------------------------------------------------------------
FOR RN IN 0 TO c_nof_rn-1 LOOP
FOR J IN 0 TO c_P_sq-1 LOOP -- bsn_monitor index
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+0, rd_data, tb_clk); --status bits
- REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2))) & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+1, rd_data, tb_clk); --bsn at sync
- REPORT "bsn_at_sync = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+3, rd_data, tb_clk); --nof_sop
- REPORT "nof_sop = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+4, rd_data, tb_clk); --nof_valid
- REPORT "nof_valid = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+5, rd_data, tb_clk); --nof_err
- REPORT "nof_err = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT", J * 8+6, rd_data, tb_clk); --latency
- REPORT "latency = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_input on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8+0, rd_data, tb_clk); --status bits
+ REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2))) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8+1, rd_data, tb_clk); --bsn at sync
+ REPORT "bsn_at_sync = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8+3, rd_data, tb_clk); --nof_sop
+ REPORT "nof_sop = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8+4, rd_data, tb_clk); --nof_valid
+ REPORT "nof_valid = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8+5, rd_data, tb_clk); --nof_err
+ REPORT "nof_err = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB", J * 8+6, rd_data, tb_clk); --latency
+ REPORT "latency = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_rx_align_xsub on RN_" & INTEGER'IMAGE(RN) & ", CH_" & INTEGER'IMAGE(J) & "." SEVERITY NOTE;
END LOOP;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 0, rd_data, tb_clk); --status bits
- REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2))) & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 1, rd_data, tb_clk); --bsn at sync
- REPORT "bsn_at_sync = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 3, rd_data, tb_clk); --nof_sop
- REPORT "nof_sop = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 4, rd_data, tb_clk); --nof_valid
- REPORT "nof_valid = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 5, rd_data, tb_clk); --nof_err
- REPORT "nof_err = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
- mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT", 6, rd_data, tb_clk); --latency
- REPORT "latency = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_bsn_align_v2_output on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 0, rd_data, tb_clk); --status bits
+ REPORT "sync_timeout = " & INTEGER'IMAGE(TO_UINT(rd_data(2 DOWNTO 2))) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 1, rd_data, tb_clk); --bsn at sync
+ REPORT "bsn_at_sync = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 3, rd_data, tb_clk); --nof_sop
+ REPORT "nof_sop = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 4, rd_data, tb_clk); --nof_valid
+ REPORT "nof_valid = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 5, rd_data, tb_clk); --nof_err
+ REPORT "nof_err = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB", 6, rd_data, tb_clk); --latency
+ REPORT "latency = " & INTEGER'IMAGE(TO_UINT(rd_data)) & " from reg_bsn_monitor_v2_aligned_xsub on RN_" & INTEGER'IMAGE(RN) & "." SEVERITY NOTE;
END LOOP;
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 9d8f88314e6a10f0605469342c88327c05d6e671..3e7aea525e5bd1afc6569562ad4ed14aab8d3619 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -107,12 +107,12 @@ ENTITY lofar2_unb2b_sdp_station IS
RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.bus_w-1 DOWNTO 0);
-- back transceivers (Note: numbered from 0)
- JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0); -- c_sdp_S_pn = 12, c_unb2b_board_nof_tr_jesd204b = 6
+ JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => '0'); -- c_sdp_S_pn = 12, c_unb2b_board_nof_tr_jesd204b = 6
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : IN STD_LOGIC; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : IN STD_LOGIC := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
- JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYSREF : IN STD_LOGIC := '0';
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0) -- c_unb2b_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
);
END lofar2_unb2b_sdp_station;
@@ -148,269 +148,309 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL pout_wdi : STD_LOGIC;
-- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_wdi_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_wdi_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst;
-- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_ppsh_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst;
-- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL rom_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-- UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_unb_sens_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_unb_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_unb_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-- pm bus
- SIGNAL reg_unb_pmbus_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_unb_pmbus_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_unb_pmbus_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_unb_pmbus_cipo : t_mem_cipo := c_mem_cipo_rst;
-- FPGA sensors
- SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_fpga_temp_sens_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-- eth1g
SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ SIGNAL eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dpmm_data_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_mmdp_data_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_epcs_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_epcs_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_remu_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_remu_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Scrap ram
- SIGNAL ram_scrap_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_scrap_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_scrap_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- AIT
----------------------------------------------
-- JESD
- SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL jesd204b_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL jesd204b_cipo : t_mem_cipo := c_mem_cipo_rst;
-- JESD control
- SIGNAL jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL jesd_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL jesd_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Shiftram (applies per-antenna delay)
- SIGNAL reg_dp_shiftram_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_shiftram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_shiftram_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_shiftram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn source
- SIGNAL reg_bsn_source_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_source_v2_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_source_v2_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_source_v2_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn scheduler
- SIGNAL reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_scheduler_wg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_scheduler_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_scheduler_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
-- WG
- SIGNAL reg_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_wg_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_wg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL ram_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
-- BSN MONITOR
- SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_monitor_input_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_monitor_input_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_input_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Data buffer bsn
- SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_diag_data_buf_bsn_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_diag_data_buf_bsn_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_diag_data_buf_bsn_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_diag_data_buf_bsn_cipo : t_mem_cipo := c_mem_cipo_rst;
-- ST Histogram
- SIGNAL ram_st_histogram_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_histogram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_histogram_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_histogram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Aduh statistics monitor
- SIGNAL reg_aduh_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_aduh_monitor_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_aduh_monitor_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- FSUB
----------------------------------------------
-- Subband statistics
- SIGNAL ram_st_sst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_sst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_sst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_sst_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Spectral Inversion
- SIGNAL reg_si_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_si_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_si_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_si_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Filter coefficients
- SIGNAL ram_fil_coefs_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_fil_coefs_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_fil_coefs_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_fil_coefs_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Equalizer gains
- SIGNAL ram_equalizer_gains_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_equalizer_gains_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_equalizer_gains_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_equalizer_gains_cipo : t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
- SIGNAL reg_dp_selector_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_selector_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_selector_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_selector_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SDP Info
----------------------------------------------
- SIGNAL reg_sdp_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_sdp_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_sdp_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_sdp_info_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- RING Info
----------------------------------------------
- SIGNAL reg_ring_info_copi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_ring_info_cipo : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- XSUB
----------------------------------------------
+
-- crosslets_info
- SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_crosslets_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_crosslets_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-- crosslets_info
- SIGNAL reg_nof_crosslets_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nof_crosslets_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nof_crosslets_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nof_crosslets_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn_scheduler_xsub
- SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_sync_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
-- st_xsq
- SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_xsq_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_xsq_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- BF
----------------------------------------------
-- Beamlet Subband Select
- SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_ss_ss_wide_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_ss_ss_wide_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_ss_ss_wide_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Local BF bf weights
- SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_bf_weights_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_bf_weights_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_bf_weights_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF bsn aligner_v2
+ SIGNAL reg_bsn_align_v2_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_align_v2_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF bsn aligner_v2 bsn monitors
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
-- mms_dp_scale Scale Beamlets
- SIGNAL reg_bf_scale_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bf_scale_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bf_scale_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bf_scale_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output header fields
- SIGNAL reg_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_hdr_dat_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
- SIGNAL reg_dp_xonoff_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_xonoff_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_xonoff_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_xonoff_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Statistics (BST)
- SIGNAL ram_st_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring lane info
+ SIGNAL reg_ring_lane_info_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ring_lane_info_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor rx
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+ -- BF ring bsn monitor tx
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring validate err
+ SIGNAL reg_dp_block_validate_err_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_block_validate_err_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn at sync
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_sst_mosi : t_mem_mosi;
- SIGNAL reg_stat_enable_sst_miso : t_mem_miso;
+ SIGNAL reg_stat_enable_sst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_sst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_sst_mosi : t_mem_mosi;
- SIGNAL reg_stat_hdr_dat_sst_miso : t_mem_miso;
+ SIGNAL reg_stat_hdr_dat_sst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_sst_cipo : t_mem_cipo;
+ -- SST UDP offload bsn monitor
+ SIGNAL reg_bsn_monitor_v2_sst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_sst_offload_cipo : t_mem_cipo;
----------------------------------------------
-- XST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_xst_mosi : t_mem_mosi;
- SIGNAL reg_stat_enable_xst_miso : t_mem_miso;
+ SIGNAL reg_stat_enable_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_xst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_xst_mosi : t_mem_mosi;
- SIGNAL reg_stat_hdr_dat_xst_miso : t_mem_miso;
+ SIGNAL reg_stat_hdr_dat_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_xst_cipo : t_mem_cipo;
-- XST bsn aligner_v2
- SIGNAL reg_bsn_align_v2_copi : t_mem_mosi;
- SIGNAL reg_bsn_align_v2_cipo : t_mem_miso;
+ SIGNAL reg_bsn_align_v2_xsub_copi : t_mem_copi;
+ SIGNAL reg_bsn_align_v2_xsub_cipo : t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_cipo : t_mem_miso;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_rx_align_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_align_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
-- XST UDP offload bsn monitor
- SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_xst_offload_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_xst_offload_cipo : t_mem_cipo;
-- XST ring lane info
- SIGNAL reg_ring_lane_info_xst_copi : t_mem_mosi;
- SIGNAL reg_ring_lane_info_xst_cipo : t_mem_miso;
+ SIGNAL reg_ring_lane_info_xst_copi : t_mem_copi;
+ SIGNAL reg_ring_lane_info_xst_cipo : t_mem_cipo;
-- XST ring bsn monitor rx
- SIGNAL reg_bsn_monitor_v2_ring_rx_xst_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_ring_rx_xst_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_xst_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_xst_cipo : t_mem_cipo;
-- XST ring bsn monitor tx
- SIGNAL reg_bsn_monitor_v2_ring_tx_xst_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_ring_tx_xst_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_xst_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_xst_cipo : t_mem_cipo;
-- XST ring validate err
- SIGNAL reg_dp_block_validate_err_xst_copi : t_mem_mosi;
- SIGNAL reg_dp_block_validate_err_xst_cipo : t_mem_miso;
+ SIGNAL reg_dp_block_validate_err_xst_copi : t_mem_copi;
+ SIGNAL reg_dp_block_validate_err_xst_cipo : t_mem_cipo;
-- XST ring bsn at sync
- SIGNAL reg_dp_block_validate_bsn_at_sync_xst_copi : t_mem_mosi;
- SIGNAL reg_dp_block_validate_bsn_at_sync_xst_cipo : t_mem_miso;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_xst_copi : t_mem_copi;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_xst_cipo : t_mem_cipo;
-- XST ring MAC10G
- SIGNAL reg_tr_10GbE_mac_copi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_mac_cipo : t_mem_miso;
+ SIGNAL reg_tr_10GbE_mac_copi : t_mem_copi;
+ SIGNAL reg_tr_10GbE_mac_cipo : t_mem_cipo;
-- XST ring ETH10G
- SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_miso;
+ SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_copi;
+ SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_cipo;
----------------------------------------------
-- BST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_stat_enable_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_stat_enable_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_stat_enable_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_stat_hdr_dat_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_stat_hdr_dat_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_stat_hdr_dat_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BST UDP offload bsn monitor
+ SIGNAL reg_bsn_monitor_v2_bst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_bst_offload_cipo : t_mem_cipo;
+ -- Beamlet output bsn monitor
+ SIGNAL reg_bsn_monitor_v2_beamlet_output_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_beamlet_output_cipo : t_mem_cipo;
----------------------------------------------
-- UDP Offload
----------------------------------------------
@@ -420,11 +460,11 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
----------------------------------------------
-- 10 GbE
----------------------------------------------
- SIGNAL reg_nw_10GbE_mac_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nw_10GbE_mac_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nw_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nw_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst;
- SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nw_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nw_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
-- 10GbE
SIGNAL i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -493,68 +533,68 @@ BEGIN
-- MM buses
-- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
-- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
-- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
-- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
-- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_sens_mosi => reg_unb_sens_copi,
+ reg_unb_sens_miso => reg_unb_sens_cipo,
-- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+ reg_unb_pmbus_mosi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_cipo,
-- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
-- eth1g
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
-- eth1g UDP streaming
udp_tx_sosi_arr => udp_tx_sosi_arr,
udp_tx_siso_arr => udp_tx_siso_arr,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
-- FPGA pins
-- . General
@@ -598,127 +638,149 @@ BEGIN
pout_wdi => pout_wdi,
-- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_unb_sens_copi => reg_unb_sens_copi,
+ reg_unb_sens_cipo => reg_unb_sens_cipo,
+ reg_unb_pmbus_copi => reg_unb_pmbus_copi,
+ reg_unb_pmbus_cipo => reg_unb_pmbus_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
-- mm buses for signal flow blocks
-- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
reg_ring_info_copi => reg_ring_info_copi,
reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
- reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
- reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
- reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
- reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
- reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
- reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
- reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
- reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_miso => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
- reg_bsn_align_v2_copi => reg_bsn_align_v2_copi,
- reg_bsn_align_v2_cipo => reg_bsn_align_v2_cipo,
- reg_bsn_monitor_v2_bsn_align_v2_input_copi => reg_bsn_monitor_v2_bsn_align_v2_input_copi,
- reg_bsn_monitor_v2_bsn_align_v2_input_cipo => reg_bsn_monitor_v2_bsn_align_v2_input_cipo,
- reg_bsn_monitor_v2_bsn_align_v2_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
- reg_bsn_monitor_v2_bsn_align_v2_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
@@ -733,8 +795,8 @@ BEGIN
reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
);
@@ -749,6 +811,7 @@ BEGIN
g_wpfb => g_wpfb,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
g_scope_selected_subband => g_scope_selected_subband,
+ g_no_jesd => c_revision_select.no_jesd,
g_use_fsub => c_revision_select.use_fsub,
g_use_xsub => c_revision_select.use_xsub,
g_use_bf => c_revision_select.use_bf,
@@ -781,101 +844,119 @@ BEGIN
udp_tx_siso_arr => udp_tx_siso_arr,
-- 10 GbE
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-- AIT
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-- FSUB
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
-- SDP Info
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
-- RING Info
reg_ring_info_copi => reg_ring_info_copi,
reg_ring_info_cipo => reg_ring_info_cipo,
-- XSUB
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_miso => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
-- BF
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
-
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
-- SST
- reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
- reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
- reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-- XST
- reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
-
- reg_bsn_align_copi => reg_bsn_align_v2_copi,
- reg_bsn_align_cipo => reg_bsn_align_v2_cipo,
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_v2_input_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_v2_input_cipo,
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
- reg_xst_udp_monitor_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_xst_udp_monitor_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
@@ -892,10 +973,14 @@ BEGIN
reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-- BST
- reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
- reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
- reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
- reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
RING_0_TX => RING_0_TX,
RING_0_RX => RING_0_RX,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index a11519eeffed0924215d62d651f8230403a4b293..f30f8846296984174033903e141b5d2d5c3f7877 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -35,17 +35,19 @@ PACKAGE lofar2_unb2b_sdp_station_pkg IS
no_jesd : BOOLEAN;
use_fsub : BOOLEAN;
use_bf : BOOLEAN;
- use_xsub : BOOLEAN;
- use_ring : BOOLEAN;
+ use_xsub : BOOLEAN;
+ use_ring : BOOLEAN;
P_sq : NATURAL;
END RECORD;
CONSTANT c_ait : t_lofar2_unb2b_sdp_station_config := (FALSE, FALSE, FALSE, FALSE, FALSE, 0);
CONSTANT c_fsub : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, FALSE, 0);
CONSTANT c_bf : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, FALSE, 0);
+ CONSTANT c_bf_ring : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, TRUE, 0);
CONSTANT c_xsub_one : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, FALSE, 1);
CONSTANT c_xsub_ring : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, TRUE, 9);
- CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, FALSE, 1);
+ CONSTANT c_full_wg : t_lofar2_unb2b_sdp_station_config := (TRUE, TRUE, TRUE, TRUE, TRUE, 9);
+ CONSTANT c_full : t_lofar2_unb2b_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, TRUE, 9);
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_sdp_station_config;
@@ -61,8 +63,10 @@ PACKAGE BODY lofar2_unb2b_sdp_station_pkg IS
IF g_design_name = "lofar2_unb2b_sdp_station_adc" THEN RETURN c_ait;
ELSIF g_design_name = "lofar2_unb2b_sdp_station_fsub" THEN RETURN c_fsub;
ELSIF g_design_name = "lofar2_unb2b_sdp_station_bf" THEN RETURN c_bf;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_bf_ring" THEN RETURN c_bf_ring;
ELSIF g_design_name = "lofar2_unb2b_sdp_station_xsub_one" THEN RETURN c_xsub_one;
ELSIF g_design_name = "lofar2_unb2b_sdp_station_xsub_ring" THEN RETURN c_xsub_ring;
+ ELSIF g_design_name = "lofar2_unb2b_sdp_station_full_wg" THEN RETURN c_full_wg;
ELSE RETURN c_full;
END IF;
END;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 49693f03c1dec83cde6d603d98d65978307fb140..13c10090a51a778b667f3f99b32412fa1b07edad 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -43,250 +43,292 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
- reg_wdi_mosi : OUT t_mem_mosi;
- reg_wdi_miso : IN t_mem_miso;
+ reg_wdi_copi : OUT t_mem_copi;
+ reg_wdi_cipo : IN t_mem_cipo;
-- system_info
- reg_unb_system_info_mosi : OUT t_mem_mosi;
- reg_unb_system_info_miso : IN t_mem_miso;
- rom_unb_system_info_mosi : OUT t_mem_mosi;
- rom_unb_system_info_miso : IN t_mem_miso;
+ reg_unb_system_info_copi : OUT t_mem_copi;
+ reg_unb_system_info_cipo : IN t_mem_cipo;
+ rom_unb_system_info_copi : OUT t_mem_copi;
+ rom_unb_system_info_cipo : IN t_mem_cipo;
-- UniBoard I2C sensors
- reg_unb_sens_mosi : OUT t_mem_mosi;
- reg_unb_sens_miso : IN t_mem_miso;
+ reg_unb_sens_copi : OUT t_mem_copi;
+ reg_unb_sens_cipo : IN t_mem_cipo;
- reg_fpga_temp_sens_mosi : OUT t_mem_mosi;
- reg_fpga_temp_sens_miso : IN t_mem_miso;
- reg_fpga_voltage_sens_mosi: OUT t_mem_mosi;
- reg_fpga_voltage_sens_miso: IN t_mem_miso;
+ reg_fpga_temp_sens_copi : OUT t_mem_copi;
+ reg_fpga_temp_sens_cipo : IN t_mem_cipo;
+ reg_fpga_voltage_sens_copi: OUT t_mem_copi;
+ reg_fpga_voltage_sens_cipo: IN t_mem_cipo;
- reg_unb_pmbus_mosi : OUT t_mem_mosi;
- reg_unb_pmbus_miso : IN t_mem_miso;
+ reg_unb_pmbus_copi : OUT t_mem_copi;
+ reg_unb_pmbus_cipo : IN t_mem_cipo;
-- PPSH
- reg_ppsh_mosi : OUT t_mem_mosi;
- reg_ppsh_miso : IN t_mem_miso;
+ reg_ppsh_copi : OUT t_mem_copi;
+ reg_ppsh_cipo : IN t_mem_cipo;
-- eth1g
eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_tse_mosi : OUT t_mem_mosi;
- eth1g_tse_miso : IN t_mem_miso;
- eth1g_reg_mosi : OUT t_mem_mosi;
- eth1g_reg_miso : IN t_mem_miso;
+ eth1g_tse_copi : OUT t_mem_copi;
+ eth1g_tse_cipo : IN t_mem_cipo;
+ eth1g_reg_copi : OUT t_mem_copi;
+ eth1g_reg_cipo : IN t_mem_cipo;
eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso;
+ eth1g_ram_copi : OUT t_mem_copi;
+ eth1g_ram_cipo : IN t_mem_cipo;
-- EPCS read
- reg_dpmm_data_mosi : OUT t_mem_mosi;
- reg_dpmm_data_miso : IN t_mem_miso;
- reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
- reg_dpmm_ctrl_miso : IN t_mem_miso;
+ reg_dpmm_data_copi : OUT t_mem_copi;
+ reg_dpmm_data_cipo : IN t_mem_cipo;
+ reg_dpmm_ctrl_copi : OUT t_mem_copi;
+ reg_dpmm_ctrl_cipo : IN t_mem_cipo;
-- EPCS write
- reg_mmdp_data_mosi : OUT t_mem_mosi;
- reg_mmdp_data_miso : IN t_mem_miso;
- reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
- reg_mmdp_ctrl_miso : IN t_mem_miso;
+ reg_mmdp_data_copi : OUT t_mem_copi;
+ reg_mmdp_data_cipo : IN t_mem_cipo;
+ reg_mmdp_ctrl_copi : OUT t_mem_copi;
+ reg_mmdp_ctrl_cipo : IN t_mem_cipo;
-- EPCS status/control
- reg_epcs_mosi : OUT t_mem_mosi;
- reg_epcs_miso : IN t_mem_miso;
+ reg_epcs_copi : OUT t_mem_copi;
+ reg_epcs_cipo : IN t_mem_cipo;
-- Remote Update
- reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso;
+ reg_remu_copi : OUT t_mem_copi;
+ reg_remu_cipo : IN t_mem_cipo;
-- Jesd control
- jesd204b_mosi : OUT t_mem_mosi;
- jesd204b_miso : IN t_mem_miso;
+ jesd204b_copi : OUT t_mem_copi;
+ jesd204b_cipo : IN t_mem_cipo;
-- Dp shiftram
- reg_dp_shiftram_mosi : OUT t_mem_mosi;
- reg_dp_shiftram_miso : IN t_mem_miso;
+ reg_dp_shiftram_copi : OUT t_mem_copi;
+ reg_dp_shiftram_cipo : IN t_mem_cipo;
-- Bsn source
- reg_bsn_source_v2_mosi : OUT t_mem_mosi;
- reg_bsn_source_v2_miso : IN t_mem_miso;
+ reg_bsn_source_v2_copi : OUT t_mem_copi;
+ reg_bsn_source_v2_cipo : IN t_mem_cipo;
-- bsn schduler for wg trigger
- reg_bsn_scheduler_mosi : OUT t_mem_mosi;
- reg_bsn_scheduler_miso : IN t_mem_miso;
+ reg_bsn_scheduler_copi : OUT t_mem_copi;
+ reg_bsn_scheduler_cipo : IN t_mem_cipo;
-- BSN Monitor
- reg_bsn_monitor_input_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_monitor_input_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_bsn_monitor_input_copi : OUT t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_input_cipo : IN t_mem_cipo := c_mem_cipo_rst;
-- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- reg_wg_mosi : OUT t_mem_mosi;
- reg_wg_miso : IN t_mem_miso;
- ram_wg_mosi : OUT t_mem_mosi;
- ram_wg_miso : IN t_mem_miso;
+ reg_wg_copi : OUT t_mem_copi;
+ reg_wg_cipo : IN t_mem_cipo;
+ ram_wg_copi : OUT t_mem_copi;
+ ram_wg_cipo : IN t_mem_cipo;
-- Bsn databuffer
- ram_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_bsn_miso : IN t_mem_miso;
- reg_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_bsn_miso : IN t_mem_miso;
+ ram_diag_data_buf_bsn_copi : OUT t_mem_copi;
+ ram_diag_data_buf_bsn_cipo : IN t_mem_cipo;
+ reg_diag_data_buf_bsn_copi : OUT t_mem_copi;
+ reg_diag_data_buf_bsn_cipo : IN t_mem_cipo;
-- ST Histogram
- ram_st_histogram_mosi : OUT t_mem_mosi;
- ram_st_histogram_miso : IN t_mem_miso;
+ ram_st_histogram_copi : OUT t_mem_copi;
+ ram_st_histogram_cipo : IN t_mem_cipo;
-- Aduh
- reg_aduh_monitor_mosi : OUT t_mem_mosi;
- reg_aduh_monitor_miso : IN t_mem_miso;
+ reg_aduh_monitor_copi : OUT t_mem_copi;
+ reg_aduh_monitor_cipo : IN t_mem_cipo;
-- Subband statistics
- ram_st_sst_mosi : OUT t_mem_mosi;
- ram_st_sst_miso : IN t_mem_miso;
+ ram_st_sst_copi : OUT t_mem_copi;
+ ram_st_sst_cipo : IN t_mem_cipo;
-- Filter coefficients
- ram_fil_coefs_mosi : OUT t_mem_mosi;
- ram_fil_coefs_miso : IN t_mem_miso;
+ ram_fil_coefs_copi : OUT t_mem_copi;
+ ram_fil_coefs_cipo : IN t_mem_cipo;
-- Spectral Inversion
- reg_si_mosi : OUT t_mem_mosi;
- reg_si_miso : IN t_mem_miso;
+ reg_si_copi : OUT t_mem_copi;
+ reg_si_cipo : IN t_mem_cipo;
-- Equalizer gains
- ram_equalizer_gains_mosi : OUT t_mem_mosi;
- ram_equalizer_gains_miso : IN t_mem_miso;
+ ram_equalizer_gains_copi : OUT t_mem_copi;
+ ram_equalizer_gains_cipo : IN t_mem_cipo;
-- DP Selector
- reg_dp_selector_mosi : OUT t_mem_mosi;
- reg_dp_selector_miso : IN t_mem_miso;
+ reg_dp_selector_copi : OUT t_mem_copi;
+ reg_dp_selector_cipo : IN t_mem_cipo;
-- SDP Info
- reg_sdp_info_mosi : OUT t_mem_mosi;
- reg_sdp_info_miso : IN t_mem_miso;
+ reg_sdp_info_copi : OUT t_mem_copi;
+ reg_sdp_info_cipo : IN t_mem_cipo;
-- RING Info
- reg_ring_info_copi : OUT t_mem_mosi;
- reg_ring_info_cipo : IN t_mem_miso;
+ reg_ring_info_copi : OUT t_mem_copi;
+ reg_ring_info_cipo : IN t_mem_cipo;
-- Beamlet Subband Select
- ram_ss_ss_wide_mosi : OUT t_mem_mosi;
- ram_ss_ss_wide_miso : IN t_mem_miso;
+ ram_ss_ss_wide_copi : OUT t_mem_copi;
+ ram_ss_ss_wide_cipo : IN t_mem_cipo;
-- Local BF bf weights
- ram_bf_weights_mosi : OUT t_mem_mosi;
- ram_bf_weights_miso : IN t_mem_miso;
+ ram_bf_weights_copi : OUT t_mem_copi;
+ ram_bf_weights_cipo : IN t_mem_cipo;
+
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : OUT t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : IN t_mem_cipo;
+
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : IN t_mem_cipo;
-- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : OUT t_mem_mosi;
- reg_bf_scale_miso : IN t_mem_miso;
+ reg_bf_scale_copi : OUT t_mem_copi;
+ reg_bf_scale_cipo : IN t_mem_cipo;
-- Beamlet Data Output header fields
- reg_hdr_dat_mosi : OUT t_mem_mosi;
- reg_hdr_dat_miso : IN t_mem_miso;
+ reg_hdr_dat_copi : OUT t_mem_copi;
+ reg_hdr_dat_cipo : IN t_mem_cipo;
-- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : OUT t_mem_mosi;
- reg_dp_xonoff_miso : IN t_mem_miso;
+ reg_dp_xonoff_copi : OUT t_mem_copi;
+ reg_dp_xonoff_cipo : IN t_mem_cipo;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : OUT t_mem_copi;
+ reg_ring_lane_info_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : OUT t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : OUT t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : IN t_mem_cipo;
-- Beamlet Statistics (BST)
- ram_st_bst_mosi : OUT t_mem_mosi;
- ram_st_bst_miso : IN t_mem_miso;
+ ram_st_bst_copi : OUT t_mem_copi;
+ ram_st_bst_cipo : IN t_mem_cipo;
-- Subband Statistics offload
- reg_stat_enable_sst_mosi : OUT t_mem_mosi;
- reg_stat_enable_sst_miso : IN t_mem_miso;
+ reg_stat_enable_sst_copi : OUT t_mem_copi;
+ reg_stat_enable_sst_cipo : IN t_mem_cipo;
-- Statistics header info
- reg_stat_hdr_dat_sst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_sst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_sst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : IN t_mem_cipo;
-- Crosslet Statistics offload
- reg_stat_enable_xst_mosi : OUT t_mem_mosi;
- reg_stat_enable_xst_miso : IN t_mem_miso;
+ reg_stat_enable_xst_copi : OUT t_mem_copi;
+ reg_stat_enable_xst_cipo : IN t_mem_cipo;
-- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_xst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_xst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : IN t_mem_cipo;
-- Beamlet Statistics offload
- reg_stat_enable_bst_mosi : OUT t_mem_mosi;
- reg_stat_enable_bst_miso : IN t_mem_miso;
+ reg_stat_enable_bst_copi : OUT t_mem_copi;
+ reg_stat_enable_bst_cipo : IN t_mem_cipo;
-- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_bst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : IN t_mem_cipo;
-- crosslets_info
- reg_crosslets_info_mosi : OUT t_mem_mosi;
- reg_crosslets_info_miso : IN t_mem_miso;
+ reg_crosslets_info_copi : OUT t_mem_copi;
+ reg_crosslets_info_cipo : IN t_mem_cipo;
-- crosslets_info
- reg_nof_crosslets_mosi : OUT t_mem_mosi;
- reg_nof_crosslets_miso : IN t_mem_miso;
+ reg_nof_crosslets_copi : OUT t_mem_copi;
+ reg_nof_crosslets_cipo : IN t_mem_cipo;
-- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
- reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
+ reg_bsn_sync_scheduler_xsub_copi : OUT t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : IN t_mem_cipo;
-- st_xsq (XST)
- ram_st_xsq_mosi : OUT t_mem_mosi;
- ram_st_xsq_miso : IN t_mem_miso;
+ ram_st_xsq_copi : OUT t_mem_copi;
+ ram_st_xsq_cipo : IN t_mem_cipo;
-- 10 GbE mac
- reg_nw_10GbE_mac_mosi : OUT t_mem_mosi;
- reg_nw_10GbE_mac_miso : IN t_mem_miso;
+ reg_nw_10GbE_mac_copi : OUT t_mem_copi;
+ reg_nw_10GbE_mac_cipo : IN t_mem_cipo;
-- 10 GbE eth
- reg_nw_10GbE_eth10g_mosi : OUT t_mem_mosi;
- reg_nw_10GbE_eth10g_miso : IN t_mem_miso;
+ reg_nw_10GbE_eth10g_copi : OUT t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2
- reg_bsn_align_v2_copi : OUT t_mem_mosi;
- reg_bsn_align_v2_cipo : IN t_mem_miso;
+ reg_bsn_align_v2_xsub_copi : OUT t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_bsn_align_v2_input_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_v2_input_cipo : IN t_mem_miso;
- reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_rx_align_xsub_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : IN t_mem_cipo;
-- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_xst_offload_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : IN t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : IN t_mem_cipo;
+
+ -- Beamlet output bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_beamlet_output_cipo : IN t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : IN t_mem_cipo;
-- XST ring lane info
- reg_ring_lane_info_xst_copi : OUT t_mem_mosi;
- reg_ring_lane_info_xst_cipo : IN t_mem_miso;
+ reg_ring_lane_info_xst_copi : OUT t_mem_copi;
+ reg_ring_lane_info_xst_cipo : IN t_mem_cipo;
-- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_mosi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_miso;
+ reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_cipo;
-- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_cipo;
-- XST ring validate err
- reg_dp_block_validate_err_xst_copi : OUT t_mem_mosi;
- reg_dp_block_validate_err_xst_cipo : IN t_mem_miso;
+ reg_dp_block_validate_err_xst_copi : OUT t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : IN t_mem_cipo;
-- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_mosi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_miso;
+ reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_cipo;
-- XST ring MAC
- reg_tr_10GbE_mac_copi : OUT t_mem_mosi;
- reg_tr_10GbE_mac_cipo : IN t_mem_miso;
+ reg_tr_10GbE_mac_copi : OUT t_mem_copi;
+ reg_tr_10GbE_mac_cipo : IN t_mem_cipo;
-- XST ring ETH
- reg_tr_10GbE_eth10g_copi : OUT t_mem_mosi;
- reg_tr_10GbE_eth10g_cipo : IN t_mem_miso;
+ reg_tr_10GbE_eth10g_copi : OUT t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : IN t_mem_cipo;
-- Scrap ram
- ram_scrap_mosi : OUT t_mem_mosi;
- ram_scrap_miso : IN t_mem_miso;
+ ram_scrap_copi : OUT t_mem_copi;
+ ram_scrap_cipo : IN t_mem_cipo;
-- Jesd reset control
- jesd_ctrl_mosi : OUT t_mem_mosi;
- jesd_ctrl_miso : IN t_mem_miso
+ jesd_ctrl_copi : OUT t_mem_copi;
+ jesd_ctrl_cipo : IN t_mem_cipo
);
END mmm_lofar2_unb2b_sdp_station;
@@ -306,153 +348,186 @@ BEGIN
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_copi, reg_unb_sens_cipo );
u_mm_file_reg_unb_pmbus : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
- PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_copi, reg_unb_pmbus_cipo );
u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- PORT MAP(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ PORT MAP(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
u_mm_file_reg_bsn_source_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
u_mm_file_reg_bsn_scheduler : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
u_mm_file_reg_bsn_monitor_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
u_mm_file_reg_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ PORT MAP(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
u_mm_file_ram_st_histogram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- PORT MAP(mm_rst, mm_clk, ram_st_histogram_mosi, ram_st_histogram_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
u_mm_file_ram_st_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- PORT MAP(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
u_mm_file_ram_fil_coefs : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- PORT MAP(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ PORT MAP(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
u_mm_file_reg_si : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- PORT MAP(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ PORT MAP(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
u_mm_file_ram_equalizer_gains : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
u_mm_file_reg_dp_selector : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- PORT MAP(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
u_mm_file_reg_ring_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
PORT MAP(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+ PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- PORT MAP(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+ PORT MAP(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
u_mm_file_reg_bf_scale : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- PORT MAP(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
u_mm_file_reg_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
u_mm_file_reg_dp_xonoff : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
u_mm_file_ram_st_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- PORT MAP(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
u_mm_file_reg_stat_enable_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_mosi, reg_stat_enable_sst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
u_mm_file_reg_stat_hdr_info_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_mosi, reg_stat_hdr_dat_sst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
u_mm_file_reg_stat_enable_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_mosi, reg_stat_enable_xst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
u_mm_file_reg_stat_hdr_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_mosi, reg_stat_hdr_dat_xst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
u_mm_file_reg_stat_enable_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_mosi, reg_stat_enable_bst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
+ PORT MAP(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
u_mm_file_reg_nof_crosslets : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_mosi, reg_nof_crosslets_miso);
+ PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
+ PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
+ PORT MAP(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
u_mm_file_reg_nw_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+
+ u_mm_file_reg_bsn_align_v2_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
- u_mm_file_reg_bsn_align_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2")
- PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_copi, reg_bsn_align_v2_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_input_copi, reg_bsn_monitor_v2_bsn_align_v2_input_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_output: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_output_copi, reg_bsn_monitor_v2_bsn_align_v2_output_cipo );
+ u_mm_file_reg_ring_lane_info_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
+ PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
- u_mm_file_reg_ring_lane_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
+
+ u_mm_file_reg_dp_block_validate_err_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
+ PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
+
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
+ PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
+
+ u_mm_file_reg_bsn_align_v2_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+
+ u_mm_file_reg_ring_lane_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
+ PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
@@ -473,7 +548,7 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ PORT MAP(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -498,282 +573,282 @@ BEGIN
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_irq_export => eth1g_reg_interrupt,
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
- reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
- reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
- reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
- reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_address_export => reg_unb_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ reg_unb_sens_write_export => reg_unb_sens_copi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_read_export => reg_unb_sens_copi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_unb_pmbus_reset_export => OPEN,
reg_unb_pmbus_clk_export => OPEN,
- reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
- reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
- reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
- reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_unb_pmbus_address_export => reg_unb_pmbus_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
+ reg_unb_pmbus_write_export => reg_unb_pmbus_copi.wr,
+ reg_unb_pmbus_writedata_export => reg_unb_pmbus_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_pmbus_read_export => reg_unb_pmbus_copi.rd,
+ reg_unb_pmbus_readdata_export => reg_unb_pmbus_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
-- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+-- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_copi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ rom_system_info_read_export => rom_unb_system_info_copi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_write_export => reg_unb_system_info_copi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_read_export => reg_unb_system_info_copi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_copi.wr,
+ pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_pps_read_export => reg_ppsh_copi.rd,
+ pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_wdi_reset_export => OPEN,
reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 DOWNTO 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_wdi_address_export => reg_wdi_copi.address(0 DOWNTO 0),
+ reg_wdi_write_export => reg_wdi_copi.wr,
+ reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wdi_read_export => reg_wdi_copi.rd,
+ reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_remu_address_export => reg_remu_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_write_export => reg_remu_copi.wr,
+ reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_remu_read_export => reg_remu_copi.rd,
+ reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w-1 DOWNTO 0),
jesd204b_reset_export => OPEN,
jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w-1 DOWNTO 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w-1 DOWNTO 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
+ jesd204b_address_export => jesd204b_copi.address(c_sdp_jesd204b_addr_w-1 DOWNTO 0),
+ jesd204b_write_export => jesd204b_copi.wr,
+ jesd204b_writedata_export => jesd204b_copi.wrdata(c_word_w-1 DOWNTO 0),
+ jesd204b_read_export => jesd204b_copi.rd,
+ jesd204b_readdata_export => jesd204b_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_jesd_ctrl_reset_export => OPEN,
pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_address_export => jesd_ctrl_copi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_copi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_copi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_copi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_copi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_copi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_copi.wrdata(c_word_w-1 DOWNTO 0),
-- waveform generators (multiplexed)
reg_wg_clk_export => OPEN,
reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w-1 DOWNTO 0),
- reg_wg_read_export => reg_wg_mosi.rd,
- reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_wg_write_export => reg_wg_mosi.wr,
- reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wg_address_export => reg_wg_copi.address(c_sdp_reg_wg_addr_w-1 DOWNTO 0),
+ reg_wg_read_export => reg_wg_copi.rd,
+ reg_wg_readdata_export => reg_wg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_wg_write_export => reg_wg_copi.wr,
+ reg_wg_writedata_export => reg_wg_copi.wrdata(c_word_w-1 DOWNTO 0),
ram_wg_clk_export => OPEN,
ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w-1 DOWNTO 0),
- ram_wg_read_export => ram_wg_mosi.rd,
- ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_wg_write_export => ram_wg_mosi.wr,
- ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_wg_address_export => ram_wg_copi.address(c_sdp_ram_wg_addr_w-1 DOWNTO 0),
+ ram_wg_read_export => ram_wg_copi.rd,
+ ram_wg_readdata_export => ram_wg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ ram_wg_write_export => ram_wg_copi.wr,
+ ram_wg_writedata_export => ram_wg_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_shiftram_clk_export => OPEN,
reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w-1 DOWNTO 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_shiftram_address_export => reg_dp_shiftram_copi.address(c_sdp_reg_dp_shiftram_addr_w-1 DOWNTO 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_copi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_copi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_source_v2_clk_export => OPEN,
reg_bsn_source_v2_reset_export => OPEN,
- reg_bsn_source_v2_address_export => reg_bsn_source_v2_mosi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
- reg_bsn_source_v2_read_export => reg_bsn_source_v2_mosi.rd,
- reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_source_v2_write_export => reg_bsn_source_v2_mosi.wr,
- reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_address_export => reg_bsn_source_v2_copi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
+ reg_bsn_source_v2_read_export => reg_bsn_source_v2_copi.rd,
+ reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_write_export => reg_bsn_source_v2_copi.wr,
+ reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_scheduler_clk_export => OPEN,
reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w-1 DOWNTO 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_copi.address(c_sdp_reg_bsn_scheduler_addr_w-1 DOWNTO 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_copi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_copi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_epcs_address_export => reg_epcs_copi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_write_export => reg_epcs_copi.wr,
+ reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_epcs_read_export => reg_epcs_copi.rd,
+ reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_ctrl_reset_export => OPEN,
reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 DOWNTO 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 DOWNTO 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_data_reset_export => OPEN,
reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 DOWNTO 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 DOWNTO 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_data_reset_export => OPEN,
reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 DOWNTO 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 DOWNTO 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_reset_export => OPEN,
reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 DOWNTO 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 DOWNTO 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_copi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_copi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_copi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_bsn_reset_export => OPEN,
reg_diag_data_buffer_bsn_clk_export => OPEN,
- reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_copi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_copi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_copi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_histogram_clk_export => OPEN,
ram_st_histogram_reset_export => OPEN,
- ram_st_histogram_address_export => ram_st_histogram_mosi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
- ram_st_histogram_write_export => ram_st_histogram_mosi.wr,
- ram_st_histogram_writedata_export => ram_st_histogram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_histogram_read_export => ram_st_histogram_mosi.rd,
- ram_st_histogram_readdata_export => ram_st_histogram_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_address_export => ram_st_histogram_copi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
+ ram_st_histogram_write_export => ram_st_histogram_copi.wr,
+ ram_st_histogram_writedata_export => ram_st_histogram_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_read_export => ram_st_histogram_copi.rd,
+ ram_st_histogram_readdata_export => ram_st_histogram_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_aduh_monitor_reset_export => OPEN,
reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_aduh_monitor_address_export => reg_aduh_monitor_copi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_copi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_copi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_clk_export => OPEN,
ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w-1 DOWNTO 0),
- ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_fil_coefs_address_export => ram_fil_coefs_copi.address(c_sdp_ram_fil_coefs_addr_w-1 DOWNTO 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_copi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_copi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_sst_clk_export => OPEN,
ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w-1 DOWNTO 0),
- ram_st_sst_write_export => ram_st_sst_mosi.wr,
- ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_sst_read_export => ram_st_sst_mosi.rd,
- ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_sst_address_export => ram_st_sst_copi.address(c_sdp_ram_st_sst_addr_w-1 DOWNTO 0),
+ ram_st_sst_write_export => ram_st_sst_copi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_sst_read_export => ram_st_sst_copi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_si_clk_export => OPEN,
reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w-1 DOWNTO 0),
- reg_si_write_export => reg_si_mosi.wr,
- reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_si_read_export => reg_si_mosi.rd,
- reg_si_readdata_export => reg_si_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_si_address_export => reg_si_copi.address(c_sdp_reg_si_addr_w-1 DOWNTO 0),
+ reg_si_write_export => reg_si_copi.wr,
+ reg_si_writedata_export => reg_si_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_si_read_export => reg_si_copi.rd,
+ reg_si_readdata_export => reg_si_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_equalizer_gains_clk_export => OPEN,
ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_address_export => ram_equalizer_gains_copi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_copi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_selector_clk_export => OPEN,
reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
- reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
+ reg_dp_selector_write_export => reg_dp_selector_copi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_selector_read_export => reg_dp_selector_copi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_sdp_info_clk_export => OPEN,
reg_sdp_info_reset_export => OPEN,
- reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
- reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_address_export => reg_sdp_info_copi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
+ reg_sdp_info_write_export => reg_sdp_info_copi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_read_export => reg_sdp_info_copi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_ring_info_clk_export => OPEN,
reg_ring_info_reset_export => OPEN,
@@ -785,171 +860,219 @@ BEGIN
ram_ss_ss_wide_clk_export => OPEN,
ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_address_export => ram_ss_ss_wide_mosi.address(c_sdp_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
- ram_ss_ss_wide_write_export => ram_ss_ss_wide_mosi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_ss_ss_wide_read_export => ram_ss_ss_wide_mosi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_address_export => ram_ss_ss_wide_copi.address(c_sdp_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
+ ram_ss_ss_wide_write_export => ram_ss_ss_wide_copi.wr,
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_read_export => ram_ss_ss_wide_copi.rd,
+ ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_bf_weights_clk_export => OPEN,
ram_bf_weights_reset_export => OPEN,
- ram_bf_weights_address_export => ram_bf_weights_mosi.address(c_sdp_ram_bf_weights_addr_w-1 DOWNTO 0),
- ram_bf_weights_write_export => ram_bf_weights_mosi.wr,
- ram_bf_weights_writedata_export => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_bf_weights_read_export => ram_bf_weights_mosi.rd,
- ram_bf_weights_readdata_export => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_bf_weights_address_export => ram_bf_weights_copi.address(c_sdp_ram_bf_weights_addr_w-1 DOWNTO 0),
+ ram_bf_weights_write_export => ram_bf_weights_copi.wr,
+ ram_bf_weights_writedata_export => ram_bf_weights_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_bf_weights_read_export => ram_bf_weights_copi.rd,
+ ram_bf_weights_readdata_export => ram_bf_weights_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bf_scale_clk_export => OPEN,
reg_bf_scale_reset_export => OPEN,
- reg_bf_scale_address_export => reg_bf_scale_mosi.address(c_sdp_reg_bf_scale_addr_w-1 DOWNTO 0),
- reg_bf_scale_write_export => reg_bf_scale_mosi.wr,
- reg_bf_scale_writedata_export => reg_bf_scale_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bf_scale_read_export => reg_bf_scale_mosi.rd,
- reg_bf_scale_readdata_export => reg_bf_scale_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bf_scale_address_export => reg_bf_scale_copi.address(c_sdp_reg_bf_scale_addr_w-1 DOWNTO 0),
+ reg_bf_scale_write_export => reg_bf_scale_copi.wr,
+ reg_bf_scale_writedata_export => reg_bf_scale_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bf_scale_read_export => reg_bf_scale_copi.rd,
+ reg_bf_scale_readdata_export => reg_bf_scale_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_hdr_dat_clk_export => OPEN,
reg_hdr_dat_reset_export => OPEN,
- reg_hdr_dat_address_export => reg_hdr_dat_mosi.address(c_sdp_reg_bf_hdr_dat_addr_w-1 DOWNTO 0),
- reg_hdr_dat_write_export => reg_hdr_dat_mosi.wr,
- reg_hdr_dat_writedata_export => reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_hdr_dat_read_export => reg_hdr_dat_mosi.rd,
- reg_hdr_dat_readdata_export => reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_address_export => reg_hdr_dat_copi.address(c_sdp_reg_bf_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_hdr_dat_write_export => reg_hdr_dat_copi.wr,
+ reg_hdr_dat_writedata_export => reg_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
+ reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_xonoff_clk_export => OPEN,
reg_dp_xonoff_reset_export => OPEN,
- reg_dp_xonoff_address_export => reg_dp_xonoff_mosi.address(c_sdp_reg_dp_xonoff_addr_w-1 DOWNTO 0),
- reg_dp_xonoff_write_export => reg_dp_xonoff_mosi.wr,
- reg_dp_xonoff_writedata_export => reg_dp_xonoff_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_xonoff_read_export => reg_dp_xonoff_mosi.rd,
- reg_dp_xonoff_readdata_export => reg_dp_xonoff_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w-1 DOWNTO 0),
+ reg_dp_xonoff_write_export => reg_dp_xonoff_copi.wr,
+ reg_dp_xonoff_writedata_export => reg_dp_xonoff_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_read_export => reg_dp_xonoff_copi.rd,
+ reg_dp_xonoff_readdata_export => reg_dp_xonoff_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_bst_clk_export => OPEN,
ram_st_bst_reset_export => OPEN,
- ram_st_bst_address_export => ram_st_bst_mosi.address(c_sdp_ram_st_bst_addr_w-1 DOWNTO 0),
- ram_st_bst_write_export => ram_st_bst_mosi.wr,
- ram_st_bst_writedata_export => ram_st_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_bst_read_export => ram_st_bst_mosi.rd,
- ram_st_bst_readdata_export => ram_st_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_bst_address_export => ram_st_bst_copi.address(c_sdp_ram_st_bst_addr_w-1 DOWNTO 0),
+ ram_st_bst_write_export => ram_st_bst_copi.wr,
+ ram_st_bst_writedata_export => ram_st_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_bst_read_export => ram_st_bst_copi.rd,
+ ram_st_bst_readdata_export => ram_st_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_sst_clk_export => OPEN,
reg_stat_enable_sst_reset_export => OPEN,
- reg_stat_enable_sst_address_export => reg_stat_enable_sst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_sst_write_export => reg_stat_enable_sst_mosi.wr,
- reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_sst_read_export => reg_stat_enable_sst_mosi.rd,
- reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_address_export => reg_stat_enable_sst_copi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_sst_write_export => reg_stat_enable_sst_copi.wr,
+ reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_read_export => reg_stat_enable_sst_copi.rd,
+ reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_sst_clk_export => OPEN,
reg_stat_hdr_dat_sst_reset_export => OPEN,
- reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_mosi.wr,
- reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_mosi.rd,
- reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_copi.wr,
+ reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_copi.rd,
+ reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_xst_clk_export => OPEN,
reg_stat_enable_xst_reset_export => OPEN,
- reg_stat_enable_xst_address_export => reg_stat_enable_xst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_xst_write_export => reg_stat_enable_xst_mosi.wr,
- reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_xst_read_export => reg_stat_enable_xst_mosi.rd,
- reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_address_export => reg_stat_enable_xst_copi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_xst_write_export => reg_stat_enable_xst_copi.wr,
+ reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_read_export => reg_stat_enable_xst_copi.rd,
+ reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_xst_clk_export => OPEN,
reg_stat_hdr_dat_xst_reset_export => OPEN,
- reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_mosi.wr,
- reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_mosi.rd,
- reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_copi.wr,
+ reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_copi.rd,
+ reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_bst_clk_export => OPEN,
reg_stat_enable_bst_reset_export => OPEN,
- reg_stat_enable_bst_address_export => reg_stat_enable_bst_mosi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
- reg_stat_enable_bst_write_export => reg_stat_enable_bst_mosi.wr,
- reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_bst_read_export => reg_stat_enable_bst_mosi.rd,
- reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_address_export => reg_stat_enable_bst_copi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
+ reg_stat_enable_bst_write_export => reg_stat_enable_bst_copi.wr,
+ reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_read_export => reg_stat_enable_bst_copi.rd,
+ reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_bst_clk_export => OPEN,
reg_stat_hdr_dat_bst_reset_export => OPEN,
- reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_mosi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_mosi.wr,
- reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
- reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_copi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_copi.wr,
+ reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_copi.rd,
+ reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_crosslets_info_clk_export => OPEN,
reg_crosslets_info_reset_export => OPEN,
- reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
- reg_crosslets_info_write_export => reg_crosslets_info_mosi.wr,
- reg_crosslets_info_writedata_export => reg_crosslets_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
- reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_address_export => reg_crosslets_info_copi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
+ reg_crosslets_info_write_export => reg_crosslets_info_copi.wr,
+ reg_crosslets_info_writedata_export => reg_crosslets_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_read_export => reg_crosslets_info_copi.rd,
+ reg_crosslets_info_readdata_export => reg_crosslets_info_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nof_crosslets_clk_export => OPEN,
reg_nof_crosslets_reset_export => OPEN,
- reg_nof_crosslets_address_export => reg_nof_crosslets_mosi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
- reg_nof_crosslets_write_export => reg_nof_crosslets_mosi.wr,
- reg_nof_crosslets_writedata_export => reg_nof_crosslets_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nof_crosslets_read_export => reg_nof_crosslets_mosi.rd,
- reg_nof_crosslets_readdata_export => reg_nof_crosslets_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_address_export => reg_nof_crosslets_copi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
+ reg_nof_crosslets_write_export => reg_nof_crosslets_copi.wr,
+ reg_nof_crosslets_writedata_export => reg_nof_crosslets_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_read_export => reg_nof_crosslets_copi.rd,
+ reg_nof_crosslets_readdata_export => reg_nof_crosslets_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
- reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
- reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_mosi.wr,
- reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_mosi.rd,
- reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_copi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_copi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_copi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_xsq_clk_export => OPEN,
ram_st_xsq_reset_export => OPEN,
- ram_st_xsq_address_export => ram_st_xsq_mosi.address(c_sdp_ram_st_xsq_arr_addr_w-1 DOWNTO 0),
- ram_st_xsq_write_export => ram_st_xsq_mosi.wr,
- ram_st_xsq_writedata_export => ram_st_xsq_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_xsq_read_export => ram_st_xsq_mosi.rd,
- ram_st_xsq_readdata_export => ram_st_xsq_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_address_export => ram_st_xsq_copi.address(c_sdp_ram_st_xsq_arr_addr_w-1 DOWNTO 0),
+ ram_st_xsq_write_export => ram_st_xsq_copi.wr,
+ ram_st_xsq_writedata_export => ram_st_xsq_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_read_export => ram_st_xsq_copi.rd,
+ ram_st_xsq_readdata_export => ram_st_xsq_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_mac_clk_export => OPEN,
reg_nw_10GbE_mac_reset_export => OPEN,
- reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
- reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_mosi.wr,
- reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_mosi.rd,
- reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_copi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_copi.wr,
+ reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_copi.rd,
+ reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_eth10g_clk_export => OPEN,
reg_nw_10GbE_eth10g_reset_export => OPEN,
- reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_mosi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w-1 DOWNTO 0),
- reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_mosi.wr,
- reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_mosi.rd,
- reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_bsn_align_v2_clk_export => OPEN,
- reg_bsn_align_v2_reset_export => OPEN,
- reg_bsn_align_v2_address_export => reg_bsn_align_v2_copi.address(c_sdp_reg_bsn_align_v2_addr_w-1 DOWNTO 0),
- reg_bsn_align_v2_write_export => reg_bsn_align_v2_copi.wr,
- reg_bsn_align_v2_writedata_export => reg_bsn_align_v2_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_align_v2_read_export => reg_bsn_align_v2_copi.rd,
- reg_bsn_align_v2_readdata_export => reg_bsn_align_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_bsn_monitor_v2_bsn_align_v2_input_clk_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_input_reset_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_input_address_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_input_write_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wr,
- reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_input_read_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.rd,
- reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_input_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_bsn_monitor_v2_bsn_align_v2_output_clk_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_output_reset_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_output_address_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_output_write_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.wr,
- reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export=> reg_bsn_monitor_v2_bsn_align_v2_output_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_output_read_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.rd,
- reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_output_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_copi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_copi.wr,
+ reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
+ reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_align_v2_bf_clk_export => OPEN,
+ reg_bsn_align_v2_bf_reset_export => OPEN,
+ reg_bsn_align_v2_bf_address_export => reg_bsn_align_v2_bf_copi.address(c_sdp_reg_bsn_align_v2_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_align_v2_bf_write_export => reg_bsn_align_v2_bf_copi.wr,
+ reg_bsn_align_v2_bf_writedata_export => reg_bsn_align_v2_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_align_v2_bf_read_export => reg_bsn_align_v2_bf_copi.rd,
+ reg_bsn_align_v2_bf_readdata_export => reg_bsn_align_v2_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_align_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_address_export => reg_bsn_monitor_v2_rx_align_bf_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_bf_write_export => reg_bsn_monitor_v2_rx_align_bf_copi.wr,
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export => reg_bsn_monitor_v2_rx_align_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_bf_read_export => reg_bsn_monitor_v2_rx_align_bf_copi.rd,
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export => reg_bsn_monitor_v2_rx_align_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_aligned_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_address_export => reg_bsn_monitor_v2_aligned_bf_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_bf_write_export => reg_bsn_monitor_v2_aligned_bf_copi.wr,
+ reg_bsn_monitor_v2_aligned_bf_writedata_export => reg_bsn_monitor_v2_aligned_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_bf_read_export => reg_bsn_monitor_v2_aligned_bf_copi.rd,
+ reg_bsn_monitor_v2_aligned_bf_readdata_export => reg_bsn_monitor_v2_aligned_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_align_v2_xsub_clk_export => OPEN,
+ reg_bsn_align_v2_xsub_reset_export => OPEN,
+ reg_bsn_align_v2_xsub_address_export => reg_bsn_align_v2_xsub_copi.address(c_sdp_reg_bsn_align_v2_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_align_v2_xsub_write_export => reg_bsn_align_v2_xsub_copi.wr,
+ reg_bsn_align_v2_xsub_writedata_export => reg_bsn_align_v2_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_align_v2_xsub_read_export => reg_bsn_align_v2_xsub_copi.rd,
+ reg_bsn_align_v2_xsub_readdata_export => reg_bsn_align_v2_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_address_export => reg_bsn_monitor_v2_rx_align_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_xsub_write_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wr,
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_xsub_read_export => reg_bsn_monitor_v2_rx_align_xsub_copi.rd,
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export => reg_bsn_monitor_v2_rx_align_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_aligned_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_address_export => reg_bsn_monitor_v2_aligned_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_xsub_write_export => reg_bsn_monitor_v2_aligned_xsub_copi.wr,
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export => reg_bsn_monitor_v2_aligned_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_xsub_read_export => reg_bsn_monitor_v2_aligned_xsub_copi.rd,
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export => reg_bsn_monitor_v2_aligned_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_address_export => reg_bsn_monitor_v2_sst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_write_export => reg_bsn_monitor_v2_sst_offload_copi.wr,
+ reg_bsn_monitor_v2_sst_offload_writedata_export => reg_bsn_monitor_v2_sst_offload_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_read_export => reg_bsn_monitor_v2_sst_offload_copi.rd,
+ reg_bsn_monitor_v2_sst_offload_readdata_export => reg_bsn_monitor_v2_sst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_bst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_address_export => reg_bsn_monitor_v2_bst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_bst_offload_write_export => reg_bsn_monitor_v2_bst_offload_copi.wr,
+ reg_bsn_monitor_v2_bst_offload_writedata_export => reg_bsn_monitor_v2_bst_offload_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_bst_offload_read_export => reg_bsn_monitor_v2_bst_offload_copi.rd,
+ reg_bsn_monitor_v2_bst_offload_readdata_export => reg_bsn_monitor_v2_bst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_beamlet_output_clk_export => OPEN,
+ reg_bsn_monitor_v2_beamlet_output_reset_export => OPEN,
+ reg_bsn_monitor_v2_beamlet_output_address_export => reg_bsn_monitor_v2_beamlet_output_copi.address(c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_beamlet_output_write_export => reg_bsn_monitor_v2_beamlet_output_copi.wr,
+ reg_bsn_monitor_v2_beamlet_output_writedata_export => reg_bsn_monitor_v2_beamlet_output_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_beamlet_output_read_export => reg_bsn_monitor_v2_beamlet_output_copi.rd,
+ reg_bsn_monitor_v2_beamlet_output_readdata_export => reg_bsn_monitor_v2_beamlet_output_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_v2_xst_offload_clk_export => OPEN,
reg_bsn_monitor_v2_xst_offload_reset_export => OPEN,
@@ -959,6 +1082,46 @@ BEGIN
reg_bsn_monitor_v2_xst_offload_read_export => reg_bsn_monitor_v2_xst_offload_copi.rd,
reg_bsn_monitor_v2_xst_offload_readdata_export => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_clk_export => OPEN,
+ reg_ring_lane_info_bf_reset_export => OPEN,
+ reg_ring_lane_info_bf_address_export => reg_ring_lane_info_bf_copi.address(c_sdp_reg_ring_lane_info_bf_addr_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_write_export => reg_ring_lane_info_bf_copi.wr,
+ reg_ring_lane_info_bf_writedata_export => reg_ring_lane_info_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_read_export => reg_ring_lane_info_bf_copi.rd,
+ reg_ring_lane_info_bf_readdata_export => reg_ring_lane_info_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_address_export => reg_bsn_monitor_v2_ring_rx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_rx_bf_write_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_rx_bf_read_export => reg_bsn_monitor_v2_ring_rx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export => reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_address_export => reg_bsn_monitor_v2_ring_tx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_tx_bf_write_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_tx_bf_read_export => reg_bsn_monitor_v2_ring_tx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export => reg_bsn_monitor_v2_ring_tx_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_block_validate_err_bf_clk_export => OPEN,
+ reg_dp_block_validate_err_bf_reset_export => OPEN,
+ reg_dp_block_validate_err_bf_address_export => reg_dp_block_validate_err_bf_copi.address(c_sdp_reg_dp_block_validate_err_bf_addr_w-1 DOWNTO 0),
+ reg_dp_block_validate_err_bf_write_export => reg_dp_block_validate_err_bf_copi.wr,
+ reg_dp_block_validate_err_bf_writedata_export => reg_dp_block_validate_err_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_block_validate_err_bf_read_export => reg_dp_block_validate_err_bf_copi.rd,
+ reg_dp_block_validate_err_bf_readdata_export => reg_dp_block_validate_err_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_address_export => reg_dp_block_validate_bsn_at_sync_bf_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w-1 DOWNTO 0),
+ reg_dp_block_validate_bsn_at_sync_bf_write_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_block_validate_bsn_at_sync_bf_read_export => reg_dp_block_validate_bsn_at_sync_bf_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export => reg_dp_block_validate_bsn_at_sync_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
reg_ring_lane_info_xst_clk_export => OPEN,
reg_ring_lane_info_xst_reset_export => OPEN,
reg_ring_lane_info_xst_address_export => reg_ring_lane_info_xst_copi.address(c_sdp_reg_ring_lane_info_xst_addr_w-1 DOWNTO 0),
@@ -1017,11 +1180,11 @@ BEGIN
ram_scrap_clk_export => OPEN,
ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(9-1 DOWNTO 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0)
+ ram_scrap_address_export => ram_scrap_copi.address(9-1 DOWNTO 0),
+ ram_scrap_write_export => ram_scrap_copi.wr,
+ ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_scrap_read_export => ram_scrap_copi.rd,
+ ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 89913f213f46cecb8b15541a547132ebae436fdb..db07ef0b19d1226822182895094b7cb64e2b3dbf 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -28,469 +28,546 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
-----------------------------------------------------------------------------
component qsys_lofar2_unb2b_sdp_station is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_clk_export : out std_logic; -- export
- reg_bsn_align_v2_read_export : out std_logic; -- export
- reg_bsn_align_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_align_v2_reset_export : out std_logic; -- export
- reg_bsn_align_v2_write_export : out std_logic; -- export
- reg_bsn_align_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_pmbus_clk_export : out std_logic; -- export
- reg_unb_pmbus_read_export : out std_logic; -- export
- reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_pmbus_reset_export : out std_logic; -- export
- reg_unb_pmbus_write_export : out std_logic; -- export
- reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
- reg_unb_sens_clk_export : out std_logic; -- export
- reg_unb_sens_read_export : out std_logic; -- export
- reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_unb_sens_reset_export : out std_logic; -- export
- reg_unb_sens_write_export : out std_logic; -- export
- reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reset_reset_n : in std_logic := 'X'; -- reset_n
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_pmbus_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_pmbus_clk_export : out std_logic; -- export
+ reg_unb_pmbus_read_export : out std_logic; -- export
+ reg_unb_pmbus_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_pmbus_reset_export : out std_logic; -- export
+ reg_unb_pmbus_write_export : out std_logic; -- export
+ reg_unb_pmbus_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_unb_sens_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_unb_sens_clk_export : out std_logic; -- export
+ reg_unb_sens_read_export : out std_logic; -- export
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_unb_sens_reset_export : out std_logic; -- export
+ reg_unb_sens_write_export : out std_logic; -- export
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_sdp_station;
END qsys_lofar2_unb2b_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/hdllib.cfg
index 08c7824c437d1fcae6c1d3f7907c0545572638fe..1ff07321c77683d0f2e5841a8d19b577f0374f1a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/hdllib.cfg
@@ -8,9 +8,9 @@ hdl_lib_include_ip =
ip_arria10_e2sg_pll_xgmii_mac_clocks
ip_arria10_e2sg_transceiver_pll_10g
ip_arria10_e2sg_phy_10gbase_r
- ip_arria10_e2sg_phy_10gbase_r_3
+ ip_arria10_e2sg_phy_10gbase_r_12
ip_arria10_e2sg_transceiver_reset_controller_1
- ip_arria10_e2sg_transceiver_reset_controller_3
+ ip_arria10_e2sg_transceiver_reset_controller_12
synth_files =
src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
index f6a22135a9c37dd3b307b6d11191e56656552c8d..03e63ea22fe31b0eb7fc282bac32b9dcf305a75f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.fpga.yaml
@@ -234,7 +234,14 @@ peripherals:
peripheral_group: sst
mm_port_names:
- REG_STAT_HDR_DAT_SST
-
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: sst_udp
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_SST_OFFLOAD
+
#############################################################################
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
@@ -274,21 +281,21 @@ peripherals:
parameter_overrides:
- { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- - REG_BSN_ALIGN_V2
+ - REG_BSN_ALIGN_V2_XSUB
- peripheral_name: dp/dp_bsn_monitor_v2
- peripheral_group: bsn_align_input
+ peripheral_group: rx_align_xsub
parameter_overrides:
- { name: g_nof_streams, value: c_P_sq }
mm_port_names:
- - REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT
+ - REG_BSN_MONITOR_V2_RX_ALIGN_XSUB
- peripheral_name: dp/dp_bsn_monitor_v2
- peripheral_group: bsn_align_output
+ peripheral_group: aligned_xsub
parameter_overrides:
- { name: g_nof_streams, value: 1 }
mm_port_names:
- - REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT
+ - REG_BSN_MONITOR_V2_ALIGNED_XSUB
- peripheral_name: dp/dp_bsn_monitor_v2
peripheral_group: xst_udp
@@ -358,6 +365,66 @@ peripherals:
mm_port_names:
- RAM_BF_WEIGHTS
+ - peripheral_name: dp/dp_bsn_align_v2
+ peripheral_group: bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 2 }
+ mm_port_names:
+ - REG_BSN_ALIGN_V2_BF
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: rx_align_bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 2 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_RX_ALIGN_BF
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: aligned_bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_ALIGNED_BF
+
+ - peripheral_name: ring/ring_lane_info
+ peripheral_group: bf
+ number_of_peripherals: c_N_beamsets
+ mm_port_names:
+ - REG_RING_LANE_INFO_BF
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: ring_rx_bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_lane_nof_rx_monitors }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_RING_RX_BF
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: ring_tx_bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_lane_nof_tx_monitors }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_RING_TX_BF
+
+ - peripheral_name: dp/dp_block_validate_err
+ peripheral_group: bf
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_err_counts, value: c_lane_nof_err_counts }
+ mm_port_names:
+ - REG_DP_BLOCK_VALIDATE_ERR_BF
+
+ - peripheral_name: dp/dp_block_validate_bsn_at_sync
+ peripheral_group: bf
+ number_of_peripherals: c_N_beamsets
+ mm_port_names:
+ - REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF
+
- peripheral_name: sdp/sdp_bf_scale
number_of_peripherals: c_N_beamsets
peripheral_span: 2 * MM_BUS_SIZE # number_of_ports = 1, mm_port_span = 2 words
@@ -402,6 +469,22 @@ peripherals:
mm_port_names:
- REG_STAT_HDR_DAT_BST
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: bst_udp
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_BST_OFFLOAD
+
+ - peripheral_name: dp/dp_bsn_monitor_v2
+ peripheral_group: beamlet_output
+ number_of_peripherals: c_N_beamsets
+ parameter_overrides:
+ - { name: g_nof_streams, value: 1 }
+ mm_port_names:
+ - REG_BSN_MONITOR_V2_BEAMLET_OUTPUT
+
- peripheral_name: nw_10GbE/nw_10GbE_unb2legacy # For beamlet output
peripheral_group: beamlet_output
parameter_overrides:
@@ -415,6 +498,3 @@ peripherals:
- { name: g_nof_macs, value: 1 }
mm_port_names:
- REG_NW_10GBE_ETH10G
-
-
-
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
index 5667d08a041be549cadabfb3df52ffe4ba172af0..7f34570bd94e1593b53bcac4633a5ec2b45dfc78 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.gold
@@ -18,523 +18,843 @@ number_of_columns = 13
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
-# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
-# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
- ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
- PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
- - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
- - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
- - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
- - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
- - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
- - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
- - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
- - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
- - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
- - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
- REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
- RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
- AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
- AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
- - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
- - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
- - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
- - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
- - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
- - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
- - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x0001c000 1 RO uint32 b[15:0] - - -
- - - - - n_rn 0x0001c001 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x0001c002 1 RW uint32 b[7:0] - - -
- - - - - n_si 0x0001c003 1 RW uint32 b[7:0] - - -
- - - - - o_si 0x0001c004 1 RW uint32 b[7:0] - - -
- - - - - beam_repositioning_flag 0x0001c005 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x0001c006 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x0001c007 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x0001c008 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x0001c009 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x0001c00a 1 RO uint32 b[0:0] - - -
- - - - - station_id 0x0001c00b 1 RW uint32 b[15:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
- - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
- JESD204B 1 12 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - 256
- - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
- - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
- - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x00024004 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
- - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
- - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
- RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024
- RAM_ST_HISTOGRAM 1 12 RAM data 0x00030000 512 RW uint32 b[31:0] b[27:0] - 512
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x00032000 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x00032001 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x00032002 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x00032003 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00034000 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x00034001 1 RO uint32 b[31:0] - - -
- RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00038000 1024 RW uint32 b[31:0] b[15:0] - 1024
- REG_SI 1 1 REG enable 0x0003c000 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x00040000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x00044000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x00046000 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x00048000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - - 0x00048001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x0004c000 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004e000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004e001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x0004e002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_statistics_per_packet 0x0004e003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_bytes_per_statistic 0x0004e004 1 RW uint32 b[7:0] - - -
- - - - - sdp_nof_signal_inputs 0x0004e005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x0004e006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_sst_signal_input_index 0x0004e006 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_sst_reserved 0x0004e006 1 RW uint32 b[31:8] - - -
- - - - - sdp_integration_interval 0x0004e007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x0004e008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x0004e009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0004e00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0004e00b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0004e00c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0004e00d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0004e00e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0004e00f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0004e010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0004e011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0004e012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0004e013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0004e014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0004e015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0004e016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0004e017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0004e018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0004e019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0004e01a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0004e01b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0004e01c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0004e01d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0004e01e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0004e01f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0004e020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0004e021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0004e022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0004e023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0004e024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0004e025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0004e026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0004e027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004e028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0004e029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0004e02a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0004e02b 1 RW uint32 b[15:0] - - -
- REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00050000 1 RW uint32 b[0:0] - - -
- - - - - ctrl_interval_size 0x00050001 1 RW uint32 b[30:0] - - -
- - - - - ctrl_start_bsn 0x00050002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00050003 - - - b[31:0] b[63:32] - -
- - - - - mon_current_input_bsn 0x00050004 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00050005 - - - b[31:0] b[63:32] - -
- - - - - mon_input_bsn_at_sync 0x00050006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00050007 - - - b[31:0] b[63:32] - -
- - - - - mon_output_enable 0x00050008 1 RO uint32 b[0:0] - - -
- - - - - mon_output_sync_bsn 0x00050009 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0005000a - - - b[31:0] b[63:32] - -
- - - - - block_size 0x0005000b 1 RO uint32 b[31:0] - - -
- RAM_ST_XSQ 1 9 RAM data 0x00060000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - - 0x00060001 - - - b[31:0] b[63:32] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x00070000 15 RW uint32 b[31:0] - - -
- - - - - step 0x0007000f 1 RW uint32 b[31:0] - - -
- REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00072000 1 RW uint32 b[31:0] - - -
- - - - - unused 0x00072001 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x00074000 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00076000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00076001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00076002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00076003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00076004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00076005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00076006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_xst_signal_input_b_index 0x00076006 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_xst_signal_input_a_index 0x00076006 1 RW uint32 b[15:8] - - -
- - - - - sdp_data_id_xst_subband_index 0x00076006 1 RW uint32 b[24:16] - - -
- - - - - sdp_data_id_xst_reserved 0x00076006 1 RW uint32 b[31:25] - - -
- - - - - sdp_integration_interval 0x00076007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00076008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00076009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0007600a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0007600b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0007600c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0007600d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0007600e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0007600f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00076010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00076011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00076012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00076013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00076014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00076015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00076016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00076017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00076018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00076019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0007601a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0007601b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0007601c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0007601d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0007601e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0007601f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00076020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00076021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00076022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00076023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00076024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00076025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00076026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00076027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00076028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00076029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0007602a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0007602b 1 RW uint32 b[15:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x00078000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x0007c000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x00084000 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x00084001 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00086000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00086001 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00086002 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00086003 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00086004 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00086005 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00086006 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00086007 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00086008 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00086009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x0008600a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x0008600b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0008600c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0008600d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0008600e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0008600f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00086010 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00086011 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00086012 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00086013 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00086014 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00086015 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00086016 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00086017 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00086018 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00086019 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0008601a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0008601b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0008601c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0008601d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0008601e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0008601f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00086020 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00086021 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00086022 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00086023 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00086024 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00086025 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00086026 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00086027 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00086028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00086029 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x00088000 1 RW uint32 b[0:0] - 2 2
- RAM_ST_BST 2 1 RAM data 0x0008a000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - - 0x0008a001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x0008c000 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x0008e000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x0008e001 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x0008e002 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x0008e003 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x0008e004 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x0008e005 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x0008e006 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x0008e006 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x0008e006 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x0008e007 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x0008e008 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x0008e009 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0008e00a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0008e00b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0008e00c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0008e00d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0008e00e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0008e00f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x0008e010 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x0008e011 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x0008e012 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x0008e013 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x0008e014 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x0008e015 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x0008e016 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x0008e017 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x0008e018 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x0008e019 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0008e01a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0008e01b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0008e01c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0008e01d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0008e01e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0008e01f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x0008e020 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x0008e021 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x0008e022 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x0008e023 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x0008e024 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x0008e025 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x0008e026 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x0008e027 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x0008e028 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x0008e029 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0008e02a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0008e02b 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00090000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x00090001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x00090002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x00090040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x00090080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x000900c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000900c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x000900c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000900c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x00090100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x00090140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x00090800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x00090801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x00090802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x00090803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x00090804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x00090805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x00090806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x00090807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x00090808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x00090809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0009080a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0009080b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x00090818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x00090c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x00090c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x00090c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x00090c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x00090c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x00090c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x00090c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x00090c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x00090c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x00090c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x00090c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x00090c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x00090c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x00090c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x00090c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x00090c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x00090c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x00090c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x00090c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x00090c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x00090c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00090c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00090c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00090c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x00090c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x00090c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x00090c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x00090c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x00090c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x00090c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x00090c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00090c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x00091001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x00091040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x00091080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x000910c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000910c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x00091100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x00091140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x00091141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x00091142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x00091180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x00091181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x00091182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x00091183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x00091184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x00091185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x00091186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x00091187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x00091190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x00091191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x00091192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x00091193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x00091194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x00091195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x00091196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x00091197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x000911a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x00091200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x00091201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x00091202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x00091801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x00091c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x00091c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x00091c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x00091c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x00091c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x00091c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x00091c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x00091c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x00091c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x00091c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x00091c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x00091c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x00091c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x00091c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x00091c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x00091c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x00091c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x00091c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x00091c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x00091c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x00091c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00091c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00091c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00091c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x00091c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x00091c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x00091c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x00091c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x00091c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x00091c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x00091c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00091c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00092000 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x00092000 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00092000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ---------------------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x00010000 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00018000 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00018000 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x00020000 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00028000 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00028000 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00028400 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00030000 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00030000 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00030000 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00030001 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00030001 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x00030002 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00038000 1 WO uint32 b[31:0] - - -
+ - - - - rden 0x00038001 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00038002 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00038003 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00038004 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00038005 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00038006 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00040000 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00040400 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x00048000 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x00048001 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x00048400 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x00050000 1 WO uint32 b[31:0] - - -
+ - - - - param 0x00050001 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x00050002 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x00050003 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x00050004 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x00050005 1 WO uint32 b[31:0] - - -
+ - - - - busy 0x00050006 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x00058000 1 RO uint32 b[15:0] - - -
+ - - - - beam_repositioning_flag 0x00058001 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x00058002 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x00058003 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x00058004 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x00058005 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x00058006 1 RW uint32 b[0:0] - - -
+ - - - - station_id 0x00058007 1 RW uint32 b[15:0] - - -
+ REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x00060000 1 RW uint32 b[0:0] - - -
+ - - - - use_cable_to_next_rn 0x00060001 1 RW uint32 b[0:0] - - -
+ - - - - n_rn 0x00060002 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x00060003 1 RW uint32 b[7:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x00068000 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x00068000 1 RW uint32 b[31:31] - - -
+ JESD204B 1 12 REG rx_lane_ctrl_common 0x00070000 1 RW uint32 b[2:0] - - 256
+ - - - - rx_lane_ctrl_0 0x00070001 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_1 0x00070002 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_2 0x00070003 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_3 0x00070004 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_4 0x00070005 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_5 0x00070006 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_6 0x00070007 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_7 0x00070008 1 RW uint32 b[2:0] - - -
+ - - - - rx_dll_ctrl 0x00070014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x00070015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x00070015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x00070015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x00070015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x00070018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x00070019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x00070020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x00070020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x00070021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x00070022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x00070023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x00070025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x00070025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x00070025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x00070025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x00070026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x00070026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x00070026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x00070026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x00070026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x00070026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x00070026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x00070026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0007003c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0007003d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0007003e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0007003f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00078000 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00080000 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00080000 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00080001 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00080002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00080003 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00080004 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00088000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00088001 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00090000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00090000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00090000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00090001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00090002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00090003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00090004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00090005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00090006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00090007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00090008 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00098000 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x00098000 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00098001 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00098002 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00098003 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x0009c000 1024 RW uint32 b[17:0] - - 1024
+ RAM_ST_HISTOGRAM 1 12 RAM data 0x000a0000 512 RW uint32 b[31:0] b[27:0] - 512
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x000a8000 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x000a8001 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x000a8002 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x000a8003 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x000b0000 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x000b0001 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x000b4000 1024 RW uint32 b[31:0] b[15:0] - 1024
+ REG_SI 1 1 REG enable 0x000b8000 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x000c0000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x000c8000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x000d0000 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x000d8000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x000d8001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x000e0000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x000e8000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000e8001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x000e8002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x000e8003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x000e8004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x000e8005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x000e8006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x000e8006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x000e8006 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x000e8007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x000e8008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x000e8009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x000e800a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x000e800b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x000e800c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x000e800d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x000e800e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x000e800f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x000e8010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x000e8011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x000e8012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x000e8013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x000e8014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x000e8015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x000e8016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x000e8017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x000e8018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x000e8019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x000e801a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x000e801b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x000e801c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x000e801d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x000e801e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x000e801f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x000e8020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x000e8021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x000e8022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x000e8023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x000e8024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x000e8025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x000e8026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x000e8027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000e8028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x000e8029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000e802a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x000e802b 1 RW uint32 b[15:0] - - -
+ REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x000f0000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x000f0000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000f0000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000f0001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f0002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000f0003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000f0004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000f0005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000f0008 1 RO uint32 b[31:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000f8000 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x000f8001 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x000f8002 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f8003 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x000f8004 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f8005 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x000f8006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f8007 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x000f8008 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x000f8009 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000f800a - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x000f800b 1 RO uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 9 RAM data 0x00100000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
+ - - - - - 0x00100001 - - - b[31:0] b[63:32] - -
+ - - - - - 0x00100002 - - - b[31:0] b[95:64] - -
+ - - - - - 0x00100003 - - - b[31:0] b[127:96] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x00110000 15 RW uint32 b[31:0] - - -
+ - - - - step 0x0011000f 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00118000 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x00118001 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x00120000 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00128000 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00128001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00128002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00128003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00128004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00128005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00128006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_xst_signal_input_b_index 0x00128006 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_xst_signal_input_a_index 0x00128006 1 RW uint32 b[15:8] - - -
+ - - - - sdp_data_id_xst_subband_index 0x00128006 1 RW uint32 b[24:16] - - -
+ - - - - sdp_data_id_xst_reserved 0x00128006 1 RW uint32 b[31:25] - - -
+ - - - - sdp_integration_interval 0x00128007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00128008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00128009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0012800a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0012800b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0012800c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0012800d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0012800e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0012800f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00128010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00128011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00128012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00128013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00128014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00128015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00128016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00128017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00128018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00128019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0012801a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0012801b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0012801c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0012801d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0012801e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0012801f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00128020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00128021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00128022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00128023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00128024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00128025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00128026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00128027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00128028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00128029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0012802a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0012802b 1 RW uint32 b[15:0] - - -
+ REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00130000 1 RW uint32 b[0:0] - - 2
+ - - - - replaced_pkt_cnt 0x00130001 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00138000 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00138000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00138000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00138001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00138002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00138003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00138004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00138005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00138008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00140000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00140000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00140000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00140001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00140002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00140003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00140004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00140005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00140008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00148000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00148000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00148000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00148001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00148002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00148003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00148004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00148005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00148008 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00150000 1 RO uint32 b[0:0] - - -
+ - - - - transport_nof_hops 0x00150001 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00158000 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00158000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00158000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00158001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00158002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00158003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00158004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00158005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00158008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_XST 1 16 REG xon_stable 0x00160000 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00160000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00160000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00160001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00160002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00160003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00160004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00160005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00160008 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00168000 8 RO uint32 b[31:0] - - -
+ - - - - total_discarded_blocks 0x00168008 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x00168009 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0016800a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x00170000 1 RO uint32 b[31:0] - - -
+ - - - - nof_sync 0x00170001 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x00170002 1 RW uint32 b[31:0] - - -
+ REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00178000 1 RW uint32 b[0:0] - - 1
+ - - - - rx_transfer_status 0x00178001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00178002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00178040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00178080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x001780c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001780c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x001780c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001780c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00178100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00178140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00178800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00178801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00178802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00178803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00178804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00178805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00178806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00178807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00178808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00178809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0017880a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0017880b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00178818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00178c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00178c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00178c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00178c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00178c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00178c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00178c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00178c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00178c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00178c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00178c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00178c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00178c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00178c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00178c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00178c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00178c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00178c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00178c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00178c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00178c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00178c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00178c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00178c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00178c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00178c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00178c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00178c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00178c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00178c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00178c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00178c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00179001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00179040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00179080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x001790c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x001790c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00179100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00179140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00179141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00179142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00179180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00179181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00179182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00179183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00179184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00179185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00179186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00179187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00179190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00179191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00179192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00179193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00179194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00179195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00179196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00179197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x001791a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00179200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00179201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00179202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00179801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00179c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00179c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00179c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00179c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00179c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00179c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00179c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00179c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00179c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00179c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00179c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00179c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00179c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00179c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00179c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00179c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00179c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00179c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00179c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00179c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00179c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00179c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00179c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00179c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00179c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00179c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00179c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00179c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00179c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00179c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00179c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00179c3d - - - b[31:0] b[31:0] - -
+ REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x00180000 1 RO uint32 b[0:0] - - 1
+ - - - - xgmii_tx_ready 0x00180000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00180000 1 RO uint32 b[3:2] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00188000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00190000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x00198000 1 RW uint32 b[0:0] - 1 2
+ - - - - replaced_pkt_cnt 0x00198001 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x001a0000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x001a0000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x001a0000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x001a0001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001a0002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x001a0003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x001a0004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x001a0005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x001a0008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x001a8000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x001a8000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x001a8000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x001a8001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001a8002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x001a8003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x001a8004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x001a8005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x001a8008 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x001b0000 1 RO uint32 b[0:0] - 1 2
+ - - - - transport_nof_hops 0x001b0001 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x001b8000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x001b8000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x001b8000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x001b8001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001b8002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x001b8003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x001b8004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x001b8005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x001b8008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x001c0000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x001c0000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x001c0000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x001c0001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001c0002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x001c0003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x001c0004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x001c0005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x001c0008 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x001c8000 8 RO uint32 b[31:0] - 1 16
+ - - - - total_discarded_blocks 0x001c8008 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x001c8009 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x001c800a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x001d0000 1 RO uint32 b[31:0] - 1 4
+ - - - - nof_sync 0x001d0001 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x001d0002 1 RW uint32 b[31:0] - - -
+ REG_BF_SCALE 2 1 REG scale 0x001d8000 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x001d8001 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x001e0000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x001e0001 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x001e0002 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x001e0003 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x001e0004 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x001e0005 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x001e0006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x001e0007 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001e0008 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x001e0009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x001e000a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x001e000b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x001e000c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x001e000d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x001e000e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x001e000f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x001e0010 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x001e0011 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x001e0012 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x001e0013 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x001e0014 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x001e0015 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x001e0016 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x001e0017 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x001e0018 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x001e0019 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x001e001a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x001e001b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x001e001c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x001e001d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x001e001e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x001e001f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x001e0020 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x001e0021 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x001e0022 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x001e0023 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x001e0024 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x001e0025 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x001e0026 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001e0027 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x001e0028 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x001e0029 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x001e8000 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x001f0000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x001f0001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x001f8000 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00200000 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00200001 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00200002 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00200003 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00200004 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00200005 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00200006 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00200006 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00200006 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00200007 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00200008 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00200009 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0020000a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0020000b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0020000c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0020000d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0020000e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0020000f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00200010 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00200011 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00200012 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00200013 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00200014 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00200015 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00200016 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00200017 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00200018 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00200019 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0020001a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0020001b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0020001c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0020001d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0020001e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0020001f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00200020 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00200021 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00200022 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00200023 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00200024 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00200025 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00200026 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00200027 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00200028 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00200029 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0020002a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0020002b 1 RW uint32 b[15:0] - - -
+ REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00208000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00208000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00208000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00208001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00208002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00208003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00208004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00208005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00208008 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00210000 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00210000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00210000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00210001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00210002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00210003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00210004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00210005 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00210008 1 RO uint32 b[31:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00218000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00218001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00218002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00218040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00218080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x002180c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x002180c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x002180c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x002180c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00218100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00218140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00218800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00218801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00218802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00218803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00218804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00218805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00218806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00218807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00218808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00218809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0021880a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0021880b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00218818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00218c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00218c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00218c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00218c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00218c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00218c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00218c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00218c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00218c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00218c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00218c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00218c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00218c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00218c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00218c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00218c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00218c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00218c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00218c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00218c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00218c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00218c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00218c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00218c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00218c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00218c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00218c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00218c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00218c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00218c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00218c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00218c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00219001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00219040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00219080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x002190c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x002190c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00219100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00219140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00219141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00219142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00219180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00219181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00219182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00219183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00219184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00219185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00219186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00219187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00219190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00219191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00219192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00219193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00219194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00219195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00219196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00219197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x002191a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00219200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00219201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00219202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00219801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00219c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00219c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00219c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00219c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00219c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00219c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00219c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00219c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00219c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00219c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00219c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00219c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00219c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00219c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00219c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00219c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00219c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00219c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00219c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00219c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00219c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00219c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00219c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00219c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00219c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00219c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00219c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00219c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00219c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00219c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00219c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00219c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00220000 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00220000 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00220000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
index be85a718fb41f93ded98fc9b737766839cca602d..b15cb41cfd1fe6f9e60fc8f13b65837b1335251b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/lofar2_unb2c_sdp_station.mmap.qsys.gold
@@ -18,523 +18,843 @@ number_of_columns = 13
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
#
-# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
-# ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
- ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
- PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
- - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
- - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
- - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
- - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
- - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
- - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
- - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
- - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
- - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
- - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
- - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
- - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
- - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
- REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
- REG_FPGA_TEMP_SENS 1 1 REG temp 0x00000dc8 1 RO uint32 b[31:0] - - -
- REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x00000db0 6 RO uint32 b[31:0] - - -
- RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
- AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
- AVS_ETH_0_REG 1 1 REG status 0x00000d80 12 RO uint32 b[31:0] - - -
- AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
- PIO_PPS 1 1 REG capture_cnt 0x00000dec 1 RO uint32 b[29:0] - - -
- - - - - stable 0x00000dec 1 RO uint32 b[30:30] - - -
- - - - - toggle 0x00000dec 1 RO uint32 b[31:31] - - -
- - - - - expected_cnt 0x00000ded 1 RW uint32 b[27:0] - - -
- - - - - edge 0x00000ded 1 RW uint32 b[31:31] - - -
- - - - - offset_cnt 0x00000dee 1 RO uint32 b[27:0] - - -
- REG_EPCS 1 1 REG addr 0x00000dd0 1 WO uint32 b[23:0] - - -
- - - - - rden 0x00000dd1 1 WO uint32 b[0:0] - - -
- - - - - read_bit 0x00000dd2 1 WO uint32 b[0:0] - - -
- - - - - write_bit 0x00000dd3 1 WO uint32 b[0:0] - - -
- - - - - sector_erase 0x00000dd4 1 WO uint32 b[0:0] - - -
- - - - - busy 0x00000dd5 1 RO uint32 b[0:0] - - -
- - - - - unprotect 0x00000dd6 1 WO uint32 b[31:0] - - -
- REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002f004 1 RO uint32 b[31:0] - - -
- REG_DPMM_DATA 1 1 FIFO data 0x0002f002 1 RO uint32 b[31:0] - - -
- REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002f000 1 RO uint32 b[31:0] - - -
- - - - - wr_availw 0x0002f001 1 RO uint32 b[31:0] - - -
- REG_MMDP_DATA 1 1 FIFO data 0x00000dfe 1 WO uint32 b[31:0] - - -
- REG_REMU 1 1 REG reconfigure 0x00000dd8 1 WO uint32 b[31:0] - - -
- - - - - param 0x00000dd9 1 WO uint32 b[2:0] - - -
- - - - - read_param 0x00000dda 1 WO uint32 b[0:0] - - -
- - - - - write_param 0x00000ddb 1 WO uint32 b[0:0] - - -
- - - - - data_out 0x00000ddc 1 RO uint32 b[23:0] - - -
- - - - - data_in 0x00000ddd 1 WO uint32 b[23:0] - - -
- - - - - busy 0x00000dde 1 RO uint32 b[0:0] - - -
- REG_SDP_INFO 1 1 REG block_period 0x00000da0 1 RO uint32 b[15:0] - - -
- - - - - n_rn 0x00000da1 1 RW uint32 b[7:0] - - -
- - - - - o_rn 0x00000da2 1 RW uint32 b[7:0] - - -
- - - - - n_si 0x00000da3 1 RW uint32 b[7:0] - - -
- - - - - o_si 0x00000da4 1 RW uint32 b[7:0] - - -
- - - - - beam_repositioning_flag 0x00000da5 1 RW uint32 b[0:0] - - -
- - - - - fsub_type 0x00000da6 1 RO uint32 b[0:0] - - -
- - - - - f_adc 0x00000da7 1 RO uint32 b[0:0] - - -
- - - - - nyquist_zone_index 0x00000da8 1 RW uint32 b[1:0] - - -
- - - - - observation_id 0x00000da9 1 RW uint32 b[31:0] - - -
- - - - - antenna_band_index 0x00000daa 1 RO uint32 b[0:0] - - -
- - - - - station_id 0x00000dab 1 RW uint32 b[15:0] - - -
- PIO_JESD_CTRL 1 1 REG enable 0x00000df4 1 RW uint32 b[30:0] - - -
- - - - - reset 0x00000df4 1 RW uint32 b[31:31] - - -
- JESD204B 1 12 REG rx_dll_ctrl 0x0002e014 1 RW uint32 b[16:0] - - 256
- - - - - rx_syncn_sysref_ctrl 0x0002e015 1 RW uint32 b[24:0] - - -
- - - - - rx_csr_sysref_always_on 0x0002e015 1 RW uint32 b[1:1] - - -
- - - - - rx_csr_rbd_offset 0x0002e015 1 RW uint32 b[10:3] - - -
- - - - - rx_csr_lmfc_offset 0x0002e015 1 RW uint32 b[19:12] - - -
- - - - - rx_err0 0x0002e018 1 RW uint32 b[8:0] - - -
- - - - - rx_err1 0x0002e019 1 RW uint32 b[9:0] - - -
- - - - - csr_dev_syncn 0x0002e020 1 RO uint32 b[0:0] - - -
- - - - - csr_rbd_count 0x0002e020 1 RO uint32 b[10:3] - - -
- - - - - rx_status1 0x0002e021 1 RW uint32 b[23:0] - - -
- - - - - rx_status2 0x0002e022 1 RW uint32 b[23:0] - - -
- - - - - rx_status3 0x0002e023 1 RW uint32 b[7:0] - - -
- - - - - rx_ilas_csr_l 0x0002e025 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_f 0x0002e025 1 RW uint32 b[15:8] - - -
- - - - - rx_ilas_csr_k 0x0002e025 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_m 0x0002e025 1 RW uint32 b[31:24] - - -
- - - - - rx_ilas_csr_n 0x0002e026 1 RW uint32 b[4:0] - - -
- - - - - rx_ilas_csr_cs 0x0002e026 1 RW uint32 b[7:6] - - -
- - - - - rx_ilas_csr_np 0x0002e026 1 RW uint32 b[12:8] - - -
- - - - - rx_ilas_csr_subclassv 0x0002e026 1 RW uint32 b[15:13] - - -
- - - - - rx_ilas_csr_s 0x0002e026 1 RW uint32 b[20:16] - - -
- - - - - rx_ilas_csr_jesdv 0x0002e026 1 RW uint32 b[23:21] - - -
- - - - - rx_ilas_csr_cf 0x0002e026 1 RW uint32 b[28:24] - - -
- - - - - rx_ilas_csr_hd 0x0002e026 1 RW uint32 b[31:31] - - -
- - - - - rx_status4 0x0002e03c 1 RW uint32 b[15:0] - - -
- - - - - rx_status5 0x0002e03d 1 RW uint32 b[15:0] - - -
- - - - - rx_status6 0x0002e03e 1 RW uint32 b[23:0] - - -
- - - - - rx_status7 0x0002e03f 1 RO uint32 b[31:0] - - -
- REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2
- REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00000dc0 1 RW uint32 b[0:0] - - -
- - - - - dp_on_pps 0x00000dc0 1 RW uint32 b[1:1] - - -
- - - - - nof_clk_per_sync 0x00000dc1 1 RW uint32 b[31:0] - - -
- - - - - bsn_init 0x00000dc2 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000dc3 - - - b[31:0] b[63:32] - -
- - - - - bsn_time_offset 0x00000dc4 1 RW uint32 b[9:0] - - -
- REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00000dfa 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000dfb - - - b[31:0] b[63:32] - -
- REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - -
- - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
- - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
- - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
- - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
- - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
- - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
- - - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000107 - - - b[31:0] b[63:32] - -
- - - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - -
- REG_WG 1 12 REG mode 0x00000d00 1 RW uint32 b[7:0] - - 4
- - - - - nof_samples 0x00000d00 1 RW uint32 b[31:16] - - -
- - - - - phase 0x00000d01 1 RW uint32 b[15:0] - - -
- - - - - freq 0x00000d02 1 RW uint32 b[30:0] - - -
- - - - - ampl 0x00000d03 1 RW uint32 b[16:0] - - -
- RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024
- RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
- REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d40 1 RO int64 b[31:0] b[31:0] - 4
- - - - - - 0x00000d41 - - - b[31:0] b[63:32] - -
- - - - - power_sum 0x00000d42 1 RO int64 b[31:0] b[31:0] - -
- - - - - - 0x00000d43 - - - b[31:0] b[63:32] - -
- REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2
- - - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - -
- RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
- REG_SI 1 1 REG enable 0x00000dfc 1 RW uint32 b[0:0] - - -
- RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024
- RAM_EQUALIZER_GAINS 1 6 RAM data 0x0002c000 1024 RW cint16_ir b[31:0] - - 1024
- REG_DP_SELECTOR 1 1 REG input_select 0x00000df8 1 RW uint32 b[0:0] - - -
- RAM_ST_SST 1 6 RAM data 0x00028000 1024 RW uint64 b[31:0] b[31:0] - 2048
- - - - - - 0x00028001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_SST 1 1 REG enable 0x00000df2 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_statistics_per_packet 0x00000c43 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_bytes_per_statistic 0x00000c44 1 RW uint32 b[7:0] - - -
- - - - - sdp_nof_signal_inputs 0x00000c45 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000c46 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_sst_signal_input_index 0x00000c46 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_sst_reserved 0x00000c46 1 RW uint32 b[31:8] - - -
- - - - - sdp_integration_interval 0x00000c47 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x00000c4f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000c50 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000c51 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000c52 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000c53 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000c54 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000c55 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000c56 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000c57 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000c58 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000c59 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00000c5a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x00000c5b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x00000c5c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x00000c5d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x00000c5e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x00000c5f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000c60 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000c61 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000c62 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000c63 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000c64 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000c65 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000c66 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000c67 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c68 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
- REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00000c10 1 RW uint32 b[0:0] - - -
- - - - - ctrl_interval_size 0x00000c11 1 RW uint32 b[30:0] - - -
- - - - - ctrl_start_bsn 0x00000c12 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c13 - - - b[31:0] b[63:32] - -
- - - - - mon_current_input_bsn 0x00000c14 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c15 - - - b[31:0] b[63:32] - -
- - - - - mon_input_bsn_at_sync 0x00000c16 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c17 - - - b[31:0] b[63:32] - -
- - - - - mon_output_enable 0x00000c18 1 RO uint32 b[0:0] - - -
- - - - - mon_output_sync_bsn 0x00000c19 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c1a - - - b[31:0] b[63:32] - -
- - - - - block_size 0x00000c1b 1 RO uint32 b[31:0] - - -
- RAM_ST_XSQ 1 9 RAM data 0x00018000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
- - - - - - 0x00018001 - - - b[31:0] b[63:32] - -
- REG_CROSSLETS_INFO 1 1 REG offset 0x00000d90 15 RW uint32 b[31:0] - - -
- - - - - step 0x00000d9f 1 RW uint32 b[31:0] - - -
- REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x00000c02 1 RW uint32 b[31:0] - - -
- - - - - unused 0x00000c03 1 RW uint32 b[31:0] - - -
- REG_STAT_ENABLE_XST 1 1 REG enable 0x00000df0 1 RW uint32 b[0:0] - - -
- REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000041 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00000043 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00000044 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00000045 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000046 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_xst_signal_input_b_index 0x00000046 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id_xst_signal_input_a_index 0x00000046 1 RW uint32 b[15:8] - - -
- - - - - sdp_data_id_xst_subband_index 0x00000046 1 RW uint32 b[24:16] - - -
- - - - - sdp_data_id_xst_reserved 0x00000046 1 RW uint32 b[31:25] - - -
- - - - - sdp_integration_interval 0x00000047 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0000004f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000050 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000051 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000052 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000053 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000054 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000055 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000056 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000057 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000058 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000059 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0000005a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0000005b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0000005c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0000005d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0000005e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0000005f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000060 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000061 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000062 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000063 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000064 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000065 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000066 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000067 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000068 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x0000006a - - - b[15:0] b[47:32] - -
- - - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
- RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024
- RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024
- REG_BF_SCALE 2 1 REG scale 0x00000de8 1 RW uint32 b[15:0] - 2 2
- - - - - unused 0x00000de9 1 RW uint32 b[31:0] - - -
- REG_HDR_DAT 2 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00000c81 - - - b[31:0] b[63:32] - -
- - - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_beamlets_per_block 0x00000c83 1 RW uint32 b[15:0] - - -
- - - - - sdp_nof_blocks_per_packet 0x00000c84 1 RW uint32 b[7:0] - - -
- - - - - sdp_beamlet_index 0x00000c85 1 RW uint32 b[15:0] - - -
- - - - - sdp_beamlet_scale 0x00000c86 1 RW uint32 b[15:0] - - -
- - - - - sdp_reserved 0x00000c87 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000c88 - - - b[7:0] b[39:32] - -
- - - - - sdp_source_info_gn_index 0x00000c89 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_beamlet_width 0x00000c8a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_repositioning_flag 0x00000c8b 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x00000c8c 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x00000c8d 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x00000c8e 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000c8f 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000c90 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000c91 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000c92 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000c93 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000c94 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000c95 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000c96 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000c97 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000c98 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x00000c99 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x00000c9a 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x00000c9b 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x00000c9c 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x00000c9d 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x00000c9e 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x00000c9f 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x00000ca0 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x00000ca1 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x00000ca2 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x00000ca3 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x00000ca4 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x00000ca5 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x00000ca6 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000ca7 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x00000ca8 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x00000ca9 - - - b[15:0] b[47:32] - -
- REG_DP_XONOFF 2 1 REG enable_stream 0x00000de4 1 RW uint32 b[0:0] - 2 2
- RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
- REG_STAT_ENABLE_BST 2 1 REG enable 0x00000de0 1 RW uint32 b[0:0] - 2 2
- REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - - - 0x00000081 - - - b[31:0] b[63:32] - -
- - - - - block_period 0x00000082 1 RW uint32 b[15:0] - - -
- - - - - nof_statistics_per_packet 0x00000083 1 RW uint32 b[15:0] - - -
- - - - - nof_bytes_per_statistic 0x00000084 1 RW uint32 b[7:0] - - -
- - - - - nof_signal_inputs 0x00000085 1 RW uint32 b[7:0] - - -
- - - - - sdp_data_id 0x00000086 1 RW uint32 b[31:0] - - -
- - - - - sdp_data_id_bst_beamlet_index 0x00000086 1 RW uint32 b[15:0] - - -
- - - - - sdp_data_id_bst_reserved 0x00000086 1 RW uint32 b[31:16] - - -
- - - - - sdp_integration_interval 0x00000087 1 RW uint32 b[23:0] - - -
- - - - - sdp_reserved 0x00000088 1 RW uint32 b[7:0] - - -
- - - - - sdp_source_info_gn_index 0x00000089 1 RW uint32 b[4:0] - - -
- - - - - sdp_source_info_reserved 0x0000008a 1 RW uint32 b[7:5] - - -
- - - - - sdp_source_info_subband_calibrated_flag 0x0000008b 1 RW uint32 b[8:8] - - -
- - - - - sdp_source_info_beam_repositioning_flag 0x0000008c 1 RW uint32 b[9:9] - - -
- - - - - sdp_source_info_payload_error 0x0000008d 1 RW uint32 b[10:10] - - -
- - - - - sdp_source_info_fsub_type 0x0000008e 1 RW uint32 b[11:11] - - -
- - - - - sdp_source_info_f_adc 0x0000008f 1 RW uint32 b[12:12] - - -
- - - - - sdp_source_info_nyquist_zone_index 0x00000090 1 RW uint32 b[14:13] - - -
- - - - - sdp_source_info_antenna_band_index 0x00000091 1 RW uint32 b[15:15] - - -
- - - - - sdp_station_id 0x00000092 1 RW uint32 b[15:0] - - -
- - - - - sdp_observation_id 0x00000093 1 RW uint32 b[31:0] - - -
- - - - - sdp_version_id 0x00000094 1 RO uint32 b[7:0] - - -
- - - - - sdp_marker 0x00000095 1 RO uint32 b[7:0] - - -
- - - - - udp_checksum 0x00000096 1 RW uint32 b[15:0] - - -
- - - - - udp_length 0x00000097 1 RW uint32 b[15:0] - - -
- - - - - udp_destination_port 0x00000098 1 RW uint32 b[15:0] - - -
- - - - - udp_source_port 0x00000099 1 RW uint32 b[15:0] - - -
- - - - - ip_destination_address 0x0000009a 1 RW uint32 b[31:0] - - -
- - - - - ip_source_address 0x0000009b 1 RW uint32 b[31:0] - - -
- - - - - ip_header_checksum 0x0000009c 1 RW uint32 b[15:0] - - -
- - - - - ip_protocol 0x0000009d 1 RW uint32 b[7:0] - - -
- - - - - ip_time_to_live 0x0000009e 1 RW uint32 b[7:0] - - -
- - - - - ip_fragment_offset 0x0000009f 1 RW uint32 b[12:0] - - -
- - - - - ip_flags 0x000000a0 1 RW uint32 b[2:0] - - -
- - - - - ip_identification 0x000000a1 1 RW uint32 b[15:0] - - -
- - - - - ip_total_length 0x000000a2 1 RW uint32 b[15:0] - - -
- - - - - ip_services 0x000000a3 1 RW uint32 b[7:0] - - -
- - - - - ip_header_length 0x000000a4 1 RW uint32 b[3:0] - - -
- - - - - ip_version 0x000000a5 1 RW uint32 b[3:0] - - -
- - - - - eth_type 0x000000a6 1 RO uint32 b[15:0] - - -
- - - - - eth_source_mac 0x000000a7 1 RO uint64 b[31:0] b[31:0] - -
- - - - - - 0x000000a8 - - - b[15:0] b[47:32] - -
- - - - - eth_destination_mac 0x000000a9 1 RW uint64 b[31:0] b[31:0] - -
- - - - - - 0x000000aa - - - b[15:0] b[47:32] - -
- - - - - word_align 0x000000ab 1 RW uint32 b[15:0] - - -
- REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
- - - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
- - - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
- - - - - rx_padcrc_control 0x00006040 1 RW uint32 b[1:0] - - -
- - - - - rx_crccheck_control 0x00006080 1 RW uint32 b[1:0] - - -
- - - - - rx_pktovrflow_error 0x000060c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000060c1 - - - b[31:0] b[31:0] - -
- - - - - rx_pktovrflow_etherstatsdropevents 0x000060c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000060c3 - - - b[31:0] b[31:0] - -
- - - - - rx_lane_decoder_preamble_control 0x00006100 1 RW uint32 b[0:0] - - -
- - - - - rx_preamble_inserter_control 0x00006140 1 RW uint32 b[0:0] - - -
- - - - - rx_frame_control 0x00006800 1 RW uint32 b[19:0] - - -
- - - - - rx_frame_maxlength 0x00006801 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr0 0x00006802 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_addr1 0x00006803 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_0 0x00006804 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr0_1 0x00006805 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_0 0x00006806 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr1_1 0x00006807 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_0 0x00006808 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr2_1 0x00006809 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_0 0x0000680a 1 RW uint32 b[15:0] - - -
- - - - - rx_frame_spaddr3_1 0x0000680b 1 RW uint32 b[15:0] - - -
- - - - - rx_pfc_control 0x00006818 1 RW uint32 b[16:0] - - -
- - - - - rx_stats_clr 0x00006c00 1 RW uint32 b[0:0] - - -
- - - - - rx_stats_framesok 0x00006c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c03 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_frameserr 0x00006c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c05 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_framescrcerr 0x00006c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c07 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_octetsok 0x00006c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c09 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pausemacctrl_frames 0x00006c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c0b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_iferrors 0x00006c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c0d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_framesok 0x00006c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c0f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicast_frameserr 0x00006c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c11 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastframesok 0x00006c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c13 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicast_frameserr 0x00006c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c15 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastframesok 0x00006c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c17 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcast_frameserr 0x00006c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c19 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatsoctets 0x00006c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c1b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatspkts 0x00006c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c1d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_undersizepkts 0x00006c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c1f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_oversizepkts 0x00006c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c21 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts64octets 0x00006c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c23 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts65to127octets 0x00006c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c25 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts128to255octets 0x00006c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c27 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts256to511octets 0x00006c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c29 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts512to1023octets 0x00006c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c2b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstat_pkts1024to1518octets 0x00006c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c2d - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_pkts1519toxoctets 0x00006c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c2f - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_fragments 0x00006c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c31 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstats_jabbers 0x00006c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c33 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_etherstatscrcerr 0x00006c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c35 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_unicastmacctrlframes 0x00006c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c37 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_multicastmac_ctrlframes 0x00006c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c39 - - - b[31:0] b[31:0] - -
- - - - - rx_stats_broadcastmac_ctrlframes 0x00006c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c3b - - - b[31:0] b[31:0] - -
- - - - - rx_stats_pfcmacctrlframes 0x00006c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00006c3d - - - b[31:0] b[31:0] - -
- - - - - tx_transfer_status 0x00007001 1 RO uint32 b[0:0] - - -
- - - - - tx_padins_control 0x00007040 1 RW uint32 b[0:0] - - -
- - - - - tx_crcins_control 0x00007080 1 RW uint32 b[1:0] - - -
- - - - - tx_pktunderflow_error 0x000070c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x000070c1 - - - b[31:0] b[31:0] - -
- - - - - tx_preamble_control 0x00007100 1 RW uint32 b[0:0] - - -
- - - - - tx_pauseframe_control 0x00007140 1 RW uint32 b[1:0] - - -
- - - - - tx_pauseframe_quanta 0x00007141 1 RW uint32 b[15:0] - - -
- - - - - tx_pauseframe_enable 0x00007142 1 RW uint32 b[0:0] - - -
- - - - - pfc_pause_quanta_0 0x00007180 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_1 0x00007181 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_2 0x00007182 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_3 0x00007183 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_4 0x00007184 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_5 0x00007185 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_6 0x00007186 1 RW uint32 b[31:0] - - -
- - - - - pfc_pause_quanta_7 0x00007187 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_0 0x00007190 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_1 0x00007191 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_2 0x00007192 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_3 0x00007193 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_4 0x00007194 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_5 0x00007195 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_6 0x00007196 1 RW uint32 b[31:0] - - -
- - - - - pfc_holdoff_quanta_7 0x00007197 1 RW uint32 b[31:0] - - -
- - - - - tx_pfc_priority_enable 0x000071a0 1 RW uint32 b[7:0] - - -
- - - - - tx_addrins_control 0x00007200 1 RW uint32 b[0:0] - - -
- - - - - tx_addrins_macaddr0 0x00007201 1 RW uint32 b[31:0] - - -
- - - - - tx_addrins_macaddr1 0x00007202 1 RW uint32 b[15:0] - - -
- - - - - tx_frame_maxlength 0x00007801 1 RW uint32 b[15:0] - - -
- - - - - tx_stats_clr 0x00007c00 1 RW uint32 b[0:0] - - -
- - - - - tx_stats_framesok 0x00007c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c03 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_frameserr 0x00007c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c05 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_framescrcerr 0x00007c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c07 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_octetsok 0x00007c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c09 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pausemacctrl_frames 0x00007c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c0b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_iferrors 0x00007c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c0d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_framesok 0x00007c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c0f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicast_frameserr 0x00007c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c11 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastframesok 0x00007c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c13 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicast_frameserr 0x00007c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c15 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastframesok 0x00007c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c17 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcast_frameserr 0x00007c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c19 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatsoctets 0x00007c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c1b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatspkts 0x00007c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c1d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_undersizepkts 0x00007c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c1f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_oversizepkts 0x00007c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c21 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts64octets 0x00007c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c23 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts65to127octets 0x00007c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c25 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts128to255octets 0x00007c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c27 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts256to511octets 0x00007c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c29 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts512to1023octets 0x00007c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c2b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstat_pkts1024to1518octets 0x00007c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c2d - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_pkts1519toxoctets 0x00007c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c2f - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_fragments 0x00007c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c31 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstats_jabbers 0x00007c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c33 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_etherstatscrcerr 0x00007c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c35 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_unicastmacctrlframes 0x00007c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c37 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_multicastmac_ctrlframes 0x00007c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c39 - - - b[31:0] b[31:0] - -
- - - - - tx_stats_broadcastmac_ctrlframes 0x00007c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
- - - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
- REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00000df6 1 RO uint32 b[0:0] - - -
- - - - - xgmii_tx_ready 0x00000df6 1 RO uint32 b[1:1] - - -
- - - - - xgmii_link_status 0x00000df6 1 RO uint32 b[3:2] - - -
\ No newline at end of file
+# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
+# ---------------------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
+ ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - -
+ PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - -
+ - - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - -
+ - - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - -
+ - - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - -
+ - - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - -
+ - - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - -
+ - - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - -
+ - - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - -
+ - - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - -
+ - - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - -
+ - - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - -
+ - - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - -
+ - - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - -
+ - - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - -
+ REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - -
+ REG_FPGA_TEMP_SENS 1 1 REG temp 0x00043418 1 RO uint32 b[31:0] - - -
+ REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x000433d0 6 RO uint32 b[31:0] - - -
+ RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - -
+ AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - -
+ AVS_ETH_0_REG 1 1 REG status 0x00043360 12 RO uint32 b[31:0] - - -
+ AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - -
+ PIO_PPS 1 1 REG capture_cnt 0x00043448 1 RO uint32 b[29:0] - - -
+ - - - - stable 0x00043448 1 RO uint32 b[30:30] - - -
+ - - - - toggle 0x00043448 1 RO uint32 b[31:31] - - -
+ - - - - expected_cnt 0x00043449 1 RW uint32 b[27:0] - - -
+ - - - - edge 0x00043449 1 RW uint32 b[31:31] - - -
+ - - - - offset_cnt 0x0004344a 1 RO uint32 b[27:0] - - -
+ REG_EPCS 1 1 REG addr 0x00043420 1 WO uint32 b[31:0] - - -
+ - - - - rden 0x00043421 1 WO uint32 b[0:0] - - -
+ - - - - read_bit 0x00043422 1 WO uint32 b[0:0] - - -
+ - - - - write_bit 0x00043423 1 WO uint32 b[0:0] - - -
+ - - - - sector_erase 0x00043424 1 WO uint32 b[0:0] - - -
+ - - - - busy 0x00043425 1 RO uint32 b[0:0] - - -
+ - - - - unprotect 0x00043426 1 WO uint32 b[31:0] - - -
+ REG_DPMM_CTRL 1 1 REG rd_usedw 0x00043462 1 RO uint32 b[31:0] - - -
+ REG_DPMM_DATA 1 1 FIFO data 0x00043460 1 RO uint32 b[31:0] - - -
+ REG_MMDP_CTRL 1 1 REG wr_usedw 0x0004345e 1 RO uint32 b[31:0] - - -
+ - - - - wr_availw 0x0004345f 1 RO uint32 b[31:0] - - -
+ REG_MMDP_DATA 1 1 FIFO data 0x0004345c 1 WO uint32 b[31:0] - - -
+ REG_REMU 1 1 REG reconfigure 0x00043428 1 WO uint32 b[31:0] - - -
+ - - - - param 0x00043429 1 WO uint32 b[2:0] - - -
+ - - - - read_param 0x0004342a 1 WO uint32 b[0:0] - - -
+ - - - - write_param 0x0004342b 1 WO uint32 b[0:0] - - -
+ - - - - data_out 0x0004342c 1 RO uint32 b[31:0] - - -
+ - - - - data_in 0x0004342d 1 WO uint32 b[31:0] - - -
+ - - - - busy 0x0004342e 1 RO uint32 b[0:0] - - -
+ REG_SDP_INFO 1 1 REG block_period 0x000433c0 1 RO uint32 b[15:0] - - -
+ - - - - beam_repositioning_flag 0x000433c1 1 RW uint32 b[0:0] - - -
+ - - - - fsub_type 0x000433c2 1 RO uint32 b[0:0] - - -
+ - - - - f_adc 0x000433c3 1 RO uint32 b[0:0] - - -
+ - - - - nyquist_zone_index 0x000433c4 1 RW uint32 b[1:0] - - -
+ - - - - observation_id 0x000433c5 1 RW uint32 b[31:0] - - -
+ - - - - antenna_band_index 0x000433c6 1 RW uint32 b[0:0] - - -
+ - - - - station_id 0x000433c7 1 RW uint32 b[15:0] - - -
+ REG_RING_INFO 1 1 REG use_cable_to_previous_rn 0x00043434 1 RW uint32 b[0:0] - - -
+ - - - - use_cable_to_next_rn 0x00043435 1 RW uint32 b[0:0] - - -
+ - - - - n_rn 0x00043436 1 RW uint32 b[7:0] - - -
+ - - - - o_rn 0x00043437 1 RW uint32 b[7:0] - - -
+ PIO_JESD_CTRL 1 1 REG enable 0x00043452 1 RW uint32 b[30:0] - - -
+ - - - - reset 0x00043452 1 RW uint32 b[31:31] - - -
+ JESD204B 1 12 REG rx_lane_ctrl_common 0x00042000 1 RW uint32 b[2:0] - - 256
+ - - - - rx_lane_ctrl_0 0x00042001 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_1 0x00042002 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_2 0x00042003 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_3 0x00042004 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_4 0x00042005 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_5 0x00042006 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_6 0x00042007 1 RW uint32 b[2:0] - - -
+ - - - - rx_lane_ctrl_7 0x00042008 1 RW uint32 b[2:0] - - -
+ - - - - rx_dll_ctrl 0x00042014 1 RW uint32 b[16:0] - - -
+ - - - - rx_syncn_sysref_ctrl 0x00042015 1 RW uint32 b[24:0] - - -
+ - - - - rx_csr_sysref_always_on 0x00042015 1 RW uint32 b[1:1] - - -
+ - - - - rx_csr_rbd_offset 0x00042015 1 RW uint32 b[10:3] - - -
+ - - - - rx_csr_lmfc_offset 0x00042015 1 RW uint32 b[19:12] - - -
+ - - - - rx_err0 0x00042018 1 RW uint32 b[8:0] - - -
+ - - - - rx_err1 0x00042019 1 RW uint32 b[9:0] - - -
+ - - - - csr_dev_syncn 0x00042020 1 RO uint32 b[0:0] - - -
+ - - - - csr_rbd_count 0x00042020 1 RO uint32 b[10:3] - - -
+ - - - - rx_status1 0x00042021 1 RW uint32 b[23:0] - - -
+ - - - - rx_status2 0x00042022 1 RW uint32 b[23:0] - - -
+ - - - - rx_status3 0x00042023 1 RW uint32 b[7:0] - - -
+ - - - - rx_ilas_csr_l 0x00042025 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_f 0x00042025 1 RW uint32 b[15:8] - - -
+ - - - - rx_ilas_csr_k 0x00042025 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_m 0x00042025 1 RW uint32 b[31:24] - - -
+ - - - - rx_ilas_csr_n 0x00042026 1 RW uint32 b[4:0] - - -
+ - - - - rx_ilas_csr_cs 0x00042026 1 RW uint32 b[7:6] - - -
+ - - - - rx_ilas_csr_np 0x00042026 1 RW uint32 b[12:8] - - -
+ - - - - rx_ilas_csr_subclassv 0x00042026 1 RW uint32 b[15:13] - - -
+ - - - - rx_ilas_csr_s 0x00042026 1 RW uint32 b[20:16] - - -
+ - - - - rx_ilas_csr_jesdv 0x00042026 1 RW uint32 b[23:21] - - -
+ - - - - rx_ilas_csr_cf 0x00042026 1 RW uint32 b[28:24] - - -
+ - - - - rx_ilas_csr_hd 0x00042026 1 RW uint32 b[31:31] - - -
+ - - - - rx_status4 0x0004203c 1 RW uint32 b[15:0] - - -
+ - - - - rx_status5 0x0004203d 1 RW uint32 b[15:0] - - -
+ - - - - rx_status6 0x0004203e 1 RW uint32 b[23:0] - - -
+ - - - - rx_status7 0x0004203f 1 RO uint32 b[31:0] - - -
+ REG_DP_SHIFTRAM 1 12 REG shift 0x00043340 1 RW uint32 b[11:0] - - 2
+ REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00043410 1 RW uint32 b[0:0] - - -
+ - - - - dp_on_pps 0x00043410 1 RW uint32 b[1:1] - - -
+ - - - - nof_clk_per_sync 0x00043411 1 RW uint32 b[31:0] - - -
+ - - - - bsn_init 0x00043412 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043413 - - - b[31:0] b[63:32] - -
+ - - - - bsn_time_offset 0x00043414 1 RW uint32 b[9:0] - - -
+ REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00043458 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043459 - - - b[31:0] b[63:32] - -
+ REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00043000 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043000 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043000 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043001 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043002 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043003 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043004 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043005 1 RO uint32 b[31:0] - - -
+ - - - - bsn_first 0x00043006 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043007 - - - b[31:0] b[63:32] - -
+ - - - - bsn_first_cycle_cnt 0x00043008 1 RO uint32 b[31:0] - - -
+ REG_WG 1 12 REG mode 0x00043280 1 RW uint32 b[7:0] - - 4
+ - - - - nof_samples 0x00043280 1 RW uint32 b[31:16] - - -
+ - - - - phase 0x00043281 1 RW uint32 b[15:0] - - -
+ - - - - freq 0x00043282 1 RW uint32 b[30:0] - - -
+ - - - - ampl 0x00043283 1 RW uint32 b[16:0] - - -
+ RAM_WG 1 12 RAM data 0x00034000 1024 RW uint32 b[17:0] - - 1024
+ RAM_ST_HISTOGRAM 1 12 RAM data 0x00002000 512 RW uint32 b[31:0] b[27:0] - 512
+ REG_ADUH_MONITOR 1 12 REG mean_sum 0x000432c0 1 RO int64 b[31:0] b[31:0] - 4
+ - - - - - 0x000432c1 - - - b[31:0] b[63:32] - -
+ - - - - power_sum 0x000432c2 1 RO int64 b[31:0] b[31:0] - -
+ - - - - - 0x000432c3 - - - b[31:0] b[63:32] - -
+ REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00043320 1 RO uint32 b[31:0] - - 2
+ - - - - word_cnt 0x00043321 1 RO uint32 b[31:0] - - -
+ RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[31:0] b[15:0] - 1024
+ REG_SI 1 1 REG enable 0x0004345a 1 RW uint32 b[0:0] - - -
+ RAM_FIL_COEFS 1 16 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
+ RAM_EQUALIZER_GAINS 1 6 RAM data 0x00040000 1024 RW cint16_ir b[31:0] - - 1024
+ REG_DP_SELECTOR 1 1 REG input_select 0x00043456 1 RW uint32 b[0:0] - - -
+ RAM_ST_SST 1 6 RAM data 0x0003c000 1024 RW uint64 b[31:0] b[31:0] - 2048
+ - - - - - 0x0003c001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_SST 1 1 REG enable 0x00043450 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c41 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_statistics_per_packet 0x00000c43 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_bytes_per_statistic 0x00000c44 1 RW uint32 b[7:0] - - -
+ - - - - sdp_nof_signal_inputs 0x00000c45 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000c46 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_sst_signal_input_index 0x00000c46 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_sst_reserved 0x00000c46 1 RW uint32 b[31:8] - - -
+ - - - - sdp_integration_interval 0x00000c47 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x00000c4b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x00000c4f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000c50 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000c51 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000c52 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000c53 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000c54 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000c55 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000c56 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000c57 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000c58 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000c59 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00000c5a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x00000c5b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x00000c5c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x00000c5d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x00000c5e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x00000c5f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000c60 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000c61 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000c62 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000c63 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000c64 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000c65 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000c66 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000c67 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c68 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c6a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - -
+ REG_BSN_MONITOR_V2_SST_OFFLOAD 1 1 REG xon_stable 0x000433f0 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x000433f0 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x000433f0 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x000433f1 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000433f2 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x000433f3 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x000433f4 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x000433f5 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x000433f8 1 RO uint32 b[31:0] - - -
+ REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x000433a0 1 RW uint32 b[0:0] - - -
+ - - - - ctrl_interval_size 0x000433a1 1 RW uint32 b[30:0] - - -
+ - - - - ctrl_start_bsn 0x000433a2 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000433a3 - - - b[31:0] b[63:32] - -
+ - - - - mon_current_input_bsn 0x000433a4 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000433a5 - - - b[31:0] b[63:32] - -
+ - - - - mon_input_bsn_at_sync 0x000433a6 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000433a7 - - - b[31:0] b[63:32] - -
+ - - - - mon_output_enable 0x000433a8 1 RO uint32 b[0:0] - - -
+ - - - - mon_output_sync_bsn 0x000433a9 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000433aa - - - b[31:0] b[63:32] - -
+ - - - - block_size 0x000433ab 1 RO uint32 b[31:0] - - -
+ RAM_ST_XSQ 1 9 RAM data 0x00010000 1008 RW cint64_ir b[31:0] b[31:0] - 4096
+ - - - - - 0x00010001 - - - b[31:0] b[63:32] - -
+ - - - - - 0x00010002 - - - b[31:0] b[95:64] - -
+ - - - - - 0x00010003 - - - b[31:0] b[127:96] - -
+ REG_CROSSLETS_INFO 1 1 REG offset 0x000433b0 15 RW uint32 b[31:0] - - -
+ - - - - step 0x000433bf 1 RW uint32 b[31:0] - - -
+ REG_NOF_CROSSLETS 1 1 REG nof_crosslets 0x0004344c 1 RW uint32 b[31:0] - - -
+ - - - - unused 0x0004344d 1 RW uint32 b[31:0] - - -
+ REG_STAT_ENABLE_XST 1 1 REG enable 0x0004344e 1 RW uint32 b[0:0] - - -
+ REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000041 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00000042 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00000043 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00000044 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00000045 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00000046 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_xst_signal_input_b_index 0x00000046 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id_xst_signal_input_a_index 0x00000046 1 RW uint32 b[15:8] - - -
+ - - - - sdp_data_id_xst_subband_index 0x00000046 1 RW uint32 b[24:16] - - -
+ - - - - sdp_data_id_xst_reserved 0x00000046 1 RW uint32 b[31:25] - - -
+ - - - - sdp_integration_interval 0x00000047 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0000004b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0000004f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00000050 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00000051 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00000052 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00000053 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00000054 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00000055 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00000056 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00000057 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00000058 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00000059 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0000005a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0000005b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0000005c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0000005d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0000005e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0000005f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x00000060 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00000061 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00000062 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00000063 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00000064 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00000065 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00000066 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00000067 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000068 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0000006a - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - -
+ REG_BSN_ALIGN_V2_XSUB 1 9 REG enable 0x00043300 1 RW uint32 b[0:0] - - 2
+ - - - - replaced_pkt_cnt 0x00043301 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_XSUB 1 9 REG xon_stable 0x00000080 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00000080 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000080 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000081 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000082 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000083 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000084 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000085 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000088 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_XSUB 1 1 REG xon_stable 0x00043408 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043408 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043408 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043409 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x0004340a - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x0004340b 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x0004340c 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x0004340d 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043410 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_XST_OFFLOAD 1 1 REG xon_stable 0x00043400 1 RO uint32 b[0:0] - - -
+ - - - - ready_stable 0x00043400 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043400 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043401 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043402 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043403 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043404 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043405 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043408 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_XST 1 1 REG lane_direction 0x00000c02 1 RO uint32 b[0:0] - - -
+ - - - - transport_nof_hops 0x00000c03 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_XST 1 16 REG xon_stable 0x00043100 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00043100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043105 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043108 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_XST 1 16 REG xon_stable 0x00000c80 1 RO uint32 b[0:0] - - 8
+ - - - - ready_stable 0x00000c80 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000c80 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000c81 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c82 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000c83 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000c84 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000c85 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000c88 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_XST 1 1 REG err_count_index 0x00043390 8 RO uint32 b[31:0] - - -
+ - - - - total_discarded_blocks 0x00043398 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x00043399 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004339a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST 1 1 REG nof_sync_discarded 0x00043438 1 RO uint32 b[31:0] - - -
+ - - - - nof_sync 0x00043439 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0004343a 1 RW uint32 b[31:0] - - -
+ REG_TR_10GBE_MAC 1 3 REG rx_transfer_control 0x00020000 1 RW uint32 b[0:0] - - 1
+ - - - - rx_transfer_status 0x00020001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00020002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00020040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00020080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000200c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000200c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000200c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000200c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00020100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00020140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00020800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00020801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00020802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00020803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00020804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00020805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00020806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00020807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00020808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00020809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0002080a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0002080b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00020818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00020c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00020c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00020c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00020c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00020c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00020c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00020c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00020c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00020c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00020c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00020c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00020c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00020c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00020c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00020c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00020c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00020c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00020c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00020c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00020c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00020c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00020c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00020c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00020c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00020c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00020c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00020c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00020c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00020c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00020c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00020c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00020c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00021001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00021040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00021080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000210c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000210c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00021100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00021140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00021141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00021142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00021180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00021181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00021182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00021183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00021184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00021185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00021186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00021187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00021190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00021191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00021192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00021193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00021194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00021195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00021196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00021197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000211a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00021200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00021201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00021202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00021801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00021c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00021c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00021c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00021c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00021c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00021c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00021c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00021c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00021c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00021c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00021c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00021c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00021c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00021c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00021c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00021c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00021c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00021c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00021c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00021c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00021c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00021c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00021c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00021c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00021c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00021c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00021c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00021c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00021c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00021c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00021c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00021c3d - - - b[31:0] b[31:0] - -
+ REG_TR_10GBE_ETH10G 1 3 REG tx_snk_out_xon 0x000433f8 1 RO uint32 b[0:0] - - 1
+ - - - - xgmii_tx_ready 0x000433f8 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x000433f8 1 RO uint32 b[3:2] - - -
+ RAM_SS_SS_WIDE 2 6 RAM data 0x00030000 976 RW uint32 b[9:0] - 8192 1024
+ RAM_BF_WEIGHTS 2 12 RAM data 0x00028000 976 RW cint16_ir b[31:0] - 16384 1024
+ REG_BSN_ALIGN_V2_BF 2 2 REG enable 0x000433e0 1 RW uint32 b[0:0] - 1 2
+ - - - - replaced_pkt_cnt 0x000433e1 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RX_ALIGN_BF 2 2 REG xon_stable 0x00000c20 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00000c20 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000c20 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000c21 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c22 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000c23 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000c24 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000c25 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000c28 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_ALIGNED_BF 2 1 REG xon_stable 0x00000c10 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00000c10 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000c10 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000c11 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000c12 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000c13 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000c14 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000c15 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000c18 1 RO uint32 b[31:0] - - -
+ REG_RING_LANE_INFO_BF 2 1 REG lane_direction 0x00000c04 1 RO uint32 b[0:0] - 1 2
+ - - - - transport_nof_hops 0x00000c05 1 RW uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_RX_BF 2 16 REG xon_stable 0x00000d00 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00000d00 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000d00 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000d01 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000d02 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000d03 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000d04 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000d05 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000d08 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_RING_TX_BF 2 16 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00000102 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00000108 1 RO uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_ERR_BF 2 1 REG err_count_index 0x00000020 8 RO uint32 b[31:0] - 1 16
+ - - - - total_discarded_blocks 0x00000028 1 RO uint32 b[31:0] - - -
+ - - - - total_block_count 0x00000029 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x0000002a 1 RW uint32 b[31:0] - - -
+ REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF 2 1 REG nof_sync_discarded 0x00000c08 1 RO uint32 b[31:0] - 1 4
+ - - - - nof_sync 0x00000c09 1 RO uint32 b[31:0] - - -
+ - - - - clear 0x00000c0a 1 RW uint32 b[31:0] - - -
+ REG_BF_SCALE 2 1 REG scale 0x00043444 1 RW uint32 b[15:0] - 2 2
+ - - - - unused 0x00043445 1 RW uint32 b[31:0] - - -
+ REG_HDR_DAT 2 1 REG bsn 0x00043200 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00043201 - - - b[31:0] b[63:32] - -
+ - - - - sdp_block_period 0x00043202 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_beamlets_per_block 0x00043203 1 RW uint32 b[15:0] - - -
+ - - - - sdp_nof_blocks_per_packet 0x00043204 1 RW uint32 b[7:0] - - -
+ - - - - sdp_beamlet_index 0x00043205 1 RW uint32 b[15:0] - - -
+ - - - - sdp_beamlet_scale 0x00043206 1 RW uint32 b[15:0] - - -
+ - - - - sdp_reserved 0x00043207 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043208 - - - b[7:0] b[39:32] - -
+ - - - - sdp_source_info_gn_index 0x00043209 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_beamlet_width 0x0004320a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_repositioning_flag 0x0004320b 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004320c 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004320d 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004320e 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x0004320f 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00043210 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00043211 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00043212 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00043213 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00043214 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00043215 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00043216 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00043217 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00043218 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x00043219 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004321a 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004321b 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004321c 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004321d 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004321e 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x0004321f 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x00043220 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x00043221 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x00043222 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x00043223 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x00043224 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x00043225 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x00043226 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043227 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x00043228 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043229 - - - b[15:0] b[47:32] - -
+ REG_DP_XONOFF 2 1 REG enable_stream 0x00043440 1 RW uint32 b[0:0] - 2 2
+ RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048
+ - - - - - 0x00001001 - - - b[21:0] b[53:32] - -
+ REG_STAT_ENABLE_BST 2 1 REG enable 0x0004343c 1 RW uint32 b[0:0] - 2 2
+ REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00043180 1 RW uint64 b[31:0] b[31:0] 64 64
+ - - - - - 0x00043181 - - - b[31:0] b[63:32] - -
+ - - - - block_period 0x00043182 1 RW uint32 b[15:0] - - -
+ - - - - nof_statistics_per_packet 0x00043183 1 RW uint32 b[15:0] - - -
+ - - - - nof_bytes_per_statistic 0x00043184 1 RW uint32 b[7:0] - - -
+ - - - - nof_signal_inputs 0x00043185 1 RW uint32 b[7:0] - - -
+ - - - - sdp_data_id 0x00043186 1 RW uint32 b[31:0] - - -
+ - - - - sdp_data_id_bst_beamlet_index 0x00043186 1 RW uint32 b[15:0] - - -
+ - - - - sdp_data_id_bst_reserved 0x00043186 1 RW uint32 b[31:16] - - -
+ - - - - sdp_integration_interval 0x00043187 1 RW uint32 b[23:0] - - -
+ - - - - sdp_reserved 0x00043188 1 RW uint32 b[7:0] - - -
+ - - - - sdp_source_info_gn_index 0x00043189 1 RW uint32 b[4:0] - - -
+ - - - - sdp_source_info_reserved 0x0004318a 1 RW uint32 b[7:5] - - -
+ - - - - sdp_source_info_weighted_subbands_flag 0x0004318b 1 RW uint32 b[8:8] - - -
+ - - - - sdp_source_info_beam_repositioning_flag 0x0004318c 1 RW uint32 b[9:9] - - -
+ - - - - sdp_source_info_payload_error 0x0004318d 1 RW uint32 b[10:10] - - -
+ - - - - sdp_source_info_fsub_type 0x0004318e 1 RW uint32 b[11:11] - - -
+ - - - - sdp_source_info_f_adc 0x0004318f 1 RW uint32 b[12:12] - - -
+ - - - - sdp_source_info_nyquist_zone_index 0x00043190 1 RW uint32 b[14:13] - - -
+ - - - - sdp_source_info_antenna_band_index 0x00043191 1 RW uint32 b[15:15] - - -
+ - - - - sdp_station_id 0x00043192 1 RW uint32 b[15:0] - - -
+ - - - - sdp_observation_id 0x00043193 1 RW uint32 b[31:0] - - -
+ - - - - sdp_version_id 0x00043194 1 RO uint32 b[7:0] - - -
+ - - - - sdp_marker 0x00043195 1 RO uint32 b[7:0] - - -
+ - - - - udp_checksum 0x00043196 1 RW uint32 b[15:0] - - -
+ - - - - udp_length 0x00043197 1 RW uint32 b[15:0] - - -
+ - - - - udp_destination_port 0x00043198 1 RW uint32 b[15:0] - - -
+ - - - - udp_source_port 0x00043199 1 RW uint32 b[15:0] - - -
+ - - - - ip_destination_address 0x0004319a 1 RW uint32 b[31:0] - - -
+ - - - - ip_source_address 0x0004319b 1 RW uint32 b[31:0] - - -
+ - - - - ip_header_checksum 0x0004319c 1 RW uint32 b[15:0] - - -
+ - - - - ip_protocol 0x0004319d 1 RW uint32 b[7:0] - - -
+ - - - - ip_time_to_live 0x0004319e 1 RW uint32 b[7:0] - - -
+ - - - - ip_fragment_offset 0x0004319f 1 RW uint32 b[12:0] - - -
+ - - - - ip_flags 0x000431a0 1 RW uint32 b[2:0] - - -
+ - - - - ip_identification 0x000431a1 1 RW uint32 b[15:0] - - -
+ - - - - ip_total_length 0x000431a2 1 RW uint32 b[15:0] - - -
+ - - - - ip_services 0x000431a3 1 RW uint32 b[7:0] - - -
+ - - - - ip_header_length 0x000431a4 1 RW uint32 b[3:0] - - -
+ - - - - ip_version 0x000431a5 1 RW uint32 b[3:0] - - -
+ - - - - eth_type 0x000431a6 1 RO uint32 b[15:0] - - -
+ - - - - eth_source_mac 0x000431a7 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431a8 - - - b[15:0] b[47:32] - -
+ - - - - eth_destination_mac 0x000431a9 1 RW uint64 b[31:0] b[31:0] - -
+ - - - - - 0x000431aa - - - b[15:0] b[47:32] - -
+ - - - - word_align 0x000431ab 1 RW uint32 b[15:0] - - -
+ REG_BSN_MONITOR_V2_BST_OFFLOAD 2 1 REG xon_stable 0x00043380 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043380 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043380 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043381 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043382 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043383 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043384 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043385 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043388 1 RO uint32 b[31:0] - - -
+ REG_BSN_MONITOR_V2_BEAMLET_OUTPUT 2 1 REG xon_stable 0x00043370 1 RO uint32 b[0:0] - 1 8
+ - - - - ready_stable 0x00043370 1 RO uint32 b[1:1] - - -
+ - - - - sync_timeout 0x00043370 1 RO uint32 b[2:2] - - -
+ - - - - bsn_at_sync 0x00043371 1 RO uint64 b[31:0] b[31:0] - -
+ - - - - - 0x00043372 - - - b[31:0] b[63:32] - -
+ - - - - nof_sop 0x00043373 1 RO uint32 b[31:0] - - -
+ - - - - nof_valid 0x00043374 1 RO uint32 b[31:0] - - -
+ - - - - nof_err 0x00043375 1 RO uint32 b[31:0] - - -
+ - - - - latency 0x00043378 1 RO uint32 b[31:0] - - -
+ REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00006000 1 RW uint32 b[0:0] - - -
+ - - - - rx_transfer_status 0x00006001 1 RO uint32 b[0:0] - - -
+ - - - - tx_transfer_control 0x00006002 1 RW uint32 b[0:0] - - -
+ - - - - rx_padcrc_control 0x00006040 1 RW uint32 b[1:0] - - -
+ - - - - rx_crccheck_control 0x00006080 1 RW uint32 b[1:0] - - -
+ - - - - rx_pktovrflow_error 0x000060c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000060c1 - - - b[31:0] b[31:0] - -
+ - - - - rx_pktovrflow_etherstatsdropevents 0x000060c2 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000060c3 - - - b[31:0] b[31:0] - -
+ - - - - rx_lane_decoder_preamble_control 0x00006100 1 RW uint32 b[0:0] - - -
+ - - - - rx_preamble_inserter_control 0x00006140 1 RW uint32 b[0:0] - - -
+ - - - - rx_frame_control 0x00006800 1 RW uint32 b[19:0] - - -
+ - - - - rx_frame_maxlength 0x00006801 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr0 0x00006802 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_addr1 0x00006803 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_0 0x00006804 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr0_1 0x00006805 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_0 0x00006806 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr1_1 0x00006807 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_0 0x00006808 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr2_1 0x00006809 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_0 0x0000680a 1 RW uint32 b[15:0] - - -
+ - - - - rx_frame_spaddr3_1 0x0000680b 1 RW uint32 b[15:0] - - -
+ - - - - rx_pfc_control 0x00006818 1 RW uint32 b[16:0] - - -
+ - - - - rx_stats_clr 0x00006c00 1 RW uint32 b[0:0] - - -
+ - - - - rx_stats_framesok 0x00006c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c03 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_frameserr 0x00006c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c05 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_framescrcerr 0x00006c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c07 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_octetsok 0x00006c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c09 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pausemacctrl_frames 0x00006c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_iferrors 0x00006c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_framesok 0x00006c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c0f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicast_frameserr 0x00006c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c11 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastframesok 0x00006c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c13 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicast_frameserr 0x00006c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c15 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastframesok 0x00006c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c17 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcast_frameserr 0x00006c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c19 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatsoctets 0x00006c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatspkts 0x00006c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_undersizepkts 0x00006c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c1f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_oversizepkts 0x00006c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c21 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts64octets 0x00006c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c23 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts65to127octets 0x00006c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c25 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts128to255octets 0x00006c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c27 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts256to511octets 0x00006c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c29 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts512to1023octets 0x00006c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstat_pkts1024to1518octets 0x00006c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2d - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_pkts1519toxoctets 0x00006c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c2f - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_fragments 0x00006c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c31 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstats_jabbers 0x00006c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c33 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_etherstatscrcerr 0x00006c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c35 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_unicastmacctrlframes 0x00006c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c37 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_multicastmac_ctrlframes 0x00006c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c39 - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_broadcastmac_ctrlframes 0x00006c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c3b - - - b[31:0] b[31:0] - -
+ - - - - rx_stats_pfcmacctrlframes 0x00006c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00006c3d - - - b[31:0] b[31:0] - -
+ - - - - tx_transfer_status 0x00007001 1 RO uint32 b[0:0] - - -
+ - - - - tx_padins_control 0x00007040 1 RW uint32 b[0:0] - - -
+ - - - - tx_crcins_control 0x00007080 1 RW uint32 b[1:0] - - -
+ - - - - tx_pktunderflow_error 0x000070c0 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x000070c1 - - - b[31:0] b[31:0] - -
+ - - - - tx_preamble_control 0x00007100 1 RW uint32 b[0:0] - - -
+ - - - - tx_pauseframe_control 0x00007140 1 RW uint32 b[1:0] - - -
+ - - - - tx_pauseframe_quanta 0x00007141 1 RW uint32 b[15:0] - - -
+ - - - - tx_pauseframe_enable 0x00007142 1 RW uint32 b[0:0] - - -
+ - - - - pfc_pause_quanta_0 0x00007180 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_1 0x00007181 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_2 0x00007182 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_3 0x00007183 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_4 0x00007184 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_5 0x00007185 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_6 0x00007186 1 RW uint32 b[31:0] - - -
+ - - - - pfc_pause_quanta_7 0x00007187 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_0 0x00007190 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_1 0x00007191 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_2 0x00007192 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_3 0x00007193 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_4 0x00007194 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_5 0x00007195 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_6 0x00007196 1 RW uint32 b[31:0] - - -
+ - - - - pfc_holdoff_quanta_7 0x00007197 1 RW uint32 b[31:0] - - -
+ - - - - tx_pfc_priority_enable 0x000071a0 1 RW uint32 b[7:0] - - -
+ - - - - tx_addrins_control 0x00007200 1 RW uint32 b[0:0] - - -
+ - - - - tx_addrins_macaddr0 0x00007201 1 RW uint32 b[31:0] - - -
+ - - - - tx_addrins_macaddr1 0x00007202 1 RW uint32 b[15:0] - - -
+ - - - - tx_frame_maxlength 0x00007801 1 RW uint32 b[15:0] - - -
+ - - - - tx_stats_clr 0x00007c00 1 RW uint32 b[0:0] - - -
+ - - - - tx_stats_framesok 0x00007c02 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c03 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_frameserr 0x00007c04 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c05 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_framescrcerr 0x00007c06 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c07 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_octetsok 0x00007c08 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c09 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pausemacctrl_frames 0x00007c0a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_iferrors 0x00007c0c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_framesok 0x00007c0e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c0f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicast_frameserr 0x00007c10 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c11 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastframesok 0x00007c12 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c13 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicast_frameserr 0x00007c14 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c15 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastframesok 0x00007c16 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c17 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcast_frameserr 0x00007c18 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c19 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatsoctets 0x00007c1a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatspkts 0x00007c1c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_undersizepkts 0x00007c1e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c1f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_oversizepkts 0x00007c20 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c21 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts64octets 0x00007c22 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c23 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts65to127octets 0x00007c24 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c25 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts128to255octets 0x00007c26 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c27 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts256to511octets 0x00007c28 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c29 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts512to1023octets 0x00007c2a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstat_pkts1024to1518octets 0x00007c2c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2d - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_pkts1519toxoctets 0x00007c2e 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c2f - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_fragments 0x00007c30 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c31 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstats_jabbers 0x00007c32 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c33 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_etherstatscrcerr 0x00007c34 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c35 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_unicastmacctrlframes 0x00007c36 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c37 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_multicastmac_ctrlframes 0x00007c38 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c39 - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_broadcastmac_ctrlframes 0x00007c3a 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c3b - - - b[31:0] b[31:0] - -
+ - - - - tx_stats_pfcmacctrlframes 0x00007c3c 1 RO uint64 b[3:0] b[35:32] - -
+ - - - - - 0x00007c3d - - - b[31:0] b[31:0] - -
+ REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x00043454 1 RO uint32 b[0:0] - - -
+ - - - - xgmii_tx_ready 0x00043454 1 RO uint32 b[1:1] - - -
+ - - - - xgmii_link_status 0x00043454 1 RO uint32 b[3:2] - - -
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
index f91ded3ee6d1f4ffdce9b94d3f661e0fc3677698..141c75ef1a08e4ba734a8b622fb3997ced78c182 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
@@ -2302,7 +2302,7 @@
<ipxact:parameter parameterId="dataSlaveMapParam" type="string">
<ipxact:name>dataSlaveMapParam</ipxact:name>
<ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
- <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C540' end='0x10C580' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C600' end='0x10C620' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C620' end='0x10C640' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C640' end='0x10C660' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C660' end='0x10C680' datawidth='32' /><slave name='reg_remu.mem' start='0x10C680' end='0x10C6A0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C6C0' end='0x10C6D0' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C6D0' end='0x10C6E0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C6E0' end='0x10C6F0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C6F0' end='0x10C700' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C700' end='0x10C708' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C708' end='0x10C710' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C710' end='0x10C718' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C720' end='0x10C728' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C728' end='0x10C730' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C730' end='0x10C738' datawidth='32' /><slave name='reg_si.mem' start='0x10C738' end='0x10C740' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C740' end='0x10C748' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C748' end='0x10C750' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10C750' end='0x10C758' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10C758' end='0x10C760' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C760' end='0x10C768' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
+ <ipxact:value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CC00' end='0x10CC80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CC80' end='0x10CD00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CD00' end='0x10CD80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CD80' end='0x10CDC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CDC0' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10CE00' end='0x10CE40' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10CE40' end='0x10CE80' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10CE80' end='0x10CEC0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10CEC0' end='0x10CF00' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10CF00' end='0x10CF40' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10CF40' end='0x10CF80' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CF80' end='0x10CFA0' datawidth='32' /><slave name='timer_0.s1' start='0x10CFA0' end='0x10CFC0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CFC0' end='0x10CFE0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CFE0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D000' end='0x10D020' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D020' end='0x10D040' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D040' end='0x10D060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D060' end='0x10D080' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D080' end='0x10D0A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D0A0' end='0x10D0C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D0C0' end='0x10D0D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D0D0' end='0x10D0E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D0E0' end='0x10D0F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D0F0' end='0x10D100' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D100' end='0x10D110' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D110' end='0x10D120' datawidth='32' /><slave name='pio_pps.mem' start='0x10D120' end='0x10D130' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D130' end='0x10D138' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D138' end='0x10D140' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D140' end='0x10D148' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D148' end='0x10D150' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D150' end='0x10D158' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D158' end='0x10D160' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D160' end='0x10D168' datawidth='32' /><slave name='reg_si.mem' start='0x10D168' end='0x10D170' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D170' end='0x10D178' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D178' end='0x10D180' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D180' end='0x10D188' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D188' end='0x10D190' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D190' end='0x10D198' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
<ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
@@ -3589,7 +3589,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10C400' end='0x10C480' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10C540' end='0x10C580' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C600' end='0x10C620' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10C620' end='0x10C640' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10C640' end='0x10C660' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10C660' end='0x10C680' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10C680' end='0x10C6A0' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10C6C0' end='0x10C6D0' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10C6D0' end='0x10C6E0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10C6E0' end='0x10C6F0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10C6F0' end='0x10C700' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10C700' end='0x10C708' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10C708' end='0x10C710' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10C710' end='0x10C718' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10C720' end='0x10C728' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10C728' end='0x10C730' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10C730' end='0x10C738' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10C738' end='0x10C740' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10C740' end='0x10C748' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10C748' end='0x10C750' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10C750' end='0x10C758' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10C758' end='0x10C760' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C760' end='0x10C768' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x10C400' end='0x10C600' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_xsub.mem' start='0x10CC00' end='0x10CC80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x10CC80' end='0x10CD00' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x10CD00' end='0x10CD80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x10CD80' end='0x10CDC0' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CDC0' end='0x10CE00' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10CE00' end='0x10CE40' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_err_xst.mem' start='0x10CE40' end='0x10CE80' datawidth='32' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10CE80' end='0x10CEC0' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0x10CEC0' end='0x10CF00' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0x10CF00' end='0x10CF40' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0x10CF40' end='0x10CF80' datawidth='32' /&gt;&lt;slave name='reg_bsn_align_v2_bf.mem' start='0x10CF80' end='0x10CFA0' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x10CFA0' end='0x10CFC0' datawidth='16' /&gt;&lt;slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CFC0' end='0x10CFE0' datawidth='32' /&gt;&lt;slave name='reg_tr_10gbe_eth10g.mem' start='0x10CFE0' end='0x10D000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D000' end='0x10D020' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D020' end='0x10D040' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0x10D040' end='0x10D060' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x10D060' end='0x10D080' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x10D080' end='0x10D0A0' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x10D0A0' end='0x10D0C0' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x10D0C0' end='0x10D0D0' datawidth='32' /&gt;&lt;slave name='reg_ring_info.mem' start='0x10D0D0' end='0x10D0E0' datawidth='32' /&gt;&lt;slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D0E0' end='0x10D0F0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0x10D0F0' end='0x10D100' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0x10D100' end='0x10D110' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0x10D110' end='0x10D120' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x10D120' end='0x10D130' datawidth='32' /&gt;&lt;slave name='reg_nof_crosslets.mem' start='0x10D130' end='0x10D138' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x10D138' end='0x10D140' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0x10D140' end='0x10D148' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0x10D148' end='0x10D150' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0x10D150' end='0x10D158' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0x10D158' end='0x10D160' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x10D160' end='0x10D168' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0x10D168' end='0x10D170' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x10D170' end='0x10D178' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x10D178' end='0x10D180' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x10D180' end='0x10D188' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x10D188' end='0x10D190' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D190' end='0x10D198' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..e1d0d66379b252210796ad88ea06043cf5a6c9de
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
index a36f15b68aab53aeefe85eb71213123917720215..7980045246e380e47e159939d2a99c67944d72fb 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</ipxact:library>
- <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</ipxact:name>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</ipxact:library>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..4269aa977719fd68cae98c2f194618df283b90aa
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>64</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
index 418509f913b3688577398724d26b4360c1e860b1..0e62f34aa41303ae2e554a860a30d49e857bbaae 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</ipxact:library>
- <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</ipxact:name>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</ipxact:library>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
new file mode 100644
index 0000000000000000000000000000000000000000..5b9a4ee1344ba29b68494e07654f754be27f1812
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>64</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
new file mode 100644
index 0000000000000000000000000000000000000000..e103c1bdbe08e10a2feebac2159a11538f49efaa
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>64</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>3</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>4</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>64</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..3606904580dff38374f462b7ace6f5f5619be314
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>1024</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>1024</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..80b7d3e2f45777c4710834eb2e19c881514b10aa
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>1024</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>7</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>1024</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..a5ce96a309f19ce012fce6468dbf9c78d8dcdd10
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
rename to applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
index e9f5a18d77418f1c82cdf526bf136fcf2f04fdd1..76e0c9a47de098e90c1dbc9cc878ef3728561d8b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</ipxact:library>
- <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</ipxact:name>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</ipxact:name>
<ipxact:version>1.0</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
@@ -851,7 +851,7 @@
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>ASTRON</ipxact:vendor>
- <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</ipxact:library>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</ipxact:library>
<ipxact:name>avs_common_mm</ipxact:name>
<ipxact:version>1.0</ipxact:version>
</altera:entity_info>
@@ -909,7 +909,7 @@
type = "String";
}
}
- element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub
{
}
}
@@ -1494,38 +1494,38 @@
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
new file mode 100644
index 0000000000000000000000000000000000000000..750df016d7ce283e342a56629beccbe347ec1019
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..b60d0e43bd25c472396deda7bf1cfbf8f8f5b7da
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>2</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>3</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..eeeb861993a457cd774616e78ecdbe1d8d499935
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>128</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>4</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>5</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>128</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>7</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
new file mode 100644
index 0000000000000000000000000000000000000000..ae2b3e4bfa82c6891224b22bc65424b846db9dda
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</ipxact:library>
+ <ipxact:name>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>system</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>clk</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="clockRate" type="longint">
+ <ipxact:name>clockRate</ipxact:name>
+ <ipxact:displayName>Clock rate</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="externallyDriven" type="bit">
+ <ipxact:name>externallyDriven</ipxact:name>
+ <ipxact:displayName>Externally driven</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="ptfSchematicName" type="string">
+ <ipxact:name>ptfSchematicName</ipxact:name>
+ <ipxact:displayName>PTF schematic name</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>system_reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>DEASSERT</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>mem</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>address</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>write</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>writedata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>read</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>readdata</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="addressAlignment" type="string">
+ <ipxact:name>addressAlignment</ipxact:name>
+ <ipxact:displayName>Slave addressing</ipxact:displayName>
+ <ipxact:value>DYNAMIC</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressGroup" type="int">
+ <ipxact:name>addressGroup</ipxact:name>
+ <ipxact:displayName>Address group</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressSpan" type="string">
+ <ipxact:name>addressSpan</ipxact:name>
+ <ipxact:displayName>Address span</ipxact:displayName>
+ <ipxact:value>16</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="addressUnits" type="string">
+ <ipxact:name>addressUnits</ipxact:name>
+ <ipxact:displayName>Address units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+ <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+ <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value>system</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>Associated reset</ipxact:displayName>
+ <ipxact:value>system_reset</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+ <ipxact:name>bitsPerSymbol</ipxact:name>
+ <ipxact:displayName>Bits per symbol</ipxact:displayName>
+ <ipxact:value>8</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+ <ipxact:name>bridgedAddressOffset</ipxact:name>
+ <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bridgesToMaster" type="string">
+ <ipxact:name>bridgesToMaster</ipxact:name>
+ <ipxact:displayName>Bridges to master</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+ <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+ <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="burstcountUnits" type="string">
+ <ipxact:name>burstcountUnits</ipxact:name>
+ <ipxact:displayName>Burstcount units</ipxact:displayName>
+ <ipxact:value>WORDS</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+ <ipxact:name>constantBurstBehavior</ipxact:name>
+ <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+ <ipxact:name>explicitAddressSpan</ipxact:name>
+ <ipxact:displayName>Explicit address span</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="holdTime" type="int">
+ <ipxact:name>holdTime</ipxact:name>
+ <ipxact:displayName>Hold</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="interleaveBursts" type="bit">
+ <ipxact:name>interleaveBursts</ipxact:name>
+ <ipxact:displayName>Interleave bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isBigEndian" type="bit">
+ <ipxact:name>isBigEndian</ipxact:name>
+ <ipxact:displayName>Big endian</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isFlash" type="bit">
+ <ipxact:name>isFlash</ipxact:name>
+ <ipxact:displayName>Flash memory</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+ <ipxact:name>isMemoryDevice</ipxact:name>
+ <ipxact:displayName>Memory device</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+ <ipxact:name>isNonVolatileStorage</ipxact:name>
+ <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="linewrapBursts" type="bit">
+ <ipxact:name>linewrapBursts</ipxact:name>
+ <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+ <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+ <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+ <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumReadLatency" type="int">
+ <ipxact:name>minimumReadLatency</ipxact:name>
+ <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+ <ipxact:name>minimumResponseLatency</ipxact:name>
+ <ipxact:displayName>Minimum response latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+ <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+ <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="printableDevice" type="bit">
+ <ipxact:name>printableDevice</ipxact:name>
+ <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readLatency" type="int">
+ <ipxact:name>readLatency</ipxact:name>
+ <ipxact:displayName>Read latency</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitStates" type="int">
+ <ipxact:name>readWaitStates</ipxact:name>
+ <ipxact:displayName>Read wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="readWaitTime" type="int">
+ <ipxact:name>readWaitTime</ipxact:name>
+ <ipxact:displayName>Read wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+ <ipxact:name>registerIncomingSignals</ipxact:name>
+ <ipxact:displayName>Register incoming signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+ <ipxact:name>registerOutgoingSignals</ipxact:name>
+ <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="setupTime" type="int">
+ <ipxact:name>setupTime</ipxact:name>
+ <ipxact:displayName>Setup</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="timingUnits" type="string">
+ <ipxact:name>timingUnits</ipxact:name>
+ <ipxact:displayName>Timing units</ipxact:displayName>
+ <ipxact:value>Cycles</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="transparentBridge" type="bit">
+ <ipxact:name>transparentBridge</ipxact:name>
+ <ipxact:displayName>Transparent bridge</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+ <ipxact:name>waitrequestAllowance</ipxact:name>
+ <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+ <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+ <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeLatency" type="int">
+ <ipxact:name>writeLatency</ipxact:name>
+ <ipxact:displayName>Write latency</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitStates" type="int">
+ <ipxact:name>writeWaitStates</ipxact:name>
+ <ipxact:displayName>Write wait states</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="writeWaitTime" type="int">
+ <ipxact:name>writeWaitTime</ipxact:name>
+ <ipxact:displayName>Write wait</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ <ipxact:vendorExtensions>
+ <altera:altera_assignments>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+ <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+ <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+ <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_assignments>
+ </ipxact:vendorExtensions>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>reset</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>clk</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>address</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_address_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>write</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_write_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>writedata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>read</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_read_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ <ipxact:busInterface>
+ <ipxact:name>readdata</ipxact:name>
+ <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>export</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ <ipxact:parameters></ipxact:parameters>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>csi_system_clk</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>csi_system_reset</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_address</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>1</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_write</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_writedata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_read</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>avs_mem_readdata</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_reset_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_clk_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_address_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>1</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_write_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_writedata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_read_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:vectors></ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ <ipxact:port>
+ <ipxact:name>coe_readdata_export</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>in</ipxact:direction>
+ <ipxact:vectors>
+ <ipxact:vector>
+ <ipxact:left>0</ipxact:left>
+ <ipxact:right>31</ipxact:right>
+ </ipxact:vector>
+ </ipxact:vectors>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>ASTRON</ipxact:vendor>
+ <ipxact:library>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</ipxact:library>
+ <ipxact:name>avs_common_mm</ipxact:name>
+ <ipxact:version>1.0</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="g_adr_w" type="int">
+ <ipxact:name>g_adr_w</ipxact:name>
+ <ipxact:displayName>g_adr_w</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="g_dat_w" type="int">
+ <ipxact:name>g_dat_w</ipxact:name>
+ <ipxact:displayName>g_dat_w</ipxact:displayName>
+ <ipxact:value>32</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+ <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+ <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+ <ipxact:value>100000000</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>10AX115U3F45E2SG</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Arria 10</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>2</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element $system
+ {
+ datum _originalDeviceFamily
+ {
+ value = "Arria 10";
+ type = "String";
+ }
+ }
+ element qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf
+ {
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value><boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>4</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c154beb86c5b3d3352bd65adc62e83311d02f6d9
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
@@ -0,0 +1,43 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+#
+### QSFP_1_0 For BF
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4c1458f377e0f097733b6f7c81d1fac5c730a511
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
@@ -0,0 +1,249 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+#=====================
+# JESD pins
+# ====================
+# Pins needed for the 12 channel JESD204B interface to the ADCs
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
+#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
+
+#set_location_assignment PIN_AC7 -to BCK_RX[23]
+#set_location_assignment PIN_AB5 -to BCK_RX[22]
+#set_location_assignment PIN_AE7 -to BCK_RX[21]
+#set_location_assignment PIN_AD5 -to BCK_RX[20]
+#set_location_assignment PIN_AG7 -to BCK_RX[19]
+#set_location_assignment PIN_AF5 -to BCK_RX[18]
+#set_location_assignment PIN_AJ7 -to BCK_RX[17]
+#set_location_assignment PIN_AH5 -to BCK_RX[16]
+#set_location_assignment PIN_AL7 -to BCK_RX[15]
+#set_location_assignment PIN_AK5 -to BCK_RX[14]
+#set_location_assignment PIN_AN7 -to BCK_RX[13]
+#set_location_assignment PIN_AM5 -to BCK_RX[12]
+set_location_assignment PIN_AR7 -to BCK_RX[11]
+set_location_assignment PIN_AP5 -to BCK_RX[10]
+set_location_assignment PIN_AU7 -to BCK_RX[9]
+set_location_assignment PIN_AT5 -to BCK_RX[8]
+set_location_assignment PIN_AW7 -to BCK_RX[7]
+set_location_assignment PIN_AV5 -to BCK_RX[6]
+set_location_assignment PIN_BA7 -to BCK_RX[5]
+set_location_assignment PIN_AY5 -to BCK_RX[4]
+set_location_assignment PIN_BC7 -to BCK_RX[3]
+set_location_assignment PIN_BB5 -to BCK_RX[2]
+set_location_assignment PIN_AY9 -to BCK_RX[1]
+set_location_assignment PIN_BB9 -to BCK_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[12]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[12]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[13]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[13]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[13]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[14]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[14]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[14]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[15]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[15]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[15]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[16]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[16]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[16]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[17]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[17]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[17]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[18]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[18]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[18]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[19]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[19]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[19]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[20]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[20]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[20]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[21]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[21]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[21]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[22]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[22]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[22]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[23]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23]
+
+# Substitute new signal names from the jesd_simple design
+set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_REF_CLK
+set_location_assignment PIN_V9 -to BCK_REF_CLK
+set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
+
+set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
+set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to JESD204B_SYSREF
+set_location_assignment PIN_Y13 -to JESD204B_SYSREF
+set_location_assignment PIN_Y12 -to "JESD204B_SYSREF(n)"
+
+set_location_assignment PIN_AD12 -to JESD204B_SYNC_N[0]
+set_location_assignment PIN_AC13 -to JESD204B_SYNC_N[1]
+set_location_assignment PIN_AA13 -to JESD204B_SYNC_N[2]
+set_location_assignment PIN_AA12 -to JESD204B_SYNC_N[3]
+#set_location_assignment PIN_V14 -to JESD204B_SYNC_N[4]
+#set_location_assignment PIN_V12 -to JESD204B_SYNC_N[5]
+#set_location_assignment PIN_U14 -to JESD204B_SYNC_N[6]
+#set_location_assignment PIN_R13 -to JESD204B_SYNC_N[7]
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
index 2d6b00be0a9e149508a7a50de80f4257e1a78bc9..99176de66880a3f3c752d77e371d2578c9bf6143 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
@@ -88,231 +88,3 @@ set_location_assignment PIN_J42 -to RING_1_TX[1]
set_location_assignment PIN_G42 -to RING_1_TX[2]
set_location_assignment PIN_F44 -to RING_1_TX[3]
-#=====================
-# JESD pins
-# ====================
-# Pins needed for the 12 channel JESD204B interface to the ADCs
-
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[0]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[1]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[2]
-set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[3]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[4]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[5]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[6]
-#set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC_N[7]
-
-#set_location_assignment PIN_AC7 -to BCK_RX[23]
-#set_location_assignment PIN_AB5 -to BCK_RX[22]
-#set_location_assignment PIN_AE7 -to BCK_RX[21]
-#set_location_assignment PIN_AD5 -to BCK_RX[20]
-#set_location_assignment PIN_AG7 -to BCK_RX[19]
-#set_location_assignment PIN_AF5 -to BCK_RX[18]
-#set_location_assignment PIN_AJ7 -to BCK_RX[17]
-#set_location_assignment PIN_AH5 -to BCK_RX[16]
-#set_location_assignment PIN_AL7 -to BCK_RX[15]
-#set_location_assignment PIN_AK5 -to BCK_RX[14]
-#set_location_assignment PIN_AN7 -to BCK_RX[13]
-#set_location_assignment PIN_AM5 -to BCK_RX[12]
-set_location_assignment PIN_AR7 -to BCK_RX[11]
-set_location_assignment PIN_AP5 -to BCK_RX[10]
-set_location_assignment PIN_AU7 -to BCK_RX[9]
-set_location_assignment PIN_AT5 -to BCK_RX[8]
-set_location_assignment PIN_AW7 -to BCK_RX[7]
-set_location_assignment PIN_AV5 -to BCK_RX[6]
-set_location_assignment PIN_BA7 -to BCK_RX[5]
-set_location_assignment PIN_AY5 -to BCK_RX[4]
-set_location_assignment PIN_BC7 -to BCK_RX[3]
-set_location_assignment PIN_BB5 -to BCK_RX[2]
-set_location_assignment PIN_AY9 -to BCK_RX[1]
-set_location_assignment PIN_BB9 -to BCK_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[1]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[1]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[1]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[1]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[1]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[1]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[2]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[2]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[2]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[2]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[2]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[2]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[3]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[3]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[3]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[3]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[3]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[3]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[4]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[4]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[4]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[4]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[4]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[4]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[5]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[5]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[5]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[5]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[5]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[5]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[6]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[6]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[6]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[6]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[6]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[6]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[7]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[7]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[7]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[7]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[7]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[7]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[8]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[8]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[8]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[8]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[8]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[8]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[9]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[9]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[9]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[9]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[9]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[9]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[10]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[10]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[10]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[10]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[10]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[10]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[11]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[11]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[11]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[11]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[11]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[11]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[12]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[12]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[12]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[12]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[12]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[12]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[13]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[13]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[13]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[13]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[13]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[13]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[14]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[14]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[14]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[14]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[14]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[14]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[15]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[15]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[15]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[15]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[15]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[15]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[16]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[16]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[16]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[16]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[16]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[16]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[17]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[17]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[17]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[17]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[17]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[17]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[18]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[18]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[18]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[18]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[18]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[18]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[19]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[19]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[19]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[19]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[19]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[19]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[20]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[20]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[20]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[20]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[20]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[20]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[21]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[21]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[21]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[21]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[21]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[21]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[22]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[22]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[22]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[22]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[22]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[22]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_TX[23]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to BCK_TX[23]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_TX[23]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to BCK_TX[23]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to BCK_TX[23]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to BCK_TX[23]
-
-# Substitute new signal names from the jesd_simple design
-set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
-set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_REF_CLK
-set_location_assignment PIN_V9 -to BCK_REF_CLK
-set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
-
-set_instance_assignment -name IO_STANDARD LVDS -to JESD204B_SYSREF
-set_instance_assignment -name IO_STANDARD LVDS -to "JESD204B_SYSREF(n)"
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to JESD204B_SYSREF
-set_location_assignment PIN_Y13 -to JESD204B_SYSREF
-set_location_assignment PIN_Y12 -to "JESD204B_SYSREF(n)"
-
-set_location_assignment PIN_AD12 -to JESD204B_SYNC_N[0]
-set_location_assignment PIN_AC13 -to JESD204B_SYNC_N[1]
-set_location_assignment PIN_AA13 -to JESD204B_SYNC_N[2]
-set_location_assignment PIN_AA12 -to JESD204B_SYNC_N[3]
-#set_location_assignment PIN_V14 -to JESD204B_SYNC_N[4]
-#set_location_assignment PIN_V12 -to JESD204B_SYNC_N[5]
-#set_location_assignment PIN_U14 -to JESD204B_SYNC_N[6]
-#set_location_assignment PIN_R13 -to JESD204B_SYNC_N[7]
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..8de2b18168e9e0867c2cfc05aac017c88af17187
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
@@ -0,0 +1,297 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+#
+### QSFP_0_0 For ring
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
+
+### QSFP_0_1 For ring
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[1]
+
+### QSFP_0_2 For ring
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[2]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[2]
+
+### QSFP_0_3 For ring
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[3]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[3]
+
+#RING_0 RX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[2]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[3]
+
+
+#RING_1 RX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[1]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[2]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[2]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[3]
+
+
+#RING_0 TX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[2]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[3]
+
+
+#RING_1 TX assignments
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[1]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[1]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[2]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[2]
+
+#set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[3]
+#set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[3]
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
index 81c0f091dab0f00a36012ea0e3a0afca46709ee4..2e75dcd2bc2112f9245128b5a5df872dfb59304f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/qsys_lofar2_unb2c_sdp_station.qsys
@@ -30,7 +30,7 @@
{
datum baseAddress
{
- value = "12352";
+ value = "1101184";
type = "String";
}
}
@@ -99,7 +99,7 @@
{
datum baseAddress
{
- value = "1099616";
+ value = "1102224";
type = "String";
}
}
@@ -144,7 +144,7 @@
{
datum baseAddress
{
- value = "1099544";
+ value = "1102152";
type = "String";
}
}
@@ -165,7 +165,7 @@
{
datum baseAddress
{
- value = "1099504";
+ value = "1102112";
type = "String";
}
}
@@ -202,7 +202,7 @@
{
datum baseAddress
{
- value = "12304";
+ value = "1102016";
type = "String";
}
}
@@ -394,7 +394,7 @@
{
datum baseAddress
{
- value = "1098496";
+ value = "1100544";
type = "String";
}
}
@@ -410,11 +410,27 @@
{
datum baseAddress
{
- value = "1099488";
+ value = "1102096";
type = "String";
}
}
- element reg_bsn_align_v2
+ element reg_bsn_align_v2_bf
+ {
+ datum _sortIndex
+ {
+ value = "71";
+ type = "int";
+ }
+ }
+ element reg_bsn_align_v2_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "1101696";
+ type = "String";
+ }
+ }
+ element reg_bsn_align_v2_xsub
{
datum _sortIndex
{
@@ -422,11 +438,11 @@
type = "int";
}
}
- element reg_bsn_align_v2.mem
+ element reg_bsn_align_v2_xsub.mem
{
datum baseAddress
{
- value = "128";
+ value = "1100800";
type = "String";
}
}
@@ -442,27 +458,27 @@
{
datum baseAddress
{
- value = "1024";
+ value = "1097728";
type = "String";
}
}
- element reg_bsn_monitor_v2_bsn_align_v2_input
+ element reg_bsn_monitor_v2_aligned_bf
{
datum _sortIndex
{
- value = "57";
+ value = "73";
type = "int";
}
}
- element reg_bsn_monitor_v2_bsn_align_v2_input.mem
+ element reg_bsn_monitor_v2_aligned_bf.mem
{
datum baseAddress
{
- value = "512";
+ value = "12352";
type = "String";
}
}
- element reg_bsn_monitor_v2_bsn_align_v2_output
+ element reg_bsn_monitor_v2_aligned_xsub
{
datum _sortIndex
{
@@ -470,11 +486,59 @@
type = "int";
}
}
- element reg_bsn_monitor_v2_bsn_align_v2_output.mem
+ element reg_bsn_monitor_v2_aligned_xsub.mem
{
datum baseAddress
{
- value = "1099264";
+ value = "1101856";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_beamlet_output
+ {
+ datum _sortIndex
+ {
+ value = "70";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_beamlet_output.mem
+ {
+ datum baseAddress
+ {
+ value = "1101248";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_bst_offload
+ {
+ datum _sortIndex
+ {
+ value = "69";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_bst_offload.mem
+ {
+ datum baseAddress
+ {
+ value = "1101312";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_ring_rx_bf
+ {
+ datum _sortIndex
+ {
+ value = "75";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_ring_rx_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "13312";
type = "String";
}
}
@@ -482,7 +546,7 @@
{
datum _sortIndex
{
- value = "61";
+ value = "60";
type = "int";
}
}
@@ -490,7 +554,23 @@
{
datum baseAddress
{
- value = "13312";
+ value = "1098752";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_ring_tx_bf
+ {
+ datum _sortIndex
+ {
+ value = "76";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_ring_tx_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
type = "String";
}
}
@@ -498,7 +578,7 @@
{
datum _sortIndex
{
- value = "62";
+ value = "61";
type = "int";
}
}
@@ -510,11 +590,59 @@
type = "String";
}
}
+ element reg_bsn_monitor_v2_rx_align_bf
+ {
+ datum _sortIndex
+ {
+ value = "72";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_align_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_align_xsub
+ {
+ datum _sortIndex
+ {
+ value = "57";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_rx_align_xsub.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "String";
+ }
+ }
+ element reg_bsn_monitor_v2_sst_offload
+ {
+ datum _sortIndex
+ {
+ value = "68";
+ type = "int";
+ }
+ }
+ element reg_bsn_monitor_v2_sst_offload.mem
+ {
+ datum baseAddress
+ {
+ value = "1101760";
+ type = "String";
+ }
+ }
element reg_bsn_monitor_v2_xst_offload
{
datum _sortIndex
{
- value = "59";
+ value = "67";
type = "int";
}
}
@@ -522,7 +650,7 @@
{
datum baseAddress
{
- value = "1099232";
+ value = "1101824";
type = "String";
}
}
@@ -538,7 +666,7 @@
{
datum baseAddress
{
- value = "1099568";
+ value = "1102176";
type = "String";
}
}
@@ -554,7 +682,7 @@
{
datum baseAddress
{
- value = "1099296";
+ value = "1101888";
type = "String";
}
}
@@ -570,7 +698,7 @@
{
datum baseAddress
{
- value = "1098944";
+ value = "1101440";
type = "String";
}
}
@@ -586,7 +714,7 @@
{
datum baseAddress
{
- value = "1099008";
+ value = "1101504";
type = "String";
}
}
@@ -602,7 +730,23 @@
{
datum baseAddress
{
- value = "12416";
+ value = "1100928";
+ type = "String";
+ }
+ }
+ element reg_dp_block_validate_bsn_at_sync_bf
+ {
+ datum _sortIndex
+ {
+ value = "78";
+ type = "int";
+ }
+ }
+ element reg_dp_block_validate_bsn_at_sync_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "12320";
type = "String";
}
}
@@ -610,7 +754,7 @@
{
datum _sortIndex
{
- value = "64";
+ value = "63";
type = "int";
}
}
@@ -618,7 +762,23 @@
{
datum baseAddress
{
- value = "1099440";
+ value = "1102048";
+ type = "String";
+ }
+ }
+ element reg_dp_block_validate_err_bf
+ {
+ datum _sortIndex
+ {
+ value = "77";
+ type = "int";
+ }
+ }
+ element reg_dp_block_validate_err_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
type = "String";
}
}
@@ -626,7 +786,7 @@
{
datum _sortIndex
{
- value = "63";
+ value = "62";
type = "int";
}
}
@@ -634,7 +794,7 @@
{
datum baseAddress
{
- value = "1098880";
+ value = "1101376";
type = "String";
}
}
@@ -650,7 +810,7 @@
{
datum baseAddress
{
- value = "1099560";
+ value = "1102168";
type = "String";
}
}
@@ -666,7 +826,7 @@
{
datum baseAddress
{
- value = "1098752";
+ value = "1101056";
type = "String";
}
}
@@ -682,7 +842,7 @@
{
datum baseAddress
{
- value = "1099472";
+ value = "1102080";
type = "String";
}
}
@@ -703,7 +863,7 @@
{
datum baseAddress
{
- value = "1099608";
+ value = "1102216";
type = "String";
}
}
@@ -724,7 +884,7 @@
{
datum baseAddress
{
- value = "1099600";
+ value = "1102208";
type = "String";
}
}
@@ -745,7 +905,7 @@
{
datum baseAddress
{
- value = "1099360";
+ value = "1101952";
type = "String";
}
}
@@ -761,7 +921,7 @@
{
datum baseAddress
{
- value = "1099328";
+ value = "1101920";
type = "String";
}
}
@@ -782,7 +942,7 @@
{
datum baseAddress
{
- value = "1099136";
+ value = "1101632";
type = "String";
}
}
@@ -798,7 +958,7 @@
{
datum baseAddress
{
- value = "1097728";
+ value = "1099776";
type = "String";
}
}
@@ -819,7 +979,7 @@
{
datum baseAddress
{
- value = "1099592";
+ value = "1102200";
type = "String";
}
}
@@ -840,7 +1000,7 @@
{
datum baseAddress
{
- value = "1099584";
+ value = "1102192";
type = "String";
}
}
@@ -856,7 +1016,7 @@
{
datum baseAddress
{
- value = "1099520";
+ value = "1102128";
type = "String";
}
}
@@ -872,7 +1032,7 @@
{
datum baseAddress
{
- value = "1099552";
+ value = "1102160";
type = "String";
}
}
@@ -909,7 +1069,7 @@
{
datum baseAddress
{
- value = "1099392";
+ value = "1101984";
type = "String";
}
}
@@ -917,7 +1077,7 @@
{
datum _sortIndex
{
- value = "65";
+ value = "64";
type = "int";
}
}
@@ -925,7 +1085,23 @@
{
datum baseAddress
{
- value = "1099424";
+ value = "1102032";
+ type = "String";
+ }
+ }
+ element reg_ring_lane_info_bf
+ {
+ datum _sortIndex
+ {
+ value = "74";
+ type = "int";
+ }
+ }
+ element reg_ring_lane_info_bf.mem
+ {
+ datum baseAddress
+ {
+ value = "12304";
type = "String";
}
}
@@ -933,7 +1109,7 @@
{
datum _sortIndex
{
- value = "60";
+ value = "59";
type = "int";
}
}
@@ -957,7 +1133,7 @@
{
datum baseAddress
{
- value = "1099072";
+ value = "1101568";
type = "String";
}
}
@@ -973,7 +1149,7 @@
{
datum baseAddress
{
- value = "1099576";
+ value = "1102184";
type = "String";
}
}
@@ -989,7 +1165,7 @@
{
datum baseAddress
{
- value = "1099456";
+ value = "1102064";
type = "String";
}
}
@@ -1005,7 +1181,7 @@
{
datum baseAddress
{
- value = "1099536";
+ value = "1102144";
type = "String";
}
}
@@ -1021,7 +1197,7 @@
{
datum baseAddress
{
- value = "1099528";
+ value = "1102136";
type = "String";
}
}
@@ -1037,7 +1213,7 @@
{
datum baseAddress
{
- value = "13824";
+ value = "1099264";
type = "String";
}
}
@@ -1077,7 +1253,7 @@
{
datum _sortIndex
{
- value = "66";
+ value = "65";
type = "int";
}
}
@@ -1085,7 +1261,7 @@
{
datum baseAddress
{
- value = "1099200";
+ value = "1101792";
type = "String";
}
}
@@ -1093,7 +1269,7 @@
{
datum _sortIndex
{
- value = "67";
+ value = "66";
type = "int";
}
}
@@ -1143,7 +1319,7 @@
{
datum baseAddress
{
- value = "1098240";
+ value = "1100288";
type = "String";
}
}
@@ -1185,7 +1361,7 @@
{
datum baseAddress
{
- value = "12320";
+ value = "1101728";
type = "String";
}
}
@@ -1893,38 +2069,73 @@
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_address"
- internal="reg_bsn_align_v2.address"
+ name="reg_bsn_align_v2_bf_address"
+ internal="reg_bsn_align_v2_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_bf_clk"
+ internal="reg_bsn_align_v2_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_bf_read"
+ internal="reg_bsn_align_v2_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_bf_readdata"
+ internal="reg_bsn_align_v2_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_bf_reset"
+ internal="reg_bsn_align_v2_bf.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_clk"
- internal="reg_bsn_align_v2.clk"
+ name="reg_bsn_align_v2_bf_write"
+ internal="reg_bsn_align_v2_bf.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_read"
- internal="reg_bsn_align_v2.read"
+ name="reg_bsn_align_v2_bf_writedata"
+ internal="reg_bsn_align_v2_bf.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_readdata"
- internal="reg_bsn_align_v2.readdata"
+ name="reg_bsn_align_v2_xsub_address"
+ internal="reg_bsn_align_v2_xsub.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_reset"
- internal="reg_bsn_align_v2.reset"
+ name="reg_bsn_align_v2_xsub_clk"
+ internal="reg_bsn_align_v2_xsub.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_write"
- internal="reg_bsn_align_v2.write"
+ name="reg_bsn_align_v2_xsub_read"
+ internal="reg_bsn_align_v2_xsub.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_align_v2_writedata"
- internal="reg_bsn_align_v2.writedata"
+ name="reg_bsn_align_v2_xsub_readdata"
+ internal="reg_bsn_align_v2_xsub.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_xsub_reset"
+ internal="reg_bsn_align_v2_xsub.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_xsub_write"
+ internal="reg_bsn_align_v2_xsub.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_align_v2_xsub_writedata"
+ internal="reg_bsn_align_v2_xsub.writedata"
type="conduit"
dir="end" />
<interface
@@ -1963,73 +2174,178 @@
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_address"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.address"
+ name="reg_bsn_monitor_v2_aligned_bf_address"
+ internal="reg_bsn_monitor_v2_aligned_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_clk"
+ internal="reg_bsn_monitor_v2_aligned_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_read"
+ internal="reg_bsn_monitor_v2_aligned_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_readdata"
+ internal="reg_bsn_monitor_v2_aligned_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_reset"
+ internal="reg_bsn_monitor_v2_aligned_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_write"
+ internal="reg_bsn_monitor_v2_aligned_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_bf_writedata"
+ internal="reg_bsn_monitor_v2_aligned_bf.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_address"
+ internal="reg_bsn_monitor_v2_aligned_xsub.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_clk"
+ internal="reg_bsn_monitor_v2_aligned_xsub.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_read"
+ internal="reg_bsn_monitor_v2_aligned_xsub.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_readdata"
+ internal="reg_bsn_monitor_v2_aligned_xsub.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_reset"
+ internal="reg_bsn_monitor_v2_aligned_xsub.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_write"
+ internal="reg_bsn_monitor_v2_aligned_xsub.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_aligned_xsub_writedata"
+ internal="reg_bsn_monitor_v2_aligned_xsub.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_address"
+ internal="reg_bsn_monitor_v2_beamlet_output.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_clk"
+ internal="reg_bsn_monitor_v2_beamlet_output.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_read"
+ internal="reg_bsn_monitor_v2_beamlet_output.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_readdata"
+ internal="reg_bsn_monitor_v2_beamlet_output.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_reset"
+ internal="reg_bsn_monitor_v2_beamlet_output.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_write"
+ internal="reg_bsn_monitor_v2_beamlet_output.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_beamlet_output_writedata"
+ internal="reg_bsn_monitor_v2_beamlet_output.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_bst_offload_address"
+ internal="reg_bsn_monitor_v2_bst_offload.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_clk"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.clk"
+ name="reg_bsn_monitor_v2_bst_offload_clk"
+ internal="reg_bsn_monitor_v2_bst_offload.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_read"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.read"
+ name="reg_bsn_monitor_v2_bst_offload_read"
+ internal="reg_bsn_monitor_v2_bst_offload.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_readdata"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.readdata"
+ name="reg_bsn_monitor_v2_bst_offload_readdata"
+ internal="reg_bsn_monitor_v2_bst_offload.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_reset"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.reset"
+ name="reg_bsn_monitor_v2_bst_offload_reset"
+ internal="reg_bsn_monitor_v2_bst_offload.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_write"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.write"
+ name="reg_bsn_monitor_v2_bst_offload_write"
+ internal="reg_bsn_monitor_v2_bst_offload.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_input_writedata"
- internal="reg_bsn_monitor_v2_bsn_align_v2_input.writedata"
+ name="reg_bsn_monitor_v2_bst_offload_writedata"
+ internal="reg_bsn_monitor_v2_bst_offload.writedata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_address"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.address"
+ name="reg_bsn_monitor_v2_ring_rx_bf_address"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_clk"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.clk"
+ name="reg_bsn_monitor_v2_ring_rx_bf_clk"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.clk"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_read"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.read"
+ name="reg_bsn_monitor_v2_ring_rx_bf_read"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_readdata"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.readdata"
+ name="reg_bsn_monitor_v2_ring_rx_bf_readdata"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_reset"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.reset"
+ name="reg_bsn_monitor_v2_ring_rx_bf_reset"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_write"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.write"
+ name="reg_bsn_monitor_v2_ring_rx_bf_write"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_monitor_v2_bsn_align_v2_output_writedata"
- internal="reg_bsn_monitor_v2_bsn_align_v2_output.writedata"
+ name="reg_bsn_monitor_v2_ring_rx_bf_writedata"
+ internal="reg_bsn_monitor_v2_ring_rx_bf.writedata"
type="conduit"
dir="end" />
<interface
@@ -2067,6 +2383,41 @@
internal="reg_bsn_monitor_v2_ring_rx_xst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_address"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_clk"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_read"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_readdata"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_reset"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_write"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_ring_tx_bf_writedata"
+ internal="reg_bsn_monitor_v2_ring_tx_bf.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_monitor_v2_ring_tx_xst_address"
internal="reg_bsn_monitor_v2_ring_tx_xst.address"
@@ -2102,6 +2453,111 @@
internal="reg_bsn_monitor_v2_ring_tx_xst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_address"
+ internal="reg_bsn_monitor_v2_rx_align_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_clk"
+ internal="reg_bsn_monitor_v2_rx_align_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_read"
+ internal="reg_bsn_monitor_v2_rx_align_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_readdata"
+ internal="reg_bsn_monitor_v2_rx_align_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_reset"
+ internal="reg_bsn_monitor_v2_rx_align_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_write"
+ internal="reg_bsn_monitor_v2_rx_align_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_bf_writedata"
+ internal="reg_bsn_monitor_v2_rx_align_bf.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_address"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_clk"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_read"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_readdata"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_reset"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_write"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_rx_align_xsub_writedata"
+ internal="reg_bsn_monitor_v2_rx_align_xsub.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_address"
+ internal="reg_bsn_monitor_v2_sst_offload.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_clk"
+ internal="reg_bsn_monitor_v2_sst_offload.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_read"
+ internal="reg_bsn_monitor_v2_sst_offload.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_readdata"
+ internal="reg_bsn_monitor_v2_sst_offload.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_reset"
+ internal="reg_bsn_monitor_v2_sst_offload.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_write"
+ internal="reg_bsn_monitor_v2_sst_offload.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_bsn_monitor_v2_sst_offload_writedata"
+ internal="reg_bsn_monitor_v2_sst_offload.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_bsn_monitor_v2_xst_offload_address"
internal="reg_bsn_monitor_v2_xst_offload.address"
@@ -2312,6 +2768,41 @@
internal="reg_diag_data_buffer_bsn.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_address"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_clk"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_read"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_readdata"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_reset"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_write"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_bsn_at_sync_bf_writedata"
+ internal="reg_dp_block_validate_bsn_at_sync_bf.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dp_block_validate_bsn_at_sync_xst_address"
internal="reg_dp_block_validate_bsn_at_sync_xst.address"
@@ -2347,6 +2838,41 @@
internal="reg_dp_block_validate_bsn_at_sync_xst.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_address"
+ internal="reg_dp_block_validate_err_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_clk"
+ internal="reg_dp_block_validate_err_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_read"
+ internal="reg_dp_block_validate_err_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_readdata"
+ internal="reg_dp_block_validate_err_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_reset"
+ internal="reg_dp_block_validate_err_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_write"
+ internal="reg_dp_block_validate_err_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_block_validate_err_bf_writedata"
+ internal="reg_dp_block_validate_err_bf.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dp_block_validate_err_xst_address"
internal="reg_dp_block_validate_err_xst.address"
@@ -2934,6 +3460,41 @@
internal="reg_ring_info.writedata"
type="conduit"
dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_address"
+ internal="reg_ring_lane_info_bf.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_clk"
+ internal="reg_ring_lane_info_bf.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_read"
+ internal="reg_ring_lane_info_bf.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_readdata"
+ internal="reg_ring_lane_info_bf.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_reset"
+ internal="reg_ring_lane_info_bf.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_write"
+ internal="reg_ring_lane_info_bf.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_ring_lane_info_bf_writedata"
+ internal="reg_ring_lane_info_bf.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_ring_lane_info_xst_address"
internal="reg_ring_lane_info_xst.address"
@@ -7936,7 +8497,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_bsn_align_v2.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_input.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x3400' end='0x3600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x3600' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C000' end='0x10C200' datawidth='32' /><slave name='reg_wg.mem' start='0x10C200' end='0x10C300' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10C300' end='0x10C400' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10C400' end='0x10C480' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10C480' end='0x10C4C0' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10C4C0' end='0x10C500' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10C500' end='0x10C540' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10C540' end='0x10C580' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10C580' end='0x10C5C0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10C5C0' end='0x10C5E0' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10C5E0' end='0x10C600' datawidth='32' /><slave name='reg_bsn_monitor_v2_bsn_align_v2_output.mem' start='0x10C600' end='0x10C620' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10C620' end='0x10C640' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10C640' end='0x10C660' datawidth='32' /><slave name='reg_epcs.mem' start='0x10C660' end='0x10C680' datawidth='32' /><slave name='reg_remu.mem' start='0x10C680' end='0x10C6A0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10C6A0' end='0x10C6B0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10C6B0' end='0x10C6C0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10C6C0' end='0x10C6D0' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10C6D0' end='0x10C6E0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10C6E0' end='0x10C6F0' datawidth='32' /><slave name='pio_pps.mem' start='0x10C6F0' end='0x10C700' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10C700' end='0x10C708' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10C708' end='0x10C710' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10C710' end='0x10C718' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10C718' end='0x10C720' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10C720' end='0x10C728' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10C728' end='0x10C730' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10C730' end='0x10C738' datawidth='32' /><slave name='reg_si.mem' start='0x10C738' end='0x10C740' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10C740' end='0x10C748' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10C748' end='0x10C750' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10C750' end='0x10C758' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10C758' end='0x10C760' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10C760' end='0x10C768' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_dp_block_validate_err_bf.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_xsub.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_bf.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_ring_lane_info_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='reg_ring_lane_info_bf.mem' start='0x3010' end='0x3020' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_bf.mem' start='0x3020' end='0x3040' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_bf.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_bsn_monitor_v2_rx_align_bf.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_tx_xst.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_bf.mem' start='0x3400' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='ram_st_histogram.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='reg_tr_10gbe_mac.mem' start='0x80000' end='0xA0000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0xA0000' end='0xC0000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0xC0000' end='0xD0000' datawidth='32' /><slave name='ram_wg.mem' start='0xD0000' end='0xE0000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0xE0000' end='0xF0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xF0000' end='0x100000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x100000' end='0x108000' datawidth='32' /><slave name='jesd204b.mem' start='0x108000' end='0x10C000' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x10C000' end='0x10C400' datawidth='32' /><slave name='reg_bsn_monitor_v2_ring_rx_xst.mem' start='0x10C400' end='0x10C600' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x10C600' end='0x10C800' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x10C800' end='0x10CA00' datawidth='32' /><slave name='reg_wg.mem' start='0x10CA00' end='0x10CB00' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x10CB00' end='0x10CC00' datawidth='32' /><slave name='reg_bsn_align_v2_xsub.mem' start='0x10CC00' end='0x10CC80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x10CC80' end='0x10CD00' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x10CD00' end='0x10CD80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x10CD80' end='0x10CDC0' datawidth='32' /><slave name='reg_bsn_monitor_v2_beamlet_output.mem' start='0x10CDC0' end='0x10CE00' datawidth='32' /><slave name='reg_bsn_monitor_v2_bst_offload.mem' start='0x10CE00' end='0x10CE40' datawidth='32' /><slave name='reg_dp_block_validate_err_xst.mem' start='0x10CE40' end='0x10CE80' datawidth='32' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x10CE80' end='0x10CEC0' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0x10CEC0' end='0x10CF00' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x10CF00' end='0x10CF40' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x10CF40' end='0x10CF80' datawidth='32' /><slave name='reg_bsn_align_v2_bf.mem' start='0x10CF80' end='0x10CFA0' datawidth='32' /><slave name='timer_0.s1' start='0x10CFA0' end='0x10CFC0' datawidth='16' /><slave name='reg_bsn_monitor_v2_sst_offload.mem' start='0x10CFC0' end='0x10CFE0' datawidth='32' /><slave name='reg_tr_10gbe_eth10g.mem' start='0x10CFE0' end='0x10D000' datawidth='32' /><slave name='reg_bsn_monitor_v2_xst_offload.mem' start='0x10D000' end='0x10D020' datawidth='32' /><slave name='reg_bsn_monitor_v2_aligned_xsub.mem' start='0x10D020' end='0x10D040' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x10D040' end='0x10D060' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x10D060' end='0x10D080' datawidth='32' /><slave name='reg_epcs.mem' start='0x10D080' end='0x10D0A0' datawidth='32' /><slave name='reg_remu.mem' start='0x10D0A0' end='0x10D0C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x10D0C0' end='0x10D0D0' datawidth='32' /><slave name='reg_ring_info.mem' start='0x10D0D0' end='0x10D0E0' datawidth='32' /><slave name='reg_dp_block_validate_bsn_at_sync_xst.mem' start='0x10D0E0' end='0x10D0F0' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0x10D0F0' end='0x10D100' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x10D100' end='0x10D110' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x10D110' end='0x10D120' datawidth='32' /><slave name='pio_pps.mem' start='0x10D120' end='0x10D130' datawidth='32' /><slave name='reg_nof_crosslets.mem' start='0x10D130' end='0x10D138' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x10D138' end='0x10D140' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0x10D140' end='0x10D148' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x10D148' end='0x10D150' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x10D150' end='0x10D158' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x10D158' end='0x10D160' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x10D160' end='0x10D168' datawidth='32' /><slave name='reg_si.mem' start='0x10D168' end='0x10D170' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x10D170' end='0x10D178' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x10D178' end='0x10D180' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x10D180' end='0x10D188' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x10D188' end='0x10D190' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10D190' end='0x10D198' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -31468,7 +32029,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_align_v2"
+ name="reg_bsn_align_v2_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -31547,7 +32108,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -31616,7 +32177,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -31845,7 +32406,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32023,11 +32584,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -32127,7 +32688,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32196,7 +32757,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32425,7 +32986,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32579,37 +33140,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_input"
+ name="reg_bsn_align_v2_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -32617,17 +33178,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>8</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -32636,27 +33197,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -32669,13 +33231,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -32689,7 +33249,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32758,7 +33318,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -32915,12 +33475,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -32947,15 +33507,47 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -32979,12 +33571,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -33011,17 +33603,17 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33030,56 +33622,25 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
+ <key>associatedClock</key>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>system</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -33106,14 +33667,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -33164,11 +33725,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>10</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -33197,17 +33758,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>8</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -33216,27 +33777,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33249,13 +33811,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -33269,7 +33829,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>8</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33338,7 +33898,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>1024</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -33495,12 +34055,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -33527,17 +34087,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -33559,17 +34119,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33591,14 +34151,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33610,31 +34170,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33644,22 +34203,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -33686,14 +34247,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -33720,37 +34281,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_bsn_align_v2_input"
+ name="reg_bsn_monitor_input"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -33758,17 +34319,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -33777,28 +34338,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -33811,11 +34371,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -33829,7 +34391,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -33898,7 +34460,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34055,12 +34617,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -34087,17 +34649,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -34119,17 +34681,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -34151,14 +34713,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -34170,30 +34732,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -34203,24 +34766,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -34247,14 +34808,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -34305,11 +34866,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -34338,17 +34899,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -34357,28 +34918,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -34391,11 +34951,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -34409,7 +34971,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -34478,7 +35040,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -34635,12 +35197,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -34667,17 +35229,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -34699,17 +35261,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -34731,14 +35293,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -34750,30 +35312,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -34783,24 +35346,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -34827,14 +35388,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -34861,37 +35422,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_bsn_align_v2_output"
+ name="reg_bsn_monitor_v2_aligned_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -34970,7 +35531,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35039,7 +35600,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35268,7 +35829,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35446,11 +36007,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -35550,7 +36111,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -35619,7 +36180,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -35848,7 +36409,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36002,37 +36563,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_rx_xst"
+ name="reg_bsn_monitor_v2_aligned_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -36111,7 +36672,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36180,7 +36741,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36409,7 +36970,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36587,11 +37148,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -36691,7 +37252,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -36760,7 +37321,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -36989,7 +37550,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37143,37 +37704,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_ring_tx_xst"
+ name="reg_bsn_monitor_v2_beamlet_output"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -37252,7 +37813,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37321,7 +37882,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -37550,7 +38111,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37728,11 +38289,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -37832,7 +38393,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -37901,7 +38462,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38130,7 +38691,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38284,37 +38845,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_monitor_v2_xst_offload"
+ name="reg_bsn_monitor_v2_bst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -38393,7 +38954,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38462,7 +39023,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -38691,7 +39252,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -38869,11 +39430,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -38973,7 +39534,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39042,7 +39603,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39271,7 +39832,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39425,37 +39986,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_scheduler"
+ name="reg_bsn_monitor_v2_ring_rx_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -39463,17 +40024,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -39482,27 +40043,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -39515,13 +40077,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -39535,7 +40095,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -39604,7 +40164,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -39761,12 +40321,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -39793,17 +40353,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -39825,17 +40385,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -39857,14 +40417,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -39876,31 +40436,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -39910,22 +40469,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -39952,14 +40513,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -40010,11 +40571,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -40043,17 +40604,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -40062,27 +40623,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -40095,13 +40657,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -40115,7 +40675,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40184,7 +40744,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40341,12 +40901,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -40373,17 +40933,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -40405,17 +40965,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -40437,14 +40997,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -40456,61 +41016,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
+ <key>associatedClock</key>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>system</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -40532,14 +41061,46 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -40566,37 +41127,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source_v2"
+ name="reg_bsn_monitor_v2_ring_rx_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -40604,17 +41165,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -40623,27 +41184,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -40656,13 +41218,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -40676,7 +41236,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -40745,7 +41305,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -40902,12 +41462,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -40934,17 +41494,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -40966,17 +41526,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -40998,14 +41558,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -41017,31 +41577,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -41051,22 +41610,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -41093,14 +41654,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -41151,11 +41712,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -41184,17 +41745,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -41203,27 +41764,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -41236,13 +41798,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -41256,7 +41816,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41325,7 +41885,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -41482,12 +42042,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -41514,15 +42074,47 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41546,12 +42138,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -41578,17 +42170,17 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -41597,56 +42189,25 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
+ <key>associatedClock</key>
</entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
<entry>
- <key>associatedClock</key>
- <value>system</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -41673,14 +42234,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -41707,37 +42268,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_sync_scheduler_xsub"
+ name="reg_bsn_monitor_v2_ring_tx_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -41816,7 +42377,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -41885,7 +42446,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42114,7 +42675,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42292,11 +42853,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x400' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>10</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -42396,7 +42957,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42465,7 +43026,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>1024</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -42694,7 +43255,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>8</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -42848,37 +43409,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_crosslets_info"
+ name="reg_bsn_monitor_v2_ring_tx_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -42886,17 +43447,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -42905,27 +43466,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -42938,13 +43500,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -42958,7 +43518,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43027,7 +43587,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43184,12 +43744,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -43216,14 +43776,110 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -43248,107 +43904,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -43375,14 +43936,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -43433,11 +43994,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -43466,17 +44027,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -43485,27 +44046,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -43518,13 +44080,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -43538,7 +44098,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -43607,7 +44167,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -43764,12 +44324,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -43796,14 +44356,110 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -43828,107 +44484,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -43955,14 +44516,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -43989,37 +44550,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_diag_data_buffer_bsn"
+ name="reg_bsn_monitor_v2_rx_align_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -44027,17 +44588,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>5</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -44046,27 +44607,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -44079,13 +44641,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -44325,12 +44885,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -44357,14 +44917,110 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -44389,107 +45045,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -44516,14 +45077,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -44607,17 +45168,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>5</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -44626,27 +45187,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -44659,13 +45221,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -44905,12 +45465,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -44937,17 +45497,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -44969,17 +45529,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -45001,14 +45561,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -45020,31 +45580,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -45054,22 +45613,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -45096,14 +45657,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -45130,37 +45691,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_bsn_at_sync_xst"
+ name="reg_bsn_monitor_v2_rx_align_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -45239,7 +45800,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45308,7 +45869,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -45537,7 +46098,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45715,11 +46276,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -45819,7 +46380,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -45888,7 +46449,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -46117,7 +46678,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46271,37 +46832,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_block_validate_err_xst"
+ name="reg_bsn_monitor_v2_sst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -46380,7 +46941,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46449,7 +47010,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -46678,7 +47239,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -46856,11 +47417,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -46960,7 +47521,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47029,7 +47590,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47258,7 +47819,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47412,37 +47973,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_selector"
+ name="reg_bsn_monitor_v2_xst_offload"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -47450,17 +48011,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -47469,27 +48030,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -47502,13 +48064,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -47522,7 +48082,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -47591,7 +48151,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -47748,12 +48308,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -47780,17 +48340,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -47812,17 +48372,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -47844,14 +48404,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -47863,31 +48423,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -47897,22 +48456,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -47939,14 +48500,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -47997,11 +48558,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -48030,17 +48591,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -48049,27 +48610,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -48082,13 +48644,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -48102,7 +48662,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48171,7 +48731,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -48328,12 +48888,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -48360,17 +48920,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -48392,17 +48952,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -48424,14 +48984,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -48443,31 +49003,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -48477,22 +49036,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -48519,14 +49080,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -48553,37 +49114,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_shiftram"
+ name="reg_bsn_scheduler"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -48599,7 +49160,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48663,7 +49224,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -48732,7 +49293,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -49138,11 +49699,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -49179,7 +49740,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49243,7 +49804,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49312,7 +49873,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -49694,37 +50255,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dp_xonoff"
+ name="reg_bsn_source_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -49740,7 +50301,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49804,7 +50365,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -49873,7 +50434,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50279,11 +50840,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -50320,7 +50881,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50384,7 +50945,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -50453,7 +51014,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -50835,37 +51396,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="reg_bsn_sync_scheduler_xsub"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -50873,17 +51434,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -50892,27 +51453,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -50925,13 +51487,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -50945,7 +51505,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51014,7 +51574,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51170,70 +51730,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>reset</name>
<type>conduit</type>
@@ -51267,75 +51763,76 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>4</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -51393,6 +51890,70 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
</interfaces>
</boundary>
<originalModuleInfo>
@@ -51420,11 +51981,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -51453,17 +52014,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -51472,27 +52033,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -51505,13 +52067,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -51525,7 +52085,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -51594,7 +52154,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -51751,12 +52311,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -51783,17 +52343,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -51815,17 +52375,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -51846,69 +52406,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>write</name>
<type>conduit</type>
@@ -51973,40 +52470,104 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_crosslets_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -52022,7 +52583,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52086,7 +52647,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52155,7 +52716,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -52561,11 +53122,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -52602,7 +53163,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52666,7 +53227,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -52735,7 +53296,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -53117,37 +53678,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_crosslets_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_diag_data_buffer_bsn"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -53163,7 +53724,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53227,7 +53788,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53296,7 +53857,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -53702,11 +54263,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -53743,7 +54304,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53807,7 +54368,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -53876,7 +54437,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -54258,37 +54819,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_dp_block_validate_bsn_at_sync_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -54296,17 +54857,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -54315,27 +54876,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -54348,13 +54910,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -54594,12 +55154,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -54626,17 +55186,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -54658,17 +55218,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -54690,14 +55250,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -54709,31 +55269,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -54743,22 +55302,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -54785,14 +55346,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -54876,17 +55437,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>3</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -54895,27 +55456,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -54928,13 +55490,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -55174,12 +55734,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -55206,17 +55766,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -55238,17 +55798,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -55270,14 +55830,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -55289,31 +55849,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -55323,22 +55882,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -55365,14 +55926,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -55399,37 +55960,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_dp_block_validate_bsn_at_sync_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -55437,17 +55998,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -55456,27 +56017,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -55489,13 +56051,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -55509,7 +56069,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -55578,7 +56138,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -55735,12 +56295,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -55767,17 +56327,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -55799,17 +56359,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -55830,69 +56390,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>write</name>
<type>conduit</type>
@@ -55957,6 +56454,70 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
</interfaces>
</boundary>
<originalModuleInfo>
@@ -55984,11 +56545,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -56017,17 +56578,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>4</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -56036,27 +56597,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -56069,13 +56631,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -56089,7 +56649,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56158,7 +56718,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56315,12 +56875,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -56347,17 +56907,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -56379,17 +56939,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -56411,14 +56971,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -56430,31 +56990,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -56464,22 +57023,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -56506,14 +57067,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -56540,37 +57101,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_hdr_dat"
+ name="reg_dp_block_validate_err_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -56578,17 +57139,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>7</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -56597,27 +57158,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -56630,13 +57192,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -56650,7 +57210,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -56719,7 +57279,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -56876,12 +57436,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -56908,17 +57468,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -56940,17 +57500,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -56972,14 +57532,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -56991,31 +57551,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -57025,22 +57584,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -57067,14 +57628,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -57125,11 +57686,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -57158,17 +57719,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>7</width>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -57177,27 +57738,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -57210,13 +57772,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -57230,7 +57790,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57299,7 +57859,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -57455,6 +58015,166 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>read</name>
<type>conduit</type>
@@ -57519,199 +58239,40 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>writedata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_dp_block_validate_err_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -57719,17 +58280,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -57738,27 +58299,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -57771,13 +58333,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -57791,7 +58351,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -57860,7 +58420,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -58017,12 +58577,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -58049,17 +58609,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -58081,17 +58641,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -58113,14 +58673,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -58132,31 +58692,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -58166,22 +58725,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -58208,14 +58769,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -58266,11 +58827,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -58299,17 +58860,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -58318,27 +58879,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -58351,13 +58913,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -58371,7 +58931,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -58440,7 +59000,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -58597,12 +59157,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -58629,17 +59189,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -58661,17 +59221,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -58693,14 +59253,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -58712,31 +59272,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -58746,22 +59305,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -58788,14 +59349,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -58822,37 +59383,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_dp_selector"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -59963,37 +60524,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nof_crosslets"
+ name="reg_dp_shiftram"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -60001,17 +60562,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -60020,28 +60581,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -60054,11 +60614,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -60072,7 +60634,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60141,7 +60703,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -60297,6 +60859,70 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>reset</name>
<type>conduit</type>
@@ -60330,14 +60956,14 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -60349,30 +60975,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -60382,13 +61009,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -60457,70 +61082,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundary>
<originalModuleInfo>
@@ -60548,11 +61109,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>7</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -60581,17 +61142,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>5</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -60600,28 +61161,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -60634,11 +61194,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -60652,7 +61214,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>5</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -60721,7 +61283,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>128</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -60878,12 +61440,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -60910,17 +61472,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -60942,17 +61504,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -60974,14 +61536,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -60993,30 +61555,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -61026,24 +61589,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -61070,14 +61631,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -61104,37 +61665,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_eth10g"
+ name="reg_dp_xonoff"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -61150,7 +61711,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61214,7 +61775,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61283,7 +61844,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -61689,11 +62250,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -61730,7 +62291,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61794,7 +62355,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -61863,7 +62424,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -62245,37 +62806,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_nw_10gbe_mac"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -62291,7 +62852,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62355,7 +62916,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62424,7 +62985,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -62830,11 +63391,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -62871,7 +63432,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -62935,7 +63496,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63004,7 +63565,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63386,37 +63947,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -63432,7 +63993,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63496,7 +64057,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -63565,7 +64126,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -63971,11 +64532,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -64012,7 +64573,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64076,7 +64637,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64145,7 +64706,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -64527,37 +65088,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_info"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -64565,17 +65126,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -64584,28 +65145,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -64618,11 +65178,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -64636,7 +65198,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -64705,7 +65267,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -64862,12 +65424,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -64894,17 +65456,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -64926,17 +65488,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -64958,14 +65520,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -64977,30 +65539,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -65010,24 +65573,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -65054,14 +65615,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -65112,11 +65673,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -65145,17 +65706,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -65164,28 +65725,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -65198,11 +65758,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -65216,7 +65778,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65285,7 +65847,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -65442,12 +66004,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -65474,17 +66036,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -65506,17 +66068,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -65538,14 +66100,14 @@
</parameters>
</interface>
<interface>
- <name>write</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -65557,30 +66119,31 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>writedata</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>32</width>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -65590,24 +66153,22 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -65634,14 +66195,14 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_writedata_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -65668,37 +66229,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_ring_lane_info_xst"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -65706,17 +66267,17 @@
<boundary>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -65725,28 +66286,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -65759,11 +66319,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -65777,7 +66339,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -65846,7 +66408,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -66002,6 +66564,70 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>reset</name>
<type>conduit</type>
@@ -66035,76 +66661,75 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>address</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_write_export</name>
+ <name>coe_write_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -66162,70 +66787,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundary>
<originalModuleInfo>
@@ -66253,11 +66814,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -66286,17 +66847,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -66305,28 +66866,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>clk</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -66339,11 +66899,13 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
@@ -66357,7 +66919,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -66426,7 +66988,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -66583,12 +67145,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -66615,17 +67177,17 @@
</parameters>
</interface>
<interface>
- <name>clk</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
- <width>1</width>
+ <direction>Input</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -66647,17 +67209,17 @@
</parameters>
</interface>
<interface>
- <name>address</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -66678,6 +67240,69 @@
</parameterValueMap>
</parameters>
</interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>write</name>
<type>conduit</type>
@@ -66742,104 +67367,40 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>read</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_read_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_sdp_info"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -67950,37 +68511,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_si"
+ name="reg_hdr_dat"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -67996,7 +68557,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68060,7 +68621,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68129,7 +68690,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -68535,11 +69096,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -68576,7 +69137,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68640,7 +69201,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -68709,7 +69270,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -69091,37 +69652,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_si</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_bst"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -69137,7 +69698,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69201,7 +69762,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69270,7 +69831,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -69676,11 +70237,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>4</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -69717,7 +70278,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69781,7 +70342,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>2</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -69850,7 +70411,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>16</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -70232,37 +70793,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_sst"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -71373,37 +71934,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_enable_xst"
+ name="reg_nof_crosslets"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -71411,17 +71972,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -71430,27 +71991,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -71463,13 +72025,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -71709,12 +72269,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -71741,44 +72301,12 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_readdata_export</name>
- <role>export</role>
- <direction>Input</direction>
- <width>32</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>reset</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -71805,17 +72333,17 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>address</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -71824,28 +72352,27 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -71858,22 +72385,56 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>writedata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -71900,14 +72461,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -71991,17 +72552,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -72010,27 +72571,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -72043,13 +72605,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -72289,12 +72849,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -72321,17 +72881,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -72353,17 +72913,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -72385,14 +72945,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -72404,31 +72964,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -72438,22 +72997,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -72480,14 +73041,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -72514,37 +73075,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_bst"
+ name="reg_nw_10gbe_eth10g"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -72560,7 +73121,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -72624,7 +73185,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -72693,7 +73254,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -73099,11 +73660,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>9</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -73140,7 +73701,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -73204,7 +73765,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>7</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -73273,7 +73834,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>512</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -73655,37 +74216,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_sst"
+ name="reg_nw_10gbe_mac"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -73701,7 +74262,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -73765,7 +74326,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -73834,7 +74395,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -74240,11 +74801,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>15</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -74281,7 +74842,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -74345,7 +74906,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>13</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -74414,7 +74975,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32768</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -74796,37 +75357,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_stat_hdr_dat_xst"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -74842,7 +75403,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -74906,7 +75467,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -74975,7 +75536,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -75381,11 +75942,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -75422,7 +75983,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -75486,7 +76047,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -75555,7 +76116,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -75937,37 +76498,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10gbe_eth10g"
+ name="reg_ring_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -76046,7 +76607,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76115,7 +76676,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -76344,7 +76905,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76522,11 +77083,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -76626,7 +77187,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -76695,7 +77256,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -76924,7 +77485,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -77078,37 +77639,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_tr_10gbe_mac"
+ name="reg_ring_lane_info_bf"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -77187,7 +77748,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>15</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -77256,7 +77817,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>131072</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -77485,7 +78046,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>15</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -77663,11 +78224,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>17</value>
+ <value>4</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -77767,7 +78328,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>15</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -77836,7 +78397,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>131072</value>
+ <value>16</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -78065,7 +78626,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>15</width>
+ <width>2</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -78219,37 +78780,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wdi"
+ name="reg_ring_lane_info_xst"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -78257,17 +78818,17 @@
<boundary>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -78276,27 +78837,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -78309,13 +78871,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -78555,12 +79115,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -78587,14 +79147,110 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -78619,107 +79275,12 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>coe_reset_export</name>
- <role>export</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system</name>
- <type>clock</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>clockRate</key>
- <value>0</value>
- </entry>
- <entry>
- <key>externallyDriven</key>
- <value>false</value>
- </entry>
- <entry>
- <key>ptfSchematicName</key>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>system_reset</name>
- <type>reset</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap/>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- <value>system</value>
- </entry>
- <entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
- <interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -78746,14 +79307,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -78837,17 +79398,17 @@
<parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
<interfaces>
<interface>
- <name>address</name>
- <type>conduit</type>
+ <name>system</name>
+ <type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_address_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -78856,27 +79417,28 @@
<parameters>
<parameterValueMap>
<entry>
- <key>associatedClock</key>
+ <key>clockRate</key>
+ <value>0</value>
</entry>
<entry>
- <key>associatedReset</key>
+ <key>externallyDriven</key>
+ <value>false</value>
</entry>
<entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>ptfSchematicName</key>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>clk</name>
- <type>conduit</type>
+ <name>system_reset</name>
+ <type>reset</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_clk_export</name>
- <role>export</role>
- <direction>Output</direction>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -78889,13 +79451,11 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
+ <value>system</value>
</entry>
<entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
</entry>
</parameterValueMap>
</parameters>
@@ -79135,12 +79695,12 @@
</parameters>
</interface>
<interface>
- <name>read</name>
+ <name>reset</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_read_export</name>
+ <name>coe_reset_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -79167,17 +79727,17 @@
</parameters>
</interface>
<interface>
- <name>readdata</name>
+ <name>clk</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_readdata_export</name>
+ <name>coe_clk_export</name>
<role>export</role>
- <direction>Input</direction>
- <width>32</width>
+ <direction>Output</direction>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
@@ -79199,17 +79759,17 @@
</parameters>
</interface>
<interface>
- <name>reset</name>
+ <name>address</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_reset_export</name>
+ <name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -79231,14 +79791,14 @@
</parameters>
</interface>
<interface>
- <name>system</name>
- <type>clock</type>
+ <name>write</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_clk</name>
- <role>clk</role>
- <direction>Input</direction>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
<width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC</vhdlType>
@@ -79250,31 +79810,30 @@
<parameters>
<parameterValueMap>
<entry>
- <key>clockRate</key>
- <value>0</value>
+ <key>associatedClock</key>
</entry>
<entry>
- <key>externallyDriven</key>
- <value>false</value>
+ <key>associatedReset</key>
</entry>
<entry>
- <key>ptfSchematicName</key>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>system_reset</name>
- <type>reset</type>
+ <name>writedata</name>
+ <type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>csi_system_reset</name>
- <role>reset</role>
- <direction>Input</direction>
- <width>1</width>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
</ports>
<assignments>
@@ -79284,22 +79843,24 @@
<parameterValueMap>
<entry>
<key>associatedClock</key>
- <value>system</value>
</entry>
<entry>
- <key>synchronousEdges</key>
- <value>DEASSERT</value>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
</entry>
</parameterValueMap>
</parameters>
</interface>
<interface>
- <name>write</name>
+ <name>read</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_write_export</name>
+ <name>coe_read_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
@@ -79326,14 +79887,14 @@
</parameters>
</interface>
<interface>
- <name>writedata</name>
+ <name>readdata</name>
<type>conduit</type>
<isStart>false</isStart>
<ports>
<port>
- <name>coe_writedata_export</name>
+ <name>coe_readdata_export</name>
<role>export</role>
- <direction>Output</direction>
+ <direction>Input</direction>
<width>32</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -79360,37 +79921,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wdi</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_wg"
+ name="reg_sdp_info"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -79406,7 +79967,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -79470,7 +80031,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -79539,7 +80100,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -79945,11 +80506,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -79986,7 +80547,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -80050,7 +80611,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -80119,7 +80680,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -80501,37 +81062,37 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wg</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="rom_system_info"
+ name="reg_si"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -80547,7 +81108,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -80611,7 +81172,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -80680,7 +81241,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -81086,11 +81647,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>15</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -81127,7 +81688,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -81191,7 +81752,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>13</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -81260,7 +81821,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32768</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -81642,50 +82203,12601 @@
</interfaces>
</boundaryDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_rom_system_info</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="timer_0"
+ name="reg_stat_enable_bst"
kind="altera_generic_component"
version="1.0"
enabled="1">
<parameter name="componentDefinition"><![CDATA[<componentDefinition>
<boundary>
<interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
<interface>
<name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
<type>clock</type>
<isStart>false</isStart>
<ports>
<port>
- <name>clk</name>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x10' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>4</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>2</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>16</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_enable_sst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_enable_xst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_hdr_dat_bst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>512</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>9</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>7</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>512</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_hdr_dat_sst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_stat_hdr_dat_xst"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_tr_10gbe_eth10g"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>5</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>3</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_tr_10gbe_mac"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>15</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>131072</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>15</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>17</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>15</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>131072</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>15</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_wdi"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wdi</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wdi</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_wg"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_reg_wg</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_reg_wg</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="rom_system_info"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32768</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x8000' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>15</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>13</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>32768</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_lofar2_unb2c_sdp_station_rom_system_info</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2c_sdp_station_rom_system_info</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">../lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="timer_0"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>clk</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>clk</name>
<role>clk</role>
<direction>Input</direction>
<width>1</width>
@@ -82981,7 +96093,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c760" />
+ <parameter name="baseAddress" value="0x0010d190" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83061,7 +96173,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c6f0" />
+ <parameter name="baseAddress" value="0x0010d120" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83101,7 +96213,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c680" />
+ <parameter name="baseAddress" value="0x0010d0a0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83121,7 +96233,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c660" />
+ <parameter name="baseAddress" value="0x0010d080" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83141,7 +96253,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c758" />
+ <parameter name="baseAddress" value="0x0010d188" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83161,7 +96273,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c750" />
+ <parameter name="baseAddress" value="0x0010d180" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83181,7 +96293,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c748" />
+ <parameter name="baseAddress" value="0x0010d178" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83201,7 +96313,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c740" />
+ <parameter name="baseAddress" value="0x0010d170" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83221,7 +96333,7 @@
start="cpu_0.data_master"
end="reg_fpga_temp_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c640" />
+ <parameter name="baseAddress" value="0x0010d060" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83241,7 +96353,7 @@
start="cpu_0.data_master"
end="reg_fpga_voltage_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c580" />
+ <parameter name="baseAddress" value="0x0010cf40" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83281,7 +96393,7 @@
start="cpu_0.data_master"
end="reg_si.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c738" />
+ <parameter name="baseAddress" value="0x0010d168" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83341,7 +96453,7 @@
start="cpu_0.data_master"
end="reg_aduh_monitor.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c300" />
+ <parameter name="baseAddress" value="0x0010cb00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83381,7 +96493,7 @@
start="cpu_0.data_master"
end="reg_dp_shiftram.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c400" />
+ <parameter name="baseAddress" value="0x0010cd00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83401,7 +96513,7 @@
start="cpu_0.data_master"
end="reg_bsn_scheduler.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c730" />
+ <parameter name="baseAddress" value="0x0010d160" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83421,7 +96533,7 @@
start="cpu_0.data_master"
end="reg_bsn_source_v2.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c620" />
+ <parameter name="baseAddress" value="0x0010d040" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83441,7 +96553,7 @@
start="cpu_0.data_master"
end="reg_wg.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c200" />
+ <parameter name="baseAddress" value="0x0010ca00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83461,7 +96573,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_input.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x0010c000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83501,7 +96613,7 @@
start="cpu_0.data_master"
end="reg_dp_selector.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c728" />
+ <parameter name="baseAddress" value="0x0010d158" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83581,7 +96693,7 @@
start="cpu_0.data_master"
end="reg_bf_scale.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c6e0" />
+ <parameter name="baseAddress" value="0x0010d110" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83601,7 +96713,7 @@
start="cpu_0.data_master"
end="reg_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c000" />
+ <parameter name="baseAddress" value="0x0010c800" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83621,7 +96733,7 @@
start="cpu_0.data_master"
end="reg_dp_xonoff.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c6d0" />
+ <parameter name="baseAddress" value="0x0010d100" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83661,7 +96773,7 @@
start="cpu_0.data_master"
end="reg_sdp_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c540" />
+ <parameter name="baseAddress" value="0x0010cf00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83681,7 +96793,7 @@
start="cpu_0.data_master"
end="reg_nw_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c720" />
+ <parameter name="baseAddress" value="0x0010d150" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83721,7 +96833,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_bsn.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x0010cc80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83761,7 +96873,7 @@
start="cpu_0.data_master"
end="pio_jesd_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c718" />
+ <parameter name="baseAddress" value="0x0010d148" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83781,7 +96893,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_sst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c710" />
+ <parameter name="baseAddress" value="0x0010d140" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83821,7 +96933,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_bst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c6c0" />
+ <parameter name="baseAddress" value="0x0010d0f0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83841,7 +96953,7 @@
start="cpu_0.data_master"
end="reg_stat_hdr_dat_bst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3600" />
+ <parameter name="baseAddress" value="0x0010c600" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83861,7 +96973,7 @@
start="cpu_0.data_master"
end="reg_crosslets_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c500" />
+ <parameter name="baseAddress" value="0x0010cec0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83901,7 +97013,7 @@
start="cpu_0.data_master"
end="reg_stat_enable_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c708" />
+ <parameter name="baseAddress" value="0x0010d138" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83941,7 +97053,7 @@
start="cpu_0.data_master"
end="reg_bsn_sync_scheduler_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c4c0" />
+ <parameter name="baseAddress" value="0x0010ce80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83981,7 +97093,7 @@
start="cpu_0.data_master"
end="reg_nof_crosslets.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c700" />
+ <parameter name="baseAddress" value="0x0010d130" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -83999,9 +97111,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_align_v2.mem">
+ end="reg_bsn_align_v2_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0080" />
+ <parameter name="baseAddress" value="0x0010cc00" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84019,9 +97131,9 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_monitor_v2_bsn_align_v2_output.mem">
+ end="reg_bsn_monitor_v2_aligned_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c600" />
+ <parameter name="baseAddress" value="0x0010d020" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84041,7 +97153,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_xst_offload.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c5e0" />
+ <parameter name="baseAddress" value="0x0010d000" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84081,7 +97193,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_v2_ring_rx_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x0010c400" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84121,7 +97233,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_err_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c480" />
+ <parameter name="baseAddress" value="0x0010ce40" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84141,7 +97253,7 @@
start="cpu_0.data_master"
end="reg_dp_block_validate_bsn_at_sync_xst.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c6b0" />
+ <parameter name="baseAddress" value="0x0010d0e0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84161,7 +97273,7 @@
start="cpu_0.data_master"
end="reg_ring_info.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c6a0" />
+ <parameter name="baseAddress" value="0x0010d0d0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84181,7 +97293,7 @@
start="cpu_0.data_master"
end="reg_tr_10gbe_eth10g.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0010c5c0" />
+ <parameter name="baseAddress" value="0x0010cfe0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84219,7 +97331,7 @@
kind="avalon"
version="19.4"
start="cpu_0.data_master"
- end="reg_bsn_monitor_v2_bsn_align_v2_input.mem">
+ end="reg_bsn_monitor_v2_rx_align_xsub.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
@@ -84235,6 +97347,226 @@
<parameter name="qsys_mm.syncResets" value="FALSE" />
<parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
</connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_sst_offload.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0010cfc0" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_bst_offload.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0010ce00" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_beamlet_output.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0010cdc0" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_align_v2_bf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0010cf80" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_rx_align_bf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3080" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_aligned_bf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3040" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_ring_lane_info_bf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3010" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_ring_rx_bf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3400" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_bsn_monitor_v2_ring_tx_bf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0400" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_dp_block_validate_err_bf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="19.4"
+ start="cpu_0.data_master"
+ end="reg_dp_block_validate_bsn_at_sync_bf.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3020" />
+ <parameter name="defaultConnection" value="false" />
+ <parameter name="domainAlias" value="" />
+ <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+ <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+ <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+ <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+ <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+ <parameter name="qsys_mm.maxAdditionalLatency" value="0" />
+ <parameter name="qsys_mm.syncResets" value="FALSE" />
+ <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
<connection
kind="avalon"
version="19.4"
@@ -84261,7 +97593,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3040" />
+ <parameter name="baseAddress" value="0x0010cd80" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84321,7 +97653,7 @@
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3010" />
+ <parameter name="baseAddress" value="0x0010d0c0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84341,7 +97673,7 @@
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3020" />
+ <parameter name="baseAddress" value="0x0010cfa0" />
<parameter name="defaultConnection" value="false" />
<parameter name="domainAlias" value="" />
<parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -84606,12 +97938,12 @@
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_align_v2.system" />
+ end="reg_bsn_align_v2_xsub.system" />
<connection
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_monitor_v2_bsn_align_v2_output.system" />
+ end="reg_bsn_monitor_v2_aligned_xsub.system" />
<connection
kind="clock"
version="19.4"
@@ -84661,7 +97993,62 @@
kind="clock"
version="19.4"
start="clk_0.clk"
- end="reg_bsn_monitor_v2_bsn_align_v2_input.system" />
+ end="reg_bsn_monitor_v2_rx_align_xsub.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_sst_offload.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_bst_offload.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_beamlet_output.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_align_v2_bf.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_rx_align_bf.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_aligned_bf.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_ring_lane_info_bf.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_ring_rx_bf.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_bsn_monitor_v2_ring_tx_bf.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_dp_block_validate_err_bf.system" />
+ <connection
+ kind="clock"
+ version="19.4"
+ start="clk_0.clk"
+ end="reg_dp_block_validate_bsn_at_sync_bf.system" />
<connection
kind="interrupt"
version="19.4"
@@ -84954,12 +98341,12 @@
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_align_v2.system_reset" />
+ end="reg_bsn_align_v2_xsub.system_reset" />
<connection
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_monitor_v2_bsn_align_v2_output.system_reset" />
+ end="reg_bsn_monitor_v2_aligned_xsub.system_reset" />
<connection
kind="reset"
version="19.4"
@@ -85009,7 +98396,62 @@
kind="reset"
version="19.4"
start="clk_0.clk_reset"
- end="reg_bsn_monitor_v2_bsn_align_v2_input.system_reset" />
+ end="reg_bsn_monitor_v2_rx_align_xsub.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_sst_offload.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_bst_offload.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_beamlet_output.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_align_v2_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_rx_align_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_aligned_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_ring_lane_info_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_ring_rx_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_bsn_monitor_v2_ring_tx_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_dp_block_validate_err_bf.system_reset" />
+ <connection
+ kind="reset"
+ version="19.4"
+ start="clk_0.clk_reset"
+ end="reg_dp_block_validate_bsn_at_sync_bf.system_reset" />
<connection
kind="reset"
version="19.4"
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
index 0e2e17e2c716a3e378cfb529a1039f70b052cacb..1b2814376d6cc37507ad76435846f6dbf15fbdd2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
@@ -32,7 +32,7 @@ quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2c_sdp_station_pins.tcl
+ lofar2_unb2c_sdp_station_adc_pins.tcl
quartus_vhdl_files =
@@ -65,19 +65,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
@@ -95,6 +105,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b689b7d674278bcc88a9dabee9475a57fe4de9a9
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl
@@ -0,0 +1,24 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
index 2dbc42a190d69aae9720163ca219e905cd8cce2a..685ae42cc21c7ce7d31d4ea4a6ff7b60977d51c9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
@@ -9,10 +9,11 @@ hdl_lib_technology = ip_arria10_e2sg
test_bench_files =
tb_lofar2_unb2c_sdp_station_bf.vhd
+ tb_tb_lofar2_unb2c_sdp_station_bf.vhd
tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
regression_test_vhdl =
- tb_lofar2_unb2c_sdp_station_bf.vhd
+ tb_tb_lofar2_unb2c_sdp_station_bf.vhd
tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
[modelsim_project_file]
@@ -40,7 +41,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2c_sdp_station_pins.tcl
+ lofar2_unb2c_sdp_station_bf_pins.tcl
quartus_vhdl_files =
@@ -73,19 +74,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
@@ -103,6 +114,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
@@ -120,3 +132,4 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..64f05f663474c04abcfb73051fdc09cea1cf843c
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl
@@ -0,0 +1,25 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index 257123269176fbca6ff5a72b651b5c6aa11f0d29..c641685358e7fcb63c7f01ad40ca2c14c3c4dc69 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -21,37 +21,98 @@
-------------------------------------------------------------------------------
--
-- Author: R. van der Walle (original), E. Kooistra (updates)
--- Purpose: Self-checking testbench for simulating lofar2_unb2c_sdp_station_bf using WG data.
+-- Purpose: Self-checking testbench for simulating lofar2_unb2c_sdp_station_bf
+-- using WG data.
--
-- Description:
+-- This tb is a balance between verification coverage and keeping it simple:
+-- - Use only one signal input (g_sp). Put same remnant WG signal on the
+-- other signal inputs.
+-- - Use different BF weight for the two beamlet polarizations (g_bf_x_gain,
+-- g_bf_x_phase and g_bf_y_phase, g_bf_y_phase) of signal input g_sp.
+-- Using different BF weights for the N_pol_bf = 2 BF polarizations allows
+-- verification of the dual polarization beamlet.
+-- - Use same remnant BF weight for the other S_pn - 1 = 11 signal inputs.
+-- The remnant signal inputs and BF weights allow verifying the BF sum if
+-- they are not 0. Using the same settings for all remnant SP simplyfies
+-- the tb, while still testing the BF sum.
+-- - Select one beamlet for the subband (g_beamlet). Selecting one beamlet
+-- other than the default beamlet for the subband is sufficient to verify
+-- the beamlet subband select.
+-- - Use same stimuli for both beamsets.
+--
-- MM control actions:
--
--- 1) Enable calc mode for WG on signal input g_sp via reg_diag_wg with:
--- g_subband = 102 --> WG freq = 19.921875MHz
--- g_ampl = 1.0 --> WG ampl = 2**13
+-- 1) Enable calc mode for WG on signal input (si) g_sp via reg_diag_wg with:
+-- g_subband = 102 --> 102 * f_sub = 19.921875 MHz
+-- g_sp_ampl = 1.0 --> 1.0 yield WG ampl = 2**13
+-- g_sp_phase --> subband phase
+-- Use g_sp_remnant_ampl = 0.1 and g_sp_remnant_phase = 0.0 for the other
+-- S_pn-1 = 11 signal inputs, than g_sp, that are not used in the BF.
--
--- 2) Read current BSN from reg_bsn_scheduler_wg and write reg_bsn_scheduler_wg
--- to trigger start of WG at BSN.
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write
+-- reg_bsn_scheduler_wg to trigger start of WG at BSN.
--
--- 3) Read and verify subband statistics (SST)
+-- 3) Read and verify subband statistics (SST) for g_sp. This also reads the
+-- SST of the other signal input of the WPFB that processes g_sp.
+--
+-- 4) Select subband g_subband for beamlets in g_beamlet
+--
+-- 5) Apply BF weight to g_beamlet X beam and Y beam, so for example if g_sp
+-- = 3, then w_x3 = g_bf_x_gain/phase and w_y3 = = g_bf_x_gain/phase. The
+-- other BF weights are 0.
--
--- 4) Select subband g_subband for beamlet g_beamlet
+-- WG BF BF
+-- si weight weight
+-- X Y
+-- 0 -----> * w_x0 ..+
+-- \--------------|----> * w_y0 ..+
+-- 1 -----> * w_x1 ..+ |
+-- \--------------|----> * w_y1 ..+
+-- 2 -----> * w_x2 ..+ |
+-- \--------------|----> * w_y2 ..+
+-- 3 -----> * w_x3 ..+ |
+-- \--------------|----> * w_y3 ..+
+-- 4 -----> * w_x4 ..+ |
+-- \--------------|----> * w_y4 ..+
+-- 5 -----> * w_x5 ..+ |
+-- \--------------|----> * w_y5 ..+
+-- 6 -----> * w_x6 ..+ |
+-- \--------------|----> * w_y6 ..+
+-- 7 -----> * w_x7 ..+ |
+-- \--------------|----> * w_y7 ..+
+-- 8 -----> * w_x8 ..+ |
+-- \--------------|----> * w_y8 ..+
+-- 9 -----> * w_x9 ..+ |
+-- \--------------|----> * w_y9 ..+
+-- 10 -----> * w_x10 ..+ |
+-- \--------------|----> * w_y10 ..+
+-- 11 -----> * w_x11 ..+ |
+-- \--------------|----> * w_y11 ..+
+-- | |
+-- \----------------|---> beamlet_x
+-- \--> beamlet_y
--
--- 5) Apply BF weight (g_bf_gain, g_bf_phase) to g_beamlet X beam and Y beam
--
-- 6) Read and verify beamlet statistics (BST)
--- View sp_subband_sst in Wave window
--- View pol_beamlet_bst in Wave window
+-- View sp_sst in Wave window
+-- View bst_x_arr, bst_y_arr in Wave window
--
-- 7) Verify 10GbE output header and output payload for g_beamlet.
+-- View rx_beamlet_sosi
+-- View rx_beamlet_cnt (in analog format)
+--
+-- Remark:
+-- . The c_wg_phase_offset and c_subband_phase_offset are used to tune the WG
+-- phase reference to 0.0 degrees at the start (sop)
--
-- Usage:
-- > as 7 # default
-- > as 12 # for detailed debugging
-- # Manually add missing signal
-- > add wave -position insertpoint \
--- sim:/tb_lofar2_unb2c_sdp_station_bf/sp_subband_ssts_arr2 \
--- sim:/tb_lofar2_unb2c_sdp_station_bf/pol_beamlet_bsts_arr2
+-- sim:/tb_lofar2_unb2c_sdp_station_bf/sp_ssts_arr2 \
+-- sim:/tb_lofar2_unb2c_sdp_station_bf/bsts_arr2
-- > run -a
-- Takes about 40 m when g_read_all_* = FALSE
-- Takes about 1h 5 m when g_read_all_* = TRUE
@@ -79,32 +140,41 @@ USE tech_pll_lib.tech_pll_component_pkg.ALL;
ENTITY tb_lofar2_unb2c_sdp_station_bf IS
GENERIC (
- g_sp : NATURAL := 0; -- WG signal path index in range(S_pn = 12)
- g_wg_ampl : REAL := 1.0; -- WG normalized amplitude
- g_subband : NATURAL := 102; -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
- g_beamlet : NATURAL := 10; -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
- g_beamlet_scale : REAL := 1.0 / 2.0**9; -- g_beamlet output scale factor
- g_bf_gain : REAL := 1.0; -- g_beamlet BF weight normalized gain
- g_bf_phase : REAL := 30.0; -- g_beamlet BF weight phase rotation in degrees
- g_read_all_SST : BOOLEAN := FALSE; -- when FALSE only read SST for g_subband, to save sim time
- g_read_all_BST : BOOLEAN := FALSE -- when FALSE only read BST for g_beamlet, to save sim time
+ g_sp : NATURAL := 3; -- WG signal path (SP) index in range(S_pn = 12)
+ g_sp_ampl : REAL := 0.5; -- WG normalized amplitude
+ g_sp_phase : REAL := -110.0; -- WG phase in degrees = subband phase
+ g_sp_remnant_ampl : REAL := 0.1; -- WG normalized amplitude for remnant sp
+ g_sp_remnant_phase : REAL := 15.0; -- WG phase in degrees for remnant sp
+ g_subband : NATURAL := 102; -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_beamlet : NATURAL := 10; -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet_scale : REAL := 1.0 / 2.0**9; -- g_beamlet output scale factor
+ g_bf_x_gain : REAL := 0.7; -- g_beamlet X BF weight normalized gain for g_sp
+ g_bf_y_gain : REAL := 0.6; -- g_beamlet Y BF weight normalized gain for g_sp
+ g_bf_x_phase : REAL := 30.0; -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_y_phase : REAL := 40.0; -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_x_gain : REAL := 0.05; -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain : REAL := 0.04; -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_x_phase : REAL := 170.0; -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_y_phase : REAL := -135.0; -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_read_all_SST : BOOLEAN := FALSE; -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_BST : BOOLEAN := FALSE -- when FALSE only read BST for g_beamlet, to save sim time
);
END tb_lofar2_unb2c_sdp_station_bf;
ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
- CONSTANT c_sim : BOOLEAN := TRUE;
- CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
- CONSTANT c_node_nr : NATURAL := 0;
- CONSTANT c_gn_index : NATURAL := c_unb_nr * 4 + c_node_nr; -- this node GN
- CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_gn_index : NATURAL := c_unb_nr * 4 + c_node_nr; -- this node GN
+ CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_gn_index, 8);
- CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
- CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0);
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_gn_index, 8);
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0);
- CONSTANT c_mac_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr, 8);
- CONSTANT c_ip_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr+1, 8); -- +1 to avoid IP = *.*.*.0
+ CONSTANT c_mac_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr, 8);
+ CONSTANT c_ip_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr, 8) & TO_UVEC(c_node_nr+1, 8); -- +1 to avoid IP = *.*.*.0
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
@@ -124,6 +194,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
CONSTANT c_stat_lo_factor : REAL := 1.0 - c_stat_percentage; -- lower boundary
CONSTANT c_stat_hi_factor : REAL := 1.0 + c_stat_percentage; -- higher boundary
+ CONSTANT c_nof_beamlets_per_data : NATURAL := 2; -- 2 dual pol beamlets (= XY, XY) per 64b data word
+
CONSTANT c_beamlet_output_delta : INTEGER := 2; -- +-delta margin
-- header fields
@@ -155,74 +227,128 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
-- .ampl
CONSTANT c_wg_ampl_full_scale : NATURAL := 2**(c_sdp_W_adc-1); -- full scale (FS) of WG, will just cause clipping of +FS to +FS-1
CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / REAL(c_wg_ampl_full_scale); -- amplitude in number of LSbit resolution steps
- CONSTANT c_wg_ampl : NATURAL := NATURAL(g_wg_ampl * REAL(c_wg_ampl_full_scale)); -- in number of lsb
+ CONSTANT c_wg_ampl : NATURAL := NATURAL(g_sp_ampl * REAL(c_wg_ampl_full_scale)); -- in number of lsb
+ CONSTANT c_wg_remnant_ampl : NATURAL := NATURAL(g_sp_remnant_ampl * REAL(c_wg_ampl_full_scale)); -- in number of lsb
CONSTANT c_exp_sp_power : REAL := REAL(c_wg_ampl**2) / 2.0;
CONSTANT c_exp_sp_ast : REAL := c_exp_sp_power * REAL(c_nof_clk_per_sync);
-- . phase
- CONSTANT c_subband_phase : REAL := 0.0; -- wanted subband phase in degrees = WG phase at sop
CONSTANT c_subband_freq : REAL := REAL(g_subband) / REAL(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
CONSTANT c_wg_latency : INTEGER := c_diag_wg_latency - 0; -- -0 to account for BSN scheduler start trigger latency
CONSTANT c_wg_phase_offset : REAL := 360.0 * REAL(c_wg_latency) * c_subband_freq; -- c_diag_wg_latency is in dp_clk cycles
- CONSTANT c_wg_phase : REAL := c_subband_phase + c_wg_phase_offset; -- WG phase in degrees
+ CONSTANT c_wg_phase : REAL := g_sp_phase + c_wg_phase_offset; -- WG phase in degrees
+ CONSTANT c_wg_remnant_phase : REAL := g_sp_remnant_phase + c_wg_phase_offset; -- WG phase in degrees
-- . freq
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
-- WPFB
- CONSTANT c_pol_index : NATURAL := g_sp MOD c_sdp_Q_fft;
- CONSTANT c_pfb_index : NATURAL := g_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
- CONSTANT c_subband_phase_offset : REAL := -90.0; -- WG with zero phase sinues yields subband with -90 degrees phase (negative Im, zero Re)
- CONSTANT c_subband_weight_gain : REAL := 1.0; -- use default unit subband weights
- CONSTANT c_subband_weight_phase : REAL := 0.0; -- use default unit subband weights
- CONSTANT c_exp_subband_sp_ampl_ratio : REAL := 7.96; -- ~= 8 for unit FIR DC gain, depends on internal WPFB quantization and FIR coefficients
- CONSTANT c_exp_subband_ampl : REAL := REAL(c_wg_ampl) * c_exp_subband_sp_ampl_ratio * c_subband_weight_gain;
- CONSTANT c_exp_subband_power : REAL := c_exp_subband_ampl**2.0; -- complex, so no divide by 2
- CONSTANT c_exp_subband_sst : REAL := c_exp_subband_power * REAL(c_nof_block_per_sync);
-
- TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
+ CONSTANT c_pol_index : NATURAL := g_sp MOD c_sdp_Q_fft;
+ CONSTANT c_pfb_index : NATURAL := g_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ CONSTANT c_subband_phase_offset : REAL := -90.0; -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
+ CONSTANT c_subband_weight_gain : REAL := 1.0; -- use default unit subband weights
+ CONSTANT c_subband_weight_phase : REAL := 0.0; -- use default unit subband weights
+ CONSTANT c_exp_subband_phase : REAL := g_sp_phase + c_subband_phase_offset + c_subband_weight_phase;
+ CONSTANT c_exp_subband_ampl : REAL := REAL(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
+ CONSTANT c_exp_subband_power : REAL := c_exp_subband_ampl**2.0; -- complex signal ampl, so no divide by 2
+ CONSTANT c_exp_subband_sst : REAL := c_exp_subband_power * REAL(c_nof_block_per_sync);
+
+ CONSTANT c_exp_remnant_subband_phase : REAL := g_sp_remnant_phase + c_subband_phase_offset + c_subband_weight_phase;
+ CONSTANT c_exp_remnant_subband_ampl : REAL := REAL(c_wg_remnant_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
+
+ TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
TYPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_sub-1); -- 512
TYPE t_slv_64_beamlets_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_beamlets_sdp-1); -- 2*488 = 976
- -- BF
+ -- BF X-pol and Y-pol
-- . select
- CONSTANT c_exp_beamlet_index : NATURAL := g_beamlet * c_sdp_N_pol_bf; -- in beamset 0
+ CONSTANT c_exp_beamlet_x_index : NATURAL := g_beamlet * c_sdp_N_pol_bf; -- X index in beamset 0
+ CONSTANT c_exp_beamlet_y_index : NATURAL := g_beamlet * c_sdp_N_pol_bf + 1; -- Y index in beamset 0
-- . Beamlet weights for selected g_sp
- CONSTANT c_bf_weight_re : INTEGER := INTEGER(g_bf_gain * REAL(c_sdp_unit_bf_weight) * COS(g_bf_phase * MATH_2_PI / 360.0));
- CONSTANT c_bf_weight_im : INTEGER := INTEGER(g_bf_gain * REAL(c_sdp_unit_bf_weight) * SIN(g_bf_phase * MATH_2_PI / 360.0));
+ CONSTANT c_bf_x_weight_re : INTEGER := INTEGER(COMPLEX_RE(g_bf_x_gain * REAL(c_sdp_unit_bf_weight), g_bf_x_phase));
+ CONSTANT c_bf_x_weight_im : INTEGER := INTEGER(COMPLEX_IM(g_bf_x_gain * REAL(c_sdp_unit_bf_weight), g_bf_x_phase));
+ CONSTANT c_bf_y_weight_re : INTEGER := INTEGER(COMPLEX_RE(g_bf_y_gain * REAL(c_sdp_unit_bf_weight), g_bf_y_phase));
+ CONSTANT c_bf_y_weight_im : INTEGER := INTEGER(COMPLEX_IM(g_bf_y_gain * REAL(c_sdp_unit_bf_weight), g_bf_y_phase));
+ CONSTANT c_bf_remnant_x_weight_re : INTEGER := INTEGER(COMPLEX_RE(g_bf_remnant_x_gain * REAL(c_sdp_unit_bf_weight), g_bf_remnant_x_phase));
+ CONSTANT c_bf_remnant_x_weight_im : INTEGER := INTEGER(COMPLEX_IM(g_bf_remnant_x_gain * REAL(c_sdp_unit_bf_weight), g_bf_remnant_x_phase));
+ CONSTANT c_bf_remnant_y_weight_re : INTEGER := INTEGER(COMPLEX_RE(g_bf_remnant_y_gain * REAL(c_sdp_unit_bf_weight), g_bf_remnant_y_phase));
+ CONSTANT c_bf_remnant_y_weight_im : INTEGER := INTEGER(COMPLEX_IM(g_bf_remnant_y_gain * REAL(c_sdp_unit_bf_weight), g_bf_remnant_y_phase));
+
+ -- Model the SDP beamformer for one g_sp and S_pn-1 = 11 remnant signal inputs
+ FUNCTION bf_calculate_expected_beamlet(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
+ rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : REAL) RETURN t_real_arr IS -- 0:3 = ampl, phase, re, im
+ CONSTANT c_nof_rem : REAL := REAL(c_sdp_S_pn - 1); -- BF for one g_sp and 11 remnant signal inputs
+ VARIABLE v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : REAL;
+ VARIABLE v_rem_ampl, v_rem_phase, v_rem_re, v_rem_im : REAL;
+ VARIABLE v_sum_ampl, v_sum_phase, v_sum_re, v_sum_im : REAL;
+ VARIABLE v_tuple : t_real_arr(0 TO 3);
+ BEGIN
+ v_sp_ampl := sp_subband_ampl * sp_bf_gain;
+ v_sp_phase := sp_subband_phase + sp_bf_phase;
+ v_sp_re := COMPLEX_RE(v_sp_ampl, v_sp_phase);
+ v_sp_im := COMPLEX_IM(v_sp_ampl, v_sp_phase);
+ v_rem_ampl := rem_subband_ampl * rem_bf_gain;
+ v_rem_phase := rem_subband_phase + rem_bf_phase;
+ v_rem_re := COMPLEX_RE(v_rem_ampl, v_rem_phase);
+ v_rem_im := COMPLEX_IM(v_rem_ampl, v_rem_phase);
+ v_sum_re := v_sp_re + c_nof_rem * v_rem_re; -- BF sum re
+ v_sum_im := v_sp_im + c_nof_rem * v_rem_im; -- BF sum im
+ v_sum_ampl := COMPLEX_RADIUS(v_sum_re, v_sum_im);
+ v_sum_phase := COMPLEX_PHASE(v_sum_re, v_sum_im);
+ v_tuple := (0 => v_sum_ampl, 1 => v_sum_phase, 2 => v_sum_re, 3 => v_sum_im);
+ RETURN v_tuple;
+ END;
+
-- . Beamlet internal
- CONSTANT c_exp_beamlet_ampl : REAL := c_exp_subband_ampl * g_bf_gain;
- CONSTANT c_exp_beamlet_phase : REAL := c_subband_phase_offset + c_subband_weight_phase + g_bf_phase;
- CONSTANT c_exp_beamlet_re : REAL := c_exp_beamlet_ampl * COS(c_exp_beamlet_phase * MATH_2_PI / 360.0);
- CONSTANT c_exp_beamlet_im : REAL := c_exp_beamlet_ampl * SIN(c_exp_beamlet_phase * MATH_2_PI / 360.0);
+ CONSTANT c_exp_beamlet_x_tuple : t_real_arr(0 TO 3) := bf_calculate_expected_beamlet(
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase);
+ CONSTANT c_exp_beamlet_x_ampl : REAL := c_exp_beamlet_x_tuple(0);
+ CONSTANT c_exp_beamlet_x_phase : REAL := c_exp_beamlet_x_tuple(1);
+ CONSTANT c_exp_beamlet_x_re : REAL := c_exp_beamlet_x_tuple(2);
+ CONSTANT c_exp_beamlet_x_im : REAL := c_exp_beamlet_x_tuple(3);
+
+ CONSTANT c_exp_beamlet_y_tuple : t_real_arr(0 TO 3) := bf_calculate_expected_beamlet(
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase);
+ CONSTANT c_exp_beamlet_y_ampl : REAL := c_exp_beamlet_y_tuple(0);
+ CONSTANT c_exp_beamlet_y_phase : REAL := c_exp_beamlet_y_tuple(1);
+ CONSTANT c_exp_beamlet_y_re : REAL := c_exp_beamlet_y_tuple(2);
+ CONSTANT c_exp_beamlet_y_im : REAL := c_exp_beamlet_y_tuple(3);
-- . BST
- CONSTANT c_exp_beamlet_power : REAL := c_exp_beamlet_ampl**2.0; -- complex, so no divide by 2
- CONSTANT c_exp_beamlet_bst : REAL := c_exp_subband_sst * g_bf_gain**2.0; -- = c_exp_beamlet_power * REAL(c_nof_block_per_sync)
+ CONSTANT c_exp_beamlet_x_power : REAL := c_exp_beamlet_x_ampl**2.0; -- complex signal ampl, so no divide by 2
+ CONSTANT c_exp_beamlet_x_bst : REAL := c_exp_beamlet_x_power * REAL(c_nof_block_per_sync);
+ CONSTANT c_exp_beamlet_y_power : REAL := c_exp_beamlet_y_ampl**2.0; -- complex signal ampl, so no divide by 2
+ CONSTANT c_exp_beamlet_y_bst : REAL := c_exp_beamlet_y_power * REAL(c_nof_block_per_sync);
-- . Beamlet output
- CONSTANT c_exp_beamlet_output_ampl : REAL := c_exp_beamlet_ampl * g_beamlet_scale;
- CONSTANT c_exp_beamlet_output_phase : REAL := c_exp_beamlet_phase;
- CONSTANT c_exp_beamlet_output_re : REAL := c_exp_beamlet_re * g_beamlet_scale;
- CONSTANT c_exp_beamlet_output_im : REAL := c_exp_beamlet_im * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_x_output_ampl : REAL := c_exp_beamlet_x_ampl * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_x_output_phase : REAL := c_exp_beamlet_x_phase;
+ CONSTANT c_exp_beamlet_x_output_re : REAL := c_exp_beamlet_x_re * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_x_output_im : REAL := c_exp_beamlet_x_im * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_y_output_ampl : REAL := c_exp_beamlet_y_ampl * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_y_output_phase : REAL := c_exp_beamlet_y_phase;
+ CONSTANT c_exp_beamlet_y_output_re : REAL := c_exp_beamlet_y_re * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_y_output_im : REAL := c_exp_beamlet_y_im * g_beamlet_scale;
-- MM
-- . Address widths of a single MM instance
-- . c_sdp_S_pn = 12 instances
- CONSTANT c_addr_w_reg_diag_wg : NATURAL := 2;
+ CONSTANT c_addr_w_reg_diag_wg : NATURAL := 2;
-- . c_sdp_N_beamsets = 2 instances
- CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
- CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
- CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
- CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol_bf*c_stat_data_sz);
+ CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
+ CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+ CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
+ CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol_bf*c_stat_data_sz);
-- . Address spans of a single MM instance
-- . c_sdp_S_pn = 12 instances
- CONSTANT c_mm_span_reg_diag_wg : NATURAL := 2**c_addr_w_reg_diag_wg;
+ CONSTANT c_mm_span_reg_diag_wg : NATURAL := 2**c_addr_w_reg_diag_wg;
-- . c_sdp_N_beamsets = 2 instances
- CONSTANT c_mm_span_ram_ss_ss_wide : NATURAL := 2**c_addr_w_ram_ss_ss_wide;
- CONSTANT c_mm_span_ram_bf_weights : NATURAL := 2**c_addr_w_ram_bf_weights;
- CONSTANT c_mm_span_reg_bf_scale : NATURAL := 2**c_addr_w_reg_bf_scale;
- CONSTANT c_mm_span_reg_hdr_dat : NATURAL := 2**c_addr_w_reg_hdr_dat;
- CONSTANT c_mm_span_reg_dp_xonoff : NATURAL := 2**c_addr_w_reg_dp_xonoff;
- CONSTANT c_mm_span_ram_st_bst : NATURAL := 2**c_addr_w_ram_st_bst;
+ CONSTANT c_mm_span_ram_ss_ss_wide : NATURAL := 2**c_addr_w_ram_ss_ss_wide;
+ CONSTANT c_mm_span_ram_bf_weights : NATURAL := 2**c_addr_w_ram_bf_weights;
+ CONSTANT c_mm_span_reg_bf_scale : NATURAL := 2**c_addr_w_reg_bf_scale;
+ CONSTANT c_mm_span_reg_hdr_dat : NATURAL := 2**c_addr_w_reg_hdr_dat;
+ CONSTANT c_mm_span_reg_dp_xonoff : NATURAL := 2**c_addr_w_reg_dp_xonoff;
+ CONSTANT c_mm_span_ram_st_bst : NATURAL := 2**c_addr_w_ram_st_bst;
CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
@@ -262,16 +388,16 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
SIGNAL rd_cep_udp_dst_port : STD_LOGIC_VECTOR(15 DOWNTO 0);
-- WG
- SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
-- FSUB
- -- . Read sp_subband_ssts_arr2 = SST for one WPFB unit that processes g_sp
- SIGNAL sp_subband_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol-1 DOWNTO 0); -- [pol][sub], for X,Y pair of A, B
- SIGNAL sp_subband_sst : REAL := 0.0;
- SIGNAL stat_data : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);
+ -- . Read sp_ssts_arr2 = SST for one WPFB unit that processes g_sp
+ SIGNAL sp_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol-1 DOWNTO 0); -- [pol][sub], for X,Y pair of A, B
+ SIGNAL sp_sst : REAL := 0.0;
+ SIGNAL stat_data : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);
-- . Selector
- SIGNAL sst_offload_weighted_subbands : STD_LOGIC;
+ SIGNAL sst_weighted_subbands_flag : STD_LOGIC;
-- . Subband equalizer
SIGNAL sp_subband_weight_re : INTEGER := 0;
@@ -280,47 +406,59 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf IS
SIGNAL sp_subband_weight_phase : REAL := 0.0;
-- BF
- SIGNAL sp_subband_select : NATURAL := 0;
- SIGNAL sp_subband_select_arr : t_natural_arr(0 TO c_sdp_S_sub_bf * c_sdp_N_pol-1) := (OTHERS => 0); -- Q_fft = N_pol = 2
- SIGNAL sp_bf_weights_re_arr : t_integer_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0);
- SIGNAL sp_bf_weights_im_arr : t_integer_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0);
- SIGNAL sp_bf_weights_gain_arr : t_real_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0.0);
- SIGNAL sp_bf_weights_phase_arr : t_real_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0.0);
-
- SIGNAL pol_beamlet_bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf-1 DOWNTO 0); -- [pol_bf][blet]
- SIGNAL pol_beamlet_bst_X_arr : t_real_arr(0 TO c_sdp_N_beamsets-1) := (OTHERS => 0.0); -- [bset]
- SIGNAL pol_beamlet_bst_Y_arr : t_real_arr(0 TO c_sdp_N_beamsets-1) := (OTHERS => 0.0); -- [bset]
-
- -- 10GbE
- SIGNAL rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
- SIGNAL rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
- SIGNAL rx_beamlet_cnt : NATURAL;
- SIGNAL rx_beamlet_valid : STD_LOGIC;
+ -- . beamlet subband selection
+ SIGNAL sp_subband_select : NATURAL := 0;
+ SIGNAL sp_subband_select_arr : t_natural_arr(0 TO c_sdp_S_sub_bf * c_sdp_N_pol-1) := (OTHERS => 0); -- Q_fft = N_pol = 2
+
+ -- . beamlet X-pol
+ SIGNAL sp_bf_x_weights_re_arr : t_integer_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0);
+ SIGNAL sp_bf_x_weights_im_arr : t_integer_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0);
+ SIGNAL sp_bf_x_weights_gain_arr : t_real_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0.0);
+ SIGNAL sp_bf_x_weights_phase_arr : t_real_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0.0);
+ -- . beamlet Y-pol
+ SIGNAL sp_bf_y_weights_re_arr : t_integer_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0);
+ SIGNAL sp_bf_y_weights_im_arr : t_integer_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0);
+ SIGNAL sp_bf_y_weights_gain_arr : t_real_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0.0);
+ SIGNAL sp_bf_y_weights_phase_arr : t_real_arr(0 TO c_sdp_S_pn-1) := (OTHERS => 0.0);
- SIGNAL rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
- SIGNAL rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
+ -- . BST
+ SIGNAL bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf-1 DOWNTO 0); -- [pol_bf][blet]
+ SIGNAL bst_x_arr : t_real_arr(0 TO c_sdp_N_beamsets-1) := (OTHERS => 0.0); -- [bset] for BF X pol
+ SIGNAL bst_y_arr : t_real_arr(0 TO c_sdp_N_beamsets-1) := (OTHERS => 0.0); -- [bset] for BF Y pol
+ -- CEP model
+ -- . 10GbE
SIGNAL tr_10GbE_src_out : t_dp_sosi;
SIGNAL tr_10GbE_src_in : t_dp_siso;
SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
- -- dp_offload_rx
- SIGNAL offload_rx_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL offload_rx_hdr_dat_miso : t_mem_miso;
+ -- . dp_offload_rx
+ SIGNAL rx_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL rx_hdr_dat_miso : t_mem_miso;
+
+ SIGNAL rx_hdr_fields_out : STD_LOGIC_VECTOR(1023 DOWNTO 0);
+ SIGNAL rx_hdr_fields_raw : STD_LOGIC_VECTOR(1023 DOWNTO 0) := (OTHERS => '0');
+
+ -- Beamlets packets header
+ SIGNAL rx_sdp_cep_header : t_sdp_cep_header;
+ SIGNAL exp_sdp_cep_header : t_sdp_cep_header;
+ SIGNAL exp_dp_bsn : NATURAL;
+
+ -- Beamlets packets data
+ SIGNAL rx_beamlet_data : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0); -- 64 bit
+ SIGNAL rx_beamlet_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL rx_beamlet_sop_cnt : NATURAL := 0;
+ SIGNAL rx_beamlet_eop_cnt : NATURAL := 0;
- SIGNAL test_offload_en : STD_LOGIC := '0';
- SIGNAL test_offload_data : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0); -- 64 bit
- SIGNAL test_offload_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL test_offload_sop_cnt : NATURAL := 0;
- SIGNAL test_offload_eop_cnt : NATURAL := 0;
+ SIGNAL rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
+ SIGNAL rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
+ SIGNAL rx_beamlet_cnt : NATURAL;
+ SIGNAL rx_beamlet_valid : STD_LOGIC;
- SIGNAL rx_hdr_fields_out : STD_LOGIC_VECTOR(1023 DOWNTO 0);
- SIGNAL rx_hdr_fields_raw : STD_LOGIC_VECTOR(1023 DOWNTO 0) := (OTHERS => '0');
- SIGNAL rx_sdp_cep_header : t_sdp_cep_header;
- SIGNAL exp_sdp_cep_header : t_sdp_cep_header;
- SIGNAL exp_dp_bsn : NATURAL;
+ SIGNAL rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
+ SIGNAL rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
@@ -416,6 +554,9 @@ BEGIN
JESD204B_SYNC_N => jesd204b_sync_n
);
+ ------------------------------------------------------------------------------
+ -- CEP model
+ ------------------------------------------------------------------------------
u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
PORT MAP (
refclk_644 => SA_CLK,
@@ -471,13 +612,13 @@ BEGIN
dp_rst => dest_rst,
dp_clk => ext_clk,
- reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
+ reg_hdr_dat_mosi => rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => rx_hdr_dat_miso,
snk_in_arr(0) => tr_10GbE_src_out,
snk_out_arr(0) => tr_10GbE_src_in,
- src_out_arr(0) => test_offload_sosi,
+ src_out_arr(0) => rx_beamlet_sosi,
hdr_fields_out_arr(0) => rx_hdr_fields_out,
hdr_fields_raw_arr(0) => rx_hdr_fields_raw
@@ -489,19 +630,52 @@ BEGIN
tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
p_mm_stimuli : PROCESS
- VARIABLE v_bsn : NATURAL;
- VARIABLE v_sp_subband_sst : REAL := 0.0;
- VARIABLE v_pol_beamlet_bst : REAL := 0.0;
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_sst : REAL := 0.0;
+ VARIABLE v_bst : REAL := 0.0;
VARIABLE v_data_lo, v_data_hi : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
VARIABLE v_stat_data : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);
VARIABLE v_len, v_span, v_offset, v_addr, v_sel : NATURAL; -- address ranges, indices
- VARIABLE v_W, v_P, v_S, v_A, v_B, v_G : NATURAL; -- array indicies
+ VARIABLE v_W, v_P, v_PB, v_S, v_A, v_B, v_G : NATURAL; -- array indicies
VARIABLE v_re, v_im, v_weight : INTEGER;
VARIABLE v_re_exp, v_im_exp : REAL := 0.0;
BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
-
+
+ print_str("");
+ print_str("WG:");
+ print_str(". c_wg_ampl = " & int_to_str(c_wg_ampl));
+ print_str(". c_exp_sp_power = " & real_to_str(c_exp_sp_power, 20, 1));
+ print_str(". c_exp_sp_ast = " & real_to_str(c_exp_sp_ast, 20, 1));
+
+ print_str("");
+ print_str("Subband weight:");
+ print_str(". sp_subband_weight_gain = " & real_to_str(sp_subband_weight_gain, 20, 6));
+ print_str(". sp_subband_weight_phase = " & real_to_str(sp_subband_weight_phase, 20, 6));
+
+ print_str("");
+ print_str("SST results:");
+ print_str(". sst_weighted_subbands_flag = " & sl_to_str(sst_weighted_subbands_flag));
+ print_str("");
+ print_str(". c_exp_subband_ampl = " & int_to_str(NATURAL(c_exp_subband_ampl)));
+ print_str(". c_exp_subband_power = " & real_to_str(c_exp_subband_power, 20, 1));
+ print_str(". c_exp_subband_sst = " & real_to_str(c_exp_subband_sst, 20, 1));
+ print_str("");
+ print_str(". sp_sst = " & real_to_str(sp_sst, 20, 1));
+ print_str(". sp_sst / c_exp_subband_sst = " & real_to_str(sp_sst / c_exp_subband_sst, 20, 6));
+
+ print_str("");
+ print_str("BST results:");
+ print_str(". c_exp_beamlet_x_ampl = " & int_to_str(NATURAL(c_exp_beamlet_x_ampl)));
+ print_str(". c_exp_beamlet_x_power = " & real_to_str(c_exp_beamlet_x_power, 20, 1));
+ print_str(". c_exp_beamlet_x_bst = " & real_to_str(c_exp_beamlet_x_bst, 20, 1));
+ print_str("");
+ print_str(". c_exp_beamlet_y_ampl = " & int_to_str(NATURAL(c_exp_beamlet_y_ampl)));
+ print_str(". c_exp_beamlet_y_power = " & real_to_str(c_exp_beamlet_y_power, 20, 1));
+ print_str(". c_exp_beamlet_y_bst = " & real_to_str(c_exp_beamlet_y_bst, 20, 1));
+ print_str("");
+
----------------------------------------------------------------------------
-- Set and check SDP info
----------------------------------------------------------------------------
@@ -635,12 +809,21 @@ BEGIN
-- 1 : phase[15:0]
-- 2 : freq[30:0]
-- 3 : ampl[16:0]
- -- . Put wanted signal on g_sp input
- v_offset := g_sp * c_mm_span_reg_diag_wg;
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, INTEGER(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, INTEGER(REAL(g_subband) * c_wg_subband_freq_unit), tb_clk); -- freq
- mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, INTEGER(REAL(c_wg_ampl) * c_wg_ampl_lsb), tb_clk); -- ampl
+ -- . Put wanted signal on g_sp input and remnant signal on the other inputs
+ FOR S IN 0 TO c_sdp_S_pn-1 LOOP
+ v_offset := S * c_mm_span_reg_diag_wg;
+ IF s = g_sp THEN
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, INTEGER(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, INTEGER(REAL(g_subband) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, INTEGER(REAL(c_wg_ampl) * c_wg_ampl_lsb), tb_clk); -- ampl
+ ELSE
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 1, INTEGER(c_wg_remnant_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 2, INTEGER(REAL(g_subband) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, v_offset + 3, INTEGER(REAL(c_wg_remnant_ampl) * c_wg_ampl_lsb), tb_clk); -- ampl
+ END IF;
+ END LOOP;
-- Read current BSN
mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
@@ -658,7 +841,7 @@ BEGIN
-- Read weighted subband selector
----------------------------------------------------------------------------
mmf_mm_bus_rd(c_mm_file_reg_dp_selector, 0, rd_data, tb_clk);
- sst_offload_weighted_subbands <= NOT rd_data(0);
+ sst_weighted_subbands_flag <= NOT rd_data(0);
proc_common_wait_some_cycles(tb_clk, 1);
----------------------------------------------------------------------------
@@ -673,8 +856,8 @@ BEGIN
v_im := unpack_complex_im(rd_data, c_sdp_W_sub_weight);
sp_subband_weight_re <= v_re;
sp_subband_weight_im <= v_im;
- sp_subband_weight_gain <= SQRT(REAL(v_re)**2.0 + REAL(v_im)**2.0) / REAL(c_sdp_unit_sub_weight);
- sp_subband_weight_phase <= atan2(Y => REAL(v_im), X => REAL(v_re)) * 360.0 / MATH_2_PI;
+ sp_subband_weight_gain <= COMPLEX_RADIUS(v_re, v_im) / REAL(c_sdp_unit_sub_weight);
+ sp_subband_weight_phase <= COMPLEX_PHASE(v_re, v_im);
-- No need to write subband weight, because default it is unit weight
@@ -716,7 +899,7 @@ BEGIN
proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
----------------------------------------------------------------------------
- -- Write beamlet weight for g_beamlet
+ -- Write beamlet weight for g_beamlet in S_sub_bf
----------------------------------------------------------------------------
-- . MM format: (cint16)RAM_BF_WEIGHTS[N_beamsets][N_pol_bf][A_pn]_[N_pol][S_sub_bf]
@@ -724,38 +907,65 @@ BEGIN
v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
-- Same BF weights for both beamsets
- FOR A IN 0 TO c_sdp_A_pn-1 LOOP
- FOR P IN 0 TO c_sdp_N_pol-1 LOOP
- v_S := A * c_sdp_N_pol + P;
- IF v_S = g_sp THEN
- -- use generic BF weight for g_sp in g_beamlet
- v_weight := pack_complex(re => c_bf_weight_re, im => c_bf_weight_im, w => c_sdp_W_bf_weight);
- ELSE
- -- default set all weights to zero
- v_weight := 0;
- END IF;
- v_addr := g_beamlet + A * v_span + U * c_mm_span_ram_bf_weights;
- v_addr := v_addr + P * c_sdp_S_sub_bf;
- mmf_mm_bus_wr(c_mm_file_ram_bf_weights, v_addr, v_weight, tb_clk);
+ FOR PB IN 0 TO c_sdp_N_pol_bf-1 LOOP
+ -- Same BF weights for both beamlet polarizations
+ FOR A IN 0 TO c_sdp_A_pn-1 LOOP
+ FOR P IN 0 TO c_sdp_N_pol-1 LOOP
+ v_S := A * c_sdp_N_pol + P;
+ IF v_S = g_sp THEN
+ -- use generic BF weight for g_sp in g_beamlet
+ IF PB = 0 THEN
+ v_weight := pack_complex(re => c_bf_x_weight_re, im => c_bf_x_weight_im, w => c_sdp_W_bf_weight);
+ ELSE
+ v_weight := pack_complex(re => c_bf_y_weight_re, im => c_bf_y_weight_im, w => c_sdp_W_bf_weight);
+ END IF;
+ ELSE
+ -- use the remnant BF weights for the other SP
+ IF PB = 0 THEN
+ v_weight := pack_complex(re => c_bf_remnant_x_weight_re, im => c_bf_remnant_x_weight_im, w => c_sdp_W_bf_weight);
+ ELSE
+ v_weight := pack_complex(re => c_bf_remnant_y_weight_re, im => c_bf_remnant_y_weight_im, w => c_sdp_W_bf_weight);
+ END IF;
+ END IF;
+ v_addr := g_beamlet; -- beamlet index
+ v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
+ v_addr := v_addr + A * v_span; -- antenna input address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ mmf_mm_bus_wr(c_mm_file_ram_bf_weights, v_addr, v_weight, tb_clk);
+ END LOOP;
END LOOP;
END LOOP;
END LOOP;
- -- . read back BF weights for g_beamlet
+ -- . read back BF weights for g_beamlet in S_sub_bf
FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
- FOR A IN 0 TO c_sdp_A_pn-1 LOOP
- FOR P IN 0 TO c_sdp_N_pol-1 LOOP
- v_addr := g_beamlet + A * v_span + U * c_mm_span_ram_bf_weights;
- v_addr := v_addr + P * c_sdp_S_sub_bf;
- mmf_mm_bus_rd(c_mm_file_ram_bf_weights, v_addr, rd_data, tb_clk);
- v_re := unpack_complex_re(rd_data, c_sdp_W_bf_weight);
- v_im := unpack_complex_im(rd_data, c_sdp_W_bf_weight);
- -- same BF weights for both beamsets, so fine to use only one sp_bf_weights_*_arr()
- v_S := A * c_sdp_N_pol + P;
- sp_bf_weights_re_arr(v_S) <= v_re;
- sp_bf_weights_im_arr(v_S) <= v_im;
- sp_bf_weights_gain_arr(v_S) <= SQRT(REAL(v_re)**2.0 + REAL(v_im)**2.0) / REAL(c_sdp_unit_bf_weight);
- sp_bf_weights_phase_arr(v_S) <= atan2(Y => REAL(v_im), X => REAL(v_re)) * 360.0 / MATH_2_PI;
+ FOR PB IN 0 TO c_sdp_N_pol_bf-1 LOOP
+ FOR A IN 0 TO c_sdp_A_pn-1 LOOP
+ FOR P IN 0 TO c_sdp_N_pol-1 LOOP
+ v_addr := g_beamlet; -- beamlet index
+ v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
+ v_addr := v_addr + A * v_span; -- antenna input address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ mmf_mm_bus_rd(c_mm_file_ram_bf_weights, v_addr, rd_data, tb_clk);
+ v_re := unpack_complex_re(rd_data, c_sdp_W_bf_weight);
+ v_im := unpack_complex_im(rd_data, c_sdp_W_bf_weight);
+ -- same BF weights for both beamsets and both beamlet polarizations,
+ -- so fine to use only one sp_bf_x_weights_*_arr()
+ v_S := A * c_sdp_N_pol + P;
+ IF PB = 0 THEN
+ sp_bf_x_weights_re_arr(v_S) <= v_re;
+ sp_bf_x_weights_im_arr(v_S) <= v_im;
+ sp_bf_x_weights_gain_arr(v_S) <= COMPLEX_RADIUS(v_re, v_im) / REAL(c_sdp_unit_bf_weight);
+ sp_bf_x_weights_phase_arr(v_S) <= COMPLEX_PHASE(v_re, v_im);
+ ELSE
+ sp_bf_y_weights_re_arr(v_S) <= v_re;
+ sp_bf_y_weights_im_arr(v_S) <= v_im;
+ sp_bf_y_weights_gain_arr(v_S) <= COMPLEX_RADIUS(v_re, v_im) / REAL(c_sdp_unit_bf_weight);
+ sp_bf_y_weights_phase_arr(v_S) <= COMPLEX_PHASE(v_re, v_im);
+ END IF;
+ END LOOP;
END LOOP;
END LOOP;
END LOOP;
@@ -804,7 +1014,7 @@ BEGIN
v_data_hi := rd_data;
v_stat_data := v_data_hi & v_data_lo;
- sp_subband_ssts_arr2(v_P)(v_B) <= v_stat_data;
+ sp_ssts_arr2(v_P)(v_B) <= v_stat_data;
stat_data <= v_stat_data; -- for time series view in Wave window
END IF;
END IF;
@@ -812,10 +1022,7 @@ BEGIN
proc_common_wait_some_cycles(tb_clk, 1);
-- Subband power of g_subband in g_sp
- -- . For the selected g_subband in g_sp the sp_subband_sst will be close
- -- to sp_subband_sst_sum_arr(c_pol_index), because the input is a
- -- sinus, so most power will be in 1 subband.
- sp_subband_sst <= TO_UREAL(sp_subband_ssts_arr2(c_pol_index)(g_subband));
+ sp_sst <= TO_UREAL(sp_ssts_arr2(c_pol_index)(g_subband));
proc_common_wait_some_cycles(tb_clk, 1);
proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
@@ -831,8 +1038,8 @@ BEGIN
v_span := true_log_pow2(v_len); -- = 2048
FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
FOR I IN 0 TO v_len-1 LOOP
- v_W := I MOD c_stat_data_sz; -- 0, 1 per statistics word, word index
- v_P := (I / c_stat_data_sz) MOD c_sdp_N_pol_bf; -- 0, 1 per BF pol, polarization index
+ v_W := I MOD c_stat_data_sz; -- 0, 1 per statistics word, word index
+ v_PB := (I / c_stat_data_sz) MOD c_sdp_N_pol_bf; -- 0, 1 per BF pol, polarization index
v_B := I / (c_sdp_N_pol_bf * c_stat_data_sz); -- beamlet index in beamset, range(S_sub_bf = 488) per dual pol
v_G := v_B + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
v_addr := I + U * v_span; -- MM address
@@ -848,7 +1055,7 @@ BEGIN
v_data_hi := rd_data;
v_stat_data := v_data_hi & v_data_lo;
- pol_beamlet_bsts_arr2(v_P)(v_G) <= v_stat_data;
+ bsts_arr2(v_PB)(v_G) <= v_stat_data;
stat_data <= v_stat_data; -- for time series view in Wave window
END IF;
END IF;
@@ -859,8 +1066,8 @@ BEGIN
-- Beamlet power of g_beamlet X and Y, same for both beamsets
FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- pol_beamlet_bst_X_arr(U) <= TO_UREAL(pol_beamlet_bsts_arr2(0)(v_G)); -- X pol beamlet
- pol_beamlet_bst_Y_arr(U) <= TO_UREAL(pol_beamlet_bsts_arr2(1)(v_G)); -- Y pol beamlet
+ bst_x_arr(U) <= TO_UREAL(bsts_arr2(0)(v_G)); -- X pol beamlet
+ bst_y_arr(U) <= TO_UREAL(bsts_arr2(1)(v_G)); -- Y pol beamlet
END LOOP;
proc_common_wait_some_cycles(tb_clk, 1);
proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
@@ -875,10 +1082,6 @@ BEGIN
print_str(". c_exp_sp_power = " & real_to_str(c_exp_sp_power, 20, 1));
print_str(". c_exp_sp_ast = " & real_to_str(c_exp_sp_ast, 20, 1));
- print_str("");
- print_str("Subband selector:");
- print_str(". sst_offload_weighted_subbands = " & sl_to_str(sst_offload_weighted_subbands));
-
print_str("");
print_str("Subband weight:");
print_str(". sp_subband_weight_gain = " & real_to_str(sp_subband_weight_gain, 20, 6));
@@ -886,69 +1089,88 @@ BEGIN
print_str("");
print_str("SST results:");
+ print_str(". sst_weighted_subbands_flag = " & sl_to_str(sst_weighted_subbands_flag));
+ print_str("");
print_str(". c_exp_subband_ampl = " & int_to_str(NATURAL(c_exp_subband_ampl)));
print_str(". c_exp_subband_power = " & real_to_str(c_exp_subband_power, 20, 1));
print_str(". c_exp_subband_sst = " & real_to_str(c_exp_subband_sst, 20, 1));
print_str("");
- print_str(". sp_subband_sst = " & real_to_str(sp_subband_sst, 20, 1));
- print_str(". sp_subband_sst / c_exp_subband_sst = " & real_to_str(sp_subband_sst / c_exp_subband_sst, 20, 6));
+ print_str(". sp_sst = " & real_to_str(sp_sst, 20, 1));
+ print_str(". sp_sst / c_exp_subband_sst = " & real_to_str(sp_sst / c_exp_subband_sst, 20, 6));
print_str("");
print_str("BST results:");
- print_str(". c_exp_beamlet_ampl = " & int_to_str(NATURAL(c_exp_beamlet_ampl)));
- print_str(". c_exp_beamlet_power = " & real_to_str(c_exp_beamlet_power, 20, 1));
- print_str(". c_exp_beamlet_bst = " & real_to_str(c_exp_beamlet_bst, 20, 1));
+ print_str(". c_exp_beamlet_x_ampl = " & int_to_str(NATURAL(c_exp_beamlet_x_ampl)));
+ print_str(". c_exp_beamlet_x_power = " & real_to_str(c_exp_beamlet_x_power, 20, 1));
+ print_str(". c_exp_beamlet_x_bst = " & real_to_str(c_exp_beamlet_x_bst, 20, 1));
+ print_str("");
+ print_str(". c_exp_beamlet_y_ampl = " & int_to_str(NATURAL(c_exp_beamlet_y_ampl)));
+ print_str(". c_exp_beamlet_y_power = " & real_to_str(c_exp_beamlet_y_power, 20, 1));
+ print_str(". c_exp_beamlet_y_bst = " & real_to_str(c_exp_beamlet_y_bst, 20, 1));
print_str("");
FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- print_str(". pol_beamlet_bst_X beamlet(" & INTEGER'IMAGE(v_G) & ") = " & real_to_str(pol_beamlet_bst_X_arr(U), 20, 1));
- print_str(". pol_beamlet_bst_Y beamlet(" & INTEGER'IMAGE(v_G) & ") = " & real_to_str(pol_beamlet_bst_Y_arr(U), 20, 1));
+ print_str(". bst_x_arr(" & INTEGER'IMAGE(v_G) & ") = " & real_to_str(bst_x_arr(U), 20, 1));
+ print_str(". bst_y_arr(" & INTEGER'IMAGE(v_G) & ") = " & real_to_str(bst_y_arr(U), 20, 1));
END LOOP;
FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
- print_str(". pol_beamlet_bst_X beamlet(" & INTEGER'IMAGE(v_G) & ") / c_exp_beamlet_bst = " & real_to_str(pol_beamlet_bst_X_arr(U) / c_exp_beamlet_bst, 20, 6));
- print_str(". pol_beamlet_bst_Y beamlet(" & INTEGER'IMAGE(v_G) & ") / c_exp_beamlet_bst = " & real_to_str(pol_beamlet_bst_Y_arr(U) / c_exp_beamlet_bst, 20, 6));
+ print_str(". bst_x_arr(" & INTEGER'IMAGE(v_G) & ") / c_exp_beamlet_x_bst = " & real_to_str(bst_x_arr(U) / c_exp_beamlet_x_bst, 20, 6));
+ print_str(". bst_y_arr(" & INTEGER'IMAGE(v_G) & ") / c_exp_beamlet_y_bst = " & real_to_str(bst_y_arr(U) / c_exp_beamlet_y_bst, 20, 6));
END LOOP;
print_str("");
print_str("Beamlet output:");
print_str(". rd_beamlet_scale = " & int_to_str(TO_UINT(rd_beamlet_scale)));
- print_str(". c_exp_beamlet_output_ampl = " & int_to_str(NATURAL(c_exp_beamlet_output_ampl)));
-
+ print_str(". c_exp_beamlet_scale = " & int_to_str(c_exp_beamlet_scale));
+ print_str("");
+ print_str(". c_exp_beamlet_x_output_ampl = " & int_to_str(NATURAL(c_exp_beamlet_x_output_ampl)));
+ print_str(". c_exp_beamlet_x_output_phase = " & int_to_str(INTEGER(c_exp_beamlet_x_output_phase)));
+ print_str(". c_exp_beamlet_x_output_re = " & int_to_str(INTEGER(c_exp_beamlet_x_output_re)));
+ print_str(". c_exp_beamlet_x_output_im = " & int_to_str(INTEGER(c_exp_beamlet_x_output_im)));
+ print_str("");
+ print_str(". c_exp_beamlet_y_output_ampl = " & int_to_str(NATURAL(c_exp_beamlet_y_output_ampl)));
+ print_str(". c_exp_beamlet_y_output_phase = " & int_to_str(INTEGER(c_exp_beamlet_y_output_phase)));
+ print_str(". c_exp_beamlet_y_output_re = " & int_to_str(INTEGER(c_exp_beamlet_y_output_re)));
+ print_str(". c_exp_beamlet_y_output_im = " & int_to_str(INTEGER(c_exp_beamlet_y_output_im)));
+
---------------------------------------------------------------------------
- -- Verify SST and BST
+ -- Verify SST
---------------------------------------------------------------------------
-
-- verify expected subband power based on WG power
- ASSERT sp_subband_sst > c_stat_lo_factor * c_exp_subband_sst REPORT "Wrong subband power for SP " & NATURAL'IMAGE(g_sp) SEVERITY ERROR;
- ASSERT sp_subband_sst < c_stat_hi_factor * c_exp_subband_sst REPORT "Wrong subband power for SP " & NATURAL'IMAGE(g_sp) SEVERITY ERROR;
+ ASSERT sp_sst > c_stat_lo_factor * c_exp_subband_sst REPORT "Wrong subband power for SP " & NATURAL'IMAGE(g_sp) SEVERITY ERROR;
+ ASSERT sp_sst < c_stat_hi_factor * c_exp_subband_sst REPORT "Wrong subband power for SP " & NATURAL'IMAGE(g_sp) SEVERITY ERROR;
+ ---------------------------------------------------------------------------
+ -- Verify BST
+ ---------------------------------------------------------------------------
-- verify expected beamlet power based on WG power and BF weigths
- --
- -- All co and cross polarization weights are equal: w = w_xx = w_xy = w_yx = w_yy
- -- With one g_sp either SP X or SP Y is used, so the other antenna polarization is 0
- -- Hence the c_exp_beamlet_bst will be the same for beamlet X and Y independent of whether g_sp is an X or Y signal input:
- -- g_sp = X --> w_xx --> beamlet X = c_exp_beamlet_bst
- -- g_sp = Y --> w_xy --> beamlet X = c_exp_beamlet_bst
- -- g_sp = X --> w_yx --> beamlet Y = c_exp_beamlet_bst
- -- g_sp = Y --> w_yy --> beamlet Y = c_exp_beamlet_bst
- --
FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
- ASSERT pol_beamlet_bst_X_arr(U) > c_stat_lo_factor * c_exp_beamlet_bst REPORT "Wrong beamlet power for X in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
- ASSERT pol_beamlet_bst_X_arr(U) < c_stat_hi_factor * c_exp_beamlet_bst REPORT "Wrong beamlet power for X in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
- ASSERT pol_beamlet_bst_Y_arr(U) > c_stat_lo_factor * c_exp_beamlet_bst REPORT "Wrong beamlet power for Y in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
- ASSERT pol_beamlet_bst_Y_arr(U) < c_stat_hi_factor * c_exp_beamlet_bst REPORT "Wrong beamlet power for Y in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
+ -- X-pol
+ ASSERT bst_x_arr(U) < c_stat_hi_factor * c_exp_beamlet_x_bst REPORT "Wrong beamlet X power in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
+ ASSERT bst_x_arr(U) > c_stat_lo_factor * c_exp_beamlet_x_bst REPORT "Wrong beamlet X power in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
+ -- Y-pol
+ ASSERT bst_y_arr(U) > c_stat_lo_factor * c_exp_beamlet_y_bst REPORT "Wrong beamlet Y power in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
+ ASSERT bst_y_arr(U) < c_stat_hi_factor * c_exp_beamlet_y_bst REPORT "Wrong beamlet Y power in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
END LOOP;
---------------------------------------------------------------------------
-- Verify beamlet output in 10GbE UDP offload
---------------------------------------------------------------------------
- v_re := TO_SINT(rx_beamlet_list_re(c_exp_beamlet_index)); v_re_exp := c_exp_beamlet_output_re;
- v_im := TO_SINT(rx_beamlet_list_im(c_exp_beamlet_index)); v_im_exp := c_exp_beamlet_output_im;
- ASSERT v_re > INTEGER(v_re_exp) - c_beamlet_output_delta REPORT "Wrong 10GbE output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
- ASSERT v_re < INTEGER(v_re_exp) + c_beamlet_output_delta REPORT "Wrong 10GbE output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
- ASSERT v_im > INTEGER(v_im_exp) - c_beamlet_output_delta REPORT "Wrong 10GbE output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
- ASSERT v_im < INTEGER(v_im_exp) + c_beamlet_output_delta REPORT "Wrong 10GbE output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
+ -- X-pol
+ v_re := TO_SINT(rx_beamlet_list_re(c_exp_beamlet_x_index)); v_re_exp := c_exp_beamlet_x_output_re;
+ v_im := TO_SINT(rx_beamlet_list_im(c_exp_beamlet_x_index)); v_im_exp := c_exp_beamlet_x_output_im;
+ ASSERT v_re > INTEGER(v_re_exp) - c_beamlet_output_delta REPORT "Wrong beamlet X output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_re < INTEGER(v_re_exp) + c_beamlet_output_delta REPORT "Wrong beamlet X output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_im > INTEGER(v_im_exp) - c_beamlet_output_delta REPORT "Wrong beamlet X output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
+ ASSERT v_im < INTEGER(v_im_exp) + c_beamlet_output_delta REPORT "Wrong beamlet X output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
+ -- Y-pol
+ v_re := TO_SINT(rx_beamlet_list_re(c_exp_beamlet_y_index)); v_re_exp := c_exp_beamlet_y_output_re;
+ v_im := TO_SINT(rx_beamlet_list_im(c_exp_beamlet_y_index)); v_im_exp := c_exp_beamlet_y_output_im;
+ ASSERT v_re > INTEGER(v_re_exp) - c_beamlet_output_delta REPORT "Wrong beamlet Y output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_re < INTEGER(v_re_exp) + c_beamlet_output_delta REPORT "Wrong beamlet Y output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_im > INTEGER(v_im_exp) - c_beamlet_output_delta REPORT "Wrong beamlet Y output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
+ ASSERT v_im < INTEGER(v_im_exp) + c_beamlet_output_delta REPORT "Wrong beamlet Y output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
---------------------------------------------------------------------------
-- End Simulation
@@ -967,22 +1189,22 @@ BEGIN
p_test_counters : PROCESS(ext_clk)
BEGIN
IF rising_edge(ext_clk) THEN
- -- Count test_offload_sosi packets
- IF test_offload_sosi.sop = '1' THEN
- test_offload_sop_cnt <= test_offload_sop_cnt + 1; -- early count
+ -- Count rx_beamlet_sosi packets
+ IF rx_beamlet_sosi.sop = '1' THEN
+ rx_beamlet_sop_cnt <= rx_beamlet_sop_cnt + 1; -- early count
END IF;
- IF test_offload_sosi.eop = '1' THEN
- test_offload_eop_cnt <= test_offload_eop_cnt + 1; -- after count
+ IF rx_beamlet_sosi.eop = '1' THEN
+ rx_beamlet_eop_cnt <= rx_beamlet_eop_cnt + 1; -- after count
END IF;
END IF;
END PROCESS;
- -- Count sync intervals using in_sosi.sync, because there is no test_offload_sosi.sync
+ -- Count sync intervals using in_sosi.sync, because there is no rx_beamlet_sosi.sync
in_sync_cnt <= in_sync_cnt + 1 WHEN rising_edge(ext_clk) AND in_sync = '1';
- test_sync_cnt <= in_sync_cnt - 1; -- optionally adjust to fit test_offload_sosi
+ test_sync_cnt <= in_sync_cnt - 1; -- optionally adjust to fit rx_beamlet_sosi
- -- Prepare exp_sdp_cep_header before test_offload_sosi.eop, so that
- -- p_exp_sdp_cep_header can verify it at test_offload_sosi.eop.
+ -- Prepare exp_sdp_cep_header before rx_beamlet_sosi.eop, so that
+ -- p_exp_sdp_cep_header can verify it at rx_beamlet_sosi.eop.
p_exp_sdp_cep_header : PROCESS(exp_dp_bsn)
BEGIN
@@ -1044,10 +1266,10 @@ BEGIN
WAIT UNTIL rising_edge(ext_clk);
-- Prepare exp_sdp_cep_header at sop, so that it can be verified at eop
- IF test_offload_sosi.sop = '1' THEN
+ IF rx_beamlet_sosi.sop = '1' THEN
-- Expected BSN increments by c_sdp_cep_nof_blocks_per_packet = 4 blocks per packet
- IF test_offload_sop_cnt MOD c_sdp_N_beamsets = 0 THEN
- exp_dp_bsn <= c_init_bsn + (test_offload_sop_cnt / c_sdp_N_beamsets) * c_sdp_cep_nof_blocks_per_packet;
+ IF rx_beamlet_sop_cnt MOD c_sdp_N_beamsets = 0 THEN
+ exp_dp_bsn <= c_init_bsn + (rx_beamlet_sop_cnt / c_sdp_N_beamsets) * c_sdp_cep_nof_blocks_per_packet;
END IF;
END IF;
@@ -1056,7 +1278,7 @@ BEGIN
-- or 1, but the order in which the packets arrive is undetermined.
-- Therefore accept any beamlet_index MOD c_sdp_S_sub_bf = 0 as correct
-- in func_sdp_verify_cep_header().
- IF test_offload_sosi.eop = '1' THEN
+ IF rx_beamlet_sosi.eop = '1' THEN
v_bool := func_sdp_verify_cep_header(rx_sdp_cep_header, exp_sdp_cep_header);
END IF;
END PROCESS;
@@ -1072,47 +1294,47 @@ BEGIN
-- . expect c_sdp_cep_nof_beamlets_per_block = c_sdp_S_sub_bf = 488 dual pol
-- and complex beamlets per packet, so 2 dual pol beamlets/64b data word.
-- . Beamlets array is stored big endian in the data, so X index 0 first in
- -- MSByte of test_offload_sosi.data.
+ -- MSByte of rx_beamlet_sosi.data.
p_rx_cep_beamlets : PROCESS
BEGIN
rx_beamlet_cnt <= 0;
rx_beamlet_valid <= '0';
-- Wait until start of a beamlet packet, capture only first block in packet
- proc_common_wait_until_high(ext_clk, test_offload_sosi.sop);
- -- 2 dual pol beamlets (= XY, XY) per 64b data word
- FOR I IN 0 TO (c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block/2)-1 LOOP
- proc_common_wait_until_high(ext_clk, test_offload_sosi.valid);
+ proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.sop);
+ -- c_nof_beamlets_per_data = 2 dual pol beamlets (= XY, XY) per 64b data word
+ FOR I IN 0 TO (c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block / c_nof_beamlets_per_data)-1 LOOP
+ proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.valid);
rx_beamlet_valid <= '1';
-- Capture rx beamlets per longword in rx_beamlet_arr, for time series view in Wave window
- rx_beamlet_arr_re(0) <= test_offload_sosi.data(55 DOWNTO 48); -- X
- rx_beamlet_arr_im(0) <= test_offload_sosi.data(63 DOWNTO 56);
- rx_beamlet_arr_re(1) <= test_offload_sosi.data(39 DOWNTO 32); -- Y
- rx_beamlet_arr_im(1) <= test_offload_sosi.data(47 DOWNTO 40);
- rx_beamlet_arr_re(2) <= test_offload_sosi.data(23 DOWNTO 16); -- X
- rx_beamlet_arr_im(2) <= test_offload_sosi.data(31 DOWNTO 24);
- rx_beamlet_arr_re(3) <= test_offload_sosi.data( 7 DOWNTO 0); -- Y
- rx_beamlet_arr_im(3) <= test_offload_sosi.data(15 DOWNTO 8);
- IF I < c_sdp_cep_nof_beamlets_per_block/2 THEN
+ rx_beamlet_arr_re(0) <= rx_beamlet_sosi.data(55 DOWNTO 48); -- X
+ rx_beamlet_arr_im(0) <= rx_beamlet_sosi.data(63 DOWNTO 56);
+ rx_beamlet_arr_re(1) <= rx_beamlet_sosi.data(39 DOWNTO 32); -- Y
+ rx_beamlet_arr_im(1) <= rx_beamlet_sosi.data(47 DOWNTO 40);
+ rx_beamlet_arr_re(2) <= rx_beamlet_sosi.data(23 DOWNTO 16); -- X
+ rx_beamlet_arr_im(2) <= rx_beamlet_sosi.data(31 DOWNTO 24);
+ rx_beamlet_arr_re(3) <= rx_beamlet_sosi.data( 7 DOWNTO 0); -- Y
+ rx_beamlet_arr_im(3) <= rx_beamlet_sosi.data(15 DOWNTO 8);
+ IF I < c_sdp_cep_nof_beamlets_per_block / c_nof_beamlets_per_data THEN
-- Only capture the first beamlets block of each packet in rx_beamlet_list
- rx_beamlet_list_re(I*4 + 0) <= test_offload_sosi.data(55 DOWNTO 48); -- X
- rx_beamlet_list_im(I*4 + 0) <= test_offload_sosi.data(63 DOWNTO 56);
- rx_beamlet_list_re(I*4 + 1) <= test_offload_sosi.data(39 DOWNTO 32); -- Y
- rx_beamlet_list_im(I*4 + 1) <= test_offload_sosi.data(47 DOWNTO 40);
- rx_beamlet_list_re(I*4 + 2) <= test_offload_sosi.data(23 DOWNTO 16); -- X
- rx_beamlet_list_im(I*4 + 2) <= test_offload_sosi.data(31 DOWNTO 24);
- rx_beamlet_list_re(I*4 + 3) <= test_offload_sosi.data( 7 DOWNTO 0); -- Y
- rx_beamlet_list_im(I*4 + 3) <= test_offload_sosi.data(15 DOWNTO 8);
+ rx_beamlet_list_re(I*4 + 0) <= rx_beamlet_sosi.data(55 DOWNTO 48); -- X
+ rx_beamlet_list_im(I*4 + 0) <= rx_beamlet_sosi.data(63 DOWNTO 56);
+ rx_beamlet_list_re(I*4 + 1) <= rx_beamlet_sosi.data(39 DOWNTO 32); -- Y
+ rx_beamlet_list_im(I*4 + 1) <= rx_beamlet_sosi.data(47 DOWNTO 40);
+ rx_beamlet_list_re(I*4 + 2) <= rx_beamlet_sosi.data(23 DOWNTO 16); -- X
+ rx_beamlet_list_im(I*4 + 2) <= rx_beamlet_sosi.data(31 DOWNTO 24);
+ rx_beamlet_list_re(I*4 + 3) <= rx_beamlet_sosi.data( 7 DOWNTO 0); -- Y
+ rx_beamlet_list_im(I*4 + 3) <= rx_beamlet_sosi.data(15 DOWNTO 8);
END IF;
- proc_common_wait_until_high(ext_clk, test_offload_sosi.valid);
+ proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.valid);
-- Use at least one WAIT instead of proc_common_wait_some_cycles() to
-- avoid Modelsim warning: (vcom-1090) Possible infinite loop: Process
-- contains no WAIT statement.
WAIT UNTIL rising_edge(ext_clk);
rx_beamlet_valid <= '0';
- rx_beamlet_cnt <= (rx_beamlet_cnt + 4) MOD c_sdp_cep_nof_beamlets_per_block; -- 4 blocks/packet
+ rx_beamlet_cnt <= (rx_beamlet_cnt + c_nof_beamlets_per_data) MOD c_sdp_cep_nof_beamlets_per_block; -- 4 blocks/packet
END LOOP;
END PROCESS;
-- To view the 64 bit 10GbE offload data more easily in the Wave window
- test_offload_data <= test_offload_sosi.data(c_longword_w-1 DOWNTO 0);
+ rx_beamlet_data <= rx_beamlet_sosi.data(c_longword_w-1 DOWNTO 0);
END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3c601579d3607b1ee85fc730359a46660b34fdcb
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -0,0 +1,65 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+--
+-- Author: E. Kooistra, 10 march 2022
+-- Purpose: Regression multi tb for tb_lofar2_unb2c_sdp_station_bf
+-- Description:
+-- The multi tb only has one instance, so the tb_tb is more a wrapper to
+-- ensure that always the same tb generics are used in the regression test.
+-- This allows modifying the generics in the tb.
+-- Usage:
+-- > as 4
+-- > run -all
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+
+ENTITY tb_tb_lofar2_unb2c_sdp_station_bf IS
+END tb_tb_lofar2_unb2c_sdp_station_bf;
+
+
+ARCHITECTURE tb OF tb_tb_lofar2_unb2c_sdp_station_bf IS
+
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+
+BEGIN
+
+ u_bf : ENTITY work.tb_lofar2_unb2c_sdp_station_bf
+ GENERIC MAP (
+ g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
+ g_sp_ampl => 0.5, -- WG normalized amplitude
+ g_sp_phase => -110.0, -- WG phase in degrees = subband phase
+ g_sp_remnant_ampl => 0.1, -- WG normalized amplitude for remnant sp
+ g_sp_remnant_phase => 15.0, -- WG phase in degrees for remnant sp
+ g_subband => 102, -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_beamlet => 10, -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet_scale => 1.0 / 2.0**9, -- g_beamlet output scale factor
+ g_bf_x_gain => 0.7, -- g_beamlet X BF weight normalized gain for g_sp
+ g_bf_y_gain => 0.6, -- g_beamlet Y BF weight normalized gain for g_sp
+ g_bf_x_phase => 30.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_y_phase => 40.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_x_gain => 0.05, -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain => 0.04, -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_x_phase => 170.0, -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_y_phase => -135.0, -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_read_all_SST => FALSE, -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_BST => FALSE -- when FALSE only read BST for g_beamlet, to save sim time
+ );
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..728eb3310d317b9891f2131dd22635378182690c
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg
@@ -0,0 +1,132 @@
+hdl_lib_name = lofar2_unb2c_sdp_station_bf_ring
+hdl_library_clause_name = lofar2_unb2c_sdp_station_bf_ring_lib
+hdl_lib_uses_synth = common mm technology unb2c_board lofar2_unb2c_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e2sg
+
+ synth_files =
+ lofar2_unb2c_sdp_station_bf_ring.vhd
+
+test_bench_files =
+ tb_lofar2_unb2c_sdp_station_bf_ring.vhd
+
+regression_test_vhdl =
+ tb_lofar2_unb2c_sdp_station_bf_ring.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2c_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ lofar2_unb2c_sdp_station_bf_ring_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e9e12923f78e08e5ae5f69ab6e74167a3c863a92
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -0,0 +1,170 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station beamformer design
+-- Description:
+-- Unb2c version for lab testing
+-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
+
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2c_sdp_station_bf IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2c_sdp_station_bf";
+ g_design_note : STRING := "Lofar2 SDP station beamformer design";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+
+
+ -- front transceivers
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+
+
+ -- back transceivers (note only 12 are used in unb2c)
+ BCK_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_tr_jesd204b-1 DOWNTO 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
+
+ -- jesd204b syncronization signals (4 syncs)
+ JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
+ );
+END lofar2_unb2c_sdp_station_bf;
+
+ARCHITECTURE str OF lofar2_unb2c_sdp_station_bf IS
+
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR((c_unb2c_board_tr_jesd204b.bus_w*c_unb2c_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+ SIGNAL jesd204b_sync_n_arr : STD_LOGIC_VECTOR(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC;
+
+
+BEGIN
+
+ -- Mapping between JESD signal names and UNB2B pin/schematic names
+ JESD204B_REFCLK <= BCK_REF_CLK;
+ JESD204B_SERIAL_DATA <= BCK_RX;
+ JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+ u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => jesd204b_sync_n_arr
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5a869c76f2093d4a8594508c9dbd601bea0717c4
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl
@@ -0,0 +1,26 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d1efebdef031e01550a6d3853bfcfaa6b94f3f10
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -0,0 +1,1421 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle (original), E. Kooistra (updates)
+-- Purpose: Self-checking testbench for simulating lofar2_unb2c_sdp_station_bf_ring
+-- using WG data.
+--
+-- Description:
+-- This tb is a balance between verification coverage and keeping it simple:
+-- - Use only one signal input (g_sp). Put same remnant WG signal on the
+-- other signal inputs.
+-- - Use different BF weight for the two beamlet polarizations (g_bf_x_gain,
+-- g_bf_x_phase and g_bf_y_phase, g_bf_y_phase) of signal input g_sp.
+-- Using different BF weights for the N_pol_bf = 2 BF polarizations allows
+-- verification of the dual polarization beamlet.
+-- - Use same remnant BF weight for the other S_pn - 1 = 11 signal inputs.
+-- The remnant signal inputs and BF weights allow verifying the BF sum if
+-- they are not 0. Using the same settings for all remnant SP simplyfies
+-- the tb, while still testing the BF sum.
+-- - Select one beamlet for the subband (g_beamlet). Selecting one beamlet
+-- other than the default beamlet for the subband is sufficient to verify
+-- the beamlet subband select.
+-- - Use same stimuli for both beamsets.
+--
+-- MM control actions:
+--
+-- 1) Enable calc mode for WG on signal input (si) g_sp via reg_diag_wg with:
+-- g_subband = 102 --> 102 * f_sub = 19.921875 MHz
+-- g_sp_ampl = 1.0 --> 1.0 yield WG ampl = 2**13
+-- g_sp_phase --> subband phase
+-- Use g_sp_remnant_ampl = 0.1 and g_sp_remnant_phase = 0.0 for the other
+-- S_pn-1 = 11 signal inputs, than g_sp, that are not used in the BF.
+--
+-- 2) Read current BSN from reg_bsn_scheduler_wg and write
+-- reg_bsn_scheduler_wg to trigger start of WG at BSN.
+--
+-- 3) Read and verify subband statistics (SST) for g_sp. This also reads the
+-- SST of the other signal input of the WPFB that processes g_sp.
+--
+-- 4) Select subband g_subband for beamlets in g_beamlet
+--
+-- 5) Apply BF weight to g_beamlet X beam and Y beam, so for example if g_sp
+-- = 3, then w_x3 = g_bf_x_gain/phase and w_y3 = = g_bf_x_gain/phase. The
+-- other BF weights are 0.
+--
+-- WG BF BF
+-- si weight weight
+-- X Y
+-- 0 -----> * w_x0 ..+
+-- \--------------|----> * w_y0 ..+
+-- 1 -----> * w_x1 ..+ |
+-- \--------------|----> * w_y1 ..+
+-- 2 -----> * w_x2 ..+ |
+-- \--------------|----> * w_y2 ..+
+-- 3 -----> * w_x3 ..+ |
+-- \--------------|----> * w_y3 ..+
+-- 4 -----> * w_x4 ..+ |
+-- \--------------|----> * w_y4 ..+
+-- 5 -----> * w_x5 ..+ |
+-- \--------------|----> * w_y5 ..+
+-- 6 -----> * w_x6 ..+ |
+-- \--------------|----> * w_y6 ..+
+-- 7 -----> * w_x7 ..+ |
+-- \--------------|----> * w_y7 ..+
+-- 8 -----> * w_x8 ..+ |
+-- \--------------|----> * w_y8 ..+
+-- 9 -----> * w_x9 ..+ |
+-- \--------------|----> * w_y9 ..+
+-- 10 -----> * w_x10 ..+ |
+-- \--------------|----> * w_y10 ..+
+-- 11 -----> * w_x11 ..+ |
+-- \--------------|----> * w_y11 ..+
+-- | |
+-- \----------------|---> beamlet_x
+-- \--> beamlet_y
+--
+--
+-- 6) Read and verify beamlet statistics (BST)
+-- View sp_sst in Wave window
+-- View bst_x_arr, bst_y_arr in Wave window
+--
+-- 7) Verify 10GbE output header and output payload for g_beamlet.
+-- View rx_beamlet_sosi
+-- View rx_beamlet_cnt (in analog format)
+--
+-- Remark:
+-- . The c_wg_phase_offset and c_subband_phase_offset are used to tune the WG
+-- phase reference to 0.0 degrees at the start (sop)
+--
+-- Usage:
+-- > as 7 # default
+-- > as 12 # for detailed debugging
+-- # Manually add missing signal
+-- > add wave -position insertpoint \
+-- sim:/tb_lofar2_unb2c_sdp_station_bf_ring/sp_ssts_arr2 \
+-- sim:/tb_lofar2_unb2c_sdp_station_bf_ring/bsts_arr2
+-- > run -a
+-- Takes about 40 m when g_read_all_* = FALSE
+-- Takes about 1h 5 m when g_read_all_* = TRUE
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, tech_pll_lib, tr_10GbE_lib, lofar2_unb2c_sdp_station_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.math_real.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE lofar2_sdp_lib.tb_sdp_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
+
+ENTITY tb_lofar2_unb2c_sdp_station_bf_ring IS
+ GENERIC (
+ g_sp : NATURAL := 3; -- WG signal path (SP) index in range(S_pn = 12)
+ g_sp_ampl : REAL := 0.5; -- WG normalized amplitude
+ g_sp_phase : REAL := -110.0; -- WG phase in degrees = subband phase
+ g_sp_remnant_ampl : REAL := 0.1; -- WG normalized amplitude for remnant sp
+ g_sp_remnant_phase : REAL := 15.0; -- WG phase in degrees for remnant sp
+ g_subband : NATURAL := 102; -- select g_subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ g_beamlet : NATURAL := 10; -- map g_subband to g_beamlet index in beamset in range(c_sdp_S_sub_bf = 488)
+ g_beamlet_scale : REAL := 1.0 / 2.0**9; -- g_beamlet output scale factor
+ g_bf_x_gain : REAL := 0.7; -- g_beamlet X BF weight normalized gain for g_sp
+ g_bf_y_gain : REAL := 0.6; -- g_beamlet Y BF weight normalized gain for g_sp
+ g_bf_x_phase : REAL := 30.0; -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_y_phase : REAL := 40.0; -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_x_gain : REAL := 0.05; -- g_beamlet X BF weight normalized gain for remnant sp
+ g_bf_remnant_y_gain : REAL := 0.04; -- g_beamlet Y BF weight normalized gain for remnant sp
+ g_bf_remnant_x_phase : REAL := 170.0; -- g_beamlet X BF weight phase rotation in degrees for g_sp
+ g_bf_remnant_y_phase : REAL := -135.0; -- g_beamlet Y BF weight phase rotation in degrees for g_sp
+ g_read_all_SST : BOOLEAN := FALSE; -- when FALSE only read SST for g_subband, to save sim time
+ g_read_all_BST : BOOLEAN := FALSE -- when FALSE only read BST for g_beamlet, to save sim time
+ );
+END tb_lofar2_unb2c_sdp_station_bf_ring;
+
+ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_bf_ring IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_nof_rn : NATURAL := 2;
+ CONSTANT c_gn_index : NATURAL := c_unb_nr * 4 + c_nof_rn-1; -- end node GN
+ CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
+ CONSTANT c_nof_lanes : NATURAL := c_sdp_N_beamsets;
+
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_gn_index, 8);
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0);
+
+ CONSTANT c_mac_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr + ((c_nof_rn-1) / c_quad), 8) & TO_UVEC((c_nof_rn-1) MOD c_quad, 8);
+ CONSTANT c_ip_15_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := TO_UVEC(c_unb_nr + ((c_nof_rn-1) / c_quad), 8) & TO_UVEC(((c_nof_rn-1) MOD c_quad) +1, 8); -- +1 to avoid IP = *.*.*.0
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_mm_clk_period : TIME := 10 ns; -- 100 MHz internal mm_clk
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+ CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
+
+ CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
+ CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
+ CONSTANT c_stat_data_sz : NATURAL := c_wpfb_sim.stat_data_sz; -- = 2
+
+ CONSTANT c_stat_percentage : REAL := 0.05; -- +-percentage margin that actual value may differ from expected value
+ CONSTANT c_stat_lo_factor : REAL := 1.0 - c_stat_percentage; -- lower boundary
+ CONSTANT c_stat_hi_factor : REAL := 1.0 + c_stat_percentage; -- higher boundary
+
+ CONSTANT c_nof_beamlets_per_data : NATURAL := 2; -- 2 dual pol beamlets (= XY, XY) per 64b data word
+
+ CONSTANT c_beamlet_output_delta : INTEGER := 2; -- +-delta margin
+
+ -- header fields
+ CONSTANT c_cep_eth_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := c_sdp_cep_eth_dst_mac; -- 00074306C700 = DOP36-eth0
+ CONSTANT c_cep_ip_dst_addr : STD_LOGIC_VECTOR(31 DOWNTO 0) := c_sdp_cep_ip_dst_addr; -- C0A80001 = '192.168.0.1' = DOP36-eth0
+ CONSTANT c_cep_udp_dst_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_sdp_cep_udp_dst_port; -- 5000
+
+ CONSTANT c_cep_eth_src_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := c_sdp_cep_eth_src_mac_47_16 & c_mac_15_0; -- x"00228608"; -- 47:16, 15:8 = backplane, 7:0 = node
+ CONSTANT c_cep_ip_src_addr : STD_LOGIC_VECTOR(31 DOWNTO 0) := c_sdp_cep_ip_src_addr_31_16 & c_ip_15_0; -- C0A80001 = '192.168.0.1' = DOP36-eth0
+ CONSTANT c_cep_udp_src_port : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_sdp_cep_udp_src_port_15_8 & c_id; -- D0 & c_id
+
+ CONSTANT c_exp_ip_header_checksum : NATURAL := 16#5BDD#; -- value obtained from rx_sdp_cep_header.ip.header_checksum in wave window for c_nof_rn = 2.
+
+ CONSTANT c_exp_beamlet_scale : NATURAL := NATURAL(g_beamlet_scale * REAL(c_sdp_unit_beamlet_scale)); -- c_sdp_unit_beamlet_scale = 2**15;
+
+ CONSTANT c_exp_sdp_info : t_sdp_info := (
+ TO_UVEC(601, 16), -- station_id
+ '0', -- antenna_band_index
+ x"7FFFFFFF", -- observation_id, use > 0 to avoid Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value -2 is not in bounds of subtype NATURAL.
+ b"01", -- nyquist_zone_index, 0 = first, 1 = second, 2 = third
+ '1', -- f_adc, 0 = 160 MHz, 1 = 200 MHz
+ '0', -- fsub_type, 0 = critically sampled, 1 = oversampled
+ '0', -- beam_repositioning_flag
+ x"1400" -- block_period = 5120
+ );
+
+ -- WG
+ CONSTANT c_bsn_start_wg : NATURAL := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ -- .ampl
+ CONSTANT c_wg_ampl_full_scale : NATURAL := 2**(c_sdp_W_adc-1); -- full scale (FS) of WG, will just cause clipping of +FS to +FS-1
+ CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / REAL(c_wg_ampl_full_scale); -- amplitude in number of LSbit resolution steps
+ CONSTANT c_wg_ampl : NATURAL := NATURAL(g_sp_ampl * REAL(c_wg_ampl_full_scale)); -- in number of lsb
+ CONSTANT c_wg_remnant_ampl : NATURAL := NATURAL(g_sp_remnant_ampl * REAL(c_wg_ampl_full_scale)); -- in number of lsb
+ CONSTANT c_exp_sp_power : REAL := REAL(c_wg_ampl**2) / 2.0;
+ CONSTANT c_exp_sp_ast : REAL := c_exp_sp_power * REAL(c_nof_clk_per_sync);
+ -- . phase
+ CONSTANT c_subband_freq : REAL := REAL(g_subband) / REAL(c_sdp_N_fft); -- normalized by fs = f_adc = 200 MHz = dp_clk rate
+ CONSTANT c_wg_latency : INTEGER := c_diag_wg_latency - 0; -- -0 to account for BSN scheduler start trigger latency
+ CONSTANT c_wg_phase_offset : REAL := 360.0 * REAL(c_wg_latency) * c_subband_freq; -- c_diag_wg_latency is in dp_clk cycles
+ CONSTANT c_wg_phase : REAL := g_sp_phase + c_wg_phase_offset; -- WG phase in degrees
+ CONSTANT c_wg_remnant_phase : REAL := g_sp_remnant_phase + c_wg_phase_offset; -- WG phase in degrees
+ -- . freq
+ CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
+
+ -- WPFB
+ CONSTANT c_pol_index : NATURAL := g_sp MOD c_sdp_Q_fft;
+ CONSTANT c_pfb_index : NATURAL := g_sp / c_sdp_Q_fft; -- only read used WPFB unit out of range(c_sdp_P_pfb = 6)
+ CONSTANT c_subband_phase_offset : REAL := -90.0; -- WG with zero phase sinus yields subband with -90 degrees phase (negative Im, zero Re)
+ CONSTANT c_subband_weight_gain : REAL := 1.0; -- use default unit subband weights
+ CONSTANT c_subband_weight_phase : REAL := 0.0; -- use default unit subband weights
+ CONSTANT c_exp_subband_phase : REAL := g_sp_phase + c_subband_phase_offset + c_subband_weight_phase;
+ CONSTANT c_exp_subband_ampl : REAL := REAL(c_wg_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
+ CONSTANT c_exp_subband_power : REAL := c_exp_subband_ampl**2.0; -- complex signal ampl, so no divide by 2
+ CONSTANT c_exp_subband_sst : REAL := c_exp_subband_power * REAL(c_nof_block_per_sync);
+
+ CONSTANT c_exp_remnant_subband_phase : REAL := g_sp_remnant_phase + c_subband_phase_offset + c_subband_weight_phase;
+ CONSTANT c_exp_remnant_subband_ampl : REAL := REAL(c_wg_remnant_ampl) * c_sdp_wpfb_subband_sp_ampl_ratio * c_subband_weight_gain;
+
+ TYPE t_real_arr IS ARRAY (INTEGER RANGE <>) OF REAL;
+ TYPE t_slv_64_subbands_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_sub-1); -- 512
+ TYPE t_slv_64_beamlets_arr IS ARRAY (INTEGER RANGE <>) OF t_slv_64_arr(0 TO c_sdp_N_beamlets_sdp-1); -- 2*488 = 976
+
+ -- BF X-pol and Y-pol
+ -- . select
+ CONSTANT c_exp_beamlet_x_index : NATURAL := g_beamlet * c_sdp_N_pol_bf; -- X index in beamset 0
+ CONSTANT c_exp_beamlet_y_index : NATURAL := g_beamlet * c_sdp_N_pol_bf + 1; -- Y index in beamset 0
+ -- . Beamlet weights for selected g_sp
+ CONSTANT c_bf_x_weight_re : INTEGER := INTEGER(COMPLEX_RE(g_bf_x_gain * REAL(c_sdp_unit_bf_weight), g_bf_x_phase));
+ CONSTANT c_bf_x_weight_im : INTEGER := INTEGER(COMPLEX_IM(g_bf_x_gain * REAL(c_sdp_unit_bf_weight), g_bf_x_phase));
+ CONSTANT c_bf_y_weight_re : INTEGER := INTEGER(COMPLEX_RE(g_bf_y_gain * REAL(c_sdp_unit_bf_weight), g_bf_y_phase));
+ CONSTANT c_bf_y_weight_im : INTEGER := INTEGER(COMPLEX_IM(g_bf_y_gain * REAL(c_sdp_unit_bf_weight), g_bf_y_phase));
+ CONSTANT c_bf_remnant_x_weight_re : INTEGER := INTEGER(COMPLEX_RE(g_bf_remnant_x_gain * REAL(c_sdp_unit_bf_weight), g_bf_remnant_x_phase));
+ CONSTANT c_bf_remnant_x_weight_im : INTEGER := INTEGER(COMPLEX_IM(g_bf_remnant_x_gain * REAL(c_sdp_unit_bf_weight), g_bf_remnant_x_phase));
+ CONSTANT c_bf_remnant_y_weight_re : INTEGER := INTEGER(COMPLEX_RE(g_bf_remnant_y_gain * REAL(c_sdp_unit_bf_weight), g_bf_remnant_y_phase));
+ CONSTANT c_bf_remnant_y_weight_im : INTEGER := INTEGER(COMPLEX_IM(g_bf_remnant_y_gain * REAL(c_sdp_unit_bf_weight), g_bf_remnant_y_phase));
+
+ -- Model the SDP beamformer for one g_sp and S_pn-1 = 11 remnant signal inputs
+ FUNCTION bf_calculate_expected_beamlet(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
+ rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : REAL) RETURN t_real_arr IS -- 0:3 = ampl, phase, re, im
+ CONSTANT c_nof_rem : REAL := REAL(c_nof_rn * c_sdp_S_pn - 1); -- BF for one g_sp and N_rn * S_PN - 1 remnant signal inputs
+ VARIABLE v_sp_ampl, v_sp_phase, v_sp_re, v_sp_im : REAL;
+ VARIABLE v_rem_ampl, v_rem_phase, v_rem_re, v_rem_im : REAL;
+ VARIABLE v_sum_ampl, v_sum_phase, v_sum_re, v_sum_im : REAL;
+ VARIABLE v_tuple : t_real_arr(0 TO 3);
+ BEGIN
+ v_sp_ampl := sp_subband_ampl * sp_bf_gain;
+ v_sp_phase := sp_subband_phase + sp_bf_phase;
+ v_sp_re := COMPLEX_RE(v_sp_ampl, v_sp_phase);
+ v_sp_im := COMPLEX_IM(v_sp_ampl, v_sp_phase);
+ v_rem_ampl := rem_subband_ampl * rem_bf_gain;
+ v_rem_phase := rem_subband_phase + rem_bf_phase;
+ v_rem_re := COMPLEX_RE(v_rem_ampl, v_rem_phase);
+ v_rem_im := COMPLEX_IM(v_rem_ampl, v_rem_phase);
+ v_sum_re := v_sp_re + c_nof_rem * v_rem_re; -- BF sum re
+ v_sum_im := v_sp_im + c_nof_rem * v_rem_im; -- BF sum im
+ v_sum_ampl := COMPLEX_RADIUS(v_sum_re, v_sum_im);
+ v_sum_phase := COMPLEX_PHASE(v_sum_re, v_sum_im);
+ v_tuple := (0 => v_sum_ampl, 1 => v_sum_phase, 2 => v_sum_re, 3 => v_sum_im);
+ RETURN v_tuple;
+ END;
+
+ -- . Beamlet internal
+ CONSTANT c_exp_beamlet_x_tuple : t_real_arr(0 TO 3) := bf_calculate_expected_beamlet(
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_x_gain, g_bf_x_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_x_gain, g_bf_remnant_x_phase);
+ CONSTANT c_exp_beamlet_x_ampl : REAL := c_exp_beamlet_x_tuple(0);
+ CONSTANT c_exp_beamlet_x_phase : REAL := c_exp_beamlet_x_tuple(1);
+ CONSTANT c_exp_beamlet_x_re : REAL := c_exp_beamlet_x_tuple(2);
+ CONSTANT c_exp_beamlet_x_im : REAL := c_exp_beamlet_x_tuple(3);
+
+ CONSTANT c_exp_beamlet_y_tuple : t_real_arr(0 TO 3) := bf_calculate_expected_beamlet(
+ c_exp_subband_ampl, c_exp_subband_phase, g_bf_y_gain, g_bf_y_phase,
+ c_exp_remnant_subband_ampl, c_exp_remnant_subband_phase, g_bf_remnant_y_gain, g_bf_remnant_y_phase);
+ CONSTANT c_exp_beamlet_y_ampl : REAL := c_exp_beamlet_y_tuple(0);
+ CONSTANT c_exp_beamlet_y_phase : REAL := c_exp_beamlet_y_tuple(1);
+ CONSTANT c_exp_beamlet_y_re : REAL := c_exp_beamlet_y_tuple(2);
+ CONSTANT c_exp_beamlet_y_im : REAL := c_exp_beamlet_y_tuple(3);
+ -- . BST
+ CONSTANT c_exp_beamlet_x_power : REAL := c_exp_beamlet_x_ampl**2.0; -- complex signal ampl, so no divide by 2
+ CONSTANT c_exp_beamlet_x_bst : REAL := c_exp_beamlet_x_power * REAL(c_nof_block_per_sync);
+ CONSTANT c_exp_beamlet_y_power : REAL := c_exp_beamlet_y_ampl**2.0; -- complex signal ampl, so no divide by 2
+ CONSTANT c_exp_beamlet_y_bst : REAL := c_exp_beamlet_y_power * REAL(c_nof_block_per_sync);
+ -- . Beamlet output
+ CONSTANT c_exp_beamlet_x_output_ampl : REAL := c_exp_beamlet_x_ampl * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_x_output_phase : REAL := c_exp_beamlet_x_phase;
+ CONSTANT c_exp_beamlet_x_output_re : REAL := c_exp_beamlet_x_re * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_x_output_im : REAL := c_exp_beamlet_x_im * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_y_output_ampl : REAL := c_exp_beamlet_y_ampl * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_y_output_phase : REAL := c_exp_beamlet_y_phase;
+ CONSTANT c_exp_beamlet_y_output_re : REAL := c_exp_beamlet_y_re * g_beamlet_scale;
+ CONSTANT c_exp_beamlet_y_output_im : REAL := c_exp_beamlet_y_im * g_beamlet_scale;
+
+ -- MM
+ -- . Address widths of a single MM instance
+ -- . c_sdp_S_pn = 12 instances
+ CONSTANT c_addr_w_reg_diag_wg : NATURAL := 2;
+ -- . c_sdp_N_beamsets = 2 instances
+ CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
+ CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+ CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
+ CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol_bf*c_stat_data_sz);
+ -- . Address spans of a single MM instance
+ -- . c_sdp_S_pn = 12 instances
+ CONSTANT c_mm_span_reg_diag_wg : NATURAL := 2**c_addr_w_reg_diag_wg;
+ -- . c_sdp_N_beamsets = 2 instances
+ CONSTANT c_mm_span_ram_ss_ss_wide : NATURAL := 2**c_addr_w_ram_ss_ss_wide;
+ CONSTANT c_mm_span_ram_bf_weights : NATURAL := 2**c_addr_w_ram_bf_weights;
+ CONSTANT c_mm_span_reg_bf_scale : NATURAL := 2**c_addr_w_reg_bf_scale;
+ CONSTANT c_mm_span_reg_hdr_dat : NATURAL := 2**c_addr_w_reg_hdr_dat;
+ CONSTANT c_mm_span_reg_dp_xonoff : NATURAL := 2**c_addr_w_reg_dp_xonoff;
+ CONSTANT c_mm_span_ram_st_bst : NATURAL := 2**c_addr_w_ram_st_bst;
+
+ CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_ram_equalizer_gains : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_EQUALIZER_GAINS";
+ CONSTANT c_mm_file_reg_dp_selector : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_SELECTOR";
+ CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
+ CONSTANT c_mm_file_ram_st_bst : STRING := mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "RAM_ST_BST"; --end RN
+ CONSTANT c_mm_file_reg_dp_xonoff : STRING := mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "REG_DP_XONOFF"; --end RN
+ CONSTANT c_mm_file_ram_ss_ss_wide : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_SS_SS_WIDE";
+ CONSTANT c_mm_file_ram_bf_weights : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_BF_WEIGHTS";
+ CONSTANT c_mm_file_reg_bf_scale : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BF_SCALE";
+ CONSTANT c_mm_file_reg_sdp_info : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
+ CONSTANT c_mm_file_reg_hdr_dat : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_HDR_DAT"; -- c_sdp_N_beamsets = 2 beamsets
+
+ -- Tb
+ SIGNAL stimuli_done : STD_LOGIC := '0';
+ SIGNAL tb_almost_end : STD_LOGIC := '0';
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+ SIGNAL dest_rst : STD_LOGIC := '1'; -- use separate destination rst for Rx 10GbE in tb
+ SIGNAL pps_rst : STD_LOGIC := '1'; -- use separate reset to release the PPS generator
+ SIGNAL gen_pps : STD_LOGIC := '0';
+
+ SIGNAL in_sync : STD_LOGIC := '0';
+ SIGNAL in_sync_cnt : NATURAL := 0;
+ SIGNAL test_sync_cnt : INTEGER := 0;
+
+ -- MM
+ SIGNAL rd_sdp_info : t_sdp_info := c_sdp_info_rst;
+ SIGNAL rd_beamlet_scale : STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL rd_cep_eth_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0);
+ SIGNAL rd_cep_ip_dst_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL rd_cep_udp_dst_port : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+ -- WG
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- FSUB
+ -- . Read sp_ssts_arr2 = SST for one WPFB unit that processes g_sp
+ SIGNAL sp_ssts_arr2 : t_slv_64_subbands_arr(c_sdp_N_pol-1 DOWNTO 0); -- [pol][sub], for X,Y pair of A, B
+ SIGNAL sp_sst : REAL := 0.0;
+ SIGNAL stat_data : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);
+
+ -- . Selector
+ SIGNAL sst_weighted_subbands_flag : STD_LOGIC;
+
+ -- . Subband equalizer
+ SIGNAL sp_subband_weight_re : INTEGER := 0;
+ SIGNAL sp_subband_weight_im : INTEGER := 0;
+ SIGNAL sp_subband_weight_gain : REAL := 0.0;
+ SIGNAL sp_subband_weight_phase : REAL := 0.0;
+
+ -- BF
+ -- . beamlet subband selection
+ SIGNAL sp_subband_select : NATURAL := 0;
+ SIGNAL sp_subband_select_arr : t_natural_arr(0 TO c_sdp_S_sub_bf * c_sdp_N_pol-1) := (OTHERS => 0); -- Q_fft = N_pol = 2
+
+ -- . beamlet X-pol
+ SIGNAL sp_bf_x_weights_re_arr : t_integer_arr(0 TO c_nof_rn * c_sdp_S_pn-1) := (OTHERS => 0);
+ SIGNAL sp_bf_x_weights_im_arr : t_integer_arr(0 TO c_nof_rn * c_sdp_S_pn-1) := (OTHERS => 0);
+ SIGNAL sp_bf_x_weights_gain_arr : t_real_arr(0 TO c_nof_rn * c_sdp_S_pn-1) := (OTHERS => 0.0);
+ SIGNAL sp_bf_x_weights_phase_arr : t_real_arr(0 TO c_nof_rn * c_sdp_S_pn-1) := (OTHERS => 0.0);
+ -- . beamlet Y-pol
+ SIGNAL sp_bf_y_weights_re_arr : t_integer_arr(0 TO c_nof_rn * c_sdp_S_pn-1) := (OTHERS => 0);
+ SIGNAL sp_bf_y_weights_im_arr : t_integer_arr(0 TO c_nof_rn * c_sdp_S_pn-1) := (OTHERS => 0);
+ SIGNAL sp_bf_y_weights_gain_arr : t_real_arr(0 TO c_nof_rn * c_sdp_S_pn-1) := (OTHERS => 0.0);
+ SIGNAL sp_bf_y_weights_phase_arr : t_real_arr(0 TO c_nof_rn * c_sdp_S_pn-1) := (OTHERS => 0.0);
+
+ -- . BST
+ SIGNAL bsts_arr2 : t_slv_64_beamlets_arr(c_sdp_N_pol_bf-1 DOWNTO 0); -- [pol_bf][blet]
+ SIGNAL bst_x_arr : t_real_arr(0 TO c_sdp_N_beamsets-1) := (OTHERS => 0.0); -- [bset] for BF X pol
+ SIGNAL bst_y_arr : t_real_arr(0 TO c_sdp_N_beamsets-1) := (OTHERS => 0.0); -- [bset] for BF Y pol
+
+ -- CEP model
+ -- . 10GbE
+ SIGNAL tr_10GbE_src_out : t_dp_sosi;
+ SIGNAL tr_10GbE_src_in : t_dp_siso;
+ SIGNAL tr_ref_clk_312 : STD_LOGIC := '0';
+ SIGNAL tr_ref_clk_156 : STD_LOGIC := '0';
+ SIGNAL tr_ref_rst_156 : STD_LOGIC := '0';
+
+ -- . dp_offload_rx
+ SIGNAL rx_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL rx_hdr_dat_miso : t_mem_miso;
+
+ SIGNAL rx_hdr_fields_out : STD_LOGIC_VECTOR(1023 DOWNTO 0);
+ SIGNAL rx_hdr_fields_raw : STD_LOGIC_VECTOR(1023 DOWNTO 0) := (OTHERS => '0');
+
+ -- Beamlets packets header
+ SIGNAL rx_sdp_cep_header : t_sdp_cep_header;
+ SIGNAL exp_sdp_cep_header : t_sdp_cep_header;
+ SIGNAL exp_dp_bsn : NATURAL;
+
+ -- Beamlets packets data
+ SIGNAL rx_beamlet_data : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0); -- 64 bit
+ SIGNAL rx_beamlet_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL rx_beamlet_sop_cnt : NATURAL := 0;
+ SIGNAL rx_beamlet_eop_cnt : NATURAL := 0;
+
+ SIGNAL rx_beamlet_arr_re : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
+ SIGNAL rx_beamlet_arr_im : t_slv_8_arr(c_sdp_cep_nof_blocks_per_packet-1 DOWNTO 0); -- [3:0]
+ SIGNAL rx_beamlet_cnt : NATURAL;
+ SIGNAL rx_beamlet_valid : STD_LOGIC;
+
+ SIGNAL rx_beamlet_list_re : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
+ SIGNAL rx_beamlet_list_im : t_slv_8_arr(c_sdp_cep_nof_beamlets_per_block * c_sdp_N_pol_bf-1 DOWNTO 0); -- [488 * 2-1:0] = [975:0]
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
+
+ SIGNAL SA_CLK : STD_LOGIC := '1';
+ SIGNAL i_QSFP_0_TX : t_unb2c_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_QSFP_0_RX : t_unb2c_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_0_TX : t_unb2c_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_0_RX : t_unb2c_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_1_TX : t_unb2c_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_RING_1_RX : t_unb2c_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+ SIGNAL i_QSFP_1_lpbk : t_unb2c_board_qsfp_bus_2arr(c_nof_rn -1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sync_n : STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0);
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+ SA_CLK <= NOT SA_CLK AFTER c_sa_clk_period/2; -- Serial Gigabit IO sa clock (644 MHz)
+ dest_rst <= '0' AFTER c_ext_clk_period * 10;
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(5, c_pps_period, '1', pps_rst, ext_clk, gen_pps);
+ jesd204b_sysref <= gen_pps;
+ ext_pps <= gen_pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ gen_dut : FOR RN IN 0 TO c_nof_rn -1 GENERATE
+ u_lofar_unb2c_sdp_station_bf : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2c_sdp_station_bf_ring",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr + (RN / c_quad),
+ g_sim_node_nr => RN MOD c_quad,
+ g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => g_subband
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => ( TO_UVEC(RN / c_quad, c_unb2c_board_nof_uniboard_w) & TO_UVEC(RN MOD c_quad, c_unb2c_board_nof_chip_w) ),
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+ -- front transceivers for ring
+ QSFP_0_RX => i_QSFP_0_RX(RN),
+ QSFP_0_TX => i_QSFP_0_TX(RN),
+
+ -- ring transceivers
+ RING_0_RX => i_RING_0_RX(RN),
+ RING_0_TX => i_RING_0_TX(RN),
+ RING_1_RX => i_RING_1_RX(RN),
+ RING_1_TX => i_RING_1_TX(RN),
+
+ -- front transceivers for CEP
+ QSFP_1_RX => i_QSFP_1_lpbk(RN),
+ QSFP_1_TX => i_QSFP_1_lpbk(RN),
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref,
+ JESD204B_SYNC_N => jesd204b_sync_n
+ );
+ END GENERATE;
+
+ -- Ring connections
+ gen_ring : FOR I IN 0 TO c_nof_rn -2 GENERATE
+ -- Connect consecutive nodes with RING interfaces (PCB)
+ i_RING_0_RX(I+1) <= i_RING_1_TX(I);
+ i_RING_1_RX(I) <= i_RING_0_TX(I+1);
+ END GENERATE;
+
+ -- Connect first and last nodes with QSFP interface.
+ i_QSFP_0_RX(0) <= i_QSFP_0_TX(c_nof_rn-1);
+ i_QSFP_0_RX(c_nof_rn-1) <= i_QSFP_0_TX(0);
+
+
+
+ ------------------------------------------------------------------------------
+ -- CEP model
+ ------------------------------------------------------------------------------
+ u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+ PORT MAP (
+ refclk_644 => SA_CLK,
+ rst_in => dest_rst,
+ clk_156 => tr_ref_clk_156,
+ clk_312 => tr_ref_clk_312,
+ rst_156 => tr_ref_rst_156,
+ rst_312 => OPEN
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP (
+ g_sim => TRUE,
+ g_sim_level => 1,
+ g_nof_macs => 1,
+ g_use_mdio => FALSE
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R
+ tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI
+ tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI
+
+ -- MM interface
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ -- DP interface
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ serial_rx_arr(0) => i_QSFP_1_lpbk(c_nof_rn-1)(0), -- Last RN must be used as end node.
+
+ src_out_arr(0) => tr_10GbE_src_out,
+ src_in_arr(0) => tr_10GbE_src_in
+ );
+
+
+ u_rx : ENTITY dp_lib.dp_offload_rx
+ GENERIC MAP (
+ g_nof_streams => 1,
+ g_data_w => c_longword_w,
+ g_symbol_w => c_octet_w,
+ g_hdr_field_arr => c_sdp_cep_hdr_field_arr,
+ g_remove_crc => FALSE,
+ g_crc_nof_words => 0
+ )
+ PORT MAP (
+ mm_rst => dest_rst,
+ mm_clk => tb_clk,
+
+ dp_rst => dest_rst,
+ dp_clk => ext_clk,
+
+ reg_hdr_dat_mosi => rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => rx_hdr_dat_miso,
+
+ snk_in_arr(0) => tr_10GbE_src_out,
+ snk_out_arr(0) => tr_10GbE_src_in,
+
+ src_out_arr(0) => rx_beamlet_sosi,
+
+ hdr_fields_out_arr(0) => rx_hdr_fields_out,
+ hdr_fields_raw_arr(0) => rx_hdr_fields_raw
+ );
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_sst : REAL := 0.0;
+ VARIABLE v_bst : REAL := 0.0;
+ VARIABLE v_data_lo, v_data_hi : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ VARIABLE v_stat_data : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0);
+ VARIABLE v_len, v_span, v_offset, v_addr, v_sel : NATURAL; -- address ranges, indices
+ VARIABLE v_W, v_P, v_PB, v_S, v_A, v_B, v_G : NATURAL; -- array indicies
+ VARIABLE v_re, v_im, v_weight : INTEGER;
+ VARIABLE v_re_exp, v_im_exp : REAL := 0.0;
+ BEGIN
+ -- Wait for DUT power up after reset
+ WAIT FOR 1 us;
+
+ print_str("");
+ print_str("WG:");
+ print_str(". c_wg_ampl = " & int_to_str(c_wg_ampl));
+ print_str(". c_exp_sp_power = " & real_to_str(c_exp_sp_power, 20, 1));
+ print_str(". c_exp_sp_ast = " & real_to_str(c_exp_sp_ast, 20, 1));
+
+ print_str("");
+ print_str("Subband weight:");
+ print_str(". sp_subband_weight_gain = " & real_to_str(sp_subband_weight_gain, 20, 6));
+ print_str(". sp_subband_weight_phase = " & real_to_str(sp_subband_weight_phase, 20, 6));
+
+ print_str("");
+ print_str("SST results:");
+ print_str(". sst_weighted_subbands_flag = " & sl_to_str(sst_weighted_subbands_flag));
+ print_str("");
+ print_str(". c_exp_subband_ampl = " & int_to_str(NATURAL(c_exp_subband_ampl)));
+ print_str(". c_exp_subband_power = " & real_to_str(c_exp_subband_power, 20, 1));
+ print_str(". c_exp_subband_sst = " & real_to_str(c_exp_subband_sst, 20, 1));
+ print_str("");
+ print_str(". sp_sst = " & real_to_str(sp_sst, 20, 1));
+ print_str(". sp_sst / c_exp_subband_sst = " & real_to_str(sp_sst / c_exp_subband_sst, 20, 6));
+
+ print_str("");
+ print_str("BST results:");
+ print_str(". c_exp_beamlet_x_ampl = " & int_to_str(NATURAL(c_exp_beamlet_x_ampl)));
+ print_str(". c_exp_beamlet_x_power = " & real_to_str(c_exp_beamlet_x_power, 20, 1));
+ print_str(". c_exp_beamlet_x_bst = " & real_to_str(c_exp_beamlet_x_bst, 20, 1));
+ print_str("");
+ print_str(". c_exp_beamlet_y_ampl = " & int_to_str(NATURAL(c_exp_beamlet_y_ampl)));
+ print_str(". c_exp_beamlet_y_power = " & real_to_str(c_exp_beamlet_y_power, 20, 1));
+ print_str(". c_exp_beamlet_y_bst = " & real_to_str(c_exp_beamlet_y_bst, 20, 1));
+ print_str("");
+
+ ----------------------------------------------------------------------------
+ -- Set and check SDP info
+ ----------------------------------------------------------------------------
+ -- TYPE t_sdp_info IS RECORD
+ -- 7 station_id : STD_LOGIC_VECTOR(15 DOWNTO 0);
+ -- 6 antenna_band_index : STD_LOGIC;
+ -- 5 observation_id : STD_LOGIC_VECTOR(31 DOWNTO 0);
+ -- 4 nyquist_zone_index : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ -- 3 f_adc : STD_LOGIC;
+ -- 2 fsub_type : STD_LOGIC;
+ -- 1 beam_repositioning_flag : STD_LOGIC;
+ -- 0 block_period : STD_LOGIC_VECTOR(15 DOWNTO 0);
+ -- END RECORD;
+ -- . Write
+
+
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_SDP_INFO", 7, TO_UINT(c_exp_sdp_info.station_id), tb_clk);
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_SDP_INFO", 6, TO_UINT(slv(c_exp_sdp_info.antenna_band_index)), tb_clk);
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_SDP_INFO", 5, TO_UINT(c_exp_sdp_info.observation_id), tb_clk);
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_SDP_INFO", 4, TO_UINT(c_exp_sdp_info.nyquist_zone_index), tb_clk);
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_SDP_INFO", 1, TO_UINT(slv(c_exp_sdp_info.beam_repositioning_flag)), tb_clk);
+ -- . Read
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_SDP_INFO", 3, rd_data, tb_clk); rd_sdp_info.f_adc <= rd_data(0);
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_SDP_INFO", 2, rd_data, tb_clk); rd_sdp_info.fsub_type <= rd_data(0);
+ mmf_mm_bus_rd(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_SDP_INFO", 0, rd_data, tb_clk); rd_sdp_info.block_period <= rd_data(15 DOWNTO 0);
+ END LOOP;
+
+ proc_common_wait_some_cycles(tb_clk, 1);
+ -- . Verify read
+ ASSERT c_exp_sdp_info.f_adc = rd_sdp_info.f_adc REPORT "Wrong MM read SDP info f_adc" SEVERITY ERROR;
+ ASSERT c_exp_sdp_info.fsub_type = rd_sdp_info.fsub_type REPORT "Wrong MM read SDP info fsub_type" SEVERITY ERROR;
+ ASSERT c_exp_sdp_info.block_period = rd_sdp_info.block_period REPORT "Wrong MM read SDP info block_period" SEVERITY ERROR;
+
+ ------------------------------------------------------------------------------
+ ---- Set and check BF per beamset
+ ------------------------------------------------------------------------------
+ FOR bset IN 0 TO c_sdp_N_beamsets-1 LOOP
+ -- MM beamlet_scale
+ -- . write
+ v_offset := bset * c_mm_span_reg_bf_scale;
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BF_SCALE", v_offset + 0, c_exp_beamlet_scale, tb_clk);
+ END LOOP;
+ proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_ext_clk_period);
+
+ -- . readback
+ mmf_mm_bus_rd(c_mm_file_reg_bf_scale, v_offset + 0, rd_data, tb_clk);
+ rd_beamlet_scale <= rd_data(15 DOWNTO 0);
+ proc_common_wait_some_cycles(tb_clk, 1);
+ ASSERT TO_UINT(rd_beamlet_scale) = c_exp_beamlet_scale REPORT "Wrong MM read beamlet_scale for beamset " & NATURAL'IMAGE(bset) SEVERITY ERROR;
+
+ -- CEP beamlet output header
+ -- c_sdp_cep_hdr_field_arr : t_common_field_arr(c_sdp_cep_nof_hdr_fields-1 DOWNTO 0) := (
+ -- 40 "eth_dst_mac" ), "RW", 48, field_default(c_sdp_cep_eth_dst_mac) ),
+ -- 38 "eth_src_mac" ), "RW", 48, field_default(0) ),
+ -- 37 "eth_type" ), "RW", 16, field_default(x"0800") ),
+ --
+ -- 36 "ip_version" ), "RW", 4, field_default(4) ),
+ -- 35 "ip_header_length" ), "RW", 4, field_default(5) ),
+ -- 34 "ip_services" ), "RW", 8, field_default(0) ),
+ -- 33 "ip_total_length" ), "RW", 16, field_default(c_sdp_cep_ip_total_length) ),
+ -- 32 "ip_identification" ), "RW", 16, field_default(0) ),
+ -- 31 "ip_flags" ), "RW", 3, field_default(2) ),
+ -- 30 "ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ -- 29 "ip_time_to_live" ), "RW", 8, field_default(127) ),
+ -- 28 "ip_protocol" ), "RW", 8, field_default(17) ),
+ -- 27 "ip_header_checksum" ), "RW", 16, field_default(0) ),
+ -- 26 "ip_src_addr" ), "RW", 32, field_default(0) ),
+ -- 25 "ip_dst_addr" ), "RW", 32, field_default(c_sdp_cep_ip_dst_addr) ),
+ --
+ -- 24 "udp_src_port" ), "RW", 16, field_default(0) ),
+ -- 23 "udp_dst_port" ), "RW", 16, field_default(c_sdp_cep_udp_dst_port) ),
+ -- 22 "udp_total_length" ), "RW", 16, field_default(c_sdp_cep_udp_total_length) ),
+ -- 21 "udp_checksum" ), "RW", 16, field_default(0) ),
+ --
+ -- 20 "sdp_marker" ), "RW", 8, field_default(c_sdp_marker_beamlets) ),
+ -- 19 "sdp_version_id" ), "RW", 8, field_default(c_sdp_cep_version_id) ),
+ -- 18 "sdp_observation_id" ), "RW", 32, field_default(0) ),
+ -- 17 "sdp_station_id" ), "RW", 16, field_default(0) ),
+ --
+ -- 16 "sdp_source_info_antenna_band_id" ), "RW", 1, field_default(0) ),
+ -- 15 "sdp_source_info_nyquist_zone_id" ), "RW", 2, field_default(0) ),
+ -- 14 "sdp_source_info_f_adc" ), "RW", 1, field_default(0) ),
+ -- 13 "sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
+ -- 12 "sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
+ -- 11 "sdp_source_info_repositioning_flag" ), "RW", 1, field_default(0) ),
+ -- 10 "sdp_source_info_beamlet_width" ), "RW", 4, field_default(c_sdp_W_beamlet) ),
+ -- 9 "sdp_source_info_gn_id" ), "RW", 5, field_default(0) ),
+ --
+ -- 7 "sdp_reserved" ), "RW", 40, field_default(0) ),
+ -- 6 "sdp_beamlet_scale" ), "RW", 16, field_default(c_sdp_beamlet_scale_default) ),
+ -- 5 "sdp_beamlet_index" ), "RW", 16, field_default(0) ),
+ -- 4 "sdp_nof_blocks_per_packet" ), "RW", 8, field_default(c_sdp_cep_nof_blocks_per_packet) ),
+ -- 3 "sdp_nof_beamlets_per_block" ), "RW", 16, field_default(c_sdp_cep_nof_beamlets_per_block) ),
+ -- 2 "sdp_block_period" ), "RW", 16, field_default(c_sdp_block_period) ),
+ --
+ -- 0 "dp_bsn" ), "RW", 64, field_default(0) )
+ -- );
+
+ v_offset := bset * c_mm_span_reg_hdr_dat;
+ -- . Use defaults, so no need to write
+ -- . Read
+ mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 41, rd_data, tb_clk); rd_cep_eth_dst_mac(47 DOWNTO 32) <= rd_data(15 DOWNTO 0);
+ mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 40, rd_data, tb_clk); rd_cep_eth_dst_mac(31 DOWNTO 0) <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 25, rd_data, tb_clk); rd_cep_ip_dst_addr <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_reg_hdr_dat, v_offset + 23, rd_data, tb_clk); rd_cep_udp_dst_port <= rd_data(15 DOWNTO 0);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- verify read
+ ASSERT rd_cep_eth_dst_mac = c_sdp_cep_eth_dst_mac REPORT "Wrong MM read rd_cep_eth_dst_mac for beamset " & NATURAL'IMAGE(bset) SEVERITY ERROR; -- 00074306C700 = DOP36-eth0
+ ASSERT rd_cep_ip_dst_addr = c_sdp_cep_ip_dst_addr REPORT "Wrong MM read rd_cep_ip_dst_addr for beamset " & NATURAL'IMAGE(bset) SEVERITY ERROR; -- C0A80001 = '192.168.0.1' = DOP36-eth0
+ ASSERT rd_cep_udp_dst_port = c_sdp_cep_udp_dst_port REPORT "Wrong MM read rd_cep_udp_dst_port for beamset " & NATURAL'IMAGE(bset) SEVERITY ERROR; -- 5000
+
+ ----------------------------------------------------------------------------
+ -- Enable beamlet UDP offload off end node (dp_xonoff)
+ ----------------------------------------------------------------------------
+ v_offset := bset * c_mm_span_reg_dp_xonoff;
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff, v_offset + 0, 1, tb_clk);
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- Enable BS
+ ----------------------------------------------------------------------------
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SOURCE_V2", 2, c_init_bsn, tb_clk); -- Init BSN
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SOURCE_V2", 3, 0, tb_clk); -- Write high part a
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SOURCE_V2", 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_syn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SOURCE_V2", 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ END LOOP;
+
+ -- Release PPS pulser, to get first PPS now and to start BSN source
+ WAIT FOR 1 us;
+ pps_rst <= '0';
+
+ ----------------------------------------------------------------------------
+ -- Ring config
+ ----------------------------------------------------------------------------
+ -- Write ring configuration to all nodes.
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_INFO", 2, c_nof_rn, tb_clk); -- N_rn
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_INFO", 3, 0, tb_clk); -- O_rn
+ END LOOP;
+
+ -- Start node specific settings
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 0, 1, tb_clk); -- use_ring_to_previous_rn = 1
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr, 0) & "REG_RING_INFO", 1, 0, tb_clk); -- use_ring_to_next_rn = 0
+
+ -- End node specific settings
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 0, 0, tb_clk); -- use_ring_to_previous_rn = 0
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + ((c_nof_rn-1) / c_quad), (c_nof_rn-1) MOD c_quad) & "REG_RING_INFO", 1, 1, tb_clk); -- use_ring_to_next_rn = 1
+
+ -- Access scheme 1. Each RN uses and sends them along the ring.
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ FOR I IN 0 TO c_nof_lanes-1 LOOP
+ IF RN = c_nof_rn-1 THEN
+ -- End RN, so set transport_nof_hops to 0.
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_LANE_INFO_BF", I*2+1, 0, tb_clk);
+ ELSE
+ -- Set transport_nof_hops to 1 on all nodes.
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_RING_LANE_INFO_BF", I*2+1, 1, tb_clk);
+ END IF;
+ END LOOP;
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- Enable and start WG
+ ----------------------------------------------------------------------------
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ -- . Put wanted signal on g_sp input and remnant signal on the other inputs
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ IF RN * c_sdp_S_pn + I = g_sp THEN
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 1, INTEGER(c_wg_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 2, INTEGER(REAL(g_subband) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 3, INTEGER(REAL(c_wg_ampl) * c_wg_ampl_lsb), tb_clk); -- ampl
+ ELSE
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 1, INTEGER(c_wg_remnant_phase * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 2, INTEGER(REAL(g_subband) * c_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_WG", I*4 + 3, INTEGER(REAL(c_wg_remnant_ampl) * c_wg_ampl_lsb), tb_clk); -- ampl
+ END IF;
+ END LOOP;
+ END LOOP;
+
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SCHEDULER", 0, c_bsn_start_wg, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "REG_BSN_SCHEDULER", 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ END LOOP;
+
+ ----------------------------------------------------------------------------
+ -- Read weighted subband selector
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_rd(c_mm_file_reg_dp_selector, 0, rd_data, tb_clk);
+ sst_weighted_subbands_flag <= NOT rd_data(0);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ ----------------------------------------------------------------------------
+ -- Subband weight
+ ----------------------------------------------------------------------------
+
+ -- . MM format: (cint16)RAM_EQUALIZER_GAINS[S_pn/Q_fft]_[Q_fft][N_sub] = [S_pn][N_sub]
+ v_addr := g_sp * c_sdp_N_sub + g_subband;
+ -- . read
+ mmf_mm_bus_rd(c_mm_file_ram_equalizer_gains, v_addr, rd_data, tb_clk);
+ v_re := unpack_complex_re(rd_data, c_sdp_W_sub_weight);
+ v_im := unpack_complex_im(rd_data, c_sdp_W_sub_weight);
+ sp_subband_weight_re <= v_re;
+ sp_subband_weight_im <= v_im;
+ sp_subband_weight_gain <= COMPLEX_RADIUS(v_re, v_im) / REAL(c_sdp_unit_sub_weight);
+ sp_subband_weight_phase <= COMPLEX_PHASE(v_re, v_im);
+
+ -- No need to write subband weight, because default it is unit weight
+
+ ----------------------------------------------------------------------------
+ -- Subband select to map subband to beamlet
+ ----------------------------------------------------------------------------
+ -- . MM format: (uint16)RAM_SS_SS_WIDE[N_beamsets][A_pn]_[S_sub_bf][Q_fft], Q_fft = N_pol = 2
+
+ -- . write selection, only for g_beamlet to save sim time
+ v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ -- Same selection for both beamsets
+ -- Select beamlet g_beamlet to subband g_subband
+ FOR A IN 0 TO c_sdp_A_pn-1 LOOP
+ -- Same selection to all SP
+ FOR P IN 0 TO c_sdp_N_pol-1 LOOP
+ v_addr := P + g_beamlet * c_sdp_N_pol + A * v_span + U * c_mm_span_ram_ss_ss_wide;
+ v_sel := P + g_subband * c_sdp_N_pol;
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "RAM_SS_SS_WIDE", v_addr, v_sel, tb_clk);
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ END LOOP;
+
+ -- . read back selection for g_sp = c_pfb_index * c_sdp_N_pol + c_pol_index
+ v_P := c_pol_index;
+ v_A := c_pfb_index;
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ -- Same selection for both beamsets, so fine to use only one sp_subband_select_arr()
+ FOR B IN 0 TO c_sdp_S_sub_bf-1 LOOP
+ -- Same selection for all SP, so fine to only read subband selection for g_sp
+ v_addr := v_P + B * c_sdp_N_pol + v_A * v_span + U * c_mm_span_ram_ss_ss_wide;
+ mmf_mm_bus_rd(c_mm_file_ram_ss_ss_wide, v_addr, rd_data, tb_clk);
+ v_sel := (TO_UINT(rd_data) - v_P) / c_sdp_N_pol;
+ sp_subband_select_arr(B) <= v_sel;
+ sp_subband_select <= v_sel; -- for time series view in Wave window
+ END LOOP;
+ END LOOP;
+ proc_common_wait_some_cycles(tb_clk, 1);
+ proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+
+ ----------------------------------------------------------------------------
+ -- Write beamlet weight for g_beamlet in S_sub_bf
+ ----------------------------------------------------------------------------
+ -- . MM format: (cint16)RAM_BF_WEIGHTS[N_beamsets][N_pol_bf][A_pn]_[N_pol][S_sub_bf]
+
+ -- . write BF weights, only for g_beamlet to save sim time
+ v_span := true_log_pow2(c_sdp_N_pol * c_sdp_S_sub_bf); -- = 1024
+ FOR RN IN 0 TO c_nof_rn-1 LOOP
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ -- Same BF weights for both beamsets
+ FOR PB IN 0 TO c_sdp_N_pol_bf-1 LOOP
+ -- Same BF weights for both beamlet polarizations
+ FOR A IN 0 TO c_sdp_A_pn-1 LOOP
+ FOR P IN 0 TO c_sdp_N_pol-1 LOOP
+ v_S := RN * c_sdp_S_pn + A * c_sdp_N_pol + P;
+ IF v_S = g_sp THEN
+ -- use generic BF weight for g_sp in g_beamlet
+ IF PB = 0 THEN
+ v_weight := pack_complex(re => c_bf_x_weight_re, im => c_bf_x_weight_im, w => c_sdp_W_bf_weight);
+ ELSE
+ v_weight := pack_complex(re => c_bf_y_weight_re, im => c_bf_y_weight_im, w => c_sdp_W_bf_weight);
+ END IF;
+ ELSE
+ -- use the remnant BF weights for the other SP
+ IF PB = 0 THEN
+ v_weight := pack_complex(re => c_bf_remnant_x_weight_re, im => c_bf_remnant_x_weight_im, w => c_sdp_W_bf_weight);
+ ELSE
+ v_weight := pack_complex(re => c_bf_remnant_y_weight_re, im => c_bf_remnant_y_weight_im, w => c_sdp_W_bf_weight);
+ END IF;
+ END IF;
+ v_addr := g_beamlet; -- beamlet index
+ v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
+ v_addr := v_addr + A * v_span; -- antenna input address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN MOD c_quad) & "RAM_BF_WEIGHTS", v_addr, v_weight, tb_clk);
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ END LOOP;
+
+ -- . read back BF weights for g_beamlet in S_sub_bf
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ FOR PB IN 0 TO c_sdp_N_pol_bf-1 LOOP
+ FOR A IN 0 TO c_sdp_A_pn-1 LOOP
+ FOR P IN 0 TO c_sdp_N_pol-1 LOOP
+ v_addr := g_beamlet; -- beamlet index
+ v_addr := v_addr + P * c_sdp_S_sub_bf; -- antenna input polarization address offset
+ v_addr := v_addr + A * v_span; -- antenna input address offset
+ v_addr := v_addr + PB * c_sdp_A_pn * v_span; -- beamlet polarization address offset
+ v_addr := v_addr + U * c_mm_span_ram_bf_weights; -- beamset address offset
+ mmf_mm_bus_rd(c_mm_file_ram_bf_weights, v_addr, rd_data, tb_clk);
+ v_re := unpack_complex_re(rd_data, c_sdp_W_bf_weight);
+ v_im := unpack_complex_im(rd_data, c_sdp_W_bf_weight);
+ -- same BF weights for both beamsets and both beamlet polarizations,
+ -- so fine to use only one sp_bf_x_weights_*_arr()
+ v_S := A * c_sdp_N_pol + P;
+ IF PB = 0 THEN
+ sp_bf_x_weights_re_arr(v_S) <= v_re;
+ sp_bf_x_weights_im_arr(v_S) <= v_im;
+ sp_bf_x_weights_gain_arr(v_S) <= COMPLEX_RADIUS(v_re, v_im) / REAL(c_sdp_unit_bf_weight);
+ sp_bf_x_weights_phase_arr(v_S) <= COMPLEX_PHASE(v_re, v_im);
+ ELSE
+ sp_bf_y_weights_re_arr(v_S) <= v_re;
+ sp_bf_y_weights_im_arr(v_S) <= v_im;
+ sp_bf_y_weights_gain_arr(v_S) <= COMPLEX_RADIUS(v_re, v_im) / REAL(c_sdp_unit_bf_weight);
+ sp_bf_y_weights_phase_arr(v_S) <= COMPLEX_PHASE(v_re, v_im);
+ END IF;
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ END LOOP;
+ proc_common_wait_some_cycles(tb_clk, 1);
+ proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+
+ ----------------------------------------------------------------------------
+ -- Wait for enough WG data and start of sync interval
+ ----------------------------------------------------------------------------
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync*3, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
+
+ -- Stimuli done, now verify results at end of test
+ stimuli_done <= '1';
+
+ ---------------------------------------------------------------------------
+ -- Read subband statistics
+ ---------------------------------------------------------------------------
+ -- . the subband statistics are c_stat_data_sz = 2 word power values.
+ -- . there are c_sdp_S_pn = 12 signal inputs A, B, C, D, E, F, G, H, I, J, K, L
+ -- . there are c_sdp_N_sub = 512 subbands per signal input (SI, = signal path, SP)
+ -- . one complex WPFB can process two real inputs A, B, so there are c_sdp_P_pfb = 6 WPFB units,
+ -- but only read for the 1 WPFB unit of the selected g_sp, to save sim time
+ -- . the outputs for A, B are time multiplexed, c_sdp_Q_fft = 2, assume that they
+ -- correspond to the c_sdp_N_pol = 2 signal polarizations
+ -- . the subbands are output alternately so A0 B0 A1 B1 ... A511 B511 for input A, B
+ -- . the subband statistics multiple WPFB units appear in order in the ram_st_sst address map
+ -- . the subband statistics are stored first lo word 0 then hi word 1
+ v_len := c_sdp_N_sub * c_sdp_N_pol * c_stat_data_sz; -- 2048 = 512 * 2 * 64/32
+ v_span := true_log_pow2(v_len); -- = 2048
+ FOR I IN 0 TO v_len-1 LOOP
+ v_W := I MOD c_stat_data_sz; -- 0, 1 per statistics word, word index
+ v_P := (I / c_stat_data_sz) MOD c_sdp_N_pol; -- 0, 1 per SP pol, polarization index
+ v_B := I / (c_sdp_N_pol * c_stat_data_sz); -- subband index, range(N_sub = 512) per dual pol
+ v_addr := I + c_pfb_index * v_span; -- MM address
+ -- Only read SST for g_subband for dual pol SP, to save sim time
+ IF g_read_all_SST = TRUE OR v_B = g_subband THEN
+ IF v_W=0 THEN
+ -- low part
+ mmf_mm_bus_rd(c_mm_file_ram_st_sst, v_addr, rd_data, tb_clk);
+ v_data_lo := rd_data;
+ ELSE
+ -- high part
+ mmf_mm_bus_rd(c_mm_file_ram_st_sst, v_addr, rd_data, tb_clk);
+ v_data_hi := rd_data;
+ v_stat_data := v_data_hi & v_data_lo;
+
+ sp_ssts_arr2(v_P)(v_B) <= v_stat_data;
+ stat_data <= v_stat_data; -- for time series view in Wave window
+ END IF;
+ END IF;
+ END LOOP;
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Subband power of g_subband in g_sp
+ sp_sst <= TO_UREAL(sp_ssts_arr2(c_pol_index)(g_subband));
+ proc_common_wait_some_cycles(tb_clk, 1);
+ proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+
+ ---------------------------------------------------------------------------
+ -- Read beamlet statistics from end node
+ ---------------------------------------------------------------------------
+ -- . the beamlet statistics are c_stat_data_sz = 2 word power values.
+ -- . there are c_sdp_S_sub_bf = 488 dual pol beamlets per beamset
+ -- . the beamlets are output alternately so X0 Y0 X1 Y1 ... X487 Y487 for polarizations X, Y
+ -- . the beamlet statistics for multiple beamsets appear in order in the ram_st_bst address map
+ -- . the beamlet statistics are stored first lo word 0 then hi word 1
+ v_len := c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_stat_data_sz; -- = 1952 = 488 * 2 * 64/32
+ v_span := true_log_pow2(v_len); -- = 2048
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ FOR I IN 0 TO v_len-1 LOOP
+ v_W := I MOD c_stat_data_sz; -- 0, 1 per statistics word, word index
+ v_PB := (I / c_stat_data_sz) MOD c_sdp_N_pol_bf; -- 0, 1 per BF pol, polarization index
+ v_B := I / (c_sdp_N_pol_bf * c_stat_data_sz); -- beamlet index in beamset, range(S_sub_bf = 488) per dual pol
+ v_G := v_B + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ v_addr := I + U * v_span; -- MM address
+ --Only read BST for g_beamlet and dual pol_bf 0 and 1 and for both beamsets, to save sim time
+ IF g_read_all_BST = TRUE OR v_B = g_beamlet THEN
+ IF v_W = 0 THEN
+ -- low part
+ mmf_mm_bus_rd(c_mm_file_ram_st_bst, v_addr, rd_data, tb_clk);
+ v_data_lo := rd_data;
+ ELSE
+ -- high part
+ mmf_mm_bus_rd(c_mm_file_ram_st_bst, v_addr, rd_data, tb_clk);
+ v_data_hi := rd_data;
+ v_stat_data := v_data_hi & v_data_lo;
+
+ bsts_arr2(v_PB)(v_G) <= v_stat_data;
+ stat_data <= v_stat_data; -- for time series view in Wave window
+ END IF;
+ END IF;
+ END LOOP;
+ END LOOP;
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Beamlet power of g_beamlet X and Y, same for both beamsets
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ bst_x_arr(U) <= TO_UREAL(bsts_arr2(0)(v_G)); -- X pol beamlet
+ bst_y_arr(U) <= TO_UREAL(bsts_arr2(1)(v_G)); -- Y pol beamlet
+ END LOOP;
+ proc_common_wait_some_cycles(tb_clk, 1);
+ proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+
+ ---------------------------------------------------------------------------
+ -- Log WG, subband and beamlet statistics
+ ---------------------------------------------------------------------------
+
+ print_str("");
+ print_str("WG:");
+ print_str(". c_wg_ampl = " & int_to_str(c_wg_ampl));
+ print_str(". c_exp_sp_power = " & real_to_str(c_exp_sp_power, 20, 1));
+ print_str(". c_exp_sp_ast = " & real_to_str(c_exp_sp_ast, 20, 1));
+
+ print_str("");
+ print_str("Subband weight:");
+ print_str(". sp_subband_weight_gain = " & real_to_str(sp_subband_weight_gain, 20, 6));
+ print_str(". sp_subband_weight_phase = " & real_to_str(sp_subband_weight_phase, 20, 6));
+
+ print_str("");
+ print_str("SST results:");
+ print_str(". sst_weighted_subbands_flag = " & sl_to_str(sst_weighted_subbands_flag));
+ print_str("");
+ print_str(". c_exp_subband_ampl = " & int_to_str(NATURAL(c_exp_subband_ampl)));
+ print_str(". c_exp_subband_power = " & real_to_str(c_exp_subband_power, 20, 1));
+ print_str(". c_exp_subband_sst = " & real_to_str(c_exp_subband_sst, 20, 1));
+ print_str("");
+ print_str(". sp_sst = " & real_to_str(sp_sst, 20, 1));
+ print_str(". sp_sst / c_exp_subband_sst = " & real_to_str(sp_sst / c_exp_subband_sst, 20, 6));
+
+ print_str("");
+ print_str("BST results:");
+ print_str(". c_exp_beamlet_x_ampl = " & int_to_str(NATURAL(c_exp_beamlet_x_ampl)));
+ print_str(". c_exp_beamlet_x_power = " & real_to_str(c_exp_beamlet_x_power, 20, 1));
+ print_str(". c_exp_beamlet_x_bst = " & real_to_str(c_exp_beamlet_x_bst, 20, 1));
+ print_str("");
+ print_str(". c_exp_beamlet_y_ampl = " & int_to_str(NATURAL(c_exp_beamlet_y_ampl)));
+ print_str(". c_exp_beamlet_y_power = " & real_to_str(c_exp_beamlet_y_power, 20, 1));
+ print_str(". c_exp_beamlet_y_bst = " & real_to_str(c_exp_beamlet_y_bst, 20, 1));
+ print_str("");
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ print_str(". bst_x_arr(" & INTEGER'IMAGE(v_G) & ") = " & real_to_str(bst_x_arr(U), 20, 1));
+ print_str(". bst_y_arr(" & INTEGER'IMAGE(v_G) & ") = " & real_to_str(bst_y_arr(U), 20, 1));
+ END LOOP;
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ v_G := g_beamlet + U * c_sdp_S_sub_bf; -- global beamlet index, range(c_sdp_N_beamlets_sdp)
+ print_str(". bst_x_arr(" & INTEGER'IMAGE(v_G) & ") / c_exp_beamlet_x_bst = " & real_to_str(bst_x_arr(U) / c_exp_beamlet_x_bst, 20, 6));
+ print_str(". bst_y_arr(" & INTEGER'IMAGE(v_G) & ") / c_exp_beamlet_y_bst = " & real_to_str(bst_y_arr(U) / c_exp_beamlet_y_bst, 20, 6));
+ END LOOP;
+
+ print_str("");
+ print_str("Beamlet output:");
+ print_str(". rd_beamlet_scale = " & int_to_str(TO_UINT(rd_beamlet_scale)));
+ print_str(". c_exp_beamlet_scale = " & int_to_str(c_exp_beamlet_scale));
+ print_str("");
+ print_str(". c_exp_beamlet_x_output_ampl = " & int_to_str(NATURAL(c_exp_beamlet_x_output_ampl)));
+ print_str(". c_exp_beamlet_x_output_phase = " & int_to_str(INTEGER(c_exp_beamlet_x_output_phase)));
+ print_str(". c_exp_beamlet_x_output_re = " & int_to_str(INTEGER(c_exp_beamlet_x_output_re)));
+ print_str(". c_exp_beamlet_x_output_im = " & int_to_str(INTEGER(c_exp_beamlet_x_output_im)));
+ print_str("");
+ print_str(". c_exp_beamlet_y_output_ampl = " & int_to_str(NATURAL(c_exp_beamlet_y_output_ampl)));
+ print_str(". c_exp_beamlet_y_output_phase = " & int_to_str(INTEGER(c_exp_beamlet_y_output_phase)));
+ print_str(". c_exp_beamlet_y_output_re = " & int_to_str(INTEGER(c_exp_beamlet_y_output_re)));
+ print_str(". c_exp_beamlet_y_output_im = " & int_to_str(INTEGER(c_exp_beamlet_y_output_im)));
+
+ ---------------------------------------------------------------------------
+ -- Verify SST
+ ---------------------------------------------------------------------------
+ -- verify expected subband power based on WG power
+ ASSERT sp_sst > c_stat_lo_factor * c_exp_subband_sst REPORT "Wrong subband power for SP " & NATURAL'IMAGE(g_sp) SEVERITY ERROR;
+ ASSERT sp_sst < c_stat_hi_factor * c_exp_subband_sst REPORT "Wrong subband power for SP " & NATURAL'IMAGE(g_sp) SEVERITY ERROR;
+
+ ---------------------------------------------------------------------------
+ -- Verify BST
+ ---------------------------------------------------------------------------
+ -- verify expected beamlet power based on WG power and BF weigths
+ FOR U IN 0 TO c_sdp_N_beamsets-1 LOOP
+ -- X-pol
+ ASSERT bst_x_arr(U) < c_stat_hi_factor * c_exp_beamlet_x_bst REPORT "Wrong beamlet X power in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
+ ASSERT bst_x_arr(U) > c_stat_lo_factor * c_exp_beamlet_x_bst REPORT "Wrong beamlet X power in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
+ -- Y-pol
+ ASSERT bst_y_arr(U) > c_stat_lo_factor * c_exp_beamlet_y_bst REPORT "Wrong beamlet Y power in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
+ ASSERT bst_y_arr(U) < c_stat_hi_factor * c_exp_beamlet_y_bst REPORT "Wrong beamlet Y power in beamset " & NATURAL'IMAGE(U) SEVERITY ERROR;
+ END LOOP;
+
+ ---------------------------------------------------------------------------
+ -- Verify beamlet output in 10GbE UDP offload
+ ---------------------------------------------------------------------------
+ -- X-pol
+ v_re := TO_SINT(rx_beamlet_list_re(c_exp_beamlet_x_index)); v_re_exp := c_exp_beamlet_x_output_re;
+ v_im := TO_SINT(rx_beamlet_list_im(c_exp_beamlet_x_index)); v_im_exp := c_exp_beamlet_x_output_im;
+ ASSERT v_re > INTEGER(v_re_exp) - c_beamlet_output_delta REPORT "Wrong beamlet X output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_re < INTEGER(v_re_exp) + c_beamlet_output_delta REPORT "Wrong beamlet X output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_im > INTEGER(v_im_exp) - c_beamlet_output_delta REPORT "Wrong beamlet X output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
+ ASSERT v_im < INTEGER(v_im_exp) + c_beamlet_output_delta REPORT "Wrong beamlet X output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
+ -- Y-pol
+ v_re := TO_SINT(rx_beamlet_list_re(c_exp_beamlet_y_index)); v_re_exp := c_exp_beamlet_y_output_re;
+ v_im := TO_SINT(rx_beamlet_list_im(c_exp_beamlet_y_index)); v_im_exp := c_exp_beamlet_y_output_im;
+ ASSERT v_re > INTEGER(v_re_exp) - c_beamlet_output_delta REPORT "Wrong beamlet Y output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_re < INTEGER(v_re_exp) + c_beamlet_output_delta REPORT "Wrong beamlet Y output (re) " & INTEGER'IMAGE(v_re) & " != " & REAL'IMAGE(v_re_exp) SEVERITY ERROR;
+ ASSERT v_im > INTEGER(v_im_exp) - c_beamlet_output_delta REPORT "Wrong beamlet Y output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
+ ASSERT v_im < INTEGER(v_im_exp) + c_beamlet_output_delta REPORT "Wrong beamlet Y output (im) " & INTEGER'IMAGE(v_im) & " != " & REAL'IMAGE(v_im_exp) SEVERITY ERROR;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ tb_almost_end <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100); -- delay for ease of view in Wave window
+ proc_common_stop_simulation(TRUE, ext_clk, tb_almost_end, tb_end);
+ WAIT;
+ END PROCESS;
+
+ -----------------------------------------------------------------------------
+ -- Verify beamlet offload packet header
+ -----------------------------------------------------------------------------
+
+ -- Counters to time expected exp_sdp_cep_header fields per offload packet
+ p_test_counters : PROCESS(ext_clk)
+ BEGIN
+ IF rising_edge(ext_clk) THEN
+ -- Count rx_beamlet_sosi packets
+ IF rx_beamlet_sosi.sop = '1' THEN
+ rx_beamlet_sop_cnt <= rx_beamlet_sop_cnt + 1; -- early count
+ END IF;
+ IF rx_beamlet_sosi.eop = '1' THEN
+ rx_beamlet_eop_cnt <= rx_beamlet_eop_cnt + 1; -- after count
+ END IF;
+ END IF;
+ END PROCESS;
+
+ -- Count sync intervals using in_sosi.sync, because there is no rx_beamlet_sosi.sync
+ in_sync_cnt <= in_sync_cnt + 1 WHEN rising_edge(ext_clk) AND in_sync = '1';
+ test_sync_cnt <= in_sync_cnt - 1; -- optionally adjust to fit rx_beamlet_sosi
+
+ -- Prepare exp_sdp_cep_header before rx_beamlet_sosi.eop, so that
+ -- p_exp_sdp_cep_header can verify it at rx_beamlet_sosi.eop.
+
+ p_exp_sdp_cep_header : PROCESS(exp_dp_bsn)
+ BEGIN
+ -- eth header
+ exp_sdp_cep_header.eth.dst_mac <= c_cep_eth_dst_mac;
+ exp_sdp_cep_header.eth.src_mac <= c_cep_eth_src_mac;
+ exp_sdp_cep_header.eth.eth_type <= x"0800";
+
+ -- ip header
+ exp_sdp_cep_header.ip.version <= TO_UVEC( 4, c_network_ip_version_w);
+ exp_sdp_cep_header.ip.header_length <= TO_UVEC( 5, c_network_ip_header_length_w);
+ exp_sdp_cep_header.ip.services <= TO_UVEC( 0, c_network_ip_services_w);
+ exp_sdp_cep_header.ip.total_length <= c_sdp_cep_ip_total_length; -- 7868, see ICD STAT-CEP
+ exp_sdp_cep_header.ip.identification <= TO_UVEC( 0, c_network_ip_identification_w);
+ exp_sdp_cep_header.ip.flags <= TO_UVEC( 2, c_network_ip_flags_w);
+ exp_sdp_cep_header.ip.fragment_offset <= TO_UVEC( 0, c_network_ip_fragment_offset_w);
+ exp_sdp_cep_header.ip.time_to_live <= TO_UVEC( 127, c_network_ip_time_to_live_w);
+ exp_sdp_cep_header.ip.protocol <= TO_UVEC( 17, c_network_ip_protocol_w);
+ exp_sdp_cep_header.ip.header_checksum <= TO_UVEC( c_exp_ip_header_checksum, c_network_ip_header_checksum_w);
+ exp_sdp_cep_header.ip.src_ip_addr <= c_cep_ip_src_addr; -- c_network_ip_addr_w
+ exp_sdp_cep_header.ip.dst_ip_addr <= c_cep_ip_dst_addr; -- c_network_ip_addr_w
+
+ -- udp header
+ exp_sdp_cep_header.udp.src_port <= c_cep_udp_src_port;
+ exp_sdp_cep_header.udp.dst_port <= c_cep_udp_dst_port;
+ exp_sdp_cep_header.udp.total_length <= c_sdp_cep_udp_total_length; -- 7848, see ICD STAT-CEP
+ exp_sdp_cep_header.udp.checksum <= TO_UVEC( 0, c_network_udp_checksum_w);
+
+ -- app header
+ exp_sdp_cep_header.app.sdp_marker <= TO_UVEC(c_sdp_marker_beamlets, 8); -- 98 = x"62" = 'b'
+ exp_sdp_cep_header.app.sdp_version_id <= TO_UVEC(c_sdp_cep_version_id, 8); -- 5
+ exp_sdp_cep_header.app.sdp_observation_id <= c_exp_sdp_info.observation_id;
+ exp_sdp_cep_header.app.sdp_station_id <= c_exp_sdp_info.station_id;
+
+ exp_sdp_cep_header.app.sdp_source_info_antenna_band_id <= slv(c_exp_sdp_info.antenna_band_index);
+ exp_sdp_cep_header.app.sdp_source_info_nyquist_zone_id <= c_exp_sdp_info.nyquist_zone_index;
+ exp_sdp_cep_header.app.sdp_source_info_f_adc <= slv(c_exp_sdp_info.f_adc);
+ exp_sdp_cep_header.app.sdp_source_info_fsub_type <= slv(c_exp_sdp_info.fsub_type);
+ exp_sdp_cep_header.app.sdp_source_info_payload_error <= TO_UVEC(0, 1);
+ exp_sdp_cep_header.app.sdp_source_info_repositioning_flag <= slv(c_exp_sdp_info.beam_repositioning_flag);
+ exp_sdp_cep_header.app.sdp_source_info_beamlet_width <= TO_UVEC(c_sdp_W_beamlet, 4);
+ exp_sdp_cep_header.app.sdp_source_info_gn_id <= TO_UVEC(c_gn_index, 5);
+
+ exp_sdp_cep_header.app.sdp_reserved <= TO_UVEC( 0, 40);
+ exp_sdp_cep_header.app.sdp_beamlet_scale <= TO_UVEC( c_exp_beamlet_scale, 16);
+ exp_sdp_cep_header.app.sdp_beamlet_index <= TO_UVEC( 0, 16); -- depends on bset
+ exp_sdp_cep_header.app.sdp_nof_blocks_per_packet <= TO_UVEC( c_sdp_cep_nof_blocks_per_packet, 8);
+ exp_sdp_cep_header.app.sdp_nof_beamlets_per_block <= TO_UVEC(c_sdp_cep_nof_beamlets_per_block, 16);
+ exp_sdp_cep_header.app.sdp_block_period <= c_exp_sdp_info.block_period;
+
+ exp_sdp_cep_header.app.dp_bsn <= TO_UVEC(exp_dp_bsn, 64); -- depends on bset and time
+ END PROCESS;
+
+ rx_sdp_cep_header <= func_sdp_map_cep_header(rx_hdr_fields_raw);
+
+ p_verify_cep_header : PROCESS
+ VARIABLE v_bool : BOOLEAN;
+ BEGIN
+ WAIT UNTIL rising_edge(ext_clk);
+
+ -- Prepare exp_sdp_cep_header at sop, so that it can be verified at eop
+ IF rx_beamlet_sosi.sop = '1' THEN
+ -- Expected BSN increments by c_sdp_cep_nof_blocks_per_packet = 4 blocks per packet
+ IF rx_beamlet_sop_cnt MOD c_sdp_N_beamsets = 0 THEN
+ exp_dp_bsn <= c_init_bsn + (rx_beamlet_sop_cnt / c_sdp_N_beamsets) * c_sdp_cep_nof_blocks_per_packet;
+ END IF;
+ END IF;
+
+ -- Verify header at eop
+ -- . The expected beamlet_index 0 or S_sub_bf = 488 depends on beamset 0
+ -- or 1, but the order in which the packets arrive is undetermined.
+ -- Therefore accept any beamlet_index MOD c_sdp_S_sub_bf = 0 as correct
+ -- in func_sdp_verify_cep_header().
+ IF rx_beamlet_sosi.eop = '1' THEN
+ v_bool := func_sdp_verify_cep_header(rx_sdp_cep_header, exp_sdp_cep_header);
+ END IF;
+ END PROCESS;
+
+ -----------------------------------------------------------------------------
+ -- CEP Read Rx 10GbE Stream
+ -----------------------------------------------------------------------------
+ -- Show received beamlets from 10GbE stream in Wave Window
+ -- . The packet header is 9.25 longwords wide. The dp_offload_rx has stripped
+ -- the header and has realigned the payload at a longword boundary.
+ -- . expect c_nof_block_per_sync / c_sdp_cep_nof_blocks_per_packet *
+ -- c_sdp_N_beamsets = 16 / 4 * 2 = 4 * 2 = 8 packets per sync interval
+ -- . expect c_sdp_cep_nof_beamlets_per_block = c_sdp_S_sub_bf = 488 dual pol
+ -- and complex beamlets per packet, so 2 dual pol beamlets/64b data word.
+ -- . Beamlets array is stored big endian in the data, so X index 0 first in
+ -- MSByte of rx_beamlet_sosi.data.
+ p_rx_cep_beamlets : PROCESS
+ BEGIN
+ rx_beamlet_cnt <= 0;
+ rx_beamlet_valid <= '0';
+ -- Wait until start of a beamlet packet, capture only first block in packet
+ proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.sop);
+ -- c_nof_beamlets_per_data = 2 dual pol beamlets (= XY, XY) per 64b data word
+ FOR I IN 0 TO (c_sdp_cep_nof_blocks_per_packet * c_sdp_cep_nof_beamlets_per_block / c_nof_beamlets_per_data)-1 LOOP
+ proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.valid);
+ rx_beamlet_valid <= '1';
+ -- Capture rx beamlets per longword in rx_beamlet_arr, for time series view in Wave window
+ rx_beamlet_arr_re(0) <= rx_beamlet_sosi.data(55 DOWNTO 48); -- X
+ rx_beamlet_arr_im(0) <= rx_beamlet_sosi.data(63 DOWNTO 56);
+ rx_beamlet_arr_re(1) <= rx_beamlet_sosi.data(39 DOWNTO 32); -- Y
+ rx_beamlet_arr_im(1) <= rx_beamlet_sosi.data(47 DOWNTO 40);
+ rx_beamlet_arr_re(2) <= rx_beamlet_sosi.data(23 DOWNTO 16); -- X
+ rx_beamlet_arr_im(2) <= rx_beamlet_sosi.data(31 DOWNTO 24);
+ rx_beamlet_arr_re(3) <= rx_beamlet_sosi.data( 7 DOWNTO 0); -- Y
+ rx_beamlet_arr_im(3) <= rx_beamlet_sosi.data(15 DOWNTO 8);
+ IF I < c_sdp_cep_nof_beamlets_per_block / c_nof_beamlets_per_data THEN
+ -- Only capture the first beamlets block of each packet in rx_beamlet_list
+ rx_beamlet_list_re(I*4 + 0) <= rx_beamlet_sosi.data(55 DOWNTO 48); -- X
+ rx_beamlet_list_im(I*4 + 0) <= rx_beamlet_sosi.data(63 DOWNTO 56);
+ rx_beamlet_list_re(I*4 + 1) <= rx_beamlet_sosi.data(39 DOWNTO 32); -- Y
+ rx_beamlet_list_im(I*4 + 1) <= rx_beamlet_sosi.data(47 DOWNTO 40);
+ rx_beamlet_list_re(I*4 + 2) <= rx_beamlet_sosi.data(23 DOWNTO 16); -- X
+ rx_beamlet_list_im(I*4 + 2) <= rx_beamlet_sosi.data(31 DOWNTO 24);
+ rx_beamlet_list_re(I*4 + 3) <= rx_beamlet_sosi.data( 7 DOWNTO 0); -- Y
+ rx_beamlet_list_im(I*4 + 3) <= rx_beamlet_sosi.data(15 DOWNTO 8);
+ END IF;
+ proc_common_wait_until_high(ext_clk, rx_beamlet_sosi.valid);
+ -- Use at least one WAIT instead of proc_common_wait_some_cycles() to
+ -- avoid Modelsim warning: (vcom-1090) Possible infinite loop: Process
+ -- contains no WAIT statement.
+ WAIT UNTIL rising_edge(ext_clk);
+ rx_beamlet_valid <= '0';
+ rx_beamlet_cnt <= (rx_beamlet_cnt + c_nof_beamlets_per_data) MOD c_sdp_cep_nof_beamlets_per_block; -- 4 blocks/packet
+ END LOOP;
+ END PROCESS;
+
+ -- To view the 64 bit 10GbE offload data more easily in the Wave window
+ rx_beamlet_data <= rx_beamlet_sosi.data(c_longword_w-1 DOWNTO 0);
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
index 484e94af1fe234769a7153f176c168a1cbaa169d..b7f54f3ab55eb7ab44c22b343344e5172a3df300 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
@@ -39,7 +39,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2c_sdp_station_pins.tcl
+ lofar2_unb2c_sdp_station_fsub_pins.tcl
quartus_vhdl_files =
@@ -72,19 +72,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
@@ -102,6 +112,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b689b7d674278bcc88a9dabee9475a57fe4de9a9
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl
@@ -0,0 +1,24 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
index 9d83b60200f9bc578fdff4487517e9be636dd54b..65ebcc129efc0e4572564dfb8ed6c942ddfb0740 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
@@ -69,19 +69,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
@@ -99,6 +109,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index bbbc8a82eef50ed16480476f7e03f31e83dc0e42..f5650bac12b1297127d39c624d1a4f2fbb3b60f6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -23,7 +23,7 @@
-- Wrapper for Lofar2 SDP Station full design
-- Description:
-- Unb2c version for lab testing
--- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB and BF
+-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
index d73951bdcc04e5d5c6c1d67dcdddf42400fb37f3..273a627af9469a3f619164eee8ded453c302cb7f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
@@ -19,102 +19,8 @@
#
###############################################################################
source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-
-# Define extra pins for this revision.
-### QSFP_0_0 For ring
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
-
-### QSFP_1_0 For BF
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_1_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]
-
-
-#RING_0 RX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
-
-#RING_1 RX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
-
-#RING_0 TX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
-
-#RING_1 TX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
-
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a410171732d585af43e09c416c83338a96453761
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg
@@ -0,0 +1,129 @@
+hdl_lib_name = lofar2_unb2c_sdp_station_full_wg
+hdl_library_clause_name = lofar2_unb2c_sdp_station_full_wg_lib
+hdl_lib_uses_synth = common mm technology unb2c_board lofar2_unb2c_sdp_station
+hdl_lib_uses_sim = eth
+hdl_lib_technology = ip_arria10_e2sg
+
+ synth_files =
+ lofar2_unb2c_sdp_station_full_wg.vhd
+
+test_bench_files =
+
+regression_test_vhdl =
+
+[modelsim_project_file]
+modelsim_copy_files =
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Overwrite bf weights with sim data
+ ../../tb/data data
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ ../../quartus .
+ ../../src/data data
+ $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+
+# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
+quartus_sdc_files =
+ ../../quartus/lofar2_unb2c_sdp_station.sdc
+ #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+
+quartus_tcl_files =
+ lofar2_unb2c_sdp_station_full_wg_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a902096026e6a3c3bba2d3018610dbdb4750e95f
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
@@ -0,0 +1,141 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : R. van der Walle
+-- Purpose:
+-- Wrapper for Lofar2 SDP Station full wg design.
+-- Description:
+-- Unb2c version for lab testing of SDP using the WG.
+-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
+
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY lofar2_unb2c_sdp_station_full_wg IS
+ GENERIC (
+ g_design_name : STRING := "lofar2_unb2c_sdp_station_full_wg";
+ g_design_note : STRING := "Lofar2 SDP station full design WG";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := "" -- revision ID -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- Clock 10GbE front (qsfp) and ring lines
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
+ QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 downto 0);
+ -- LEDs
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
+
+ -- ring transceivers
+ RING_0_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS => '0'); -- Using qsfp bus width also for ring interfaces
+ RING_0_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0);
+ RING_1_RX : IN STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ RING_1_TX : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.bus_w-1 DOWNTO 0)
+ );
+END lofar2_unb2c_sdp_station_full_wg;
+
+ARCHITECTURE str OF lofar2_unb2c_sdp_station_full_wg IS
+
+BEGIN
+
+ u_revision : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- Transceiver clocks
+ SA_CLK => SA_CLK,
+
+ -- front transceivers QSFP0 for Ring.
+ QSFP_0_RX => QSFP_0_RX,
+ QSFP_0_TX => QSFP_0_TX,
+
+ -- front transceivers QSFP1 for 10GbE output to CEP.
+ QSFP_1_RX => QSFP_1_RX,
+ QSFP_1_TX => QSFP_1_TX,
+ -- LEDs
+ QSFP_LED => QSFP_LED,
+
+ -- ring transceivers
+ RING_0_RX => RING_0_RX,
+ RING_0_TX => RING_0_TX,
+ RING_1_RX => RING_1_RX,
+ RING_1_TX => RING_1_TX
+ );
+END str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4ceebdedad386e07a109627cae9cd0a15507fa48
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl
@@ -0,0 +1,25 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
index f6fa5a6eac75df3d04bd63de04829cf4fb1a0546..f0be972dafa25c7ad741cf512460045c6d0c3353 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
@@ -39,7 +39,7 @@ quartus_sdc_files =
#$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
- ../../quartus/lofar2_unb2c_sdp_station_pins.tcl
+ lofar2_unb2c_sdp_station_xsub_one_pins.tcl
quartus_vhdl_files =
@@ -72,19 +72,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
@@ -102,6 +112,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b689b7d674278bcc88a9dabee9475a57fe4de9a9
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl
@@ -0,0 +1,24 @@
+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+
+
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
index 450d250eb39ac7ef39fef10cbc921ecea949a125..159fb7bde4200cc8bb7f9c552d869ece565e9800 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
@@ -69,19 +69,29 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bsn_align_v2_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
@@ -99,6 +109,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
index 040b4944154fd4ea20cb143ee635ed9f534f0b68..78cb5f4e829362546751392aef42a210ad13b168 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
@@ -19,78 +19,7 @@
#
###############################################################################
source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-
-# Define extra pins for this revision.
-### QSFP_0_0 For ring
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to QSFP_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_RX[0]
-
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to QSFP_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_0_TX[0]
-
-#RING_0 RX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_0_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_0_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_RX[0]
-
-#RING_1 RX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to RING_1_RX[0]
-set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to RING_1_RX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_RX[0]
-
-#RING_0 TX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_0_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_0_TX[0]
-
-#RING_1 TX assignments
-set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to RING_1_TX[0]
-set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to RING_1_TX[0]
-set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to RING_1_TX[0]
-
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 45baadee029688b91db26f4e13b0c6a81ead2a91..b1aa7701e5f171c6446ab5ac22ca7631626e4ca5 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -100,12 +100,12 @@ ENTITY lofar2_unb2c_sdp_station IS
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- back transceivers (Note: numbered from 0)
- JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
+ JESD204B_SERIAL_DATA : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => '0'); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
-- Connect to the BCK_RX pins in the top wrapper
- JESD204B_REFCLK : IN STD_LOGIC; -- Connect to BCK_REF_CLK pin in the top level wrapper
+ JESD204B_REFCLK : IN STD_LOGIC := '0'; -- Connect to BCK_REF_CLK pin in the top level wrapper
-- jesd204b syncronization signals
- JESD204B_SYSREF : IN STD_LOGIC;
+ JESD204B_SYSREF : IN STD_LOGIC := '0';
JESD204B_SYNC_N : OUT STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0) -- c_unb2c_board_nof_sync_jesd204b = c_sdp_N_sync_jesd = 4
);
END lofar2_unb2c_sdp_station;
@@ -141,262 +141,301 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
SIGNAL pout_wdi : STD_LOGIC;
-- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_wdi_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_wdi_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_wdi_cipo : t_mem_cipo := c_mem_cipo_rst;
-- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_ppsh_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ppsh_cipo : t_mem_cipo := c_mem_cipo_rst;
-- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL rom_unb_system_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL rom_unb_system_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL rom_unb_system_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-- FPGA sensors
- SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_fpga_temp_sens_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_fpga_temp_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_fpga_temp_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_fpga_voltage_sens_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_fpga_voltage_sens_cipo : t_mem_cipo := c_mem_cipo_rst;
-- eth1g
SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL eth1g_reg_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_tse_copi : t_mem_copi := c_mem_copi_rst; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL eth1g_reg_copi : t_mem_copi := c_mem_copi_rst; -- ETH control and status registers
+ SIGNAL eth1g_reg_cipo : t_mem_cipo := c_mem_cipo_rst;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL eth1g_ram_copi : t_mem_copi := c_mem_copi_rst; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dpmm_data_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dpmm_data_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dpmm_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_dpmm_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dpmm_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_mmdp_data_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_mmdp_data_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_mmdp_data_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_mmdp_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_mmdp_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_epcs_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_epcs_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_epcs_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_remu_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_remu_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_remu_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Scrap ram
- SIGNAL ram_scrap_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_scrap_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_scrap_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_scrap_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- AIT
----------------------------------------------
-- JESD
- SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL jesd204b_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL jesd204b_cipo : t_mem_cipo := c_mem_cipo_rst;
-- JESD control
- SIGNAL jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL jesd_ctrl_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL jesd_ctrl_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Shiftram (applies per-antenna delay)
- SIGNAL reg_dp_shiftram_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_shiftram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_shiftram_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_shiftram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn source
- SIGNAL reg_bsn_source_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_source_v2_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_source_v2_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_source_v2_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn scheduler
- SIGNAL reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_scheduler_wg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_scheduler_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_scheduler_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
-- WG
- SIGNAL reg_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_wg_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL ram_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_wg_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL ram_wg_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_wg_cipo : t_mem_cipo := c_mem_cipo_rst;
-- BSN MONITOR
- SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_monitor_input_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_monitor_input_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_input_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Data buffer bsn
- SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
- SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_diag_data_buf_bsn_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_diag_data_buf_bsn_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_diag_data_buf_bsn_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_diag_data_buf_bsn_cipo : t_mem_cipo := c_mem_cipo_rst;
-- ST Histogram
- SIGNAL ram_st_histogram_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_histogram_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_histogram_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_histogram_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Aduh statistics monitor
- SIGNAL reg_aduh_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_aduh_monitor_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_aduh_monitor_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_aduh_monitor_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- FSUB
----------------------------------------------
-- Subband statistics
- SIGNAL ram_st_sst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_sst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_sst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_sst_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Spectral Inversion
- SIGNAL reg_si_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_si_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_si_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_si_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Filter coefficients
- SIGNAL ram_fil_coefs_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_fil_coefs_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_fil_coefs_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_fil_coefs_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Equalizer gains
- SIGNAL ram_equalizer_gains_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_equalizer_gains_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_equalizer_gains_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_equalizer_gains_cipo : t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
- SIGNAL reg_dp_selector_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_selector_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_selector_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_selector_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SDP Info
----------------------------------------------
- SIGNAL reg_sdp_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_sdp_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_sdp_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_sdp_info_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- RING Info
----------------------------------------------
- SIGNAL reg_ring_info_copi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_ring_info_cipo : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_ring_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ring_info_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- XSUB
----------------------------------------------
-- crosslets_info
- SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_crosslets_info_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_crosslets_info_cipo : t_mem_cipo := c_mem_cipo_rst;
-- crosslets_info
- SIGNAL reg_nof_crosslets_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nof_crosslets_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nof_crosslets_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nof_crosslets_cipo : t_mem_cipo := c_mem_cipo_rst;
-- bsn_scheduler_xsub
- SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_sync_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_sync_scheduler_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
-- st_xsq
- SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_xsq_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_xsq_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- BF
----------------------------------------------
-- Beamlet Subband Select
- SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_ss_ss_wide_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_ss_ss_wide_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_ss_ss_wide_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Local BF bf weights
- SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_bf_weights_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_bf_weights_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_bf_weights_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF bsn aligner_v2
+ SIGNAL reg_bsn_align_v2_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_align_v2_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF bsn aligner_v2 bsn monitors
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
-- mms_dp_scale Scale Beamlets
- SIGNAL reg_bf_scale_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bf_scale_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bf_scale_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bf_scale_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output header fields
- SIGNAL reg_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_hdr_dat_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_hdr_dat_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
- SIGNAL reg_dp_xonoff_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_dp_xonoff_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_xonoff_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_xonoff_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Statistics (BST)
- SIGNAL ram_st_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL ram_st_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL ram_st_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL ram_st_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring lane info
+ SIGNAL reg_ring_lane_info_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_ring_lane_info_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor rx
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor tx
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+ -- BF ring validate err
+ SIGNAL reg_dp_block_validate_err_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_block_validate_err_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn at sync
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_cipo : t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_sst_mosi : t_mem_mosi;
- SIGNAL reg_stat_enable_sst_miso : t_mem_miso;
+ SIGNAL reg_stat_enable_sst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_sst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_sst_mosi : t_mem_mosi;
- SIGNAL reg_stat_hdr_dat_sst_miso : t_mem_miso;
+ SIGNAL reg_stat_hdr_dat_sst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_sst_cipo : t_mem_cipo;
+ -- SST UDP offload bsn monitor
+ SIGNAL reg_bsn_monitor_v2_sst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_sst_offload_cipo : t_mem_cipo;
----------------------------------------------
-- XST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_xst_mosi : t_mem_mosi;
- SIGNAL reg_stat_enable_xst_miso : t_mem_miso;
+ SIGNAL reg_stat_enable_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_enable_xst_cipo : t_mem_cipo;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_xst_mosi : t_mem_mosi;
- SIGNAL reg_stat_hdr_dat_xst_miso : t_mem_miso;
+ SIGNAL reg_stat_hdr_dat_xst_copi : t_mem_copi;
+ SIGNAL reg_stat_hdr_dat_xst_cipo : t_mem_cipo;
-- XST bsn aligner_v2
- SIGNAL reg_bsn_align_v2_copi : t_mem_mosi;
- SIGNAL reg_bsn_align_v2_cipo : t_mem_miso;
+ SIGNAL reg_bsn_align_v2_xsub_copi : t_mem_copi;
+ SIGNAL reg_bsn_align_v2_xsub_cipo : t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_input_cipo : t_mem_miso;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_bsn_align_v2_output_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_rx_align_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_rx_align_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_xsub_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_bsn_monitor_v2_aligned_xsub_cipo : t_mem_cipo := c_mem_cipo_rst;
-- XST UDP offload bsn monitor
- SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_xst_offload_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_xst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_xst_offload_cipo : t_mem_cipo;
-- XST ring lane info
- SIGNAL reg_ring_lane_info_xst_copi : t_mem_mosi;
- SIGNAL reg_ring_lane_info_xst_cipo : t_mem_miso;
+ SIGNAL reg_ring_lane_info_xst_copi : t_mem_copi;
+ SIGNAL reg_ring_lane_info_xst_cipo : t_mem_cipo;
-- XST ring bsn monitor rx
- SIGNAL reg_bsn_monitor_v2_ring_rx_xst_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_ring_rx_xst_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_xst_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_ring_rx_xst_cipo : t_mem_cipo;
-- XST ring bsn monitor tx
- SIGNAL reg_bsn_monitor_v2_ring_tx_xst_copi : t_mem_mosi;
- SIGNAL reg_bsn_monitor_v2_ring_tx_xst_cipo : t_mem_miso;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_xst_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_ring_tx_xst_cipo : t_mem_cipo;
-- XST ring validate err
- SIGNAL reg_dp_block_validate_err_xst_copi : t_mem_mosi;
- SIGNAL reg_dp_block_validate_err_xst_cipo : t_mem_miso;
+ SIGNAL reg_dp_block_validate_err_xst_copi : t_mem_copi;
+ SIGNAL reg_dp_block_validate_err_xst_cipo : t_mem_cipo;
-- XST ring bsn at sync
- SIGNAL reg_dp_block_validate_bsn_at_sync_xst_copi : t_mem_mosi;
- SIGNAL reg_dp_block_validate_bsn_at_sync_xst_cipo : t_mem_miso;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_xst_copi : t_mem_copi;
+ SIGNAL reg_dp_block_validate_bsn_at_sync_xst_cipo : t_mem_cipo;
-- XST ring MAC10G
- SIGNAL reg_tr_10GbE_mac_copi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_mac_cipo : t_mem_miso;
+ SIGNAL reg_tr_10GbE_mac_copi : t_mem_copi;
+ SIGNAL reg_tr_10GbE_mac_cipo : t_mem_cipo;
-- XST ring ETH10G
- SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_mosi;
- SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_miso;
+ SIGNAL reg_tr_10GbE_eth10g_copi : t_mem_copi;
+ SIGNAL reg_tr_10GbE_eth10g_cipo : t_mem_cipo;
----------------------------------------------
-- BST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_stat_enable_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_stat_enable_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_stat_enable_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_bst_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_stat_hdr_dat_bst_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_stat_hdr_dat_bst_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_stat_hdr_dat_bst_cipo : t_mem_cipo := c_mem_cipo_rst;
+
+ -- BST UDP offload bsn monitor
+ SIGNAL reg_bsn_monitor_v2_bst_offload_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_bst_offload_cipo : t_mem_cipo;
+ -- Beamlet output bsn monitor
+ SIGNAL reg_bsn_monitor_v2_beamlet_output_copi : t_mem_copi;
+ SIGNAL reg_bsn_monitor_v2_beamlet_output_cipo : t_mem_cipo;
----------------------------------------------
-- UDP Offload
----------------------------------------------
@@ -406,11 +445,11 @@ ARCHITECTURE str OF lofar2_unb2c_sdp_station IS
----------------------------------------------
-- 10 GbE
----------------------------------------------
- SIGNAL reg_nw_10GbE_mac_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nw_10GbE_mac_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nw_10GbE_mac_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nw_10GbE_mac_cipo : t_mem_cipo := c_mem_cipo_rst;
- SIGNAL reg_nw_10GbE_eth10g_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_nw_10GbE_eth10g_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_nw_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
+ SIGNAL reg_nw_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
-- 10GbE
SIGNAL i_QSFP_TX : t_unb2c_board_qsfp_bus_2arr(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0) := (OTHERS => (OTHERS => '0'));
@@ -479,61 +518,61 @@ BEGIN
-- MM buses
-- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ reg_remu_mosi => reg_remu_copi,
+ reg_remu_miso => reg_remu_cipo,
-- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_copi,
+ reg_dpmm_data_miso => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_cipo,
-- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_copi,
+ reg_mmdp_data_miso => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_cipo,
-- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
+ reg_epcs_mosi => reg_epcs_copi,
+ reg_epcs_miso => reg_epcs_cipo,
-- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
+ reg_wdi_mosi => reg_wdi_copi,
+ reg_wdi_miso => reg_wdi_cipo,
-- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_copi,
+ reg_unb_system_info_miso => reg_unb_system_info_cipo,
+ rom_unb_system_info_mosi => rom_unb_system_info_copi,
+ rom_unb_system_info_miso => rom_unb_system_info_cipo,
-- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_cipo,
-- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_ppsh_mosi => reg_ppsh_copi,
+ reg_ppsh_miso => reg_ppsh_cipo,
-- eth1g
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_copi,
+ eth1g_tse_miso => eth1g_tse_cipo,
+ eth1g_reg_mosi => eth1g_reg_copi,
+ eth1g_reg_miso => eth1g_reg_cipo,
eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_ram_mosi => eth1g_ram_copi,
+ eth1g_ram_miso => eth1g_ram_cipo,
-- eth1g UDP streaming
udp_tx_sosi_arr => udp_tx_sosi_arr,
udp_tx_siso_arr => udp_tx_siso_arr,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
+ ram_scrap_mosi => ram_scrap_copi,
+ ram_scrap_miso => ram_scrap_cipo,
-- FPGA pins
-- . General
@@ -570,123 +609,145 @@ BEGIN
pout_wdi => pout_wdi,
-- mm interfaces for control
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_wdi_copi => reg_wdi_copi,
+ reg_wdi_cipo => reg_wdi_cipo,
+ reg_unb_system_info_copi => reg_unb_system_info_copi,
+ reg_unb_system_info_cipo => reg_unb_system_info_cipo,
+ rom_unb_system_info_copi => rom_unb_system_info_copi,
+ rom_unb_system_info_cipo => rom_unb_system_info_cipo,
+ reg_fpga_temp_sens_copi => reg_fpga_temp_sens_copi,
+ reg_fpga_temp_sens_cipo => reg_fpga_temp_sens_cipo,
+ reg_fpga_voltage_sens_copi => reg_fpga_voltage_sens_copi,
+ reg_fpga_voltage_sens_cipo => reg_fpga_voltage_sens_cipo,
+ reg_ppsh_copi => reg_ppsh_copi,
+ reg_ppsh_cipo => reg_ppsh_cipo,
eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_copi => eth1g_tse_copi,
+ eth1g_tse_cipo => eth1g_tse_cipo,
+ eth1g_reg_copi => eth1g_reg_copi,
+ eth1g_reg_cipo => eth1g_reg_cipo,
eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ eth1g_ram_copi => eth1g_ram_copi,
+ eth1g_ram_cipo => eth1g_ram_cipo,
+ reg_dpmm_data_copi => reg_dpmm_data_copi,
+ reg_dpmm_data_cipo => reg_dpmm_data_cipo,
+ reg_dpmm_ctrl_copi => reg_dpmm_ctrl_copi,
+ reg_dpmm_ctrl_cipo => reg_dpmm_ctrl_cipo,
+ reg_mmdp_data_copi => reg_mmdp_data_copi,
+ reg_mmdp_data_cipo => reg_mmdp_data_cipo,
+ reg_mmdp_ctrl_copi => reg_mmdp_ctrl_copi,
+ reg_mmdp_ctrl_cipo => reg_mmdp_ctrl_cipo,
+ reg_epcs_copi => reg_epcs_copi,
+ reg_epcs_cipo => reg_epcs_cipo,
+ reg_remu_copi => reg_remu_copi,
+ reg_remu_cipo => reg_remu_cipo,
-- mm buses for signal flow blocks
-- Jesd ip status/control
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
reg_ring_info_copi => reg_ring_info_copi,
reg_ring_info_cipo => reg_ring_info_cipo,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
- ram_scrap_mosi => ram_scrap_mosi,
- ram_scrap_miso => ram_scrap_miso,
- reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
- reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
- reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
- reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
- reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
- reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
- reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
- reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_miso => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
- reg_bsn_align_v2_copi => reg_bsn_align_v2_copi,
- reg_bsn_align_v2_cipo => reg_bsn_align_v2_cipo,
- reg_bsn_monitor_v2_bsn_align_v2_input_copi => reg_bsn_monitor_v2_bsn_align_v2_input_copi,
- reg_bsn_monitor_v2_bsn_align_v2_input_cipo => reg_bsn_monitor_v2_bsn_align_v2_input_cipo,
- reg_bsn_monitor_v2_bsn_align_v2_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
- reg_bsn_monitor_v2_bsn_align_v2_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
+ ram_scrap_copi => ram_scrap_copi,
+ ram_scrap_cipo => ram_scrap_cipo,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
@@ -701,8 +762,8 @@ BEGIN
reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo
);
@@ -717,6 +778,7 @@ BEGIN
g_wpfb => g_wpfb,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
g_scope_selected_subband => g_scope_selected_subband,
+ g_no_jesd => c_revision_select.no_jesd,
g_use_fsub => c_revision_select.use_fsub,
g_use_xsub => c_revision_select.use_xsub,
g_use_bf => c_revision_select.use_bf,
@@ -749,101 +811,119 @@ BEGIN
udp_tx_siso_arr => udp_tx_siso_arr,
-- 10 GbE
- reg_nw_10GbE_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_nw_10GbE_mac_miso => reg_nw_10GbE_mac_miso,
- reg_nw_10GbE_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_nw_10GbE_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ reg_nw_10GbE_mac_copi => reg_nw_10GbE_mac_copi,
+ reg_nw_10GbE_mac_cipo => reg_nw_10GbE_mac_cipo,
+ reg_nw_10GbE_eth10g_copi => reg_nw_10GbE_eth10g_copi,
+ reg_nw_10GbE_eth10g_cipo => reg_nw_10GbE_eth10g_cipo,
-- AIT
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd204b_copi => jesd204b_copi,
+ jesd204b_cipo => jesd204b_cipo,
+ jesd_ctrl_copi => jesd_ctrl_copi,
+ jesd_ctrl_cipo => jesd_ctrl_cipo,
+ reg_dp_shiftram_copi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_cipo => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_copi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_cipo => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_copi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_cipo => reg_bsn_scheduler_wg_cipo,
+ reg_wg_copi => reg_wg_copi,
+ reg_wg_cipo => reg_wg_cipo,
+ ram_wg_copi => ram_wg_copi,
+ ram_wg_cipo => ram_wg_cipo,
+ reg_bsn_monitor_input_copi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_cipo => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_copi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_cipo => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_copi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_cipo => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_copi => ram_st_histogram_copi,
+ ram_st_histogram_cipo => ram_st_histogram_cipo,
+ reg_aduh_monitor_copi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_cipo => reg_aduh_monitor_cipo,
-- FSUB
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_equalizer_gains_mosi => ram_equalizer_gains_mosi,
- ram_equalizer_gains_miso => ram_equalizer_gains_miso,
- reg_dp_selector_mosi => reg_dp_selector_mosi,
- reg_dp_selector_miso => reg_dp_selector_miso,
+ ram_st_sst_copi => ram_st_sst_copi,
+ ram_st_sst_cipo => ram_st_sst_cipo,
+ reg_si_copi => reg_si_copi,
+ reg_si_cipo => reg_si_cipo,
+ ram_fil_coefs_copi => ram_fil_coefs_copi,
+ ram_fil_coefs_cipo => ram_fil_coefs_cipo,
+ ram_equalizer_gains_copi => ram_equalizer_gains_copi,
+ ram_equalizer_gains_cipo => ram_equalizer_gains_cipo,
+ reg_dp_selector_copi => reg_dp_selector_copi,
+ reg_dp_selector_cipo => reg_dp_selector_cipo,
-- SDP Info
- reg_sdp_info_mosi => reg_sdp_info_mosi,
- reg_sdp_info_miso => reg_sdp_info_miso,
+ reg_sdp_info_copi => reg_sdp_info_copi,
+ reg_sdp_info_cipo => reg_sdp_info_cipo,
-- RING Info
reg_ring_info_copi => reg_ring_info_copi,
reg_ring_info_cipo => reg_ring_info_cipo,
-- XSUB
- reg_crosslets_info_mosi => reg_crosslets_info_mosi,
- reg_crosslets_info_miso => reg_crosslets_info_miso,
- reg_nof_crosslets_mosi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_miso => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
- ram_st_xsq_mosi => ram_st_xsq_mosi,
- ram_st_xsq_miso => ram_st_xsq_miso,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
-- BF
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
- ram_bf_weights_mosi => ram_bf_weights_mosi,
- ram_bf_weights_miso => ram_bf_weights_miso,
- reg_bf_scale_mosi => reg_bf_scale_mosi,
- reg_bf_scale_miso => reg_bf_scale_miso,
- reg_hdr_dat_mosi => reg_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_hdr_dat_miso,
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
- reg_dp_xonoff_miso => reg_dp_xonoff_miso,
- ram_st_bst_mosi => ram_st_bst_mosi,
- ram_st_bst_miso => ram_st_bst_miso,
-
+ ram_ss_ss_wide_copi => ram_ss_ss_wide_copi,
+ ram_ss_ss_wide_cipo => ram_ss_ss_wide_cipo,
+ ram_bf_weights_copi => ram_bf_weights_copi,
+ ram_bf_weights_cipo => ram_bf_weights_cipo,
+ reg_bf_scale_copi => reg_bf_scale_copi,
+ reg_bf_scale_cipo => reg_bf_scale_cipo,
+ reg_hdr_dat_copi => reg_hdr_dat_copi,
+ reg_hdr_dat_cipo => reg_hdr_dat_cipo,
+ reg_dp_xonoff_copi => reg_dp_xonoff_copi,
+ reg_dp_xonoff_cipo => reg_dp_xonoff_cipo,
+ ram_st_bst_copi => ram_st_bst_copi,
+ ram_st_bst_cipo => ram_st_bst_cipo,
+ reg_bsn_align_v2_bf_copi => reg_bsn_align_v2_bf_copi,
+ reg_bsn_align_v2_bf_cipo => reg_bsn_align_v2_bf_cipo,
+ reg_bsn_monitor_v2_rx_align_bf_copi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ reg_bsn_monitor_v2_rx_align_bf_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ reg_bsn_monitor_v2_aligned_bf_copi => reg_bsn_monitor_v2_aligned_bf_copi,
+ reg_bsn_monitor_v2_aligned_bf_cipo => reg_bsn_monitor_v2_aligned_bf_cipo,
+ reg_ring_lane_info_bf_copi => reg_ring_lane_info_bf_copi,
+ reg_ring_lane_info_bf_cipo => reg_ring_lane_info_bf_cipo,
+ reg_bsn_monitor_v2_ring_rx_bf_copi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ reg_bsn_monitor_v2_ring_rx_bf_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ reg_bsn_monitor_v2_ring_tx_bf_copi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ reg_bsn_monitor_v2_ring_tx_bf_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ reg_dp_block_validate_err_bf_copi => reg_dp_block_validate_err_bf_copi,
+ reg_dp_block_validate_err_bf_cipo => reg_dp_block_validate_err_bf_cipo,
+ reg_dp_block_validate_bsn_at_sync_bf_copi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ reg_dp_block_validate_bsn_at_sync_bf_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+
-- SST
- reg_stat_enable_sst_mosi => reg_stat_enable_sst_mosi,
- reg_stat_enable_sst_miso => reg_stat_enable_sst_miso,
- reg_stat_hdr_dat_sst_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_stat_hdr_dat_sst_miso => reg_stat_hdr_dat_sst_miso,
+ reg_stat_enable_sst_copi => reg_stat_enable_sst_copi,
+ reg_stat_enable_sst_cipo => reg_stat_enable_sst_cipo,
+ reg_stat_hdr_dat_sst_copi => reg_stat_hdr_dat_sst_copi,
+ reg_stat_hdr_dat_sst_cipo => reg_stat_hdr_dat_sst_cipo,
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
-- XST
- reg_stat_enable_xst_mosi => reg_stat_enable_xst_mosi,
- reg_stat_enable_xst_miso => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_xst_mosi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_xst_miso => reg_stat_hdr_dat_xst_miso,
+ reg_stat_enable_xst_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_xst_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_xst_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_xst_cipo => reg_stat_hdr_dat_xst_cipo,
- reg_bsn_align_copi => reg_bsn_align_v2_copi,
- reg_bsn_align_cipo => reg_bsn_align_v2_cipo,
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_v2_input_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_v2_input_cipo,
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_v2_output_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_v2_output_cipo,
- reg_xst_udp_monitor_copi => reg_bsn_monitor_v2_xst_offload_copi,
- reg_xst_udp_monitor_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+ reg_bsn_align_v2_xsub_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_v2_xsub_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_rx_align_xsub_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_rx_align_xsub_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_aligned_xsub_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_aligned_xsub_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
reg_ring_lane_info_xst_copi => reg_ring_lane_info_xst_copi,
reg_ring_lane_info_xst_cipo => reg_ring_lane_info_xst_cipo,
reg_bsn_monitor_v2_ring_rx_xst_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
@@ -858,12 +938,16 @@ BEGIN
reg_tr_10GbE_mac_cipo => reg_tr_10GbE_mac_cipo,
reg_tr_10GbE_eth10g_copi => reg_tr_10GbE_eth10g_copi,
reg_tr_10GbE_eth10g_cipo => reg_tr_10GbE_eth10g_cipo,
-
+
-- BST
- reg_stat_enable_bst_mosi => reg_stat_enable_bst_mosi,
- reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
- reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
- reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
+ reg_stat_enable_bst_copi => reg_stat_enable_bst_copi,
+ reg_stat_enable_bst_cipo => reg_stat_enable_bst_cipo,
+ reg_stat_hdr_dat_bst_copi => reg_stat_hdr_dat_bst_copi,
+ reg_stat_hdr_dat_bst_cipo => reg_stat_hdr_dat_bst_cipo,
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo,
RING_0_TX => RING_0_TX,
RING_0_RX => RING_0_RX,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index 1cf8f2d16ef84f2aaa5a4cb31ae35ef44100b90c..903b88e1ec98003c2d99c329173ef30ccc424c9f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -43,8 +43,10 @@ PACKAGE lofar2_unb2c_sdp_station_pkg IS
CONSTANT c_ait : t_lofar2_unb2c_sdp_station_config := (FALSE, FALSE, FALSE, FALSE, FALSE, 0);
CONSTANT c_fsub : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, FALSE, FALSE, 0);
CONSTANT c_bf : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, FALSE, 0);
+ CONSTANT c_bf_ring : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, TRUE, FALSE, TRUE, 0);
CONSTANT c_xsub_one : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, FALSE, 1);
CONSTANT c_xsub_ring : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, FALSE, TRUE, TRUE, 9);
+ CONSTANT c_full_wg : t_lofar2_unb2c_sdp_station_config := (TRUE, TRUE, TRUE, TRUE, TRUE, 9);
CONSTANT c_full : t_lofar2_unb2c_sdp_station_config := (FALSE, TRUE, TRUE, TRUE, TRUE, 9);
-- Function to select the revision configuration.
@@ -61,8 +63,10 @@ PACKAGE BODY lofar2_unb2c_sdp_station_pkg IS
IF g_design_name = "lofar2_unb2c_sdp_station_adc" THEN RETURN c_ait;
ELSIF g_design_name = "lofar2_unb2c_sdp_station_fsub" THEN RETURN c_fsub;
ELSIF g_design_name = "lofar2_unb2c_sdp_station_bf" THEN RETURN c_bf;
+ ELSIF g_design_name = "lofar2_unb2c_sdp_station_bf_ring" THEN RETURN c_bf_ring;
ELSIF g_design_name = "lofar2_unb2c_sdp_station_xsub_one" THEN RETURN c_xsub_one;
ELSIF g_design_name = "lofar2_unb2c_sdp_station_xsub_ring" THEN RETURN c_xsub_ring;
+ ELSIF g_design_name = "lofar2_unb2c_sdp_station_full_wg" THEN RETURN c_full_wg;
ELSE RETURN c_full;
END IF;
END;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 891f1d9e142edb221b29b545294285327f711465..5194a4392368001350704206205946a5429255bb 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -43,244 +43,285 @@ ENTITY mmm_lofar2_unb2c_sdp_station IS
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
- reg_wdi_mosi : OUT t_mem_mosi;
- reg_wdi_miso : IN t_mem_miso;
+ reg_wdi_copi : OUT t_mem_copi;
+ reg_wdi_cipo : IN t_mem_cipo;
-- system_info
- reg_unb_system_info_mosi : OUT t_mem_mosi;
- reg_unb_system_info_miso : IN t_mem_miso;
- rom_unb_system_info_mosi : OUT t_mem_mosi;
- rom_unb_system_info_miso : IN t_mem_miso;
+ reg_unb_system_info_copi : OUT t_mem_copi;
+ reg_unb_system_info_cipo : IN t_mem_cipo;
+ rom_unb_system_info_copi : OUT t_mem_copi;
+ rom_unb_system_info_cipo : IN t_mem_cipo;
- reg_fpga_temp_sens_mosi : OUT t_mem_mosi;
- reg_fpga_temp_sens_miso : IN t_mem_miso;
- reg_fpga_voltage_sens_mosi: OUT t_mem_mosi;
- reg_fpga_voltage_sens_miso: IN t_mem_miso;
+ reg_fpga_temp_sens_copi : OUT t_mem_copi;
+ reg_fpga_temp_sens_cipo : IN t_mem_cipo;
+ reg_fpga_voltage_sens_copi: OUT t_mem_copi;
+ reg_fpga_voltage_sens_cipo: IN t_mem_cipo;
-- PPSH
- reg_ppsh_mosi : OUT t_mem_mosi;
- reg_ppsh_miso : IN t_mem_miso;
+ reg_ppsh_copi : OUT t_mem_copi;
+ reg_ppsh_cipo : IN t_mem_cipo;
-- eth1g
eth1g_mm_rst : OUT STD_LOGIC;
- eth1g_tse_mosi : OUT t_mem_mosi;
- eth1g_tse_miso : IN t_mem_miso;
- eth1g_reg_mosi : OUT t_mem_mosi;
- eth1g_reg_miso : IN t_mem_miso;
+ eth1g_tse_copi : OUT t_mem_copi;
+ eth1g_tse_cipo : IN t_mem_cipo;
+ eth1g_reg_copi : OUT t_mem_copi;
+ eth1g_reg_cipo : IN t_mem_cipo;
eth1g_reg_interrupt : IN STD_LOGIC;
- eth1g_ram_mosi : OUT t_mem_mosi;
- eth1g_ram_miso : IN t_mem_miso;
+ eth1g_ram_copi : OUT t_mem_copi;
+ eth1g_ram_cipo : IN t_mem_cipo;
-- EPCS read
- reg_dpmm_data_mosi : OUT t_mem_mosi;
- reg_dpmm_data_miso : IN t_mem_miso;
- reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
- reg_dpmm_ctrl_miso : IN t_mem_miso;
+ reg_dpmm_data_copi : OUT t_mem_copi;
+ reg_dpmm_data_cipo : IN t_mem_cipo;
+ reg_dpmm_ctrl_copi : OUT t_mem_copi;
+ reg_dpmm_ctrl_cipo : IN t_mem_cipo;
-- EPCS write
- reg_mmdp_data_mosi : OUT t_mem_mosi;
- reg_mmdp_data_miso : IN t_mem_miso;
- reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
- reg_mmdp_ctrl_miso : IN t_mem_miso;
+ reg_mmdp_data_copi : OUT t_mem_copi;
+ reg_mmdp_data_cipo : IN t_mem_cipo;
+ reg_mmdp_ctrl_copi : OUT t_mem_copi;
+ reg_mmdp_ctrl_cipo : IN t_mem_cipo;
-- EPCS status/control
- reg_epcs_mosi : OUT t_mem_mosi;
- reg_epcs_miso : IN t_mem_miso;
+ reg_epcs_copi : OUT t_mem_copi;
+ reg_epcs_cipo : IN t_mem_cipo;
-- Remote Update
- reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso;
+ reg_remu_copi : OUT t_mem_copi;
+ reg_remu_cipo : IN t_mem_cipo;
-- Jesd control
- jesd204b_mosi : OUT t_mem_mosi;
- jesd204b_miso : IN t_mem_miso;
+ jesd204b_copi : OUT t_mem_copi;
+ jesd204b_cipo : IN t_mem_cipo;
-- Dp shiftram
- reg_dp_shiftram_mosi : OUT t_mem_mosi;
- reg_dp_shiftram_miso : IN t_mem_miso;
+ reg_dp_shiftram_copi : OUT t_mem_copi;
+ reg_dp_shiftram_cipo : IN t_mem_cipo;
-- Bsn source
- reg_bsn_source_v2_mosi : OUT t_mem_mosi;
- reg_bsn_source_v2_miso : IN t_mem_miso;
+ reg_bsn_source_v2_copi : OUT t_mem_copi;
+ reg_bsn_source_v2_cipo : IN t_mem_cipo;
-- bsn schduler for wg trigger
- reg_bsn_scheduler_mosi : OUT t_mem_mosi;
- reg_bsn_scheduler_miso : IN t_mem_miso;
+ reg_bsn_scheduler_copi : OUT t_mem_copi;
+ reg_bsn_scheduler_cipo : IN t_mem_cipo;
-- BSN Monitor
- reg_bsn_monitor_input_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_monitor_input_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_bsn_monitor_input_copi : OUT t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_input_cipo : IN t_mem_cipo := c_mem_cipo_rst;
-- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
- reg_wg_mosi : OUT t_mem_mosi;
- reg_wg_miso : IN t_mem_miso;
- ram_wg_mosi : OUT t_mem_mosi;
- ram_wg_miso : IN t_mem_miso;
+ reg_wg_copi : OUT t_mem_copi;
+ reg_wg_cipo : IN t_mem_cipo;
+ ram_wg_copi : OUT t_mem_copi;
+ ram_wg_cipo : IN t_mem_cipo;
-- Bsn databuffer
- ram_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
- ram_diag_data_buf_bsn_miso : IN t_mem_miso;
- reg_diag_data_buf_bsn_mosi : OUT t_mem_mosi;
- reg_diag_data_buf_bsn_miso : IN t_mem_miso;
+ ram_diag_data_buf_bsn_copi : OUT t_mem_copi;
+ ram_diag_data_buf_bsn_cipo : IN t_mem_cipo;
+ reg_diag_data_buf_bsn_copi : OUT t_mem_copi;
+ reg_diag_data_buf_bsn_cipo : IN t_mem_cipo;
-- ST Histogram
- ram_st_histogram_mosi : OUT t_mem_mosi;
- ram_st_histogram_miso : IN t_mem_miso;
+ ram_st_histogram_copi : OUT t_mem_copi;
+ ram_st_histogram_cipo : IN t_mem_cipo;
-- Aduh
- reg_aduh_monitor_mosi : OUT t_mem_mosi;
- reg_aduh_monitor_miso : IN t_mem_miso;
+ reg_aduh_monitor_copi : OUT t_mem_copi;
+ reg_aduh_monitor_cipo : IN t_mem_cipo;
-- Subband statistics
- ram_st_sst_mosi : OUT t_mem_mosi;
- ram_st_sst_miso : IN t_mem_miso;
+ ram_st_sst_copi : OUT t_mem_copi;
+ ram_st_sst_cipo : IN t_mem_cipo;
-- Filter coefficients
- ram_fil_coefs_mosi : OUT t_mem_mosi;
- ram_fil_coefs_miso : IN t_mem_miso;
+ ram_fil_coefs_copi : OUT t_mem_copi;
+ ram_fil_coefs_cipo : IN t_mem_cipo;
-- Spectral Inversion
- reg_si_mosi : OUT t_mem_mosi;
- reg_si_miso : IN t_mem_miso;
+ reg_si_copi : OUT t_mem_copi;
+ reg_si_cipo : IN t_mem_cipo;
-- Equalizer gains
- ram_equalizer_gains_mosi : OUT t_mem_mosi;
- ram_equalizer_gains_miso : IN t_mem_miso;
+ ram_equalizer_gains_copi : OUT t_mem_copi;
+ ram_equalizer_gains_cipo : IN t_mem_cipo;
-- DP Selector
- reg_dp_selector_mosi : OUT t_mem_mosi;
- reg_dp_selector_miso : IN t_mem_miso;
+ reg_dp_selector_copi : OUT t_mem_copi;
+ reg_dp_selector_cipo : IN t_mem_cipo;
-- SDP Info
- reg_sdp_info_mosi : OUT t_mem_mosi;
- reg_sdp_info_miso : IN t_mem_miso;
+ reg_sdp_info_copi : OUT t_mem_copi;
+ reg_sdp_info_cipo : IN t_mem_cipo;
-- RING Info
- reg_ring_info_copi : OUT t_mem_mosi;
- reg_ring_info_cipo : IN t_mem_miso;
-
+ reg_ring_info_copi : OUT t_mem_copi;
+ reg_ring_info_cipo : IN t_mem_cipo;
-- Beamlet Subband Select
- ram_ss_ss_wide_mosi : OUT t_mem_mosi;
- ram_ss_ss_wide_miso : IN t_mem_miso;
+ ram_ss_ss_wide_copi : OUT t_mem_copi;
+ ram_ss_ss_wide_cipo : IN t_mem_cipo;
-- Local BF bf weights
- ram_bf_weights_mosi : OUT t_mem_mosi;
- ram_bf_weights_miso : IN t_mem_miso;
+ ram_bf_weights_copi : OUT t_mem_copi;
+ ram_bf_weights_cipo : IN t_mem_cipo;
+
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : OUT t_mem_copi;
+ reg_bsn_align_v2_bf_cipo : IN t_mem_cipo;
+
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_aligned_bf_cipo : IN t_mem_cipo;
-- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : OUT t_mem_mosi;
- reg_bf_scale_miso : IN t_mem_miso;
+ reg_bf_scale_copi : OUT t_mem_copi;
+ reg_bf_scale_cipo : IN t_mem_cipo;
-- Beamlet Data Output header fields
- reg_hdr_dat_mosi : OUT t_mem_mosi;
- reg_hdr_dat_miso : IN t_mem_miso;
+ reg_hdr_dat_copi : OUT t_mem_copi;
+ reg_hdr_dat_cipo : IN t_mem_cipo;
-- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : OUT t_mem_mosi;
- reg_dp_xonoff_miso : IN t_mem_miso;
+ reg_dp_xonoff_copi : OUT t_mem_copi;
+ reg_dp_xonoff_cipo : IN t_mem_cipo;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : OUT t_mem_copi;
+ reg_ring_lane_info_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : OUT t_mem_copi;
+ reg_dp_block_validate_err_bf_cipo : IN t_mem_cipo;
+
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : OUT t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : IN t_mem_cipo;
-- Beamlet Statistics (BST)
- ram_st_bst_mosi : OUT t_mem_mosi;
- ram_st_bst_miso : IN t_mem_miso;
+ ram_st_bst_copi : OUT t_mem_copi;
+ ram_st_bst_cipo : IN t_mem_cipo;
-- Subband Statistics offload
- reg_stat_enable_sst_mosi : OUT t_mem_mosi;
- reg_stat_enable_sst_miso : IN t_mem_miso;
+ reg_stat_enable_sst_copi : OUT t_mem_copi;
+ reg_stat_enable_sst_cipo : IN t_mem_cipo;
-- Statistics header info
- reg_stat_hdr_dat_sst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_sst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_sst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_sst_cipo : IN t_mem_cipo;
-- Crosslet Statistics offload
- reg_stat_enable_xst_mosi : OUT t_mem_mosi;
- reg_stat_enable_xst_miso : IN t_mem_miso;
+ reg_stat_enable_xst_copi : OUT t_mem_copi;
+ reg_stat_enable_xst_cipo : IN t_mem_cipo;
-- Crosslet Statistics header info
- reg_stat_hdr_dat_xst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_xst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_xst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_xst_cipo : IN t_mem_cipo;
-- Beamlet Statistics offload
- reg_stat_enable_bst_mosi : OUT t_mem_mosi;
- reg_stat_enable_bst_miso : IN t_mem_miso;
+ reg_stat_enable_bst_copi : OUT t_mem_copi;
+ reg_stat_enable_bst_cipo : IN t_mem_cipo;
-- Beamlet Statistics header info
- reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
- reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
+ reg_stat_hdr_dat_bst_copi : OUT t_mem_copi;
+ reg_stat_hdr_dat_bst_cipo : IN t_mem_cipo;
-- crosslets_info
- reg_crosslets_info_mosi : OUT t_mem_mosi;
- reg_crosslets_info_miso : IN t_mem_miso;
+ reg_crosslets_info_copi : OUT t_mem_copi;
+ reg_crosslets_info_cipo : IN t_mem_cipo;
-- crosslets_info
- reg_nof_crosslets_mosi : OUT t_mem_mosi;
- reg_nof_crosslets_miso : IN t_mem_miso;
+ reg_nof_crosslets_copi : OUT t_mem_copi;
+ reg_nof_crosslets_cipo : IN t_mem_cipo;
-- bsn_sync_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
- reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
+ reg_bsn_sync_scheduler_xsub_copi : OUT t_mem_copi;
+ reg_bsn_sync_scheduler_xsub_cipo : IN t_mem_cipo;
-- st_xsq (XST)
- ram_st_xsq_mosi : OUT t_mem_mosi;
- ram_st_xsq_miso : IN t_mem_miso;
+ ram_st_xsq_copi : OUT t_mem_copi;
+ ram_st_xsq_cipo : IN t_mem_cipo;
-- 10 GbE mac
- reg_nw_10GbE_mac_mosi : OUT t_mem_mosi;
- reg_nw_10GbE_mac_miso : IN t_mem_miso;
+ reg_nw_10GbE_mac_copi : OUT t_mem_copi;
+ reg_nw_10GbE_mac_cipo : IN t_mem_cipo;
-- 10 GbE eth
- reg_nw_10GbE_eth10g_mosi : OUT t_mem_mosi;
- reg_nw_10GbE_eth10g_miso : IN t_mem_miso;
+ reg_nw_10GbE_eth10g_copi : OUT t_mem_copi;
+ reg_nw_10GbE_eth10g_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2
- reg_bsn_align_v2_copi : OUT t_mem_mosi;
- reg_bsn_align_v2_cipo : IN t_mem_miso;
+ reg_bsn_align_v2_xsub_copi : OUT t_mem_copi;
+ reg_bsn_align_v2_xsub_cipo : IN t_mem_cipo;
-- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_bsn_align_v2_input_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_v2_input_cipo : IN t_mem_miso;
- reg_bsn_monitor_v2_bsn_align_v2_output_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_v2_output_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_rx_align_xsub_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : IN t_mem_cipo;
+ reg_bsn_monitor_v2_aligned_xsub_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : IN t_mem_cipo;
-- XST UDP offload bsn monitor
- reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_xst_offload_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_xst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_xst_offload_cipo : IN t_mem_cipo;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_bst_offload_cipo : IN t_mem_cipo;
+
+ -- Beamlet output bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_beamlet_output_cipo : IN t_mem_cipo;
+
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_sst_offload_cipo : IN t_mem_cipo;
-- XST ring lane info
- reg_ring_lane_info_xst_copi : OUT t_mem_mosi;
- reg_ring_lane_info_xst_cipo : IN t_mem_miso;
+ reg_ring_lane_info_xst_copi : OUT t_mem_copi;
+ reg_ring_lane_info_xst_cipo : IN t_mem_cipo;
-- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_mosi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_miso;
+ reg_bsn_monitor_v2_ring_rx_xst_copi: OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo: IN t_mem_cipo;
-- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_mosi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_miso;
+ reg_bsn_monitor_v2_ring_tx_xst_copi : OUT t_mem_copi;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : IN t_mem_cipo;
-- XST ring validate err
- reg_dp_block_validate_err_xst_copi : OUT t_mem_mosi;
- reg_dp_block_validate_err_xst_cipo : IN t_mem_miso;
+ reg_dp_block_validate_err_xst_copi : OUT t_mem_copi;
+ reg_dp_block_validate_err_xst_cipo : IN t_mem_cipo;
-- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_mosi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_miso;
+ reg_dp_block_validate_bsn_at_sync_xst_copi : OUT t_mem_copi;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : IN t_mem_cipo;
-- XST ring MAC
- reg_tr_10GbE_mac_copi : OUT t_mem_mosi;
- reg_tr_10GbE_mac_cipo : IN t_mem_miso;
+ reg_tr_10GbE_mac_copi : OUT t_mem_copi;
+ reg_tr_10GbE_mac_cipo : IN t_mem_cipo;
-- XST ring ETH
- reg_tr_10GbE_eth10g_copi : OUT t_mem_mosi;
- reg_tr_10GbE_eth10g_cipo : IN t_mem_miso;
+ reg_tr_10GbE_eth10g_copi : OUT t_mem_copi;
+ reg_tr_10GbE_eth10g_cipo : IN t_mem_cipo;
-- Scrap ram
- ram_scrap_mosi : OUT t_mem_mosi;
- ram_scrap_miso : IN t_mem_miso;
+ ram_scrap_copi : OUT t_mem_copi;
+ ram_scrap_cipo : IN t_mem_cipo;
-- Jesd reset control
- jesd_ctrl_mosi : OUT t_mem_mosi;
- jesd_ctrl_miso : IN t_mem_miso
+ jesd_ctrl_copi : OUT t_mem_copi;
+ jesd_ctrl_cipo : IN t_mem_cipo
);
END mmm_lofar2_unb2c_sdp_station;
@@ -300,147 +341,180 @@ BEGIN
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_copi, rom_unb_system_info_cipo );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wdi_copi, reg_wdi_cipo );
u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_copi, reg_fpga_temp_sens_cipo );
u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
- PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_copi, reg_fpga_voltage_sens_cipo );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_copi, reg_ppsh_cipo );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
- PORT MAP(mm_rst, mm_clk, jesd204b_mosi, jesd204b_miso );
+ PORT MAP(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
- PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
u_mm_file_reg_bsn_source_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
- PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_copi, reg_bsn_source_v2_cipo );
u_mm_file_reg_bsn_scheduler : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
- PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_copi, reg_bsn_scheduler_cipo );
u_mm_file_reg_bsn_monitor_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_INPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_mosi, reg_bsn_monitor_input_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_input_copi, reg_bsn_monitor_input_cipo );
u_mm_file_reg_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WG")
- PORT MAP(mm_rst, mm_clk, reg_wg_mosi, reg_wg_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wg_copi, reg_wg_cipo );
u_mm_file_ram_wg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_WG")
- PORT MAP(mm_rst, mm_clk, ram_wg_mosi, ram_wg_miso );
+ PORT MAP(mm_rst, mm_clk, ram_wg_copi, ram_wg_cipo );
u_mm_file_ram_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_mosi, ram_diag_data_buf_bsn_miso );
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_bsn_copi, ram_diag_data_buf_bsn_cipo );
u_mm_file_reg_diag_data_buf_bsn : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_BSN")
- PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_mosi, reg_diag_data_buf_bsn_miso );
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_bsn_copi, reg_diag_data_buf_bsn_cipo );
u_mm_file_ram_st_histogram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_HISTOGRAM")
- PORT MAP(mm_rst, mm_clk, ram_st_histogram_mosi, ram_st_histogram_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_histogram_copi, ram_st_histogram_cipo );
u_mm_file_reg_aduh_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ADUH_MONITOR")
- PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_mosi, reg_aduh_monitor_miso );
+ PORT MAP(mm_rst, mm_clk, reg_aduh_monitor_copi, reg_aduh_monitor_cipo );
u_mm_file_ram_st_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
- PORT MAP(mm_rst, mm_clk, ram_st_sst_mosi, ram_st_sst_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_sst_copi, ram_st_sst_cipo );
u_mm_file_ram_fil_coefs : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_FIL_COEFS")
- PORT MAP(mm_rst, mm_clk, ram_fil_coefs_mosi, ram_fil_coefs_miso );
+ PORT MAP(mm_rst, mm_clk, ram_fil_coefs_copi, ram_fil_coefs_cipo );
u_mm_file_reg_si : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SI")
- PORT MAP(mm_rst, mm_clk, reg_si_mosi, reg_si_miso );
+ PORT MAP(mm_rst, mm_clk, reg_si_copi, reg_si_cipo );
u_mm_file_ram_equalizer_gains : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_EQUALIZER_GAINS")
- PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_mosi, ram_equalizer_gains_miso );
+ PORT MAP(mm_rst, mm_clk, ram_equalizer_gains_copi, ram_equalizer_gains_cipo );
u_mm_file_reg_dp_selector : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SELECTOR")
- PORT MAP(mm_rst, mm_clk, reg_dp_selector_mosi, reg_dp_selector_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_selector_copi, reg_dp_selector_cipo );
u_mm_file_reg_sdp_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_SDP_INFO")
- PORT MAP(mm_rst, mm_clk, reg_sdp_info_mosi, reg_sdp_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_sdp_info_copi, reg_sdp_info_cipo );
u_mm_file_reg_ring_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_INFO")
PORT MAP(mm_rst, mm_clk, reg_ring_info_copi, reg_ring_info_cipo );
u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
- PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
+ PORT MAP(mm_rst, mm_clk, ram_ss_ss_wide_copi, ram_ss_ss_wide_cipo );
u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
- PORT MAP(mm_rst, mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
+ PORT MAP(mm_rst, mm_clk, ram_bf_weights_copi, ram_bf_weights_cipo );
u_mm_file_reg_bf_scale : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BF_SCALE")
- PORT MAP(mm_rst, mm_clk, reg_bf_scale_mosi, reg_bf_scale_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bf_scale_copi, reg_bf_scale_cipo );
u_mm_file_reg_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_hdr_dat_mosi, reg_hdr_dat_miso );
+ PORT MAP(mm_rst, mm_clk, reg_hdr_dat_copi, reg_hdr_dat_cipo );
u_mm_file_reg_dp_xonoff : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_XONOFF")
- PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_mosi, reg_dp_xonoff_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_xonoff_copi, reg_dp_xonoff_cipo );
u_mm_file_ram_st_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_BST")
- PORT MAP(mm_rst, mm_clk, ram_st_bst_mosi, ram_st_bst_miso );
+ PORT MAP(mm_rst, mm_clk, ram_st_bst_copi, ram_st_bst_cipo );
u_mm_file_reg_stat_enable_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_SST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_mosi, reg_stat_enable_sst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_sst_copi, reg_stat_enable_sst_cipo );
u_mm_file_reg_stat_hdr_info_sst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_SST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_mosi, reg_stat_hdr_dat_sst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_sst_copi, reg_stat_hdr_dat_sst_cipo);
u_mm_file_reg_stat_enable_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_XST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_mosi, reg_stat_enable_xst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_xst_copi, reg_stat_enable_xst_cipo );
u_mm_file_reg_stat_hdr_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_XST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_mosi, reg_stat_hdr_dat_xst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_xst_copi, reg_stat_hdr_dat_xst_cipo);
u_mm_file_reg_stat_enable_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_ENABLE_BST")
- PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_mosi, reg_stat_enable_bst_miso );
+ PORT MAP(mm_rst, mm_clk, reg_stat_enable_bst_copi, reg_stat_enable_bst_cipo );
u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
- PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
+ PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_copi, reg_stat_hdr_dat_bst_cipo);
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
- PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
+ PORT MAP(mm_rst, mm_clk, reg_crosslets_info_copi, reg_crosslets_info_cipo);
u_mm_file_reg_nof_crosslets : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NOF_CROSSLETS")
- PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_mosi, reg_nof_crosslets_miso);
+ PORT MAP(mm_rst, mm_clk, reg_nof_crosslets_copi, reg_nof_crosslets_cipo);
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
- PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
+ PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_copi, reg_bsn_sync_scheduler_xsub_cipo);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
- PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
+ PORT MAP(mm_rst, mm_clk, ram_st_xsq_copi, ram_st_xsq_cipo);
u_mm_file_reg_nw_10GbE_mac : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_MAC")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_mosi, reg_nw_10GbE_mac_miso );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_mac_copi, reg_nw_10GbE_mac_cipo );
u_mm_file_reg_nw_10GbE_eth10g : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_NW_10GBE_ETH10G")
- PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_mosi, reg_nw_10GbE_eth10g_miso );
+ PORT MAP(mm_rst, mm_clk, reg_nw_10GbE_eth10g_copi, reg_nw_10GbE_eth10g_cipo );
+
+ u_mm_file_reg_bsn_align_v2_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_bf_copi, reg_bsn_align_v2_bf_cipo );
- u_mm_file_reg_bsn_align_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2")
- PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_copi, reg_bsn_align_v2_cipo );
+ u_mm_file_reg_bsn_monitor_v2_rx_align_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_bf_copi, reg_bsn_monitor_v2_rx_align_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_input : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_INPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_input_copi, reg_bsn_monitor_v2_bsn_align_v2_input_cipo );
+ u_mm_file_reg_bsn_monitor_v2_aligned_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_bf_copi, reg_bsn_monitor_v2_aligned_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_bsn_align_v2_output: mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BSN_ALIGN_V2_OUTPUT")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bsn_align_v2_output_copi, reg_bsn_monitor_v2_bsn_align_v2_output_cipo );
+ u_mm_file_reg_ring_lane_info_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_BF")
+ PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_bf_copi, reg_ring_lane_info_bf_cipo );
- u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_rx_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_copi, reg_bsn_monitor_v2_ring_rx_bf_cipo );
- u_mm_file_reg_ring_lane_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
- PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
+ u_mm_file_reg_bsn_monitor_v2_ring_tx_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_TX_BF")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_copi, reg_bsn_monitor_v2_ring_tx_bf_cipo );
+
+ u_mm_file_reg_dp_block_validate_err_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_ERR_BF")
+ PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_err_bf_copi, reg_dp_block_validate_err_bf_cipo );
+
+ u_mm_file_reg_dp_block_validate_bsn_at_sync_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF")
+ PORT MAP(mm_rst, mm_clk, reg_dp_block_validate_bsn_at_sync_bf_copi, reg_dp_block_validate_bsn_at_sync_bf_cipo );
+
+ u_mm_file_reg_bsn_align_v2_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_ALIGN_V2_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_align_v2_xsub_copi, reg_bsn_align_v2_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_rx_align_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RX_ALIGN_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_rx_align_xsub_copi, reg_bsn_monitor_v2_rx_align_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_aligned_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_ALIGNED_XSUB")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_aligned_xsub_copi, reg_bsn_monitor_v2_aligned_xsub_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_sst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_SST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_sst_offload_copi, reg_bsn_monitor_v2_sst_offload_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_bst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_bst_offload_copi, reg_bsn_monitor_v2_bst_offload_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_beamlet_output : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_BEAMLET_OUTPUT")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_beamlet_output_copi, reg_bsn_monitor_v2_beamlet_output_cipo );
+
+ u_mm_file_reg_bsn_monitor_v2_xst_offload : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_XST_OFFLOAD")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_xst_offload_copi, reg_bsn_monitor_v2_xst_offload_cipo );
+
+ u_mm_file_reg_ring_lane_info_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RING_LANE_INFO_XST")
+ PORT MAP(mm_rst, mm_clk, reg_ring_lane_info_xst_copi, reg_ring_lane_info_xst_cipo );
u_mm_file_reg_bsn_monitor_v2_ring_rx_xst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_V2_RING_RX_XST")
PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_v2_ring_rx_xst_copi, reg_bsn_monitor_v2_ring_rx_xst_cipo );
@@ -461,7 +535,7 @@ BEGIN
PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_eth10g_copi, reg_tr_10GbE_eth10g_cipo );
u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
- PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+ PORT MAP(mm_rst, mm_clk, ram_scrap_copi, ram_scrap_cipo );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
@@ -486,266 +560,266 @@ BEGIN
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
- avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
- avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
- avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
- avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
- avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
- avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
- avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
- avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_address_export => eth1g_tse_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ avs_eth_0_tse_write_export => eth1g_tse_copi.wr,
+ avs_eth_0_tse_read_export => eth1g_tse_copi.rd,
+ avs_eth_0_tse_writedata_export => eth1g_tse_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_readdata_export => eth1g_tse_cipo.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_tse_waitrequest_export => eth1g_tse_cipo.waitrequest,
+ avs_eth_0_reg_address_export => eth1g_reg_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_reg_write_export => eth1g_reg_copi.wr,
+ avs_eth_0_reg_read_export => eth1g_reg_copi.rd,
+ avs_eth_0_reg_writedata_export => eth1g_reg_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_reg_readdata_export => eth1g_reg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_address_export => eth1g_ram_copi.address(c_unb2c_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ avs_eth_0_ram_write_export => eth1g_ram_copi.wr,
+ avs_eth_0_ram_read_export => eth1g_ram_copi.rd,
+ avs_eth_0_ram_writedata_export => eth1g_ram_copi.wrdata(c_word_w-1 DOWNTO 0),
+ avs_eth_0_ram_readdata_export => eth1g_ram_cipo.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_irq_export => eth1g_reg_interrupt,
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
- reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
- reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
- reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
- reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_copi.wr,
+ reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_copi.rd,
+ reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
- reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
- reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
- reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
- reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_copi.wr,
+ reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_copi.rd,
+ reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_cipo.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
-- ToDo: This has changed in the peripherals package
--- rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
- rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- rom_system_info_write_export => rom_unb_system_info_mosi.wr,
- rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- rom_system_info_read_export => rom_unb_system_info_mosi.rd,
- rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+-- rom_system_info_address_export => rom_unb_system_info_copi.address(9 DOWNTO 0),
+ rom_system_info_address_export => rom_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ rom_system_info_write_export => rom_unb_system_info_copi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ rom_system_info_read_export => rom_unb_system_info_copi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
- pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
- pio_system_info_write_export => reg_unb_system_info_mosi.wr,
- pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_system_info_read_export => reg_unb_system_info_mosi.rd,
- pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ pio_system_info_write_export => reg_unb_system_info_copi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_read_export => reg_unb_system_info_copi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
- pio_pps_address_export => reg_ppsh_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
- pio_pps_write_export => reg_ppsh_mosi.wr,
- pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_pps_read_export => reg_ppsh_mosi.rd,
- pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_pps_address_export => reg_ppsh_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+ pio_pps_write_export => reg_ppsh_copi.wr,
+ pio_pps_writedata_export => reg_ppsh_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_pps_read_export => reg_ppsh_copi.rd,
+ pio_pps_readdata_export => reg_ppsh_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_wdi_reset_export => OPEN,
reg_wdi_clk_export => OPEN,
- reg_wdi_address_export => reg_wdi_mosi.address(0 DOWNTO 0),
- reg_wdi_write_export => reg_wdi_mosi.wr,
- reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_wdi_read_export => reg_wdi_mosi.rd,
- reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_wdi_address_export => reg_wdi_copi.address(0 DOWNTO 0),
+ reg_wdi_write_export => reg_wdi_copi.wr,
+ reg_wdi_writedata_export => reg_wdi_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wdi_read_export => reg_wdi_copi.rd,
+ reg_wdi_readdata_export => reg_wdi_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
- reg_remu_address_export => reg_remu_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
- reg_remu_write_export => reg_remu_mosi.wr,
- reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_remu_read_export => reg_remu_mosi.rd,
- reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_remu_address_export => reg_remu_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
+ reg_remu_write_export => reg_remu_copi.wr,
+ reg_remu_writedata_export => reg_remu_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_remu_read_export => reg_remu_copi.rd,
+ reg_remu_readdata_export => reg_remu_cipo.rddata(c_word_w-1 DOWNTO 0),
jesd204b_reset_export => OPEN,
jesd204b_clk_export => OPEN,
- jesd204b_address_export => jesd204b_mosi.address(c_sdp_jesd204b_addr_w-1 DOWNTO 0),
- jesd204b_write_export => jesd204b_mosi.wr,
- jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w-1 DOWNTO 0),
- jesd204b_read_export => jesd204b_mosi.rd,
- jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
+ jesd204b_address_export => jesd204b_copi.address(c_sdp_jesd204b_addr_w-1 DOWNTO 0),
+ jesd204b_write_export => jesd204b_copi.wr,
+ jesd204b_writedata_export => jesd204b_copi.wrdata(c_word_w-1 DOWNTO 0),
+ jesd204b_read_export => jesd204b_copi.rd,
+ jesd204b_readdata_export => jesd204b_cipo.rddata(c_word_w-1 DOWNTO 0),
pio_jesd_ctrl_reset_export => OPEN,
pio_jesd_ctrl_clk_export => OPEN,
- pio_jesd_ctrl_address_export => jesd_ctrl_mosi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
- pio_jesd_ctrl_write_export => jesd_ctrl_mosi.wr,
- pio_jesd_ctrl_writedata_export => jesd_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- pio_jesd_ctrl_read_export => jesd_ctrl_mosi.rd,
- pio_jesd_ctrl_readdata_export => jesd_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_address_export => jesd_ctrl_copi.address(c_sdp_jesd_ctrl_addr_w-1 DOWNTO 0),
+ pio_jesd_ctrl_write_export => jesd_ctrl_copi.wr,
+ pio_jesd_ctrl_writedata_export => jesd_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_jesd_ctrl_read_export => jesd_ctrl_copi.rd,
+ pio_jesd_ctrl_readdata_export => jesd_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_mosi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_address_export => reg_bsn_monitor_input_copi.address(c_sdp_reg_bsn_monitor_input_addr_w-1 DOWNTO 0),
reg_bsn_monitor_input_clk_export => OPEN,
- reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_mosi.rd,
- reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_read_export => reg_bsn_monitor_input_copi.rd,
+ reg_bsn_monitor_input_readdata_export => reg_bsn_monitor_input_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_input_reset_export => OPEN,
- reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_mosi.wr,
- reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_input_write_export => reg_bsn_monitor_input_copi.wr,
+ reg_bsn_monitor_input_writedata_export => reg_bsn_monitor_input_copi.wrdata(c_word_w-1 DOWNTO 0),
-- waveform generators (multiplexed)
reg_wg_clk_export => OPEN,
reg_wg_reset_export => OPEN,
- reg_wg_address_export => reg_wg_mosi.address(c_sdp_reg_wg_addr_w-1 DOWNTO 0),
- reg_wg_read_export => reg_wg_mosi.rd,
- reg_wg_readdata_export => reg_wg_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_wg_write_export => reg_wg_mosi.wr,
- reg_wg_writedata_export => reg_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wg_address_export => reg_wg_copi.address(c_sdp_reg_wg_addr_w-1 DOWNTO 0),
+ reg_wg_read_export => reg_wg_copi.rd,
+ reg_wg_readdata_export => reg_wg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_wg_write_export => reg_wg_copi.wr,
+ reg_wg_writedata_export => reg_wg_copi.wrdata(c_word_w-1 DOWNTO 0),
ram_wg_clk_export => OPEN,
ram_wg_reset_export => OPEN,
- ram_wg_address_export => ram_wg_mosi.address(c_sdp_ram_wg_addr_w-1 DOWNTO 0),
- ram_wg_read_export => ram_wg_mosi.rd,
- ram_wg_readdata_export => ram_wg_miso.rddata(c_word_w-1 DOWNTO 0),
- ram_wg_write_export => ram_wg_mosi.wr,
- ram_wg_writedata_export => ram_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_wg_address_export => ram_wg_copi.address(c_sdp_ram_wg_addr_w-1 DOWNTO 0),
+ ram_wg_read_export => ram_wg_copi.rd,
+ ram_wg_readdata_export => ram_wg_cipo.rddata(c_word_w-1 DOWNTO 0),
+ ram_wg_write_export => ram_wg_copi.wr,
+ ram_wg_writedata_export => ram_wg_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_shiftram_clk_export => OPEN,
reg_dp_shiftram_reset_export => OPEN,
- reg_dp_shiftram_address_export => reg_dp_shiftram_mosi.address(c_sdp_reg_dp_shiftram_addr_w-1 DOWNTO 0),
- reg_dp_shiftram_read_export => reg_dp_shiftram_mosi.rd,
- reg_dp_shiftram_readdata_export => reg_dp_shiftram_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
- reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_shiftram_address_export => reg_dp_shiftram_copi.address(c_sdp_reg_dp_shiftram_addr_w-1 DOWNTO 0),
+ reg_dp_shiftram_read_export => reg_dp_shiftram_copi.rd,
+ reg_dp_shiftram_readdata_export => reg_dp_shiftram_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_shiftram_write_export => reg_dp_shiftram_copi.wr,
+ reg_dp_shiftram_writedata_export => reg_dp_shiftram_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_source_v2_clk_export => OPEN,
reg_bsn_source_v2_reset_export => OPEN,
- reg_bsn_source_v2_address_export => reg_bsn_source_v2_mosi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
- reg_bsn_source_v2_read_export => reg_bsn_source_v2_mosi.rd,
- reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_source_v2_write_export => reg_bsn_source_v2_mosi.wr,
- reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_address_export => reg_bsn_source_v2_copi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
+ reg_bsn_source_v2_read_export => reg_bsn_source_v2_copi.rd,
+ reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_write_export => reg_bsn_source_v2_copi.wr,
+ reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_scheduler_clk_export => OPEN,
reg_bsn_scheduler_reset_export => OPEN,
- reg_bsn_scheduler_address_export => reg_bsn_scheduler_mosi.address(c_sdp_reg_bsn_scheduler_addr_w-1 DOWNTO 0),
- reg_bsn_scheduler_read_export => reg_bsn_scheduler_mosi.rd,
- reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_scheduler_write_export => reg_bsn_scheduler_mosi.wr,
- reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_address_export => reg_bsn_scheduler_copi.address(c_sdp_reg_bsn_scheduler_addr_w-1 DOWNTO 0),
+ reg_bsn_scheduler_read_export => reg_bsn_scheduler_copi.rd,
+ reg_bsn_scheduler_readdata_export => reg_bsn_scheduler_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_scheduler_write_export => reg_bsn_scheduler_copi.wr,
+ reg_bsn_scheduler_writedata_export => reg_bsn_scheduler_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
- reg_epcs_address_export => reg_epcs_mosi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
- reg_epcs_write_export => reg_epcs_mosi.wr,
- reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_epcs_read_export => reg_epcs_mosi.rd,
- reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_epcs_address_export => reg_epcs_copi.address(c_unb2c_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
+ reg_epcs_write_export => reg_epcs_copi.wr,
+ reg_epcs_writedata_export => reg_epcs_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_epcs_read_export => reg_epcs_copi.rd,
+ reg_epcs_readdata_export => reg_epcs_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_ctrl_reset_export => OPEN,
reg_dpmm_ctrl_clk_export => OPEN,
- reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 DOWNTO 0),
- reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
- reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
- reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_copi.address(0 DOWNTO 0),
+ reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_copi.wr,
+ reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_copi.rd,
+ reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_data_reset_export => OPEN,
reg_mmdp_data_clk_export => OPEN,
- reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 DOWNTO 0),
- reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
- reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
- reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_address_export => reg_mmdp_data_copi.address(0 DOWNTO 0),
+ reg_mmdp_data_write_export => reg_mmdp_data_copi.wr,
+ reg_mmdp_data_writedata_export => reg_mmdp_data_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_data_read_export => reg_mmdp_data_copi.rd,
+ reg_mmdp_data_readdata_export => reg_mmdp_data_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_data_reset_export => OPEN,
reg_dpmm_data_clk_export => OPEN,
- reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 DOWNTO 0),
- reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
- reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
- reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_address_export => reg_dpmm_data_copi.address(0 DOWNTO 0),
+ reg_dpmm_data_read_export => reg_dpmm_data_copi.rd,
+ reg_dpmm_data_readdata_export => reg_dpmm_data_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_dpmm_data_write_export => reg_dpmm_data_copi.wr,
+ reg_dpmm_data_writedata_export => reg_dpmm_data_copi.wrdata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_reset_export => OPEN,
reg_mmdp_ctrl_clk_export => OPEN,
- reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 DOWNTO 0),
- reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
- reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_copi.address(0 DOWNTO 0),
+ reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_copi.rd,
+ reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_copi.wr,
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_copi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
- ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_mosi.wr,
- ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_mosi.rd,
- ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_copi.address(c_sdp_ram_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_write_export => ram_diag_data_buf_bsn_copi.wr,
+ ram_diag_data_buffer_bsn_writedata_export => ram_diag_data_buf_bsn_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_diag_data_buffer_bsn_read_export => ram_diag_data_buf_bsn_copi.rd,
+ ram_diag_data_buffer_bsn_readdata_export => ram_diag_data_buf_bsn_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_bsn_reset_export => OPEN,
reg_diag_data_buffer_bsn_clk_export => OPEN,
- reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_mosi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
- reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_mosi.wr,
- reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_mosi.rd,
- reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_address_export => reg_diag_data_buf_bsn_copi.address(c_sdp_reg_diag_data_buf_bsn_addr_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_write_export => reg_diag_data_buf_bsn_copi.wr,
+ reg_diag_data_buffer_bsn_writedata_export => reg_diag_data_buf_bsn_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diag_data_buffer_bsn_read_export => reg_diag_data_buf_bsn_copi.rd,
+ reg_diag_data_buffer_bsn_readdata_export => reg_diag_data_buf_bsn_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_histogram_clk_export => OPEN,
ram_st_histogram_reset_export => OPEN,
- ram_st_histogram_address_export => ram_st_histogram_mosi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
- ram_st_histogram_write_export => ram_st_histogram_mosi.wr,
- ram_st_histogram_writedata_export => ram_st_histogram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_histogram_read_export => ram_st_histogram_mosi.rd,
- ram_st_histogram_readdata_export => ram_st_histogram_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_address_export => ram_st_histogram_copi.address(c_sdp_ram_st_histogram_addr_w-1 DOWNTO 0),
+ ram_st_histogram_write_export => ram_st_histogram_copi.wr,
+ ram_st_histogram_writedata_export => ram_st_histogram_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_histogram_read_export => ram_st_histogram_copi.rd,
+ ram_st_histogram_readdata_export => ram_st_histogram_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_aduh_monitor_reset_export => OPEN,
reg_aduh_monitor_clk_export => OPEN,
- reg_aduh_monitor_address_export => reg_aduh_monitor_mosi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
- reg_aduh_monitor_write_export => reg_aduh_monitor_mosi.wr,
- reg_aduh_monitor_writedata_export => reg_aduh_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_aduh_monitor_read_export => reg_aduh_monitor_mosi.rd,
- reg_aduh_monitor_readdata_export => reg_aduh_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_aduh_monitor_address_export => reg_aduh_monitor_copi.address(c_sdp_reg_aduh_monitor_addr_w-1 DOWNTO 0),
+ reg_aduh_monitor_write_export => reg_aduh_monitor_copi.wr,
+ reg_aduh_monitor_writedata_export => reg_aduh_monitor_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_aduh_monitor_read_export => reg_aduh_monitor_copi.rd,
+ reg_aduh_monitor_readdata_export => reg_aduh_monitor_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_fil_coefs_clk_export => OPEN,
ram_fil_coefs_reset_export => OPEN,
- ram_fil_coefs_address_export => ram_fil_coefs_mosi.address(c_sdp_ram_fil_coefs_addr_w-1 DOWNTO 0),
- ram_fil_coefs_write_export => ram_fil_coefs_mosi.wr,
- ram_fil_coefs_writedata_export => ram_fil_coefs_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_fil_coefs_read_export => ram_fil_coefs_mosi.rd,
- ram_fil_coefs_readdata_export => ram_fil_coefs_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_fil_coefs_address_export => ram_fil_coefs_copi.address(c_sdp_ram_fil_coefs_addr_w-1 DOWNTO 0),
+ ram_fil_coefs_write_export => ram_fil_coefs_copi.wr,
+ ram_fil_coefs_writedata_export => ram_fil_coefs_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_fil_coefs_read_export => ram_fil_coefs_copi.rd,
+ ram_fil_coefs_readdata_export => ram_fil_coefs_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_sst_clk_export => OPEN,
ram_st_sst_reset_export => OPEN,
- ram_st_sst_address_export => ram_st_sst_mosi.address(c_sdp_ram_st_sst_addr_w-1 DOWNTO 0),
- ram_st_sst_write_export => ram_st_sst_mosi.wr,
- ram_st_sst_writedata_export => ram_st_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_sst_read_export => ram_st_sst_mosi.rd,
- ram_st_sst_readdata_export => ram_st_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_sst_address_export => ram_st_sst_copi.address(c_sdp_ram_st_sst_addr_w-1 DOWNTO 0),
+ ram_st_sst_write_export => ram_st_sst_copi.wr,
+ ram_st_sst_writedata_export => ram_st_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_sst_read_export => ram_st_sst_copi.rd,
+ ram_st_sst_readdata_export => ram_st_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_si_clk_export => OPEN,
reg_si_reset_export => OPEN,
- reg_si_address_export => reg_si_mosi.address(c_sdp_reg_si_addr_w-1 DOWNTO 0),
- reg_si_write_export => reg_si_mosi.wr,
- reg_si_writedata_export => reg_si_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_si_read_export => reg_si_mosi.rd,
- reg_si_readdata_export => reg_si_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_si_address_export => reg_si_copi.address(c_sdp_reg_si_addr_w-1 DOWNTO 0),
+ reg_si_write_export => reg_si_copi.wr,
+ reg_si_writedata_export => reg_si_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_si_read_export => reg_si_copi.rd,
+ reg_si_readdata_export => reg_si_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_equalizer_gains_clk_export => OPEN,
ram_equalizer_gains_reset_export => OPEN,
- ram_equalizer_gains_address_export => ram_equalizer_gains_mosi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
- ram_equalizer_gains_write_export => ram_equalizer_gains_mosi.wr,
- ram_equalizer_gains_writedata_export => ram_equalizer_gains_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_equalizer_gains_read_export => ram_equalizer_gains_mosi.rd,
- ram_equalizer_gains_readdata_export => ram_equalizer_gains_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_address_export => ram_equalizer_gains_copi.address(c_sdp_ram_equalizer_gains_addr_w-1 DOWNTO 0),
+ ram_equalizer_gains_write_export => ram_equalizer_gains_copi.wr,
+ ram_equalizer_gains_writedata_export => ram_equalizer_gains_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_equalizer_gains_read_export => ram_equalizer_gains_copi.rd,
+ ram_equalizer_gains_readdata_export => ram_equalizer_gains_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_selector_clk_export => OPEN,
reg_dp_selector_reset_export => OPEN,
- reg_dp_selector_address_export => reg_dp_selector_mosi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
- reg_dp_selector_write_export => reg_dp_selector_mosi.wr,
- reg_dp_selector_writedata_export => reg_dp_selector_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_selector_read_export => reg_dp_selector_mosi.rd,
- reg_dp_selector_readdata_export => reg_dp_selector_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_selector_address_export => reg_dp_selector_copi.address(c_sdp_reg_dp_selector_addr_w-1 DOWNTO 0),
+ reg_dp_selector_write_export => reg_dp_selector_copi.wr,
+ reg_dp_selector_writedata_export => reg_dp_selector_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_selector_read_export => reg_dp_selector_copi.rd,
+ reg_dp_selector_readdata_export => reg_dp_selector_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_sdp_info_clk_export => OPEN,
reg_sdp_info_reset_export => OPEN,
- reg_sdp_info_address_export => reg_sdp_info_mosi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
- reg_sdp_info_write_export => reg_sdp_info_mosi.wr,
- reg_sdp_info_writedata_export => reg_sdp_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_sdp_info_read_export => reg_sdp_info_mosi.rd,
- reg_sdp_info_readdata_export => reg_sdp_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_address_export => reg_sdp_info_copi.address(c_sdp_reg_sdp_info_addr_w-1 DOWNTO 0),
+ reg_sdp_info_write_export => reg_sdp_info_copi.wr,
+ reg_sdp_info_writedata_export => reg_sdp_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_sdp_info_read_export => reg_sdp_info_copi.rd,
+ reg_sdp_info_readdata_export => reg_sdp_info_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_ring_info_clk_export => OPEN,
reg_ring_info_reset_export => OPEN,
@@ -757,171 +831,219 @@ BEGIN
ram_ss_ss_wide_clk_export => OPEN,
ram_ss_ss_wide_reset_export => OPEN,
- ram_ss_ss_wide_address_export => ram_ss_ss_wide_mosi.address(c_sdp_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
- ram_ss_ss_wide_write_export => ram_ss_ss_wide_mosi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_ss_ss_wide_read_export => ram_ss_ss_wide_mosi.rd,
- ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_address_export => ram_ss_ss_wide_copi.address(c_sdp_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
+ ram_ss_ss_wide_write_export => ram_ss_ss_wide_copi.wr,
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_wide_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_ss_ss_wide_read_export => ram_ss_ss_wide_copi.rd,
+ ram_ss_ss_wide_readdata_export => ram_ss_ss_wide_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_bf_weights_clk_export => OPEN,
ram_bf_weights_reset_export => OPEN,
- ram_bf_weights_address_export => ram_bf_weights_mosi.address(c_sdp_ram_bf_weights_addr_w-1 DOWNTO 0),
- ram_bf_weights_write_export => ram_bf_weights_mosi.wr,
- ram_bf_weights_writedata_export => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_bf_weights_read_export => ram_bf_weights_mosi.rd,
- ram_bf_weights_readdata_export => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_bf_weights_address_export => ram_bf_weights_copi.address(c_sdp_ram_bf_weights_addr_w-1 DOWNTO 0),
+ ram_bf_weights_write_export => ram_bf_weights_copi.wr,
+ ram_bf_weights_writedata_export => ram_bf_weights_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_bf_weights_read_export => ram_bf_weights_copi.rd,
+ ram_bf_weights_readdata_export => ram_bf_weights_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bf_scale_clk_export => OPEN,
reg_bf_scale_reset_export => OPEN,
- reg_bf_scale_address_export => reg_bf_scale_mosi.address(c_sdp_reg_bf_scale_addr_w-1 DOWNTO 0),
- reg_bf_scale_write_export => reg_bf_scale_mosi.wr,
- reg_bf_scale_writedata_export => reg_bf_scale_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bf_scale_read_export => reg_bf_scale_mosi.rd,
- reg_bf_scale_readdata_export => reg_bf_scale_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bf_scale_address_export => reg_bf_scale_copi.address(c_sdp_reg_bf_scale_addr_w-1 DOWNTO 0),
+ reg_bf_scale_write_export => reg_bf_scale_copi.wr,
+ reg_bf_scale_writedata_export => reg_bf_scale_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bf_scale_read_export => reg_bf_scale_copi.rd,
+ reg_bf_scale_readdata_export => reg_bf_scale_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_hdr_dat_clk_export => OPEN,
reg_hdr_dat_reset_export => OPEN,
- reg_hdr_dat_address_export => reg_hdr_dat_mosi.address(c_sdp_reg_bf_hdr_dat_addr_w-1 DOWNTO 0),
- reg_hdr_dat_write_export => reg_hdr_dat_mosi.wr,
- reg_hdr_dat_writedata_export => reg_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_hdr_dat_read_export => reg_hdr_dat_mosi.rd,
- reg_hdr_dat_readdata_export => reg_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_address_export => reg_hdr_dat_copi.address(c_sdp_reg_bf_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_hdr_dat_write_export => reg_hdr_dat_copi.wr,
+ reg_hdr_dat_writedata_export => reg_hdr_dat_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_hdr_dat_read_export => reg_hdr_dat_copi.rd,
+ reg_hdr_dat_readdata_export => reg_hdr_dat_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_dp_xonoff_clk_export => OPEN,
reg_dp_xonoff_reset_export => OPEN,
- reg_dp_xonoff_address_export => reg_dp_xonoff_mosi.address(c_sdp_reg_dp_xonoff_addr_w-1 DOWNTO 0),
- reg_dp_xonoff_write_export => reg_dp_xonoff_mosi.wr,
- reg_dp_xonoff_writedata_export => reg_dp_xonoff_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_dp_xonoff_read_export => reg_dp_xonoff_mosi.rd,
- reg_dp_xonoff_readdata_export => reg_dp_xonoff_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_address_export => reg_dp_xonoff_copi.address(c_sdp_reg_dp_xonoff_addr_w-1 DOWNTO 0),
+ reg_dp_xonoff_write_export => reg_dp_xonoff_copi.wr,
+ reg_dp_xonoff_writedata_export => reg_dp_xonoff_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_xonoff_read_export => reg_dp_xonoff_copi.rd,
+ reg_dp_xonoff_readdata_export => reg_dp_xonoff_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_bst_clk_export => OPEN,
ram_st_bst_reset_export => OPEN,
- ram_st_bst_address_export => ram_st_bst_mosi.address(c_sdp_ram_st_bst_addr_w-1 DOWNTO 0),
- ram_st_bst_write_export => ram_st_bst_mosi.wr,
- ram_st_bst_writedata_export => ram_st_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_bst_read_export => ram_st_bst_mosi.rd,
- ram_st_bst_readdata_export => ram_st_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_bst_address_export => ram_st_bst_copi.address(c_sdp_ram_st_bst_addr_w-1 DOWNTO 0),
+ ram_st_bst_write_export => ram_st_bst_copi.wr,
+ ram_st_bst_writedata_export => ram_st_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_bst_read_export => ram_st_bst_copi.rd,
+ ram_st_bst_readdata_export => ram_st_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_sst_clk_export => OPEN,
reg_stat_enable_sst_reset_export => OPEN,
- reg_stat_enable_sst_address_export => reg_stat_enable_sst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_sst_write_export => reg_stat_enable_sst_mosi.wr,
- reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_sst_read_export => reg_stat_enable_sst_mosi.rd,
- reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_address_export => reg_stat_enable_sst_copi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_sst_write_export => reg_stat_enable_sst_copi.wr,
+ reg_stat_enable_sst_writedata_export => reg_stat_enable_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_sst_read_export => reg_stat_enable_sst_copi.rd,
+ reg_stat_enable_sst_readdata_export => reg_stat_enable_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_sst_clk_export => OPEN,
reg_stat_hdr_dat_sst_reset_export => OPEN,
- reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_mosi.wr,
- reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_mosi.rd,
- reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_address_export => reg_stat_hdr_dat_sst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_write_export => reg_stat_hdr_dat_sst_copi.wr,
+ reg_stat_hdr_dat_sst_writedata_export => reg_stat_hdr_dat_sst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_sst_read_export => reg_stat_hdr_dat_sst_copi.rd,
+ reg_stat_hdr_dat_sst_readdata_export => reg_stat_hdr_dat_sst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_xst_clk_export => OPEN,
reg_stat_enable_xst_reset_export => OPEN,
- reg_stat_enable_xst_address_export => reg_stat_enable_xst_mosi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
- reg_stat_enable_xst_write_export => reg_stat_enable_xst_mosi.wr,
- reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_xst_read_export => reg_stat_enable_xst_mosi.rd,
- reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_address_export => reg_stat_enable_xst_copi.address(c_sdp_reg_stat_enable_addr_w-1 DOWNTO 0),
+ reg_stat_enable_xst_write_export => reg_stat_enable_xst_copi.wr,
+ reg_stat_enable_xst_writedata_export => reg_stat_enable_xst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_xst_read_export => reg_stat_enable_xst_copi.rd,
+ reg_stat_enable_xst_readdata_export => reg_stat_enable_xst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_xst_clk_export => OPEN,
reg_stat_hdr_dat_xst_reset_export => OPEN,
- reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_mosi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_mosi.wr,
- reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_mosi.rd,
- reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_address_export => reg_stat_hdr_dat_xst_copi.address(c_sdp_reg_stat_hdr_dat_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_write_export => reg_stat_hdr_dat_xst_copi.wr,
+ reg_stat_hdr_dat_xst_writedata_export => reg_stat_hdr_dat_xst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_xst_read_export => reg_stat_hdr_dat_xst_copi.rd,
+ reg_stat_hdr_dat_xst_readdata_export => reg_stat_hdr_dat_xst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_enable_bst_clk_export => OPEN,
reg_stat_enable_bst_reset_export => OPEN,
- reg_stat_enable_bst_address_export => reg_stat_enable_bst_mosi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
- reg_stat_enable_bst_write_export => reg_stat_enable_bst_mosi.wr,
- reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_enable_bst_read_export => reg_stat_enable_bst_mosi.rd,
- reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_address_export => reg_stat_enable_bst_copi.address(c_sdp_reg_stat_enable_bst_addr_w-1 DOWNTO 0),
+ reg_stat_enable_bst_write_export => reg_stat_enable_bst_copi.wr,
+ reg_stat_enable_bst_writedata_export => reg_stat_enable_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_enable_bst_read_export => reg_stat_enable_bst_copi.rd,
+ reg_stat_enable_bst_readdata_export => reg_stat_enable_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_stat_hdr_dat_bst_clk_export => OPEN,
reg_stat_hdr_dat_bst_reset_export => OPEN,
- reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_mosi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_mosi.wr,
- reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
- reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_address_export => reg_stat_hdr_dat_bst_copi.address(c_sdp_reg_stat_hdr_dat_bst_addr_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_write_export => reg_stat_hdr_dat_bst_copi.wr,
+ reg_stat_hdr_dat_bst_writedata_export => reg_stat_hdr_dat_bst_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_copi.rd,
+ reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_crosslets_info_clk_export => OPEN,
reg_crosslets_info_reset_export => OPEN,
- reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
- reg_crosslets_info_write_export => reg_crosslets_info_mosi.wr,
- reg_crosslets_info_writedata_export => reg_crosslets_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
- reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_address_export => reg_crosslets_info_copi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
+ reg_crosslets_info_write_export => reg_crosslets_info_copi.wr,
+ reg_crosslets_info_writedata_export => reg_crosslets_info_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_crosslets_info_read_export => reg_crosslets_info_copi.rd,
+ reg_crosslets_info_readdata_export => reg_crosslets_info_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nof_crosslets_clk_export => OPEN,
reg_nof_crosslets_reset_export => OPEN,
- reg_nof_crosslets_address_export => reg_nof_crosslets_mosi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
- reg_nof_crosslets_write_export => reg_nof_crosslets_mosi.wr,
- reg_nof_crosslets_writedata_export => reg_nof_crosslets_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nof_crosslets_read_export => reg_nof_crosslets_mosi.rd,
- reg_nof_crosslets_readdata_export => reg_nof_crosslets_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_address_export => reg_nof_crosslets_copi.address(c_sdp_reg_nof_crosslets_addr_w-1 DOWNTO 0),
+ reg_nof_crosslets_write_export => reg_nof_crosslets_copi.wr,
+ reg_nof_crosslets_writedata_export => reg_nof_crosslets_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nof_crosslets_read_export => reg_nof_crosslets_copi.rd,
+ reg_nof_crosslets_readdata_export => reg_nof_crosslets_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
- reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
- reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_mosi.wr,
- reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_mosi.rd,
- reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_copi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_copi.wr,
+ reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_copi.rd,
+ reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
ram_st_xsq_clk_export => OPEN,
ram_st_xsq_reset_export => OPEN,
- ram_st_xsq_address_export => ram_st_xsq_mosi.address(c_sdp_ram_st_xsq_arr_addr_w-1 DOWNTO 0),
- ram_st_xsq_write_export => ram_st_xsq_mosi.wr,
- ram_st_xsq_writedata_export => ram_st_xsq_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_st_xsq_read_export => ram_st_xsq_mosi.rd,
- ram_st_xsq_readdata_export => ram_st_xsq_miso.rddata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_address_export => ram_st_xsq_copi.address(c_sdp_ram_st_xsq_arr_addr_w-1 DOWNTO 0),
+ ram_st_xsq_write_export => ram_st_xsq_copi.wr,
+ ram_st_xsq_writedata_export => ram_st_xsq_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_st_xsq_read_export => ram_st_xsq_copi.rd,
+ ram_st_xsq_readdata_export => ram_st_xsq_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_mac_clk_export => OPEN,
reg_nw_10GbE_mac_reset_export => OPEN,
- reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_mosi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
- reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_mosi.wr,
- reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_mosi.rd,
- reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_address_export => reg_nw_10GbE_mac_copi.address(c_sdp_reg_nw_10GbE_mac_addr_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_write_export => reg_nw_10GbE_mac_copi.wr,
+ reg_nw_10GbE_mac_writedata_export => reg_nw_10GbE_mac_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_mac_read_export => reg_nw_10GbE_mac_copi.rd,
+ reg_nw_10GbE_mac_readdata_export => reg_nw_10GbE_mac_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_nw_10GbE_eth10g_clk_export => OPEN,
reg_nw_10GbE_eth10g_reset_export => OPEN,
- reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_mosi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w-1 DOWNTO 0),
- reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_mosi.wr,
- reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_mosi.rd,
- reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_miso.rddata(c_word_w-1 DOWNTO 0),
-
- reg_bsn_align_v2_clk_export => OPEN,
- reg_bsn_align_v2_reset_export => OPEN,
- reg_bsn_align_v2_address_export => reg_bsn_align_v2_copi.address(c_sdp_reg_bsn_align_v2_addr_w-1 DOWNTO 0),
- reg_bsn_align_v2_write_export => reg_bsn_align_v2_copi.wr,
- reg_bsn_align_v2_writedata_export => reg_bsn_align_v2_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_align_v2_read_export => reg_bsn_align_v2_copi.rd,
- reg_bsn_align_v2_readdata_export => reg_bsn_align_v2_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_bsn_monitor_v2_bsn_align_v2_input_clk_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_input_reset_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_input_address_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_input_write_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wr,
- reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_input_read_export => reg_bsn_monitor_v2_bsn_align_v2_input_copi.rd,
- reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_input_cipo.rddata(c_word_w-1 DOWNTO 0),
-
- reg_bsn_monitor_v2_bsn_align_v2_output_clk_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_output_reset_export => OPEN,
- reg_bsn_monitor_v2_bsn_align_v2_output_address_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.address(c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_output_write_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.wr,
- reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export=> reg_bsn_monitor_v2_bsn_align_v2_output_copi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_monitor_v2_bsn_align_v2_output_read_export => reg_bsn_monitor_v2_bsn_align_v2_output_copi.rd,
- reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export => reg_bsn_monitor_v2_bsn_align_v2_output_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_address_export => reg_nw_10GbE_eth10g_copi.address(c_sdp_reg_nw_10GbE_eth10g_addr_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_write_export => reg_nw_10GbE_eth10g_copi.wr,
+ reg_nw_10GbE_eth10g_writedata_export => reg_nw_10GbE_eth10g_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_nw_10GbE_eth10g_read_export => reg_nw_10GbE_eth10g_copi.rd,
+ reg_nw_10GbE_eth10g_readdata_export => reg_nw_10GbE_eth10g_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_align_v2_bf_clk_export => OPEN,
+ reg_bsn_align_v2_bf_reset_export => OPEN,
+ reg_bsn_align_v2_bf_address_export => reg_bsn_align_v2_bf_copi.address(c_sdp_reg_bsn_align_v2_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_align_v2_bf_write_export => reg_bsn_align_v2_bf_copi.wr,
+ reg_bsn_align_v2_bf_writedata_export => reg_bsn_align_v2_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_align_v2_bf_read_export => reg_bsn_align_v2_bf_copi.rd,
+ reg_bsn_align_v2_bf_readdata_export => reg_bsn_align_v2_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_align_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_bf_address_export => reg_bsn_monitor_v2_rx_align_bf_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_bf_write_export => reg_bsn_monitor_v2_rx_align_bf_copi.wr,
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export => reg_bsn_monitor_v2_rx_align_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_bf_read_export => reg_bsn_monitor_v2_rx_align_bf_copi.rd,
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export => reg_bsn_monitor_v2_rx_align_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_aligned_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_bf_address_export => reg_bsn_monitor_v2_aligned_bf_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_bf_write_export => reg_bsn_monitor_v2_aligned_bf_copi.wr,
+ reg_bsn_monitor_v2_aligned_bf_writedata_export => reg_bsn_monitor_v2_aligned_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_bf_read_export => reg_bsn_monitor_v2_aligned_bf_copi.rd,
+ reg_bsn_monitor_v2_aligned_bf_readdata_export => reg_bsn_monitor_v2_aligned_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_align_v2_xsub_clk_export => OPEN,
+ reg_bsn_align_v2_xsub_reset_export => OPEN,
+ reg_bsn_align_v2_xsub_address_export => reg_bsn_align_v2_xsub_copi.address(c_sdp_reg_bsn_align_v2_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_align_v2_xsub_write_export => reg_bsn_align_v2_xsub_copi.wr,
+ reg_bsn_align_v2_xsub_writedata_export => reg_bsn_align_v2_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_align_v2_xsub_read_export => reg_bsn_align_v2_xsub_copi.rd,
+ reg_bsn_align_v2_xsub_readdata_export => reg_bsn_align_v2_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_rx_align_xsub_address_export => reg_bsn_monitor_v2_rx_align_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_xsub_write_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wr,
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export => reg_bsn_monitor_v2_rx_align_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_rx_align_xsub_read_export => reg_bsn_monitor_v2_rx_align_xsub_copi.rd,
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export => reg_bsn_monitor_v2_rx_align_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_aligned_xsub_clk_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_reset_export => OPEN,
+ reg_bsn_monitor_v2_aligned_xsub_address_export => reg_bsn_monitor_v2_aligned_xsub_copi.address(c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_xsub_write_export => reg_bsn_monitor_v2_aligned_xsub_copi.wr,
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export => reg_bsn_monitor_v2_aligned_xsub_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_aligned_xsub_read_export => reg_bsn_monitor_v2_aligned_xsub_copi.rd,
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export => reg_bsn_monitor_v2_aligned_xsub_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_sst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_sst_offload_address_export => reg_bsn_monitor_v2_sst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_write_export => reg_bsn_monitor_v2_sst_offload_copi.wr,
+ reg_bsn_monitor_v2_sst_offload_writedata_export => reg_bsn_monitor_v2_sst_offload_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_sst_offload_read_export => reg_bsn_monitor_v2_sst_offload_copi.rd,
+ reg_bsn_monitor_v2_sst_offload_readdata_export => reg_bsn_monitor_v2_sst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_bst_offload_clk_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_reset_export => OPEN,
+ reg_bsn_monitor_v2_bst_offload_address_export => reg_bsn_monitor_v2_bst_offload_copi.address(c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_bst_offload_write_export => reg_bsn_monitor_v2_bst_offload_copi.wr,
+ reg_bsn_monitor_v2_bst_offload_writedata_export => reg_bsn_monitor_v2_bst_offload_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_bst_offload_read_export => reg_bsn_monitor_v2_bst_offload_copi.rd,
+ reg_bsn_monitor_v2_bst_offload_readdata_export => reg_bsn_monitor_v2_bst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_beamlet_output_clk_export => OPEN,
+ reg_bsn_monitor_v2_beamlet_output_reset_export => OPEN,
+ reg_bsn_monitor_v2_beamlet_output_address_export => reg_bsn_monitor_v2_beamlet_output_copi.address(c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_beamlet_output_write_export => reg_bsn_monitor_v2_beamlet_output_copi.wr,
+ reg_bsn_monitor_v2_beamlet_output_writedata_export => reg_bsn_monitor_v2_beamlet_output_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_beamlet_output_read_export => reg_bsn_monitor_v2_beamlet_output_copi.rd,
+ reg_bsn_monitor_v2_beamlet_output_readdata_export => reg_bsn_monitor_v2_beamlet_output_cipo.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_monitor_v2_xst_offload_clk_export => OPEN,
reg_bsn_monitor_v2_xst_offload_reset_export => OPEN,
@@ -931,6 +1053,46 @@ BEGIN
reg_bsn_monitor_v2_xst_offload_read_export => reg_bsn_monitor_v2_xst_offload_copi.rd,
reg_bsn_monitor_v2_xst_offload_readdata_export => reg_bsn_monitor_v2_xst_offload_cipo.rddata(c_word_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_clk_export => OPEN,
+ reg_ring_lane_info_bf_reset_export => OPEN,
+ reg_ring_lane_info_bf_address_export => reg_ring_lane_info_bf_copi.address(c_sdp_reg_ring_lane_info_bf_addr_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_write_export => reg_ring_lane_info_bf_copi.wr,
+ reg_ring_lane_info_bf_writedata_export => reg_ring_lane_info_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_ring_lane_info_bf_read_export => reg_ring_lane_info_bf_copi.rd,
+ reg_ring_lane_info_bf_readdata_export => reg_ring_lane_info_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_rx_bf_address_export => reg_bsn_monitor_v2_ring_rx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_rx_bf_write_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export => reg_bsn_monitor_v2_ring_rx_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_rx_bf_read_export => reg_bsn_monitor_v2_ring_rx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export => reg_bsn_monitor_v2_ring_rx_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export => OPEN,
+ reg_bsn_monitor_v2_ring_tx_bf_address_export => reg_bsn_monitor_v2_ring_tx_bf_copi.address(c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_tx_bf_write_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wr,
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export => reg_bsn_monitor_v2_ring_tx_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_monitor_v2_ring_tx_bf_read_export => reg_bsn_monitor_v2_ring_tx_bf_copi.rd,
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export => reg_bsn_monitor_v2_ring_tx_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_block_validate_err_bf_clk_export => OPEN,
+ reg_dp_block_validate_err_bf_reset_export => OPEN,
+ reg_dp_block_validate_err_bf_address_export => reg_dp_block_validate_err_bf_copi.address(c_sdp_reg_dp_block_validate_err_bf_addr_w-1 DOWNTO 0),
+ reg_dp_block_validate_err_bf_write_export => reg_dp_block_validate_err_bf_copi.wr,
+ reg_dp_block_validate_err_bf_writedata_export => reg_dp_block_validate_err_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_block_validate_err_bf_read_export => reg_dp_block_validate_err_bf_copi.rd,
+ reg_dp_block_validate_err_bf_readdata_export => reg_dp_block_validate_err_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export => OPEN,
+ reg_dp_block_validate_bsn_at_sync_bf_address_export => reg_dp_block_validate_bsn_at_sync_bf_copi.address(c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w-1 DOWNTO 0),
+ reg_dp_block_validate_bsn_at_sync_bf_write_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wr,
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export => reg_dp_block_validate_bsn_at_sync_bf_copi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_block_validate_bsn_at_sync_bf_read_export => reg_dp_block_validate_bsn_at_sync_bf_copi.rd,
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export => reg_dp_block_validate_bsn_at_sync_bf_cipo.rddata(c_word_w-1 DOWNTO 0),
+
reg_ring_lane_info_xst_clk_export => OPEN,
reg_ring_lane_info_xst_reset_export => OPEN,
reg_ring_lane_info_xst_address_export => reg_ring_lane_info_xst_copi.address(c_sdp_reg_ring_lane_info_xst_addr_w-1 DOWNTO 0),
@@ -989,11 +1151,11 @@ BEGIN
ram_scrap_clk_export => OPEN,
ram_scrap_reset_export => OPEN,
- ram_scrap_address_export => ram_scrap_mosi.address(9-1 DOWNTO 0),
- ram_scrap_write_export => ram_scrap_mosi.wr,
- ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
- ram_scrap_read_export => ram_scrap_mosi.rd,
- ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0)
+ ram_scrap_address_export => ram_scrap_copi.address(9-1 DOWNTO 0),
+ ram_scrap_write_export => ram_scrap_copi.wr,
+ ram_scrap_writedata_export => ram_scrap_copi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_scrap_read_export => ram_scrap_copi.rd,
+ ram_scrap_readdata_export => ram_scrap_cipo.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index ccfb20e569aaf3f3afad4aa9d7060c376dbcc847..b702216d0617f1ba897f4c9165cee418ce2afcc3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -28,455 +28,532 @@ PACKAGE qsys_lofar2_unb2c_sdp_station_pkg IS
-----------------------------------------------------------------------------
component qsys_lofar2_unb2c_sdp_station is
port (
- avs_eth_0_clk_export : out std_logic; -- export
- avs_eth_0_irq_export : in std_logic := 'X'; -- export
- avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_ram_read_export : out std_logic; -- export
- avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_ram_write_export : out std_logic; -- export
- avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
- avs_eth_0_reg_read_export : out std_logic; -- export
- avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_reg_write_export : out std_logic; -- export
- avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- avs_eth_0_reset_export : out std_logic; -- export
- avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
- avs_eth_0_tse_read_export : out std_logic; -- export
- avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
- avs_eth_0_tse_write_export : out std_logic; -- export
- avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
- clk_clk : in std_logic := 'X'; -- clk
- reset_reset_n : in std_logic := 'X'; -- reset_n
- jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
- jesd204b_clk_export : out std_logic; -- export
- jesd204b_read_export : out std_logic; -- export
- jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204b_reset_export : out std_logic; -- export
- jesd204b_write_export : out std_logic; -- export
- jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- pio_jesd_ctrl_clk_export : out std_logic; -- export
- pio_jesd_ctrl_read_export : out std_logic; -- export
- pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_jesd_ctrl_reset_export : out std_logic; -- export
- pio_jesd_ctrl_write_export : out std_logic; -- export
- pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
- pio_pps_clk_export : out std_logic; -- export
- pio_pps_read_export : out std_logic; -- export
- pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_pps_reset_export : out std_logic; -- export
- pio_pps_write_export : out std_logic; -- export
- pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
- pio_system_info_clk_export : out std_logic; -- export
- pio_system_info_read_export : out std_logic; -- export
- pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- pio_system_info_reset_export : out std_logic; -- export
- pio_system_info_write_export : out std_logic; -- export
- pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- pio_wdi_external_connection_export : out std_logic; -- export
- ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
- ram_bf_weights_clk_export : out std_logic; -- export
- ram_bf_weights_read_export : out std_logic; -- export
- ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_bf_weights_reset_export : out std_logic; -- export
- ram_bf_weights_write_export : out std_logic; -- export
- ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
- ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
- ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
- ram_equalizer_gains_clk_export : out std_logic; -- export
- ram_equalizer_gains_read_export : out std_logic; -- export
- ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_equalizer_gains_reset_export : out std_logic; -- export
- ram_equalizer_gains_write_export : out std_logic; -- export
- ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
- ram_fil_coefs_clk_export : out std_logic; -- export
- ram_fil_coefs_read_export : out std_logic; -- export
- ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_fil_coefs_reset_export : out std_logic; -- export
- ram_fil_coefs_write_export : out std_logic; -- export
- ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
- ram_scrap_clk_export : out std_logic; -- export
- ram_scrap_read_export : out std_logic; -- export
- ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_scrap_reset_export : out std_logic; -- export
- ram_scrap_write_export : out std_logic; -- export
- ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
- ram_ss_ss_wide_clk_export : out std_logic; -- export
- ram_ss_ss_wide_read_export : out std_logic; -- export
- ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_ss_ss_wide_reset_export : out std_logic; -- export
- ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
- ram_st_bst_clk_export : out std_logic; -- export
- ram_st_bst_read_export : out std_logic; -- export
- ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_bst_reset_export : out std_logic; -- export
- ram_st_bst_write_export : out std_logic; -- export
- ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_reset_export : out std_logic; -- export
- ram_st_histogram_clk_export : out std_logic; -- export
- ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
- ram_st_histogram_write_export : out std_logic; -- export
- ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_histogram_read_export : out std_logic; -- export
- ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
- ram_st_sst_clk_export : out std_logic; -- export
- ram_st_sst_read_export : out std_logic; -- export
- ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_sst_reset_export : out std_logic; -- export
- ram_st_sst_write_export : out std_logic; -- export
- ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
- ram_st_xsq_clk_export : out std_logic; -- export
- ram_st_xsq_read_export : out std_logic; -- export
- ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_st_xsq_reset_export : out std_logic; -- export
- ram_st_xsq_write_export : out std_logic; -- export
- ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
- ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
- ram_wg_clk_export : out std_logic; -- export
- ram_wg_read_export : out std_logic; -- export
- ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- ram_wg_reset_export : out std_logic; -- export
- ram_wg_write_export : out std_logic; -- export
- ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
- reg_aduh_monitor_clk_export : out std_logic; -- export
- reg_aduh_monitor_read_export : out std_logic; -- export
- reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_aduh_monitor_reset_export : out std_logic; -- export
- reg_aduh_monitor_write_export : out std_logic; -- export
- reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
- reg_bf_scale_clk_export : out std_logic; -- export
- reg_bf_scale_read_export : out std_logic; -- export
- reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bf_scale_reset_export : out std_logic; -- export
- reg_bf_scale_write_export : out std_logic; -- export
- reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_reset_export : out std_logic; -- export
- reg_bsn_align_v2_clk_export : out std_logic; -- export
- reg_bsn_align_v2_address_export : out std_logic_vector(4 downto 0); -- export
- reg_bsn_align_v2_write_export : out std_logic; -- export
- reg_bsn_align_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_align_v2_read_export : out std_logic; -- export
- reg_bsn_align_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
- reg_bsn_monitor_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_input_read_export : out std_logic; -- export
- reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_input_write_export : out std_logic; -- export
- reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_bsn_align_v2_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
- reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
- reg_bsn_scheduler_clk_export : out std_logic; -- export
- reg_bsn_scheduler_read_export : out std_logic; -- export
- reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_scheduler_reset_export : out std_logic; -- export
- reg_bsn_scheduler_write_export : out std_logic; -- export
- reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_v2_clk_export : out std_logic; -- export
- reg_bsn_source_v2_read_export : out std_logic; -- export
- reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_v2_reset_export : out std_logic; -- export
- reg_bsn_source_v2_write_export : out std_logic; -- export
- reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
- reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_crosslets_info_clk_export : out std_logic; -- export
- reg_crosslets_info_read_export : out std_logic; -- export
- reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_crosslets_info_reset_export : out std_logic; -- export
- reg_crosslets_info_write_export : out std_logic; -- export
- reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
- reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
- reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
- reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
- reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dp_selector_clk_export : out std_logic; -- export
- reg_dp_selector_read_export : out std_logic; -- export
- reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_selector_reset_export : out std_logic; -- export
- reg_dp_selector_write_export : out std_logic; -- export
- reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
- reg_dp_shiftram_clk_export : out std_logic; -- export
- reg_dp_shiftram_read_export : out std_logic; -- export
- reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_shiftram_reset_export : out std_logic; -- export
- reg_dp_shiftram_write_export : out std_logic; -- export
- reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
- reg_dp_xonoff_clk_export : out std_logic; -- export
- reg_dp_xonoff_read_export : out std_logic; -- export
- reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dp_xonoff_reset_export : out std_logic; -- export
- reg_dp_xonoff_write_export : out std_logic; -- export
- reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_ctrl_clk_export : out std_logic; -- export
- reg_dpmm_ctrl_read_export : out std_logic; -- export
- reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_ctrl_reset_export : out std_logic; -- export
- reg_dpmm_ctrl_write_export : out std_logic; -- export
- reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_dpmm_data_clk_export : out std_logic; -- export
- reg_dpmm_data_read_export : out std_logic; -- export
- reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_dpmm_data_reset_export : out std_logic; -- export
- reg_dpmm_data_write_export : out std_logic; -- export
- reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
- reg_epcs_clk_export : out std_logic; -- export
- reg_epcs_read_export : out std_logic; -- export
- reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_epcs_reset_export : out std_logic; -- export
- reg_epcs_write_export : out std_logic; -- export
- reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
- reg_fpga_temp_sens_clk_export : out std_logic; -- export
- reg_fpga_temp_sens_read_export : out std_logic; -- export
- reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_temp_sens_reset_export : out std_logic; -- export
- reg_fpga_temp_sens_write_export : out std_logic; -- export
- reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
- reg_fpga_voltage_sens_clk_export : out std_logic; -- export
- reg_fpga_voltage_sens_read_export : out std_logic; -- export
- reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_fpga_voltage_sens_reset_export : out std_logic; -- export
- reg_fpga_voltage_sens_write_export : out std_logic; -- export
- reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
- reg_hdr_dat_clk_export : out std_logic; -- export
- reg_hdr_dat_read_export : out std_logic; -- export
- reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_hdr_dat_reset_export : out std_logic; -- export
- reg_hdr_dat_write_export : out std_logic; -- export
- reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_ctrl_clk_export : out std_logic; -- export
- reg_mmdp_ctrl_read_export : out std_logic; -- export
- reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_ctrl_reset_export : out std_logic; -- export
- reg_mmdp_ctrl_write_export : out std_logic; -- export
- reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
- reg_mmdp_data_clk_export : out std_logic; -- export
- reg_mmdp_data_read_export : out std_logic; -- export
- reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_mmdp_data_reset_export : out std_logic; -- export
- reg_mmdp_data_write_export : out std_logic; -- export
- reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_reset_export : out std_logic; -- export
- reg_nof_crosslets_clk_export : out std_logic; -- export
- reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nof_crosslets_write_export : out std_logic; -- export
- reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nof_crosslets_read_export : out std_logic; -- export
- reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
- reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
- reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
- reg_nw_10gbe_mac_clk_export : out std_logic; -- export
- reg_nw_10gbe_mac_read_export : out std_logic; -- export
- reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_nw_10gbe_mac_reset_export : out std_logic; -- export
- reg_nw_10gbe_mac_write_export : out std_logic; -- export
- reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
- reg_remu_clk_export : out std_logic; -- export
- reg_remu_read_export : out std_logic; -- export
- reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_remu_reset_export : out std_logic; -- export
- reg_remu_write_export : out std_logic; -- export
- reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_reset_export : out std_logic; -- export
- reg_ring_info_clk_export : out std_logic; -- export
- reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
- reg_ring_info_write_export : out std_logic; -- export
- reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_info_read_export : out std_logic; -- export
- reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_ring_lane_info_xst_reset_export : out std_logic; -- export
- reg_ring_lane_info_xst_clk_export : out std_logic; -- export
- reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_ring_lane_info_xst_write_export : out std_logic; -- export
- reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_ring_lane_info_xst_read_export : out std_logic; -- export
- reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
- reg_sdp_info_clk_export : out std_logic; -- export
- reg_sdp_info_read_export : out std_logic; -- export
- reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_sdp_info_reset_export : out std_logic; -- export
- reg_sdp_info_write_export : out std_logic; -- export
- reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_si_address_export : out std_logic_vector(0 downto 0); -- export
- reg_si_clk_export : out std_logic; -- export
- reg_si_read_export : out std_logic; -- export
- reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_si_reset_export : out std_logic; -- export
- reg_si_write_export : out std_logic; -- export
- reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
- reg_stat_enable_bst_clk_export : out std_logic; -- export
- reg_stat_enable_bst_read_export : out std_logic; -- export
- reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_bst_reset_export : out std_logic; -- export
- reg_stat_enable_bst_write_export : out std_logic; -- export
- reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_sst_clk_export : out std_logic; -- export
- reg_stat_enable_sst_read_export : out std_logic; -- export
- reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_sst_reset_export : out std_logic; -- export
- reg_stat_enable_sst_write_export : out std_logic; -- export
- reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
- reg_stat_enable_xst_clk_export : out std_logic; -- export
- reg_stat_enable_xst_read_export : out std_logic; -- export
- reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_enable_xst_reset_export : out std_logic; -- export
- reg_stat_enable_xst_write_export : out std_logic; -- export
- reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
- reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
- reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
- reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
- reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
- reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_tr_10gbe_mac_reset_export : out std_logic; -- export
- reg_tr_10gbe_mac_clk_export : out std_logic; -- export
- reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
- reg_tr_10gbe_mac_write_export : out std_logic; -- export
- reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_tr_10gbe_mac_read_export : out std_logic; -- export
- reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
- reg_wdi_clk_export : out std_logic; -- export
- reg_wdi_read_export : out std_logic; -- export
- reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wdi_reset_export : out std_logic; -- export
- reg_wdi_write_export : out std_logic; -- export
- reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
- reg_wg_clk_export : out std_logic; -- export
- reg_wg_read_export : out std_logic; -- export
- reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_wg_reset_export : out std_logic; -- export
- reg_wg_write_export : out std_logic; -- export
- reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
- rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
- rom_system_info_clk_export : out std_logic; -- export
- rom_system_info_read_export : out std_logic; -- export
- rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- rom_system_info_reset_export : out std_logic; -- export
- rom_system_info_write_export : out std_logic; -- export
- rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
+ avs_eth_0_clk_export : out std_logic; -- export
+ avs_eth_0_irq_export : in std_logic := 'X'; -- export
+ avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_ram_read_export : out std_logic; -- export
+ avs_eth_0_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_ram_write_export : out std_logic; -- export
+ avs_eth_0_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ avs_eth_0_reg_read_export : out std_logic; -- export
+ avs_eth_0_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_reg_write_export : out std_logic; -- export
+ avs_eth_0_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ avs_eth_0_reset_export : out std_logic; -- export
+ avs_eth_0_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ avs_eth_0_tse_read_export : out std_logic; -- export
+ avs_eth_0_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ avs_eth_0_tse_waitrequest_export : in std_logic := 'X'; -- export
+ avs_eth_0_tse_write_export : out std_logic; -- export
+ avs_eth_0_tse_writedata_export : out std_logic_vector(31 downto 0); -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ jesd204b_address_export : out std_logic_vector(11 downto 0); -- export
+ jesd204b_clk_export : out std_logic; -- export
+ jesd204b_read_export : out std_logic; -- export
+ jesd204b_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204b_reset_export : out std_logic; -- export
+ jesd204b_write_export : out std_logic; -- export
+ jesd204b_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_jesd_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ pio_jesd_ctrl_clk_export : out std_logic; -- export
+ pio_jesd_ctrl_read_export : out std_logic; -- export
+ pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_jesd_ctrl_reset_export : out std_logic; -- export
+ pio_jesd_ctrl_write_export : out std_logic; -- export
+ pio_jesd_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_pps_address_export : out std_logic_vector(1 downto 0); -- export
+ pio_pps_clk_export : out std_logic; -- export
+ pio_pps_read_export : out std_logic; -- export
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_pps_reset_export : out std_logic; -- export
+ pio_pps_write_export : out std_logic; -- export
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_system_info_address_export : out std_logic_vector(4 downto 0); -- export
+ pio_system_info_clk_export : out std_logic; -- export
+ pio_system_info_read_export : out std_logic; -- export
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ pio_system_info_reset_export : out std_logic; -- export
+ pio_system_info_write_export : out std_logic; -- export
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ pio_wdi_external_connection_export : out std_logic; -- export
+ ram_bf_weights_address_export : out std_logic_vector(14 downto 0); -- export
+ ram_bf_weights_clk_export : out std_logic; -- export
+ ram_bf_weights_read_export : out std_logic; -- export
+ ram_bf_weights_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_bf_weights_reset_export : out std_logic; -- export
+ ram_bf_weights_write_export : out std_logic; -- export
+ ram_bf_weights_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_diag_data_buffer_bsn_address_export : out std_logic_vector(20 downto 0); -- export
+ ram_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ ram_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_equalizer_gains_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_equalizer_gains_clk_export : out std_logic; -- export
+ ram_equalizer_gains_read_export : out std_logic; -- export
+ ram_equalizer_gains_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_equalizer_gains_reset_export : out std_logic; -- export
+ ram_equalizer_gains_write_export : out std_logic; -- export
+ ram_equalizer_gains_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_fil_coefs_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_fil_coefs_clk_export : out std_logic; -- export
+ ram_fil_coefs_read_export : out std_logic; -- export
+ ram_fil_coefs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_fil_coefs_reset_export : out std_logic; -- export
+ ram_fil_coefs_write_export : out std_logic; -- export
+ ram_fil_coefs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_ss_ss_wide_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_ss_ss_wide_clk_export : out std_logic; -- export
+ ram_ss_ss_wide_read_export : out std_logic; -- export
+ ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_ss_ss_wide_reset_export : out std_logic; -- export
+ ram_ss_ss_wide_write_export : out std_logic; -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_bst_address_export : out std_logic_vector(11 downto 0); -- export
+ ram_st_bst_clk_export : out std_logic; -- export
+ ram_st_bst_read_export : out std_logic; -- export
+ ram_st_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_bst_reset_export : out std_logic; -- export
+ ram_st_bst_write_export : out std_logic; -- export
+ ram_st_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_reset_export : out std_logic; -- export
+ ram_st_histogram_clk_export : out std_logic; -- export
+ ram_st_histogram_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_st_histogram_write_export : out std_logic; -- export
+ ram_st_histogram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_histogram_read_export : out std_logic; -- export
+ ram_st_histogram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_st_sst_clk_export : out std_logic; -- export
+ ram_st_sst_read_export : out std_logic; -- export
+ ram_st_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_sst_reset_export : out std_logic; -- export
+ ram_st_sst_write_export : out std_logic; -- export
+ ram_st_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_st_xsq_address_export : out std_logic_vector(15 downto 0); -- export
+ ram_st_xsq_clk_export : out std_logic; -- export
+ ram_st_xsq_read_export : out std_logic; -- export
+ ram_st_xsq_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_st_xsq_reset_export : out std_logic; -- export
+ ram_st_xsq_write_export : out std_logic; -- export
+ ram_st_xsq_writedata_export : out std_logic_vector(31 downto 0); -- export
+ ram_wg_address_export : out std_logic_vector(13 downto 0); -- export
+ ram_wg_clk_export : out std_logic; -- export
+ ram_wg_read_export : out std_logic; -- export
+ ram_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_wg_reset_export : out std_logic; -- export
+ ram_wg_write_export : out std_logic; -- export
+ ram_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_aduh_monitor_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_aduh_monitor_clk_export : out std_logic; -- export
+ reg_aduh_monitor_read_export : out std_logic; -- export
+ reg_aduh_monitor_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_aduh_monitor_reset_export : out std_logic; -- export
+ reg_aduh_monitor_write_export : out std_logic; -- export
+ reg_aduh_monitor_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bf_scale_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_bf_scale_clk_export : out std_logic; -- export
+ reg_bf_scale_read_export : out std_logic; -- export
+ reg_bf_scale_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bf_scale_reset_export : out std_logic; -- export
+ reg_bf_scale_write_export : out std_logic; -- export
+ reg_bf_scale_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_align_v2_bf_write_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_bf_read_export : out std_logic; -- export
+ reg_bsn_align_v2_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_align_v2_xsub_reset_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_clk_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_align_v2_xsub_write_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_align_v2_xsub_read_export : out std_logic; -- export
+ reg_bsn_align_v2_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_input_clk_export : out std_logic; -- export
+ reg_bsn_monitor_input_read_export : out std_logic; -- export
+ reg_bsn_monitor_input_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_input_reset_export : out std_logic; -- export
+ reg_bsn_monitor_input_write_export : out std_logic; -- export
+ reg_bsn_monitor_input_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_aligned_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_aligned_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_aligned_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_beamlet_output_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_beamlet_output_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_beamlet_output_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_bst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_bst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_bst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_rx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_rx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_ring_tx_xst_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_ring_tx_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_bf_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_bf_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_rx_align_xsub_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_rx_align_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_sst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_sst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_sst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_monitor_v2_xst_offload_reset_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_clk_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_write_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_monitor_v2_xst_offload_read_export : out std_logic; -- export
+ reg_bsn_monitor_v2_xst_offload_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_bsn_scheduler_clk_export : out std_logic; -- export
+ reg_bsn_scheduler_read_export : out std_logic; -- export
+ reg_bsn_scheduler_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_scheduler_reset_export : out std_logic; -- export
+ reg_bsn_scheduler_write_export : out std_logic; -- export
+ reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
+ reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_crosslets_info_clk_export : out std_logic; -- export
+ reg_crosslets_info_read_export : out std_logic; -- export
+ reg_crosslets_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_crosslets_info_reset_export : out std_logic; -- export
+ reg_crosslets_info_write_export : out std_logic; -- export
+ reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_diag_data_buffer_bsn_reset_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_write_export : out std_logic; -- export
+ reg_diag_data_buffer_bsn_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_bsn_at_sync_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_bsn_at_sync_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_bf_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_block_validate_err_bf_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_bf_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_block_validate_err_xst_reset_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_clk_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_block_validate_err_xst_write_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_block_validate_err_xst_read_export : out std_logic; -- export
+ reg_dp_block_validate_err_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dp_selector_clk_export : out std_logic; -- export
+ reg_dp_selector_read_export : out std_logic; -- export
+ reg_dp_selector_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_selector_reset_export : out std_logic; -- export
+ reg_dp_selector_write_export : out std_logic; -- export
+ reg_dp_selector_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_shiftram_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_dp_shiftram_clk_export : out std_logic; -- export
+ reg_dp_shiftram_read_export : out std_logic; -- export
+ reg_dp_shiftram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_shiftram_reset_export : out std_logic; -- export
+ reg_dp_shiftram_write_export : out std_logic; -- export
+ reg_dp_shiftram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dp_xonoff_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_dp_xonoff_clk_export : out std_logic; -- export
+ reg_dp_xonoff_read_export : out std_logic; -- export
+ reg_dp_xonoff_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dp_xonoff_reset_export : out std_logic; -- export
+ reg_dp_xonoff_write_export : out std_logic; -- export
+ reg_dp_xonoff_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_ctrl_clk_export : out std_logic; -- export
+ reg_dpmm_ctrl_read_export : out std_logic; -- export
+ reg_dpmm_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_ctrl_reset_export : out std_logic; -- export
+ reg_dpmm_ctrl_write_export : out std_logic; -- export
+ reg_dpmm_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_dpmm_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_dpmm_data_clk_export : out std_logic; -- export
+ reg_dpmm_data_read_export : out std_logic; -- export
+ reg_dpmm_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_dpmm_data_reset_export : out std_logic; -- export
+ reg_dpmm_data_write_export : out std_logic; -- export
+ reg_dpmm_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_epcs_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_epcs_clk_export : out std_logic; -- export
+ reg_epcs_read_export : out std_logic; -- export
+ reg_epcs_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_epcs_reset_export : out std_logic; -- export
+ reg_epcs_write_export : out std_logic; -- export
+ reg_epcs_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_temp_sens_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_fpga_temp_sens_clk_export : out std_logic; -- export
+ reg_fpga_temp_sens_read_export : out std_logic; -- export
+ reg_fpga_temp_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_temp_sens_reset_export : out std_logic; -- export
+ reg_fpga_temp_sens_write_export : out std_logic; -- export
+ reg_fpga_temp_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_fpga_voltage_sens_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_fpga_voltage_sens_clk_export : out std_logic; -- export
+ reg_fpga_voltage_sens_read_export : out std_logic; -- export
+ reg_fpga_voltage_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_fpga_voltage_sens_reset_export : out std_logic; -- export
+ reg_fpga_voltage_sens_write_export : out std_logic; -- export
+ reg_fpga_voltage_sens_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_hdr_dat_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_hdr_dat_clk_export : out std_logic; -- export
+ reg_hdr_dat_read_export : out std_logic; -- export
+ reg_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_hdr_dat_reset_export : out std_logic; -- export
+ reg_hdr_dat_write_export : out std_logic; -- export
+ reg_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_ctrl_clk_export : out std_logic; -- export
+ reg_mmdp_ctrl_read_export : out std_logic; -- export
+ reg_mmdp_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_ctrl_reset_export : out std_logic; -- export
+ reg_mmdp_ctrl_write_export : out std_logic; -- export
+ reg_mmdp_ctrl_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_mmdp_data_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_mmdp_data_clk_export : out std_logic; -- export
+ reg_mmdp_data_read_export : out std_logic; -- export
+ reg_mmdp_data_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_mmdp_data_reset_export : out std_logic; -- export
+ reg_mmdp_data_write_export : out std_logic; -- export
+ reg_mmdp_data_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_reset_export : out std_logic; -- export
+ reg_nof_crosslets_clk_export : out std_logic; -- export
+ reg_nof_crosslets_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nof_crosslets_write_export : out std_logic; -- export
+ reg_nof_crosslets_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nof_crosslets_read_export : out std_logic; -- export
+ reg_nof_crosslets_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_nw_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_nw_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_nw_10gbe_mac_address_export : out std_logic_vector(12 downto 0); -- export
+ reg_nw_10gbe_mac_clk_export : out std_logic; -- export
+ reg_nw_10gbe_mac_read_export : out std_logic; -- export
+ reg_nw_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_nw_10gbe_mac_reset_export : out std_logic; -- export
+ reg_nw_10gbe_mac_write_export : out std_logic; -- export
+ reg_nw_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_remu_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_remu_clk_export : out std_logic; -- export
+ reg_remu_read_export : out std_logic; -- export
+ reg_remu_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_remu_reset_export : out std_logic; -- export
+ reg_remu_write_export : out std_logic; -- export
+ reg_remu_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_reset_export : out std_logic; -- export
+ reg_ring_info_clk_export : out std_logic; -- export
+ reg_ring_info_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_info_write_export : out std_logic; -- export
+ reg_ring_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_info_read_export : out std_logic; -- export
+ reg_ring_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_bf_reset_export : out std_logic; -- export
+ reg_ring_lane_info_bf_clk_export : out std_logic; -- export
+ reg_ring_lane_info_bf_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_ring_lane_info_bf_write_export : out std_logic; -- export
+ reg_ring_lane_info_bf_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_bf_read_export : out std_logic; -- export
+ reg_ring_lane_info_bf_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_ring_lane_info_xst_reset_export : out std_logic; -- export
+ reg_ring_lane_info_xst_clk_export : out std_logic; -- export
+ reg_ring_lane_info_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_ring_lane_info_xst_write_export : out std_logic; -- export
+ reg_ring_lane_info_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_ring_lane_info_xst_read_export : out std_logic; -- export
+ reg_ring_lane_info_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_sdp_info_clk_export : out std_logic; -- export
+ reg_sdp_info_read_export : out std_logic; -- export
+ reg_sdp_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_sdp_info_reset_export : out std_logic; -- export
+ reg_sdp_info_write_export : out std_logic; -- export
+ reg_sdp_info_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_si_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_si_clk_export : out std_logic; -- export
+ reg_si_read_export : out std_logic; -- export
+ reg_si_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_si_reset_export : out std_logic; -- export
+ reg_si_write_export : out std_logic; -- export
+ reg_si_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_bst_address_export : out std_logic_vector(1 downto 0); -- export
+ reg_stat_enable_bst_clk_export : out std_logic; -- export
+ reg_stat_enable_bst_read_export : out std_logic; -- export
+ reg_stat_enable_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_bst_reset_export : out std_logic; -- export
+ reg_stat_enable_bst_write_export : out std_logic; -- export
+ reg_stat_enable_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_sst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_sst_clk_export : out std_logic; -- export
+ reg_stat_enable_sst_read_export : out std_logic; -- export
+ reg_stat_enable_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_sst_reset_export : out std_logic; -- export
+ reg_stat_enable_sst_write_export : out std_logic; -- export
+ reg_stat_enable_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_enable_xst_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_stat_enable_xst_clk_export : out std_logic; -- export
+ reg_stat_enable_xst_read_export : out std_logic; -- export
+ reg_stat_enable_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_enable_xst_reset_export : out std_logic; -- export
+ reg_stat_enable_xst_write_export : out std_logic; -- export
+ reg_stat_enable_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_bst_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_stat_hdr_dat_bst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_sst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_sst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_sst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_sst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_stat_hdr_dat_xst_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_stat_hdr_dat_xst_clk_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_read_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_stat_hdr_dat_xst_reset_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_write_export : out std_logic; -- export
+ reg_stat_hdr_dat_xst_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_reset_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_clk_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_tr_10gbe_eth10g_write_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_eth10g_read_export : out std_logic; -- export
+ reg_tr_10gbe_eth10g_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_tr_10gbe_mac_reset_export : out std_logic; -- export
+ reg_tr_10gbe_mac_clk_export : out std_logic; -- export
+ reg_tr_10gbe_mac_address_export : out std_logic_vector(14 downto 0); -- export
+ reg_tr_10gbe_mac_write_export : out std_logic; -- export
+ reg_tr_10gbe_mac_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_tr_10gbe_mac_read_export : out std_logic; -- export
+ reg_tr_10gbe_mac_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_address_export : out std_logic_vector(0 downto 0); -- export
+ reg_wdi_clk_export : out std_logic; -- export
+ reg_wdi_read_export : out std_logic; -- export
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wdi_reset_export : out std_logic; -- export
+ reg_wdi_write_export : out std_logic; -- export
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_wg_address_export : out std_logic_vector(5 downto 0); -- export
+ reg_wg_clk_export : out std_logic; -- export
+ reg_wg_read_export : out std_logic; -- export
+ reg_wg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_wg_reset_export : out std_logic; -- export
+ reg_wg_write_export : out std_logic; -- export
+ reg_wg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ rom_system_info_address_export : out std_logic_vector(12 downto 0); -- export
+ rom_system_info_clk_export : out std_logic; -- export
+ rom_system_info_read_export : out std_logic; -- export
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ rom_system_info_reset_export : out std_logic; -- export
+ rom_system_info_write_export : out std_logic; -- export
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2c_sdp_station;
END qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/images/images.txt b/applications/lofar2/images/images.txt
index f7f918986067a2bf413c825c81765dbde587689c..17d89fa986982fa10443299c098044d9a0763b2e 100644
--- a/applications/lofar2/images/images.txt
+++ b/applications/lofar2/images/images.txt
@@ -10,4 +10,5 @@ lofar2_unb2b_sdp_station_bf-r087d98be6 | 2021-06-14 | R vd Walle
lofar2_unb2b_sdp_station_xsub_one-r087d98be6 | 2021-06-14 | R vd Walle |
unb2b_minimal-rce6b96eed | 2021-08-26 | P. Donker | unb2b_minimal with new mmap, rbf maid with option --unb2_factory
lofar2_unb2b_sdp_station_full-r9ff51058a | 2022-01-12 | R vd Walle | Lofar2 SDP station full design for UniBoard2b.
-lofar2_unb2c_sdp_station_full-rfc9844d8e | 2021-12-16 | R vd Walle | Lofar2 SDP station full design for UniBoard2c.
+lofar2_unb2b_sdp_station_full_wg-r241070441 | 2022-04-13 | R vd Walle | Lofar2 SDP station design without ADC inputs, only WG. Uses dp_clk + dp_pps instead of rx_clk + rx_sysref.
+lofar2_unb2c_sdp_station_full-rb8464ee23 | 2022-04-12 | R vd Walle | Lofar2 SDP station full design for UniBoard2c.
diff --git a/applications/lofar2/images/lofar2_unb2b_sdp_station_full.tar.gz b/applications/lofar2/images/lofar2_unb2b_sdp_station_full.tar.gz
index 7dee884c8253b5084754d0bdfe736673225b1cc8..34e6355a90e71d0161f12765a330aa0b6cd398a4 120000
--- a/applications/lofar2/images/lofar2_unb2b_sdp_station_full.tar.gz
+++ b/applications/lofar2/images/lofar2_unb2b_sdp_station_full.tar.gz
@@ -1 +1 @@
-lofar2_unb2b_sdp_station_bf-r087d98be6.tar.gz
\ No newline at end of file
+lofar2_unb2b_sdp_station_full-r9ff51058a.tar.gz
\ No newline at end of file
diff --git a/applications/lofar2/images/lofar2_unb2b_sdp_station_full_wg-r241070441.tar.gz b/applications/lofar2/images/lofar2_unb2b_sdp_station_full_wg-r241070441.tar.gz
new file mode 100644
index 0000000000000000000000000000000000000000..3da58680470a8eb1488dd7127ad5ccef85a2d6e7
Binary files /dev/null and b/applications/lofar2/images/lofar2_unb2b_sdp_station_full_wg-r241070441.tar.gz differ
diff --git a/applications/lofar2/images/lofar2_unb2c_sdp_station_full-rfc9844d8e.tar.gz b/applications/lofar2/images/lofar2_unb2c_sdp_station_full-rb8464ee23.tar.gz
similarity index 57%
rename from applications/lofar2/images/lofar2_unb2c_sdp_station_full-rfc9844d8e.tar.gz
rename to applications/lofar2/images/lofar2_unb2c_sdp_station_full-rb8464ee23.tar.gz
index f57442d780cbf0b76b04a15594fa222704b02c19..8b830c14061a1a807b8aefe8e422cbc9197508c4 100644
Binary files a/applications/lofar2/images/lofar2_unb2c_sdp_station_full-rfc9844d8e.tar.gz and b/applications/lofar2/images/lofar2_unb2c_sdp_station_full-rb8464ee23.tar.gz differ
diff --git a/applications/lofar2/libraries/sdp/hdllib.cfg b/applications/lofar2/libraries/sdp/hdllib.cfg
index 20b9cf3d5a1a27bf384f3e33d35ee91ecd7e7705..380e327a6bc72885dc4b16121b43a70e32146aca 100644
--- a/applications/lofar2/libraries/sdp/hdllib.cfg
+++ b/applications/lofar2/libraries/sdp/hdllib.cfg
@@ -10,6 +10,7 @@ synth_files =
src/vhdl/sdp_subband_equalizer.vhd
src/vhdl/sdp_bf_weights.vhd
src/vhdl/sdp_beamformer_local.vhd
+ src/vhdl/sdp_beamformer_remote.vhd
src/vhdl/sdp_info_reg.vhd
src/vhdl/sdp_info.vhd
src/vhdl/sdp_beamformer_output.vhd
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index e45e1d737a5f1ea3b1f1cdff74bdc333e9a3e6b9..94c9ce8b457e0347216606a067062f7a58981f36 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -303,7 +303,7 @@ peripherals:
- - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
- - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
- - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
- - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_weighted_subbands_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
- - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
- - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
- - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
@@ -372,7 +372,7 @@ peripherals:
- - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
- - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
- - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
- - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_weighted_subbands_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
- - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
- - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
- - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
@@ -442,7 +442,7 @@ peripherals:
- - { field_name: sdp_source_info_fsub_type, mm_width: 1, bit_offset: 11, access_mode: RW, address_offset: 0x38 }
- - { field_name: sdp_source_info_payload_error, mm_width: 1, bit_offset: 10, access_mode: RW, address_offset: 0x34 }
- - { field_name: sdp_source_info_beam_repositioning_flag, mm_width: 1, bit_offset: 9, access_mode: RW, address_offset: 0x30 }
- - - { field_name: sdp_source_info_subband_calibrated_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
+ - - { field_name: sdp_source_info_weighted_subbands_flag, mm_width: 1, bit_offset: 8, access_mode: RW, address_offset: 0x2C }
- - { field_name: sdp_source_info_reserved, mm_width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x28 }
- - { field_name: sdp_source_info_gn_index, mm_width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
- - { field_name: sdp_reserved, mm_width: 8, access_mode: RW, address_offset: 0x20 }
diff --git a/applications/lofar2/libraries/sdp/src/python/sdp_hex.py b/applications/lofar2/libraries/sdp/src/python/sdp_hex.py
new file mode 100644
index 0000000000000000000000000000000000000000..1efa228e1a8f74ad63293b7c5ef1b7bd9fd63286
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/src/python/sdp_hex.py
@@ -0,0 +1,52 @@
+#! /usr/bin/env python3
+###############################################################################
+#
+# Copyright 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+###############################################################################
+# Author: Reinier vd Walle
+# Purpose: Generate the hex files for RAM initialization in SDP designs
+###############################################################################
+
+from intelhex import IntelHex
+import struct
+
+for i in range(0,6):
+ f = IntelHex()
+ for j in range(0,2*488):
+ #f.puts(j*4, struct.pack(">I",j))
+ f.puts(j*2, struct.pack(">H",j))
+
+ f.write_hex_file("bf_unit_ss_wide_"+str(i)+".hex", byte_count = 2)
+
+for i in range(0,12):
+ f = IntelHex()
+ for j in range(0,2*488):
+ f[4*j] = 0x00
+ f[4*j + 1] = 0x00
+ f[4*j + 2] = 0x40
+ f[4*j + 3] = 0x00
+ f.write_hex_file("bf_unit_weights_"+str(i)+".hex", byte_count = 4)
+
+for i in range(0,6):
+ f = IntelHex()
+ for j in range(0,1024):
+ f[4*j] = 0x00
+ f[4*j + 1] = 0x00
+ f[4*j + 2] = 0x20
+ f[4*j + 3] = 0x00
+ f.write_hex_file("gains_1024_complex_16b13f_unit_"+str(i)+".hex", byte_count = 4)
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 54d4befcf255eeb8d7b3f1ce8e07e4c193c48f59..4bca947d2bf3d642596b9b977a21ca0e319f3620 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -40,6 +40,7 @@ USE work.sdp_pkg.ALL;
ENTITY node_sdp_adc_input_and_timing IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
+ g_no_jesd : BOOLEAN := FALSE;
g_buf_nof_data : NATURAL := c_sdp_V_si_db;
g_bsn_nof_clk_per_sync : NATURAL := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
g_sim : BOOLEAN := FALSE
@@ -50,7 +51,7 @@ ENTITY node_sdp_adc_input_and_timing IS
mm_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
-
+ dp_pps : IN STD_LOGIC := '0';
-- mm control buses
-- JESD
@@ -98,10 +99,10 @@ ENTITY node_sdp_adc_input_and_timing IS
jesd_ctrl_miso : OUT t_mem_miso;
-- JESD io signals
- jesd204b_serial_data : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
- jesd204b_refclk : IN STD_LOGIC;
- jesd204b_sysref : IN STD_LOGIC;
- jesd204b_sync_n : OUT STD_LOGIC_VECTOR(c_sdp_N_sync_jesd - 1 DOWNTO 0);
+ jesd204b_serial_data : IN STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0) := (OTHERS => '0');
+ jesd204b_refclk : IN STD_LOGIC := '0';
+ jesd204b_sysref : IN STD_LOGIC := '0';
+ jesd204b_sync_n : OUT STD_LOGIC_VECTOR(c_sdp_N_sync_jesd - 1 DOWNTO 0) := (OTHERS => '0');
-- Streaming data output
out_sosi_arr : OUT t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
@@ -133,26 +134,31 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
SIGNAL rx_bsn_source_restart : STD_LOGIC;
-- Sosis and sosi arrays
- SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL ant_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL bs_sosi : t_dp_sosi;
- SIGNAL wg_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL mux_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL nxt_mux_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL st_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
+ SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL dp_shiftram_snk_in_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL ant_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL bs_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL wg_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL mux_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL nxt_mux_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL st_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL mm_rst_internal : STD_LOGIC;
SIGNAL mm_jesd_ctrl_reg : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL jesd204b_disable_arr : STD_LOGIC_VECTOR(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL jesd204b_reset : STD_LOGIC;
BEGIN
- -- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
+ gen_no_jesd : IF g_no_jesd = TRUE GENERATE
+ rx_clk <= dp_clk;
+ rx_rst <= dp_rst;
+ rx_sysref <= dp_pps;
+ END GENERATE;
+
+ -- The node AIT is reset at power up by mm_rst and under software control by jesd204b_disable_arr.
-- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
- -- The MM jesd204b_reset is intended for node AIT resynchronisation tests of the u_jesd204b.
- -- The MM jesd204b_reset should not be applied in an SDP application, because this will cause
+ -- The MM jesd204b_disable_arr is intended for node AIT resynchronisation tests of the u_jesd204b.
+ -- The MM jesd204b_disable_arr should not be applied in an SDP application, because this will cause
-- a disturbance in the block timing of the out_sosi_arr(i).sync,bsn,sop,eop. The other logic
-- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
-- complete blocks, so from sop to eop.
@@ -162,84 +168,86 @@ BEGIN
jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
END GENERATE;
- -----------------------------------------------------------------------------
- -- JESD204B IP (ADC Handler)
- -----------------------------------------------------------------------------
+ gen_jesd : IF g_no_jesd = FALSE GENERATE
+ -----------------------------------------------------------------------------
+ -- JESD204B IP (ADC Handler)
+ -----------------------------------------------------------------------------
+
+ u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_nof_streams => c_sdp_S_pn,
+ g_nof_sync_n => c_sdp_N_sync_jesd,
+ g_jesd_freq => c_sdp_jesd204b_freq
+ )
+ PORT MAP(
+ jesd204b_refclk => JESD204B_REFCLK,
+ jesd204b_sysref => JESD204B_SYSREF,
+ jesd204b_sync_n_arr => jesd204b_sync_n,
+
+ rx_sosi_arr => rx_sosi_arr,
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+ rx_sysref => rx_sysref,
- u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
- GENERIC MAP(
- g_sim => g_sim,
- g_nof_streams => c_sdp_S_pn,
- g_nof_sync_n => c_sdp_N_sync_jesd,
- g_jesd_freq => c_sdp_jesd204b_freq
- )
- PORT MAP(
- jesd204b_refclk => JESD204B_REFCLK,
- jesd204b_sysref => JESD204B_SYSREF,
- jesd204b_sync_n_arr => jesd204b_sync_n,
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst_internal,
+
+ jesd204b_mosi => jesd204b_mosi,
+ jesd204b_miso => jesd204b_miso,
+
+ -- Serial
+ serial_tx_arr => open,
+ serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn-1 downto 0)
+ );
- rx_sosi_arr => rx_sosi_arr,
- rx_clk => rx_clk,
- rx_rst => rx_rst,
- rx_sysref => rx_sysref,
-
- jesd204b_disable_arr => jesd204b_disable_arr,
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst_internal,
+ -----------------------------------------------------------------------------
+ -- Time delay: dp_shiftram
+ -- . copied from unb1_bn_capture_input (apertif)
+ -- Array range reversal is not done because everything is DOWNTO
+ -- . the input valid is always '1', even when there is no data
+ -----------------------------------------------------------------------------
+
+ p_dp_shiftram_snk_in_arr : PROCESS(rx_sosi_arr)
+ BEGIN
+ dp_shiftram_snk_in_arr <= rx_sosi_arr;
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ -- ADC data is stored in the upper 14 bits of the jesd rx_sosi.
+ dp_shiftram_snk_in_arr(I).data <= RESIZE_DP_SDATA(rx_sosi_arr(I).data(c_sdp_W_adc_jesd-1 DOWNTO (c_sdp_W_adc_jesd - c_sdp_W_adc) ));
+ -- Force valid.
+ dp_shiftram_snk_in_arr(I).valid <= '1';
+ END LOOP;
+ END PROCESS;
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- -- Serial
- serial_tx_arr => open,
- serial_rx_arr => JESD204B_SERIAL_DATA(c_sdp_S_pn-1 downto 0)
- );
-
-
- -----------------------------------------------------------------------------
- -- Time delay: dp_shiftram
- -- . copied from unb1_bn_capture_input (apertif)
- -- Array range reversal is not done because everything is DOWNTO
- -- . the input valid is always '1', even when there is no data
- -----------------------------------------------------------------------------
+ u_dp_shiftram : ENTITY dp_lib.dp_shiftram
+ GENERIC MAP (
+ g_nof_streams => c_sdp_S_pn,
+ g_nof_words => c_sdp_V_sample_delay,
+ g_data_w => c_sdp_W_adc,
+ g_use_sync_in => TRUE
+ )
+ PORT MAP (
+ dp_rst => rx_rst,
+ dp_clk => rx_clk,
- p_dp_shiftram_snk_in_arr : PROCESS(rx_sosi_arr)
- BEGIN
- dp_shiftram_snk_in_arr <= rx_sosi_arr;
- FOR I IN 0 TO c_sdp_S_pn-1 LOOP
- -- ADC data is stored in the upper 14 bits of the jesd rx_sosi.
- dp_shiftram_snk_in_arr(I).data <= RESIZE_DP_SDATA(rx_sosi_arr(I).data(c_sdp_W_adc_jesd-1 DOWNTO (c_sdp_W_adc_jesd - c_sdp_W_adc) ));
- -- Force valid.
- dp_shiftram_snk_in_arr(I).valid <= '1';
- END LOOP;
- END PROCESS;
-
-
- u_dp_shiftram : ENTITY dp_lib.dp_shiftram
- GENERIC MAP (
- g_nof_streams => c_sdp_S_pn,
- g_nof_words => c_sdp_V_sample_delay,
- g_data_w => c_sdp_W_adc,
- g_use_sync_in => TRUE
- )
- PORT MAP (
- dp_rst => rx_rst,
- dp_clk => rx_clk,
-
- mm_rst => mm_rst_internal,
- mm_clk => mm_clk,
-
- sync_in => bs_sosi.sync,
-
- reg_mosi => reg_dp_shiftram_mosi,
- reg_miso => reg_dp_shiftram_miso,
-
- snk_in_arr => dp_shiftram_snk_in_arr,
-
- src_out_arr => ant_sosi_arr
- );
+ mm_rst => mm_rst_internal,
+ mm_clk => mm_clk,
+
+ sync_in => bs_sosi.sync,
+
+ reg_mosi => reg_dp_shiftram_mosi,
+ reg_miso => reg_dp_shiftram_miso,
+
+ snk_in_arr => dp_shiftram_snk_in_arr,
+
+ src_out_arr => ant_sosi_arr
+ );
+ END GENERATE;
-----------------------------------------------------------------------------
-- Timestamp
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index c82f450ad9525890f4a7ba21931f133b48df1123..3053b5f21d4b25e3851a0c57cd02ddec09accbac 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -29,12 +29,13 @@
-- .
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib;
+LIBRARY IEEE, common_lib, dp_lib, reorder_lib, st_lib, mm_lib, ring_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE ring_lib.ring_pkg.ALL;
USE work.sdp_pkg.ALL;
ENTITY node_sdp_beamformer IS
@@ -49,6 +50,8 @@ ENTITY node_sdp_beamformer IS
dp_rst : IN STD_LOGIC;
in_sosi_arr : IN t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ from_ri_sosi : IN t_dp_sosi;
+ to_ri_sosi : OUT t_dp_sosi;
bf_udp_sosi : OUT t_dp_sosi;
bf_udp_siso : IN t_dp_siso;
bst_udp_sosi : OUT t_dp_sosi;
@@ -73,9 +76,19 @@ ENTITY node_sdp_beamformer IS
reg_stat_enable_miso : OUT t_mem_miso;
reg_stat_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_stat_hdr_dat_miso : OUT t_mem_miso;
-
- sdp_info : IN t_sdp_info;
- gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
+ reg_bsn_align_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_bsn_align_input_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_bst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bst_offload_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_beamlet_output_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_beamlet_output_cipo : OUT t_mem_cipo;
+ sdp_info : IN t_sdp_info;
+ ring_info : IN t_ring_info;
+ gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
-- beamlet data output
bdo_eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
@@ -94,8 +107,9 @@ END node_sdp_beamformer;
ARCHITECTURE str OF node_sdp_beamformer IS
+ -- Note that the sdp library contains src/python/sdp_hex.py to generate hex files.
CONSTANT c_bf_select_file_prefix : STRING := "data/bf_unit_ss_wide";
- CONSTANT c_bf_weights_file_name : STRING := "data/bf_unit_weights";
+ CONSTANT c_bf_weights_file_name : STRING := sel_a_b(g_sim, "data/bf_unit_weights", "UNUSED");
CONSTANT c_nof_masters : POSITIVE := 2;
@@ -112,11 +126,18 @@ ARCHITECTURE str OF node_sdp_beamformer IS
SIGNAL local_bf_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL bf_sum_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL bf_out_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL mon_bf_udp_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL scope_local_bf_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol_bf-1 DOWNTO 0);
SIGNAL scope_bf_sum_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol_bf-1 DOWNTO 0);
SIGNAL scope_bf_out_sosi_arr : t_dp_sosi_integer_arr(c_sdp_N_pol_bf-1 DOWNTO 0);
SIGNAL beamlet_scale : STD_LOGIC_VECTOR(c_sdp_W_beamlet_scale-1 DOWNTO 0);
+
+ SIGNAL rn_index : NATURAL RANGE 0 TO c_sdp_N_pn_max-1 := 0;
+
BEGIN
+
+ rn_index <= TO_UINT(SUB_UVEC(gn_id, ring_info.O_rn)) WHEN rising_edge(dp_clk); -- Using register to ease timing closure.
+
---------------------------------------------------------------
-- Beamlet Subband Select
---------------------------------------------------------------
@@ -165,8 +186,28 @@ BEGIN
---------------------------------------------------------------
-- Remote BF
---------------------------------------------------------------
- -- Not yet implemented
- bf_sum_sosi <= local_bf_sosi;
+ u_sdp_beamformer_remote : ENTITY work.sdp_beamformer_remote
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ rn_index => rn_index,
+ local_bf_sosi => local_bf_sosi,
+ from_ri_sosi => from_ri_sosi,
+ to_ri_sosi => to_ri_sosi,
+ bf_sum_sosi => bf_sum_sosi,
+
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo
+ );
---------------------------------------------------------------
-- Scale Beamlets
@@ -215,7 +256,7 @@ BEGIN
dp_clk => dp_clk,
in_sosi => bf_out_sosi,
- out_sosi => bf_udp_sosi,
+ out_sosi => mon_bf_udp_sosi,
src_in => bf_udp_siso,
beamlet_scale => beamlet_scale,
@@ -233,6 +274,33 @@ BEGIN
reg_dp_xonoff_mosi => reg_dp_xonoff_mosi,
reg_dp_xonoff_miso => reg_dp_xonoff_miso
);
+ bf_udp_sosi <= mon_bf_udp_sosi;
+
+ u_bsn_mon_udp : ENTITY dp_lib.mms_dp_bsn_monitor_v2
+ GENERIC MAP (
+ g_nof_streams => 1,
+ g_cross_clock_domain => TRUE,
+ g_sync_timeout => c_sdp_N_clk_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ PORT MAP (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_beamlet_output_copi,
+ reg_miso => reg_bsn_monitor_v2_beamlet_output_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => mon_bf_udp_sosi.sync,
+
+ in_sosi_arr(0) => mon_bf_udp_sosi
+ );
---------------------------------------------------------------
-- Beamlet Statistics (BST)
@@ -302,6 +370,9 @@ BEGIN
reg_hdr_dat_mosi => reg_stat_hdr_dat_mosi,
reg_hdr_dat_miso => reg_stat_hdr_dat_miso,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_bst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo,
+
in_sosi => bf_sum_sosi,
out_sosi => bst_udp_sosi,
out_siso => bst_udp_siso,
@@ -310,8 +381,10 @@ BEGIN
udp_src_port => stat_udp_src_port,
ip_src_addr => stat_ip_src_addr,
+ gn_index => TO_UINT(gn_id),
+ ring_info => ring_info,
sdp_info => sdp_info,
- gn_index => TO_UINT(gn_id)
+ weighted_subbands_flag => '1' -- because BF uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
);
---------------------------------------------------------------
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 03f715308242a93f66576406a97ecc7148d20e3d..ec8180f396e3c3a6837878b26792c6f01f29274b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -75,8 +75,8 @@ ENTITY node_sdp_correlator IS
reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_cipo;
reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_copi := c_mem_copi_rst;
reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_cipo;
- reg_xst_udp_monitor_copi : IN t_mem_copi := c_mem_copi_rst;
- reg_xst_udp_monitor_cipo : OUT t_mem_cipo;
+ reg_bsn_monitor_v2_xst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_xst_offload_cipo : OUT t_mem_cipo;
sdp_info : IN t_sdp_info;
ring_info : IN t_ring_info;
@@ -457,6 +457,9 @@ BEGIN
reg_hdr_dat_mosi => reg_stat_hdr_dat_copi,
reg_hdr_dat_miso => reg_stat_hdr_dat_cipo,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
+
in_sosi => crosslets_sosi,
out_sosi => mon_xst_udp_sosi_arr(0),
out_siso => xst_udp_siso,
@@ -468,37 +471,9 @@ BEGIN
gn_index => TO_UINT(gn_id),
ring_info => ring_info,
sdp_info => sdp_info,
+ weighted_subbands_flag => '1', -- because XSub uses in_sosi_arr = fsub_sosi_arr, so weighted subbands
nof_crosslets => nof_crosslets,
crosslets_info => crosslets_info
);
- ---------------------------------------------------------------
- -- BSN Monitor for XST UDP offload
- ---------------------------------------------------------------
- u_bsn_mon_xst_udp : ENTITY dp_lib.mms_dp_bsn_monitor_v2
- GENERIC MAP (
- g_nof_streams => 1,
- g_cross_clock_domain => TRUE,
- g_sync_timeout => c_sdp_N_clk_per_sync,
- g_bsn_w => c_dp_stream_bsn_w,
- g_error_bi => 0,
- g_cnt_sop_w => c_word_w,
- g_cnt_valid_w => c_word_w,
- g_cnt_latency_w => c_word_w
- )
- PORT MAP (
- -- Memory-mapped clock domain
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_xst_udp_monitor_copi,
- reg_miso => reg_xst_udp_monitor_cipo,
-
- -- Streaming clock domain
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- ref_sync => crosslets_sosi.sync, -- using crosslets_sosi sync instead of xst_udp_sosi as it has no sync.
-
- in_sosi_arr => mon_xst_udp_sosi_arr
- );
-
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index aadbfee3b3af8fc6980d565c488d954dad0ec29c..e5634c5516d0e5f5b3adfb766ed9ddb8b195118a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -82,6 +82,8 @@ ENTITY node_sdp_filterbank IS
reg_enable_miso : OUT t_mem_miso;
reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_hdr_dat_miso : OUT t_mem_miso;
+ reg_bsn_monitor_v2_sst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_sst_offload_cipo : OUT t_mem_cipo;
sdp_info : IN t_sdp_info;
gn_id : IN STD_LOGIC_VECTOR(c_sdp_W_gn_id-1 DOWNTO 0);
@@ -95,7 +97,7 @@ END node_sdp_filterbank;
ARCHITECTURE str OF node_sdp_filterbank IS
CONSTANT c_coefs_file_prefix : STRING := "data/Coeffs16384Kaiser-quant_1wb";
- CONSTANT c_gains_file_name : STRING := "data/gains_1024_complex_16b13f_unit";
+ CONSTANT c_gains_file_name : STRING := "data/gains_1024_complex_16b13f_unit"; -- Can be generated by src/python/sdp_hex.py
CONSTANT c_subband_equalizer_latency : NATURAL := 4;
@@ -124,7 +126,7 @@ ARCHITECTURE str OF node_sdp_filterbank IS
SIGNAL scope_sosi_arr : t_dp_sosi_integer_arr(c_sdp_S_pn-1 DOWNTO 0);
SIGNAL selector_en : STD_LOGIC;
- SIGNAL subband_calibrated_flag : STD_LOGIC;
+ SIGNAL weighted_subbands_flag : STD_LOGIC;
SIGNAL dp_bsn_source_restart_pipe : STD_LOGIC;
BEGIN
---------------------------------------------------------------
@@ -331,7 +333,7 @@ BEGIN
---------------------------------------------------------------
-- STATISTICS OFFLOAD
---------------------------------------------------------------
- subband_calibrated_flag <= NOT selector_en;
+ weighted_subbands_flag <= NOT selector_en;
u_sdp_sst_udp_offload: ENTITY work.sdp_statistics_offload
GENERIC MAP (
@@ -354,6 +356,9 @@ BEGIN
reg_hdr_dat_mosi => reg_hdr_dat_mosi,
reg_hdr_dat_miso => reg_hdr_dat_miso,
+ reg_bsn_monitor_v2_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
in_sosi => dp_selector_out_sosi_arr(0),
out_sosi => sst_udp_sosi,
out_siso => sst_udp_siso,
@@ -364,7 +369,7 @@ BEGIN
gn_index => TO_UINT(gn_id),
sdp_info => sdp_info,
- subband_calibrated_flag => subband_calibrated_flag
+ weighted_subbands_flag => weighted_subbands_flag
);
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
index 134b80aa33fee8a984a5e9a0d60fe94f8023ba5e..39f94923b302fcb5ac28f72cf5cc5185b84901b8 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
@@ -77,11 +77,15 @@ ARCHITECTURE str OF sdp_beamformer_local IS
BEGIN
---------------------------------------------------------------
- -- COPY INPUT STERAMS FOR X AND Y POLARIZATION PATHS
- ---------------------------------------------------------------
- gen_pol : FOR N_pol_bf IN 0 TO c_sdp_N_pol_bf-1 GENERATE
- gen_pfb : FOR P_pfb IN 0 TO c_sdp_P_pfb-1 GENERATE
- sub_sosi_arr(N_pol_bf * c_sdp_P_pfb + P_pfb) <= in_sosi_arr(P_pfb);
+ -- COPY INPUT STREAMS FOR X AND Y POLARIZATION PATHS
+ -- 0: 5 = S_pn signal inputs (time multiplexed by Q_fft) for BF X pol
+ -- 6:11 = S_pn signal inputs (time multiplexed by Q_fft) for BF Y pol
+ ---------------------------------------------------------------
+ -- Use short index variables PB (= Polarization Beamlet), I (= Instance)
+ -- names, to ease recognizing them as loop indices.
+ gen_pol : FOR PB IN 0 TO c_sdp_N_pol_bf-1 GENERATE
+ gen_pfb : FOR I IN 0 TO c_sdp_P_pfb-1 GENERATE
+ sub_sosi_arr(PB * c_sdp_P_pfb + I) <= in_sosi_arr(I);
END GENERATE;
END GENERATE;
@@ -109,23 +113,8 @@ BEGIN
-- X pol is lower half of bf_weights_out
bf_weights_x_sosi_arr <= bf_weights_out_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- ---------------------------------------------------------------
- -- DP PIPELINE Y PATH
- ---------------------------------------------------------------
- -- The weighted subbands from the Y polarization path are pipelined
- -- by one cycle so that they can be time multiplexed with the
- -- weighted subbands from the X polarization.
- u_pipeline_y_pol : ENTITY dp_lib.dp_pipeline_arr
- GENERIC MAP (
- g_nof_streams => c_sdp_P_pfb,
- g_pipeline => 1
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => bf_weights_out_sosi_arr(2*c_sdp_P_pfb-1 DOWNTO c_sdp_P_pfb),
- src_out_arr => bf_weights_y_sosi_arr
- );
+ -- Y pol is upper half of bf_weights_out
+ bf_weights_y_sosi_arr <= bf_weights_out_sosi_arr(2*c_sdp_P_pfb-1 DOWNTO c_sdp_P_pfb);
---------------------------------------------------------------
-- DEINTERLEAVE X PATH
@@ -157,7 +146,7 @@ BEGIN
rst => dp_rst,
clk => dp_clk,
- snk_in => bf_weights_y_sosi_arr(I),
+ snk_in => bf_weights_y_sosi_arr(I),
src_out_arr(0) => deinterleaved_y_sosi_arr(c_sdp_Q_fft*I),
src_out_arr(1) => deinterleaved_y_sosi_arr(c_sdp_Q_fft*I+1)
);
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7d0ef9619c8e17c15c703d1b2428a6c982266ed2
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
@@ -0,0 +1,245 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose:
+-- . Implements the functionality of beamformer_remote in node_sdp_beamformer.
+-- Description:
+-- The remote BF function adds the local and remote sums.
+-- Remark:
+-- .
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.sdp_pkg.ALL;
+
+ENTITY sdp_beamformer_remote IS
+ PORT (
+ dp_clk : IN STD_LOGIC;
+ dp_rst : IN STD_LOGIC;
+
+ rn_index : IN NATURAL RANGE 0 TO c_sdp_N_pn_max-1 := 0;
+
+ local_bf_sosi : IN t_dp_sosi;
+ from_ri_sosi : IN t_dp_sosi;
+ to_ri_sosi : OUT t_dp_sosi;
+ bf_sum_sosi : OUT t_dp_sosi;
+
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ reg_bsn_align_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_cipo : OUT t_mem_cipo;
+
+ reg_bsn_monitor_v2_bsn_align_input_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_cipo;
+
+ reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_cipo
+ );
+END sdp_beamformer_remote;
+
+ARCHITECTURE str OF sdp_beamformer_remote IS
+
+ CONSTANT c_data_w : NATURAL := c_nof_complex * c_sdp_W_beamlet_sum;
+ CONSTANT c_block_size : NATURAL := c_sdp_S_sub_bf * c_sdp_N_pol_bf;
+ CONSTANT c_fifo_size : NATURAL := 2** ceil_log2((c_block_size * 9) / 16); -- 9/16 = 36/64, 1 block of 64 bit words rounded to the next power of 2 = 1024.
+ CONSTANT c_complex_adder_latency : NATURAL := ceil_log2(c_dual);
+
+ SIGNAL dispatch_sosi_arr : t_dp_sosi_arr(c_dual-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- 1 for local, 1 for remote.
+ SIGNAL dp_fifo_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL dp_fifo_siso : t_dp_siso := c_dp_siso_rdy;
+ SIGNAL beamlets_data_sosi_arr : t_dp_sosi_arr(c_dual-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL beamlets_sosi_arr : t_dp_sosi_arr(c_dual-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL pipelined_beamlets_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL i_bf_sum_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL bf_sum_data_sosi : t_dp_sosi := c_dp_sosi_rst;
+BEGIN
+
+
+ -- repacking beamlets re/im to data field.
+ p_wire_local_bf_sosi : PROCESS(local_bf_sosi)
+ BEGIN
+ dispatch_sosi_arr(0) <= local_bf_sosi;
+ dispatch_sosi_arr(0).data(c_sdp_W_beamlet_sum -1 DOWNTO 0) <= local_bf_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0);
+ dispatch_sosi_arr(0).data(c_data_w -1 DOWNTO c_sdp_W_beamlet_sum) <= local_bf_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0);
+ END PROCESS;
+
+ ---------------------------------------------------------------
+ -- FIFO
+ ---------------------------------------------------------------
+ u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP (
+ g_data_w => c_longword_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_use_bsn => TRUE,
+ g_use_sync => TRUE,
+ g_fifo_size => c_fifo_size
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => from_ri_sosi,
+ src_in => dp_fifo_siso,
+ src_out => dp_fifo_sosi
+ );
+
+ ---------------------------------------------------------------
+ -- Repack 64b to 36b
+ ---------------------------------------------------------------
+ u_dp_repack_data_rx : ENTITY dp_lib.dp_repack_data
+ GENERIC MAP (
+ g_in_dat_w => c_longword_w,
+ g_in_nof_words => 9, -- 9/16 = 36/64
+ g_out_dat_w => c_data_w,
+ g_out_nof_words => 16, -- 9/16 = 36/64
+ g_pipeline_ready => TRUE
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_fifo_sosi,
+ snk_out => dp_fifo_siso,
+ src_out => dispatch_sosi_arr(1)
+ );
+
+ ---------------------------------------------------------------
+ -- dp_bsn_aligner_v2
+ ---------------------------------------------------------------
+ u_mmp_dp_bsn_align_v2 : ENTITY dp_lib.mmp_dp_bsn_align_v2
+ GENERIC MAP(
+ -- for dp_bsn_align_v2
+ g_nof_streams => c_dual,
+ g_bsn_latency_max => 2, -- max 2 blocks latency
+ g_nof_aligners_max => c_sdp_N_pn_max,
+ g_block_size => c_block_size,
+ g_data_w => c_data_w,
+ g_use_mm_output => FALSE,
+ g_rd_latency => 1,
+ -- for mms_dp_bsn_monitor_v2
+ g_nof_clk_per_sync => c_sdp_N_clk_sync_timeout, -- Using c_sdp_N_clk_sync_timeout as g_nof_clk_per_sync is used for BSN monitor timeout.
+ g_nof_input_bsn_monitors => c_dual,
+ g_use_bsn_output_monitor => TRUE
+ )
+ PORT MAP (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_bsn_align_copi => reg_bsn_align_copi,
+ reg_bsn_align_cipo => reg_bsn_align_cipo,
+
+ reg_input_monitor_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
+ reg_input_monitor_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
+
+ reg_output_monitor_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
+ reg_output_monitor_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ node_index => rn_index,
+
+ -- Streaming input
+ in_sosi_arr => dispatch_sosi_arr,
+ out_sosi_arr => beamlets_data_sosi_arr
+ );
+
+ -- repacking beamlets data to re/im field.
+ p_wire_beamlets_sosi : PROCESS(beamlets_data_sosi_arr)
+ BEGIN
+ beamlets_sosi_arr(0) <= beamlets_data_sosi_arr(0);
+ beamlets_sosi_arr(1) <= beamlets_data_sosi_arr(1);
+ beamlets_sosi_arr(0).re <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(0).data(c_sdp_W_beamlet_sum -1 DOWNTO 0));
+ beamlets_sosi_arr(0).im <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(0).data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum));
+ beamlets_sosi_arr(1).re <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(1).data(c_sdp_W_beamlet_sum -1 DOWNTO 0));
+ beamlets_sosi_arr(1).im <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(1).data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum));
+ END PROCESS;
+
+ ---------------------------------------------------------------
+ -- DP PIPELINE IN_SOSI FIELDS
+ ---------------------------------------------------------------
+ u_pipeline : ENTITY dp_lib.dp_pipeline
+ GENERIC MAP (
+ g_pipeline => c_complex_adder_latency
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ snk_in => beamlets_sosi_arr(0),
+ src_out => pipelined_beamlets_sosi
+ );
+
+ ---------------------------------------------------------------
+ -- ADD
+ ---------------------------------------------------------------
+ u_dp_complex_add : ENTITY dp_lib.dp_complex_add
+ GENERIC MAP(
+ g_nof_inputs => c_dual,
+ g_data_w => c_sdp_W_beamlet_sum
+ )
+ PORT MAP(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in_arr => beamlets_sosi_arr,
+ src_out => i_bf_sum_sosi
+ );
+
+ ---------------------------------------------------------------
+ -- Repack 36b to 64b
+ ---------------------------------------------------------------
+ -- repacking bf_sum re/im to data field and combine with pipelined_beamlets_sosi.
+ p_wire_bf_sum_sosi : PROCESS(pipelined_beamlets_sosi, i_bf_sum_sosi)
+ BEGIN
+ bf_sum_data_sosi <= pipelined_beamlets_sosi; -- To preserve sosi control signals as dp_complex_add removes them.
+ bf_sum_sosi <= pipelined_beamlets_sosi; -- To preserve sosi control signals as dp_complex_add removes them.
+ bf_sum_data_sosi.data(c_sdp_W_beamlet_sum -1 DOWNTO 0) <= i_bf_sum_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0);
+ bf_sum_data_sosi.data( c_data_w -1 DOWNTO c_sdp_W_beamlet_sum) <= i_bf_sum_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0);
+ bf_sum_sosi.re <= RESIZE_DP_DSP_DATA(i_bf_sum_sosi.re(c_sdp_W_beamlet_sum-1 DOWNTO 0));
+ bf_sum_sosi.im <= RESIZE_DP_DSP_DATA(i_bf_sum_sosi.im(c_sdp_W_beamlet_sum-1 DOWNTO 0));
+ END PROCESS;
+
+ u_dp_repack_data_local : ENTITY dp_lib.dp_repack_data
+ GENERIC MAP (
+ g_in_dat_w => c_data_w,
+ g_in_nof_words => 16, -- 16/9 = 64/36
+ g_out_dat_w => c_longword_w,
+ g_out_nof_words => 9, -- 16/9 = 64/36
+ g_pipeline_ready => TRUE
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => bf_sum_data_sosi,
+ src_out => to_ri_sosi
+ );
+
+END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index 0b868af821c25a614814cb356f9f93a6fbadeadf..3dec6eb52968ae1f86598a42c32e9e7771852cf2 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -77,30 +77,32 @@ BEGIN
-- [N_pol_bf][S_pn/Q_fft]_[S_sub_bf][Q_fft]. Therefore this counter
-- has to account for this difference in order.
p_cnt : PROCESS(dp_clk, dp_rst)
- VARIABLE v_Q_fft, v_S_sub_bf : NATURAL;
+ -- Use short index variables v_Q, v_BLET names in capitals, to ease
+ -- recognizing them as (loop) indices.
+ VARIABLE v_Q, v_BLET : NATURAL;
BEGIN
IF dp_rst = '1' THEN
cnt <= 0;
- v_Q_fft := 0;
- v_S_sub_bf := 0;
+ v_Q := 0;
+ v_BLET := 0;
ELSIF rising_edge(dp_clk) THEN
IF in_sosi_arr(0).valid = '1' THEN
IF in_sosi_arr(0).eop = '1' THEN
- v_Q_fft := 0;
- v_S_sub_bf := 0;
+ v_Q := 0;
+ v_BLET := 0;
ELSE
- IF v_Q_fft >= c_sdp_Q_fft-1 THEN
- v_Q_fft := 0;
- IF v_S_sub_bf >= c_sdp_S_sub_bf-1 THEN
- v_S_sub_bf := 0;
+ IF v_Q >= c_sdp_Q_fft-1 THEN
+ v_Q := 0;
+ IF v_BLET >= c_sdp_S_sub_bf-1 THEN
+ v_BLET := 0;
ELSE
- v_S_sub_bf := v_S_sub_bf + 1;
+ v_BLET := v_BLET + 1;
END IF;
ELSE
- v_Q_fft := v_Q_fft + 1;
+ v_Q := v_Q + 1;
END IF;
END IF;
- cnt <= v_Q_fft * c_sdp_S_sub_bf + v_S_sub_bf;
+ cnt <= v_Q * c_sdp_S_sub_bf + v_BLET;
END IF;
END IF;
END PROCESS;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 1b4d1753f9c49ad38b28390d1df7906969393848..2cc902a393ad0a179fe76657d4931681ca520549 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -61,7 +61,6 @@ ENTITY sdp_crosslets_subband_select IS
reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
-
);
END sdp_crosslets_subband_select;
@@ -105,6 +104,14 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
SIGNAL crosslets_info_reg : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL crosslets_info_reg_in : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL active_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL i_out_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+
+ -- Map crosslets_info slv to record for easier view in Wave window
+ SIGNAL crosslets_info_rec : t_sdp_crosslets_info;
+ SIGNAL crosslets_info_rec_inout : t_sdp_crosslets_info;
+ SIGNAL active_crosslets_info_rec : t_sdp_crosslets_info;
+ SIGNAL out_crosslets_info_rec : t_sdp_crosslets_info;
+
BEGIN
---------------------------------------------------------------
@@ -152,9 +159,11 @@ BEGIN
in_reg => crosslets_info_reg_in,
out_reg => crosslets_info_reg
);
- p_set_unused_crosslets : PROCESS(crosslets_info_reg)
+
+ p_set_unused_crosslets : PROCESS(i_out_crosslets_info)
BEGIN
- crosslets_info_reg_in <= crosslets_info_reg; -- Always use crosslets info 6:0 + step(@ index 15)
+ -- MM readback the currently active crosslets info, instead of the initial MM written crosslets_info_reg
+ crosslets_info_reg_in <= i_out_crosslets_info; -- Always use crosslets info 6:0 + step(@ index 15)
-- Set crosslets 14:7 to -1
FOR I IN g_N_crosslets TO c_sdp_mm_reg_crosslets_info.nof_dat - 2 LOOP
crosslets_info_reg_in((I+1) * c_sdp_crosslets_index_w - 1 DOWNTO I * c_sdp_crosslets_index_w ) <= TO_SVEC(-1, c_sdp_crosslets_index_w);
@@ -301,7 +310,6 @@ BEGIN
output_sosi_arr(0) => row_sosi
);
-
---------------------------------------------------------------
-- Out Crosslet info pipeline
---------------------------------------------------------------
@@ -309,6 +317,7 @@ BEGIN
gen_crosslets_info : FOR I IN 0 TO g_N_crosslets-1 GENERATE
active_crosslets_info((I+1)*c_sdp_crosslets_index_w-1 DOWNTO I*c_sdp_crosslets_index_w) <= TO_UVEC(r.offsets(I), c_sdp_crosslets_index_w);
END GENERATE;
+
-- pipeline for alignment with sync
u_common_pipeline : ENTITY common_lib.common_pipeline
GENERIC MAP(
@@ -321,9 +330,11 @@ BEGIN
clk => dp_clk,
in_en => row_sosi.sync,
in_dat => active_crosslets_info,
- out_dat => out_crosslets_info
+ out_dat => i_out_crosslets_info
);
+ out_crosslets_info <= i_out_crosslets_info;
+
---------------------------------------------------------------
-- Out sosi pipeline
---------------------------------------------------------------
@@ -340,4 +351,10 @@ BEGIN
src_out => out_sosi
);
+ -- Map crosslets_info slv to record for easier view in Wave window
+ crosslets_info_rec <= func_sdp_map_crosslets_info(crosslets_info_reg);
+ crosslets_info_rec_inout <= func_sdp_map_crosslets_info(crosslets_info_reg_in);
+ active_crosslets_info_rec <= func_sdp_map_crosslets_info(active_crosslets_info);
+ out_crosslets_info_rec <= func_sdp_map_crosslets_info(i_out_crosslets_info);
+
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 554dc4248add36930664d7f767a9554118eba53c..e9e7f6c3ad9dc6ddb43161bb98e7862d677bed61 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -28,8 +28,9 @@
-- . See Document: L3 SDP Decision: SDP Parameter definitions.
-- https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+SDP+Parameter+definitions
-------------------------------------------------------------------------------
-LIBRARY ieee, common_lib, rTwoSDF_lib, fft_lib, filter_lib, wpfb_lib;
+LIBRARY IEEE, common_lib, rTwoSDF_lib, fft_lib, filter_lib, wpfb_lib;
USE IEEE.std_logic_1164.ALL;
+USE IEEE.math_real.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
@@ -77,7 +78,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_N_sub : NATURAL := 512;
CONSTANT c_sdp_N_sync_rcu : NATURAL := 1;
CONSTANT c_sdp_N_taps : NATURAL := 16;
- CONSTANT c_sdp_P_sq : NATURAL := 9;
+ CONSTANT c_sdp_P_sq : NATURAL := 9; -- = N_pn / 2 + 1
CONSTANT c_sdp_Q_fft : NATURAL := 2;
CONSTANT c_sdp_S_pn : NATURAL := 12;
CONSTANT c_sdp_S_rcu : NATURAL := 3;
@@ -115,10 +116,10 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_N_sync_jesd : NATURAL := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
CONSTANT c_sdp_A_pn : NATURAL := c_sdp_S_pn / c_sdp_N_pol; -- = 6 dual pol antenna per PN, is 6 signal input pairs
CONSTANT c_sdp_P_pfb : NATURAL := c_sdp_S_pn / c_sdp_Q_fft; -- = 6 PFB units, for 6 signal input pairs
- CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps;
- CONSTANT c_sdp_T_sub : TIME := c_sdp_N_fft * c_sdp_T_adc;
+ CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps; -- = 5 ns @ 200MHz
+ CONSTANT c_sdp_T_sub : TIME := c_sdp_N_fft * c_sdp_T_adc; -- = 5.12 us @ 200MHz
CONSTANT c_sdp_W_bf_product : NATURAL := c_sdp_W_subband + c_sdp_W_bf_weight -1;
- CONSTANT c_sdp_X_sq : NATURAL := c_sdp_S_pn * c_sdp_S_pn;
+ CONSTANT c_sdp_X_sq : NATURAL := c_sdp_S_pn * c_sdp_S_pn; -- = 144
CONSTANT c_sdp_block_period : NATURAL := c_sdp_N_fft * 1000 / c_sdp_f_adc_MHz; -- = 5120 [ns]
CONSTANT c_sdp_N_beamlets_sdp : NATURAL := c_sdp_N_beamsets * c_sdp_S_sub_bf; -- = 976
CONSTANT c_sdp_unit_sub_weight : NATURAL := 2**c_sdp_W_sub_weight_fraction; -- 2**13, so range +-4.0 for 16 bit signed weight
@@ -138,21 +139,37 @@ PACKAGE sdp_pkg is
--CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
-- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
-- c_sdp_N_taps, 1, c_sdp_W_adc, 16, c_sdp_W_fir_coef,
- -- true, false, true, 16, c_sdp_W_subband, 1, 18, 2,
- -- true, 54, 2, 195313, c_fft_pipeline, c_fft_pipeline,
- -- c_fil_ppf_pipeline);
+ -- true, false, true, 16, c_sdp_W_subband, 1, 18, 2, true, 54, 2, 195313,
+ -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
+
-- LTS 2021-02-03, changes based on results from u_wpfb_stage22 in tb_tb_verify_pfb_wg.vhd:
-- . fil_backoff_w = 0 (was 1)
-- . fil_out_dat_w = fft_in_dat_w = 17 (was 16)
-- . g_fft_out_gain_w = 0 (was 1)
-- . g_fft_stage_dat_w = 22 (was 18)
-- . g_fft_guard_w = 1 (was 2)
+ --CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
+ -- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
+ -- c_sdp_N_taps, 0, c_sdp_W_adc, 17, c_sdp_W_fir_coef,
+ -- true, false, true, 17, c_sdp_W_subband, 0, 22, 1, true, 54, c_sdp_W_statistic_sz, 195313,
+ -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_lts_2021
+
+ -- DTS 2022-04-04, changes based on results from in tb_tb_verify_pfb_wg.vhd:
+ -- . fil_backoff_w = 1
+ -- . fil_out_dat_w = fft_in_dat_w = 0 (use g_fft_stage_dat_w - g_fft_guard_w)
+ -- . g_fft_out_gain_w = 1 (compensate for fil_backoff_w = 1)
+ -- . g_fft_stage_dat_w = 24
+ -- . g_fft_guard_w = 1
CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
(1, c_sdp_N_fft, 0, c_sdp_P_pfb,
- c_sdp_N_taps, 0, c_sdp_W_adc, 17, c_sdp_W_fir_coef,
- true, false, true, 17, c_sdp_W_subband, 0, 22, 1,
- true, 54, c_sdp_W_statistic_sz, 195313, c_fft_pipeline, c_fft_pipeline,
- c_fil_ppf_pipeline);
+ c_sdp_N_taps, 1, c_sdp_W_adc, 23, c_sdp_W_fir_coef,
+ true, false, true, 23, c_sdp_W_subband, 1, 24, 1, true, 54, c_sdp_W_statistic_sz, 195313,
+ c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- = c_wpfb_lofar2_subbands_dts_18b
+
+ -- DC gain of WPFB FIR filter obtained from applications/lofar2/model/run_pfir_coef.m using application = 'lofar_subband'
+ -- Not used in RTL, only used in test benches to verify expected suband levels
+ CONSTANT c_sdp_wpfb_fir_filter_dc_gain : REAL := c_fil_lofar1_fir_filter_dc_gain; -- = 0.994817, almost unit DC gain
+ CONSTANT c_sdp_wpfb_subband_sp_ampl_ratio : REAL := func_wpfb_subband_gain(c_sdp_wpfb_subbands, c_sdp_wpfb_fir_filter_dc_gain);
-----------------------------------------------------------------------------
-- Statistics offload
@@ -224,7 +241,7 @@ PACKAGE sdp_pkg is
( field_name_pad("sdp_source_info_fsub_type" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_payload_error" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_beam_repositioning_flag" ), "RW", 1, field_default(0) ),
- ( field_name_pad("sdp_source_info_subband_calibrated_flag" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("sdp_source_info_weighted_subbands_flag" ), "RW", 1, field_default(0) ),
( field_name_pad("sdp_source_info_reserved" ), "RW", 3, field_default(0) ),
( field_name_pad("sdp_source_info_gn_id" ), "RW", 5, field_default(0) ),
@@ -252,7 +269,7 @@ PACKAGE sdp_pkg is
sdp_source_info_fsub_type : STD_LOGIC_VECTOR( 0 DOWNTO 0);
sdp_source_info_payload_error : STD_LOGIC_VECTOR( 0 DOWNTO 0);
sdp_source_info_beam_repositioning_flag : STD_LOGIC_VECTOR( 0 DOWNTO 0);
- sdp_source_info_subband_calibrated_flag : STD_LOGIC_VECTOR( 0 DOWNTO 0);
+ sdp_source_info_weighted_subbands_flag : STD_LOGIC_VECTOR( 0 DOWNTO 0);
sdp_source_info_reserved : STD_LOGIC_VECTOR( 2 DOWNTO 0);
sdp_source_info_gn_id : STD_LOGIC_VECTOR( 4 DOWNTO 0);
@@ -394,7 +411,10 @@ PACKAGE sdp_pkg is
-----------------------------------------------------------------------------
-- MM
-----------------------------------------------------------------------------
-
+ -- BSN monitor V2 address width
+ CONSTANT c_sdp_reg_bsn_monitor_v2_addr_w : NATURAL := ceil_Log2(7);
+ -- BSN align address width
+ CONSTANT c_sdp_reg_bsn_align_v2_addr_w : NATURAL := ceil_log2(2);
-- 10GbE MM address widths
CONSTANT c_sdp_reg_bf_hdr_dat_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_cep_hdr_dat_addr_w;
CONSTANT c_sdp_reg_nw_10GbE_mac_addr_w : NATURAL := 13;
@@ -423,24 +443,35 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_aduh_monitor_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 2;
-- FSUB MM address widths
- CONSTANT c_sdp_ram_fil_coefs_addr_w : NATURAL := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
- CONSTANT c_sdp_ram_st_sst_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz);
- CONSTANT c_sdp_reg_si_addr_w : NATURAL := 1; --enable/disable
- CONSTANT c_sdp_ram_equalizer_gains_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb*c_sdp_N_sub*c_sdp_Q_fft);
- CONSTANT c_sdp_reg_dp_selector_addr_w : NATURAL := 1; --Select input 0 or 1.
+ CONSTANT c_sdp_ram_fil_coefs_addr_w : NATURAL := ceil_log2(c_sdp_N_fft * c_sdp_N_taps);
+ CONSTANT c_sdp_ram_st_sst_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_N_sub * c_sdp_Q_fft * c_sdp_W_statistic_sz);
+ CONSTANT c_sdp_reg_si_addr_w : NATURAL := 1; --enable/disable
+ CONSTANT c_sdp_ram_equalizer_gains_addr_w : NATURAL := ceil_log2(c_sdp_P_pfb*c_sdp_N_sub*c_sdp_Q_fft);
+ CONSTANT c_sdp_reg_dp_selector_addr_w : NATURAL := 1; --Select input 0 or 1.
+ CONSTANT c_sdp_reg_bsn_monitor_v2_sst_offload_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
-- STAT UDP offload MM address widths
CONSTANT c_sdp_reg_stat_enable_addr_w : NATURAL := 1;
-- BF MM address widths
- CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
- CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
- CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_sdp_W_statistic_sz);
- CONSTANT c_sdp_reg_stat_enable_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
- CONSTANT c_sdp_reg_stat_hdr_dat_bst_addr_w: NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
+ CONSTANT c_sdp_reg_sdp_info_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pol_bf * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_sdp_reg_bf_scale_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_reg_dp_xonoff_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_ram_st_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol_bf * c_sdp_W_statistic_sz);
+ CONSTANT c_sdp_reg_stat_enable_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_enable_addr_w;
+ CONSTANT c_sdp_reg_stat_hdr_dat_bst_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_stat_hdr_dat_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_bst_offload_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_beamlet_output_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_align_v2_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_dual) + c_sdp_reg_bsn_align_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_rx_align_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_dual) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_aligned_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_ring_lane_info_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 1;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_dp_block_validate_err_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 4;
+ CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_bf_addr_w : NATURAL := ceil_log2(c_sdp_N_beamsets) + 2;
-- XSUB
CONSTANT c_sdp_crosslets_index_w : NATURAL := ceil_log2(c_sdp_N_sub);
@@ -467,25 +498,25 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_xst_nof_clk_per_sync_min : NATURAL := c_sdp_N_clk_per_sync / 10; -- 0.1 second
-- XSUB MM address widths
- CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
- CONSTANT c_sdp_reg_nof_crosslets_addr_w : NATURAL := c_sdp_mm_reg_nof_crosslets.adr_w;
- CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
- CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz);
- CONSTANT c_sdp_ram_st_xsq_arr_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_ram_st_xsq_addr_w;
- CONSTANT c_sdp_reg_bsn_align_v2_addr_w : NATURAL := ceil_log2(2*c_sdp_P_sq);
- CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_input_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_Log2(7);
- CONSTANT c_sdp_reg_bsn_monitor_v2_bsn_align_v2_output_addr_w : NATURAL := ceil_Log2(7);
- CONSTANT c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w : NATURAL := ceil_Log2(7);
- CONSTANT c_sdp_reg_ring_lane_info_xst_addr_w : NATURAL := 1;
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
- CONSTANT c_sdp_reg_dp_block_validate_err_xst_addr_w : NATURAL := 4;
- CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w : NATURAL := 2;
+ CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
+ CONSTANT c_sdp_reg_nof_crosslets_addr_w : NATURAL := c_sdp_mm_reg_nof_crosslets.adr_w;
+ CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_N_crosslets_max * c_sdp_X_sq * c_nof_complex * c_sdp_W_statistic_sz);
+ CONSTANT c_sdp_ram_st_xsq_arr_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_ram_st_xsq_addr_w;
+ CONSTANT c_sdp_reg_bsn_align_v2_xsub_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_align_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_rx_align_xsub_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_aligned_xsub_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_xst_offload_addr_w : NATURAL := c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_ring_lane_info_xst_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_xst_addr_w : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_dp_block_validate_err_xst_addr_w : NATURAL := 4;
+ CONSTANT c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w : NATURAL := 2;
-- RING MM address widths
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
- CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + ceil_Log2(7);
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
CONSTANT c_sdp_reg_ring_lane_info_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
CONSTANT c_sdp_reg_dp_xonoff_lane_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
CONSTANT c_sdp_reg_dp_xonoff_local_addr_w : NATURAL := ceil_log2(c_sdp_N_ring_lanes_max) + 1;
@@ -719,7 +750,7 @@ PACKAGE BODY sdp_pkg IS
v.app.sdp_source_info_fsub_type := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type"));
v.app.sdp_source_info_payload_error := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error"));
v.app.sdp_source_info_beam_repositioning_flag := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag"));
- v.app.sdp_source_info_subband_calibrated_flag := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag"));
+ v.app.sdp_source_info_weighted_subbands_flag := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_weighted_subbands_flag") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_weighted_subbands_flag"));
v.app.sdp_source_info_reserved := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_reserved") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_reserved"));
v.app.sdp_source_info_gn_id := hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id"));
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index 36ab5c31f894559bb67b51e2e29f1c5e8afdc804..3c2752619b4bd714de592fc2be94539d9c2c003e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -50,6 +50,7 @@ ENTITY sdp_station IS
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
g_bsn_nof_clk_per_sync : NATURAL := c_sdp_N_clk_per_sync; -- Default 200M, overide for short simulation
g_scope_selected_subband : NATURAL := 0;
+ g_no_jesd : BOOLEAN := FALSE;
g_use_fsub : BOOLEAN := TRUE;
g_use_xsub : BOOLEAN := TRUE;
g_use_bf : BOOLEAN := TRUE;
@@ -92,215 +93,255 @@ ENTITY sdp_station IS
----------------------------------------------
-- 10 GbE
----------------------------------------------
- reg_nw_10GbE_mac_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_nw_10GbE_mac_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_nw_10GbE_mac_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_nw_10GbE_mac_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
- reg_nw_10GbE_eth10g_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_nw_10GbE_eth10g_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_nw_10GbE_eth10g_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_nw_10GbE_eth10g_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- AIT
----------------------------------------------
-- JESD
- jesd204b_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- jesd204b_miso : OUT t_mem_miso := c_mem_miso_rst;
+ jesd204b_copi : IN t_mem_copi := c_mem_copi_rst;
+ jesd204b_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- JESD control
- jesd_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- jesd_ctrl_miso : OUT t_mem_miso := c_mem_miso_rst;
+ jesd_ctrl_copi : IN t_mem_copi := c_mem_copi_rst;
+ jesd_ctrl_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Shiftram (applies per-antenna delay)
- reg_dp_shiftram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_shiftram_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_dp_shiftram_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_shiftram_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- bsn source
- reg_bsn_source_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_source_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_source_v2_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_source_v2_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- bsn scheduler
- reg_bsn_scheduler_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_scheduler_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_scheduler_wg_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_scheduler_wg_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- WG
- reg_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
- ram_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_wg_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_wg_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_wg_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ ram_wg_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_wg_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- BSN MONITOR
- reg_bsn_monitor_input_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_monitor_input_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_monitor_input_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_input_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Data buffer bsn
- ram_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
- reg_diag_data_buf_bsn_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_diag_data_buf_bsn_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_diag_data_buf_bsn_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_diag_data_buf_bsn_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ reg_diag_data_buf_bsn_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_diag_data_buf_bsn_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- ST Histogram
- ram_st_histogram_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_histogram_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_histogram_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_st_histogram_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Aduh statistics monitor
- reg_aduh_monitor_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_aduh_monitor_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_aduh_monitor_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_aduh_monitor_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- FSUB
----------------------------------------------
-- Subband statistics
- ram_st_sst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_sst_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_sst_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_st_sst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Spectral Inversion
- reg_si_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_si_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_si_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_si_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Filter coefficients
- ram_fil_coefs_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_fil_coefs_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_fil_coefs_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_fil_coefs_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Equalizer gains
- ram_equalizer_gains_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_equalizer_gains_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_equalizer_gains_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_equalizer_gains_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- DP Selector
- reg_dp_selector_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_selector_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_dp_selector_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_selector_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ -- SST UDP offload bsn monitor
+ reg_bsn_monitor_v2_sst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_sst_offload_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SDP Info
----------------------------------------------
- reg_sdp_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_sdp_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_sdp_info_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_sdp_info_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- RING Info
----------------------------------------------
- reg_ring_info_copi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_ring_info_cipo : OUT t_mem_miso := c_mem_miso_rst;
+ reg_ring_info_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_ring_info_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- XSUB
----------------------------------------------
-- crosslets_info
- reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_crosslets_info_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_crosslets_info_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- nof_crosslets
- reg_nof_crosslets_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_nof_crosslets_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_nof_crosslets_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_nof_crosslets_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- bsn_scheduler_xsub
- reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_sync_scheduler_xsub_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_sync_scheduler_xsub_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- st_xsq
- ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_xsq_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_xsq_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_st_xsq_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- BF
----------------------------------------------
-- Beamlet Subband Select
- ram_ss_ss_wide_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_ss_ss_wide_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_ss_ss_wide_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_ss_ss_wide_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Local BF bf weights
- ram_bf_weights_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_bf_weights_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_bf_weights_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_bf_weights_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF bsn aligner_v2
+ reg_bsn_align_v2_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_v2_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF bsn aligner_v2 bsn monitors
+ reg_bsn_monitor_v2_rx_align_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_rx_align_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ reg_bsn_monitor_v2_aligned_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_aligned_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- mms_dp_scale Scale Beamlets
- reg_bf_scale_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bf_scale_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bf_scale_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bf_scale_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output header fields
- reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_hdr_dat_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_hdr_dat_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Data Output xonoff
- reg_dp_xonoff_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_xonoff_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_dp_xonoff_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_xonoff_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Beamlet Statistics (BST)
- ram_st_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- ram_st_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+ ram_st_bst_copi : IN t_mem_copi := c_mem_copi_rst;
+ ram_st_bst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_bst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_bst_offload_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BST UDP offload bsn monitor
+ reg_bsn_monitor_v2_beamlet_output_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_beamlet_output_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring lane info
+ reg_ring_lane_info_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_ring_lane_info_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor rx
+ reg_bsn_monitor_v2_ring_rx_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_rx_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring bsn monitor tx
+ reg_bsn_monitor_v2_ring_tx_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_tx_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+
+ -- BF ring validate err
+ reg_dp_block_validate_err_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_block_validate_err_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ -- BF ring bsn at sync
+ reg_dp_block_validate_bsn_at_sync_bf_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_block_validate_bsn_at_sync_bf_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- SST
----------------------------------------------
-- Statistics Enable
- reg_stat_enable_sst_mosi : IN t_mem_mosi;
- reg_stat_enable_sst_miso : OUT t_mem_miso;
+ reg_stat_enable_sst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_enable_sst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- reg_stat_hdr_dat_sst_mosi : IN t_mem_mosi;
- reg_stat_hdr_dat_sst_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_sst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_hdr_dat_sst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- XST
----------------------------------------------
-- Statistics Enable
- reg_stat_enable_xst_mosi : IN t_mem_mosi;
- reg_stat_enable_xst_miso : OUT t_mem_miso;
+ reg_stat_enable_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_enable_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- reg_stat_hdr_dat_xst_mosi : IN t_mem_mosi;
- reg_stat_hdr_dat_xst_miso : OUT t_mem_miso;
+ reg_stat_hdr_dat_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_hdr_dat_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST bsn aligner_v2
- reg_bsn_align_copi : IN t_mem_mosi;
- reg_bsn_align_cipo : OUT t_mem_miso;
+ reg_bsn_align_v2_xsub_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_align_v2_xsub_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST bsn aligner_v2 bsn monitors
- reg_bsn_monitor_v2_bsn_align_input_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_input_cipo : OUT t_mem_miso;
- reg_bsn_monitor_v2_bsn_align_output_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_bsn_align_output_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_rx_align_xsub_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_rx_align_xsub_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
+ reg_bsn_monitor_v2_aligned_xsub_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_aligned_xsub_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST UDP offload bsn monitor
- reg_xst_udp_monitor_copi : IN t_mem_mosi;
- reg_xst_udp_monitor_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_xst_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_xst_offload_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring lane info
- reg_ring_lane_info_xst_copi : IN t_mem_mosi;
- reg_ring_lane_info_xst_cipo : OUT t_mem_miso;
+ reg_ring_lane_info_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_ring_lane_info_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring bsn monitor rx
- reg_bsn_monitor_v2_ring_rx_xst_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_ring_rx_xst_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_ring_rx_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_rx_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring bsn monitor tx
- reg_bsn_monitor_v2_ring_tx_xst_copi : IN t_mem_mosi;
- reg_bsn_monitor_v2_ring_tx_xst_cipo : OUT t_mem_miso;
+ reg_bsn_monitor_v2_ring_tx_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_ring_tx_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring validate err
- reg_dp_block_validate_err_xst_copi : IN t_mem_mosi;
- reg_dp_block_validate_err_xst_cipo : OUT t_mem_miso;
+ reg_dp_block_validate_err_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_block_validate_err_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring bsn at sync
- reg_dp_block_validate_bsn_at_sync_xst_copi : IN t_mem_mosi;
- reg_dp_block_validate_bsn_at_sync_xst_cipo : OUT t_mem_miso;
+ reg_dp_block_validate_bsn_at_sync_xst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_dp_block_validate_bsn_at_sync_xst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring MAC
- reg_tr_10GbE_mac_copi : IN t_mem_mosi;
- reg_tr_10GbE_mac_cipo : OUT t_mem_miso;
+ reg_tr_10GbE_mac_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_tr_10GbE_mac_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- XST ring ETH
- reg_tr_10GbE_eth10g_copi : IN t_mem_mosi;
- reg_tr_10GbE_eth10g_cipo : OUT t_mem_miso;
+ reg_tr_10GbE_eth10g_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_tr_10GbE_eth10g_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
----------------------------------------------
-- BST
----------------------------------------------
-- Statistics Enable
- reg_stat_enable_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_enable_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_stat_enable_bst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_enable_bst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- Statistics header info
- reg_stat_hdr_dat_bst_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_stat_hdr_dat_bst_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_stat_hdr_dat_bst_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_stat_hdr_dat_bst_cipo : OUT t_mem_cipo := c_mem_cipo_rst;
-- RING_0 serial
RING_0_TX: OUT STD_LOGIC_VECTOR( c_quad - 1 DOWNTO 0) := (OTHERS => '0');
@@ -333,33 +374,40 @@ ARCHITECTURE str OF sdp_station IS
CONSTANT c_fifo_tx_size : NATURAL := c_fifo_tx_fill + 11; -- Make fifo size large enough for adding header.
-- Address widths of a single MM instance
- CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
- CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
- CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
- CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
- CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
-
+ CONSTANT c_addr_w_ram_ss_ss_wide : NATURAL := ceil_log2(c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_ram_bf_weights : NATURAL := ceil_log2(c_sdp_N_pol * c_sdp_P_pfb * c_sdp_S_sub_bf * c_sdp_Q_fft);
+ CONSTANT c_addr_w_reg_bf_scale : NATURAL := 1;
+ CONSTANT c_addr_w_reg_hdr_dat : NATURAL := ceil_log2(field_nof_words(c_sdp_cep_hdr_field_arr, c_word_w));
+ CONSTANT c_addr_w_reg_dp_xonoff : NATURAL := 1;
+ CONSTANT c_addr_w_ram_st_bst : NATURAL := ceil_log2(c_sdp_S_sub_bf*c_sdp_N_pol*(c_longword_sz/c_word_sz));
+ CONSTANT c_addr_w_reg_bsn_align_v2_bf : NATURAL := ceil_log2(c_dual) + c_sdp_reg_bsn_align_v2_addr_w;
+ CONSTANT c_addr_w_reg_bsn_monitor_v2_rx_align_bf : NATURAL := ceil_log2(c_dual) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_rx_bf : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_addr_w_reg_bsn_monitor_v2_ring_tx_bf : NATURAL := ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
+ CONSTANT c_addr_w_reg_ring_lane_info_bf : NATURAL := 1;
+
-- Read only sdp_info values
CONSTANT c_f_adc : STD_LOGIC := '1'; -- '0' => 160M, '1' => 200M
CONSTANT c_fsub_type : STD_LOGIC := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
CONSTANT c_use_dp_layer : BOOLEAN := TRUE;
- CONSTANT c_lane_packet_length : NATURAL := c_sdp_N_crosslets_max * c_sdp_S_pn / 2; -- = crosslet subband select block size devided by 2 as it is repacked from 32b to 64b.
+ CONSTANT c_lane_packet_length_xst : NATURAL := c_sdp_N_crosslets_max * c_sdp_S_pn / 2; -- = crosslet subband select block size devided by 2 as it is repacked from 32b to 64b. = 42 words
+ CONSTANT c_lane_packet_length_bf : NATURAL := (c_sdp_S_sub_bf * c_sdp_N_pol_bf * 9) / 16; -- = beamlet block size repacked from 36b to 64b (9/16 = 36/64). = 549 words
CONSTANT c_err_bi : NATURAL := 0;
CONSTANT c_nof_err_counts : NATURAL := 8;
CONSTANT c_bsn_at_sync_check_channel : NATURAL := 1;
CONSTANT c_validate_channel : BOOLEAN := TRUE;
CONSTANT c_validate_channel_mode : STRING := "=";
CONSTANT c_sync_timeout : NATURAL := sel_a_b(g_sim, g_sim_sync_timeout, c_sdp_N_clk_sync_timeout );
- CONSTANT c_xsub_fifo_tx_fill : NATURAL := c_lane_packet_length + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); --total packet length
- CONSTANT c_xsub_fifo_tx_size : NATURAL := 2 * c_lane_packet_length;
+ CONSTANT c_xsub_fifo_tx_fill : NATURAL := c_lane_packet_length_bf + sel_a_b(c_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size); --total max packet length (bf has largest packets)
+ CONSTANT c_xsub_fifo_tx_size : NATURAL := 2 * c_lane_packet_length_bf;
+ CONSTANT c_nof_lane : NATURAL := 3; -- 0 = XST, 1 = BF_0, 2 = BF_1.
CONSTANT c_nof_if : NATURAL := 3; -- 3 different interfaces, QSFP, RING_0 and RING_1
CONSTANT c_qsfp_if_offset : NATURAL := 0; -- QSFP signals are indexed at c_nof_if * I.
CONSTANT c_ring_0_if_offset : NATURAL := 1; -- RING_0 signals are indexed at c_nof_if * I + 1.
CONSTANT c_ring_1_if_offset : NATURAL := 2; -- RING_1 signals are indexed at c_nof_if * I + 2.
- CONSTANT c_nof_mac : NATURAL := 3; -- must match one of the MAC IP variations, e.g. 1, 3, 4, 12, 24, 48
+ CONSTANT c_nof_mac : NATURAL := 12; -- Using 9 out of 12 (this is NOT optimized away during synthesis), must match one of the MAC IP variations, e.g. 1, 3, 4, 12, 24, 48
SIGNAL gn_index : NATURAL := 0;
SIGNAL this_rn : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
@@ -367,52 +415,93 @@ ARCHITECTURE str OF sdp_station IS
-- BF
----------------------------------------------
-- Beamlet Subband Select
- SIGNAL ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_ss_ss_wide_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL ram_ss_ss_wide_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL ram_ss_ss_wide_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Local BF bf weights
- SIGNAL ram_bf_weights_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_bf_weights_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL ram_bf_weights_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL ram_bf_weights_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- mms_dp_scale Scale Beamlets
- SIGNAL reg_bf_scale_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_bf_scale_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_bf_scale_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bf_scale_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Beamlet Data Output header fields
- SIGNAL reg_hdr_dat_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_hdr_dat_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_hdr_dat_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_hdr_dat_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Beamlet Data Output xonoff
- SIGNAL reg_dp_xonoff_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_dp_xonoff_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_dp_xonoff_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_dp_xonoff_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Beamlet Statistics (BST)
- SIGNAL ram_st_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL ram_st_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL ram_st_bst_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL ram_st_bst_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF bsn align v2
+ SIGNAL reg_bsn_align_v2_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_align_v2_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF bsn monitor v2 rx align
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_rx_align_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF bsn monitor v2 aligned
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_aligned_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring lane info
+ SIGNAL reg_ring_lane_info_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_ring_lane_info_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring bsn monitor rx
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_ring_rx_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring bsn monitor tx
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_ring_tx_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring validate err
+ SIGNAL reg_dp_block_validate_err_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_dp_block_validate_err_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ -- BF ring bsn at sync
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_dp_block_validate_bsn_at_sync_bf_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
----------------------------------------------
-- BST
----------------------------------------------
-- Statistics Enable
- SIGNAL reg_stat_enable_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_stat_enable_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_stat_enable_bst_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_stat_enable_bst_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
-- Statistics header info
- SIGNAL reg_stat_hdr_dat_bst_mosi_arr : t_mem_mosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
- SIGNAL reg_stat_hdr_dat_bst_miso_arr : t_mem_miso_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
+ SIGNAL reg_stat_hdr_dat_bst_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_stat_hdr_dat_bst_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ SIGNAL reg_bsn_monitor_v2_bst_offload_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_bst_offload_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
+ SIGNAL reg_bsn_monitor_v2_beamlet_output_copi_arr : t_mem_copi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_copi_rst);
+ SIGNAL reg_bsn_monitor_v2_beamlet_output_cipo_arr : t_mem_cipo_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_mem_cipo_rst);
+
----------------------------------------------
SIGNAL ait_sosi_arr : t_dp_sosi_arr(c_sdp_S_pn-1 DOWNTO 0);
- SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
- SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
+ SIGNAL pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0); -- raw subbands
+ SIGNAL fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0); -- weighted subbands
SIGNAL bs_sosi : t_dp_sosi;
- SIGNAL xst_from_ri_sosi : t_dp_sosi;
- SIGNAL xst_to_ri_sosi : t_dp_sosi;
- SIGNAL lane_rx_cable_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
- SIGNAL lane_tx_cable_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
- SIGNAL lane_rx_board_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
- SIGNAL lane_tx_board_sosi_arr : t_dp_sosi_arr(2 DOWNTO 0); -- 3 as, a total of 3 lanes will be used.
+ SIGNAL xst_from_ri_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL xst_to_ri_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL bf_from_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL bf_to_ri_sosi_arr : t_dp_sosi_arr(c_sdp_N_beamsets-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL lane_rx_cable_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
+ SIGNAL lane_tx_cable_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
+ SIGNAL lane_rx_board_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
+ SIGNAL lane_tx_board_sosi_arr : t_dp_sosi_arr(c_nof_lane-1 DOWNTO 0);
SIGNAL dp_bsn_source_restart : STD_LOGIC;
@@ -479,8 +568,8 @@ BEGIN
dp_clk => dp_clk,
dp_rst => dp_rst,
- reg_mosi => reg_sdp_info_mosi,
- reg_miso => reg_sdp_info_miso,
+ reg_mosi => reg_sdp_info_copi,
+ reg_miso => reg_sdp_info_cipo,
-- inputs from other blocks
gn_index => gn_index,
@@ -518,6 +607,7 @@ BEGIN
GENERIC MAP(
g_technology => g_technology,
g_sim => g_sim,
+ g_no_jesd => g_no_jesd,
g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
)
PORT MAP(
@@ -525,33 +615,34 @@ BEGIN
mm_clk => mm_clk,
mm_rst => mm_rst,
dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_rst => dp_rst,
+ dp_pps => dp_pps,
-- mm control buses
- jesd_ctrl_mosi => jesd_ctrl_mosi,
- jesd_ctrl_miso => jesd_ctrl_miso,
- jesd204b_mosi => jesd204b_mosi,
- jesd204b_miso => jesd204b_miso,
- reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
- reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
- reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
- reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
- reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
- reg_wg_mosi => reg_wg_mosi,
- reg_wg_miso => reg_wg_miso,
- ram_wg_mosi => ram_wg_mosi,
- ram_wg_miso => ram_wg_miso,
- reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
- reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
- ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_mosi,
- ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_miso,
- reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_mosi,
- reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_miso,
- ram_st_histogram_mosi => ram_st_histogram_mosi,
- ram_st_histogram_miso => ram_st_histogram_miso,
- reg_aduh_monitor_mosi => reg_aduh_monitor_mosi,
- reg_aduh_monitor_miso => reg_aduh_monitor_miso,
+ jesd_ctrl_mosi => jesd_ctrl_copi,
+ jesd_ctrl_miso => jesd_ctrl_cipo,
+ jesd204b_mosi => jesd204b_copi,
+ jesd204b_miso => jesd204b_cipo,
+ reg_dp_shiftram_mosi => reg_dp_shiftram_copi,
+ reg_dp_shiftram_miso => reg_dp_shiftram_cipo,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_copi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_cipo,
+ reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_copi,
+ reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_cipo,
+ reg_wg_mosi => reg_wg_copi,
+ reg_wg_miso => reg_wg_cipo,
+ ram_wg_mosi => ram_wg_copi,
+ ram_wg_miso => ram_wg_cipo,
+ reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_copi,
+ reg_bsn_monitor_input_miso => reg_bsn_monitor_input_cipo,
+ ram_diag_data_buf_bsn_mosi => ram_diag_data_buf_bsn_copi,
+ ram_diag_data_buf_bsn_miso => ram_diag_data_buf_bsn_cipo,
+ reg_diag_data_buf_bsn_mosi => reg_diag_data_buf_bsn_copi,
+ reg_diag_data_buf_bsn_miso => reg_diag_data_buf_bsn_cipo,
+ ram_st_histogram_mosi => ram_st_histogram_copi,
+ ram_st_histogram_miso => ram_st_histogram_cipo,
+ reg_aduh_monitor_mosi => reg_aduh_monitor_copi,
+ reg_aduh_monitor_miso => reg_aduh_monitor_cipo,
-- Jesd external IOs
jesd204b_serial_data => JESD204B_SERIAL_DATA,
@@ -576,41 +667,44 @@ BEGIN
g_scope_selected_subband => g_scope_selected_subband
)
PORT MAP(
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- in_sosi_arr => ait_sosi_arr,
- pfb_sosi_arr => pfb_sosi_arr,
- fsub_sosi_arr => fsub_sosi_arr,
- dp_bsn_source_restart => dp_bsn_source_restart,
-
- sst_udp_sosi => udp_tx_sosi_arr(0),
- sst_udp_siso => udp_tx_siso_arr(0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_si_mosi => reg_si_mosi,
- reg_si_miso => reg_si_miso,
- ram_st_sst_mosi => ram_st_sst_mosi,
- ram_st_sst_miso => ram_st_sst_miso,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_gains_mosi => ram_equalizer_gains_mosi,
- ram_gains_miso => ram_equalizer_gains_miso,
- reg_selector_mosi => reg_dp_selector_mosi,
- reg_selector_miso => reg_dp_selector_miso,
-
- reg_enable_mosi => reg_stat_enable_sst_mosi,
- reg_enable_miso => reg_stat_enable_sst_miso,
- reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_mosi,
- reg_hdr_dat_miso => reg_stat_hdr_dat_sst_miso,
-
- sdp_info => sdp_info,
- gn_id => gn_id,
- eth_src_mac => stat_eth_src_mac,
- ip_src_addr => stat_ip_src_addr,
- udp_src_port => sst_udp_src_port
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ in_sosi_arr => ait_sosi_arr,
+ pfb_sosi_arr => pfb_sosi_arr,
+ fsub_sosi_arr => fsub_sosi_arr,
+ dp_bsn_source_restart => dp_bsn_source_restart,
+
+ sst_udp_sosi => udp_tx_sosi_arr(0),
+ sst_udp_siso => udp_tx_siso_arr(0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_si_mosi => reg_si_copi,
+ reg_si_miso => reg_si_cipo,
+ ram_st_sst_mosi => ram_st_sst_copi,
+ ram_st_sst_miso => ram_st_sst_cipo,
+ ram_fil_coefs_mosi => ram_fil_coefs_copi,
+ ram_fil_coefs_miso => ram_fil_coefs_cipo,
+ ram_gains_mosi => ram_equalizer_gains_copi,
+ ram_gains_miso => ram_equalizer_gains_cipo,
+ reg_selector_mosi => reg_dp_selector_copi,
+ reg_selector_miso => reg_dp_selector_cipo,
+
+ reg_enable_mosi => reg_stat_enable_sst_copi,
+ reg_enable_miso => reg_stat_enable_sst_cipo,
+ reg_hdr_dat_mosi => reg_stat_hdr_dat_sst_copi,
+ reg_hdr_dat_miso => reg_stat_hdr_dat_sst_cipo,
+
+ reg_bsn_monitor_v2_sst_offload_copi => reg_bsn_monitor_v2_sst_offload_copi,
+ reg_bsn_monitor_v2_sst_offload_cipo => reg_bsn_monitor_v2_sst_offload_cipo,
+
+ sdp_info => sdp_info,
+ gn_id => gn_id,
+ eth_src_mac => stat_eth_src_mac,
+ ip_src_addr => stat_ip_src_addr,
+ udp_src_port => sst_udp_src_port
);
END GENERATE;
@@ -642,28 +736,28 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- reg_crosslets_info_copi => reg_crosslets_info_mosi,
- reg_crosslets_info_cipo => reg_crosslets_info_miso,
- reg_nof_crosslets_copi => reg_nof_crosslets_mosi,
- reg_nof_crosslets_cipo => reg_nof_crosslets_miso,
- reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_mosi,
- reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_miso,
- ram_st_xsq_copi => ram_st_xsq_mosi,
- ram_st_xsq_cipo => ram_st_xsq_miso,
-
- reg_stat_enable_copi => reg_stat_enable_xst_mosi,
- reg_stat_enable_cipo => reg_stat_enable_xst_miso,
- reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_mosi,
- reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_miso,
-
- reg_bsn_align_copi => reg_bsn_align_copi,
- reg_bsn_align_cipo => reg_bsn_align_cipo,
- reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_bsn_align_input_copi,
- reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_bsn_align_input_cipo,
- reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_bsn_align_output_copi,
- reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_bsn_align_output_cipo,
- reg_xst_udp_monitor_copi => reg_xst_udp_monitor_copi,
- reg_xst_udp_monitor_cipo => reg_xst_udp_monitor_cipo,
+ reg_crosslets_info_copi => reg_crosslets_info_copi,
+ reg_crosslets_info_cipo => reg_crosslets_info_cipo,
+ reg_nof_crosslets_copi => reg_nof_crosslets_copi,
+ reg_nof_crosslets_cipo => reg_nof_crosslets_cipo,
+ reg_bsn_sync_scheduler_xsub_copi => reg_bsn_sync_scheduler_xsub_copi,
+ reg_bsn_sync_scheduler_xsub_cipo => reg_bsn_sync_scheduler_xsub_cipo,
+ ram_st_xsq_copi => ram_st_xsq_copi,
+ ram_st_xsq_cipo => ram_st_xsq_cipo,
+
+ reg_stat_enable_copi => reg_stat_enable_xst_copi,
+ reg_stat_enable_cipo => reg_stat_enable_xst_cipo,
+ reg_stat_hdr_dat_copi => reg_stat_hdr_dat_xst_copi,
+ reg_stat_hdr_dat_cipo => reg_stat_hdr_dat_xst_cipo,
+
+ reg_bsn_align_copi => reg_bsn_align_v2_xsub_copi,
+ reg_bsn_align_cipo => reg_bsn_align_v2_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_xsub_cipo,
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_xsub_copi,
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_xsub_cipo,
+ reg_bsn_monitor_v2_xst_offload_copi => reg_bsn_monitor_v2_xst_offload_copi,
+ reg_bsn_monitor_v2_xst_offload_cipo => reg_bsn_monitor_v2_xst_offload_cipo,
sdp_info => sdp_info,
ring_info => ring_info,
@@ -673,132 +767,6 @@ BEGIN
stat_udp_src_port => xst_udp_src_port
);
- gen_use_xsub_ring : IF g_use_ring GENERATE
- u_ring_lane_xst : ENTITY ring_lib.ring_lane
- GENERIC MAP (
- g_lane_direction => 1, -- transport in positive direction.
- g_lane_data_w => c_longword_w,
- g_lane_packet_length => c_lane_packet_length,
- g_use_dp_layer => c_use_dp_layer,
- g_nof_rx_monitors => c_sdp_N_pn_max,
- g_nof_tx_monitors => c_sdp_N_pn_max,
- g_err_bi => c_err_bi,
- g_nof_err_counts => c_nof_err_counts,
- g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
- g_validate_channel => c_validate_channel,
- g_validate_channel_mode => c_validate_channel_mode,
- g_sync_timeout => c_sync_timeout
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
- from_lane_sosi => xst_from_ri_sosi,
- to_lane_sosi => xst_to_ri_sosi,
- lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
- lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
- lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
- lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
- bs_sosi => bs_sosi,
-
- reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
- reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
- reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
- reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
- reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
- reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
- reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
- reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
- reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
- reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
-
- this_rn => this_rn,
- N_rn => ring_info.N_rn,
- rx_select => ring_info.use_cable_to_previous_rn,
- tx_select => ring_info.use_cable_to_next_rn
- );
-
- -----------------------------------------------------------------------------
- -- Combine seperate signals into array for tr_10GbE
- -----------------------------------------------------------------------------
- -- QSFP_RX
- lane_rx_cable_sosi_arr(0) <= tr_10gbe_src_out_arr(c_qsfp_if_offset) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> even lanes receive from cable
- -- QSFP_TX
- tr_10gbe_snk_in_arr(c_qsfp_if_offset) <= lane_tx_cable_sosi_arr(0) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> even lanes transmit to cable
-
- -- RING_0_RX even lanes receive from RING_0 (from the left)
- lane_rx_board_sosi_arr(0) <= tr_10gbe_src_out_arr(c_ring_0_if_offset);
-
- -- RING_1_TX even lanes transmit to RING_1 (to the right)
- tr_10gbe_snk_in_arr(c_ring_1_if_offset) <= lane_tx_board_sosi_arr(0);
-
- -----------------------------------------------------------------------------
- -- tr_10GbE
- -----------------------------------------------------------------------------
- u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
- GENERIC MAP (
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_mac,
- g_direction => "TX_RX",
- g_tx_fifo_fill => c_xsub_fifo_tx_fill,
- g_tx_fifo_size => c_xsub_fifo_tx_size
- )
- PORT MAP (
- -- Transceiver PLL reference clock
- tr_ref_clk_644 => SA_CLK,
- tr_ref_clk_312 => tr_ref_clk_312,
- tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mac_copi,
- reg_mac_miso => reg_tr_10GbE_mac_cipo,
-
- reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
- reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => tr_10gbe_src_out_arr,
- src_in_arr => tr_10gbe_src_in_arr,
-
- snk_out_arr => tr_10gbe_snk_out_arr,
- snk_in_arr => tr_10gbe_snk_in_arr,
-
- -- Serial IO
- serial_tx_arr => tr_10gbe_serial_tx_arr,
- serial_rx_arr => tr_10gbe_serial_rx_arr
- );
-
-
- -----------------------------------------------------------------------------
- -- Seperate serial tx/rx array
- -----------------------------------------------------------------------------
- -- Seperating the one large serial tx/rx array from tr_10GbE to the 3 port arrays:
- -- QSFP port, RING_0 port and RING_1 port.
- -- QSFP_TX
- unb2_board_front_io_serial_tx_arr(0) <= tr_10gbe_serial_tx_arr(c_qsfp_if_offset);
- -- QSFP_RX
- tr_10gbe_serial_rx_arr(c_qsfp_if_offset) <= unb2_board_front_io_serial_rx_arr(0);
-
- -- RING_0_TX
- RING_0_TX(0) <= tr_10gbe_serial_tx_arr(c_ring_0_if_offset);
- -- RING_0_RX
- tr_10gbe_serial_rx_arr(c_ring_0_if_offset) <= RING_0_RX(0);
-
- -- RING_1_TX
- RING_1_TX(0) <= tr_10gbe_serial_tx_arr(c_ring_1_if_offset);
- -- RING_1_RX
- tr_10gbe_serial_rx_arr(c_ring_1_if_offset) <= RING_1_RX(0);
- END GENERATE;
END GENERATE;
-----------------------------------------------------------------------------
@@ -818,7 +786,9 @@ BEGIN
dp_clk => dp_clk,
dp_rst => dp_rst,
- in_sosi_arr => fsub_sosi_arr,
+ in_sosi_arr => fsub_sosi_arr,
+ from_ri_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_ri_sosi => bf_to_ri_sosi_arr(beamset_id),
bf_udp_sosi => bf_udp_sosi_arr(beamset_id),
bf_udp_siso => bf_udp_siso_arr(beamset_id),
bst_udp_sosi => udp_tx_sosi_arr(2+ beamset_id),
@@ -827,24 +797,35 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi_arr(beamset_id),
- ram_ss_ss_wide_miso => ram_ss_ss_wide_miso_arr(beamset_id),
- ram_bf_weights_mosi => ram_bf_weights_mosi_arr(beamset_id),
- ram_bf_weights_miso => ram_bf_weights_miso_arr(beamset_id),
- reg_bf_scale_mosi => reg_bf_scale_mosi_arr(beamset_id),
- reg_bf_scale_miso => reg_bf_scale_miso_arr(beamset_id),
- reg_hdr_dat_mosi => reg_hdr_dat_mosi_arr(beamset_id),
- reg_hdr_dat_miso => reg_hdr_dat_miso_arr(beamset_id),
- reg_dp_xonoff_mosi => reg_dp_xonoff_mosi_arr(beamset_id),
- reg_dp_xonoff_miso => reg_dp_xonoff_miso_arr(beamset_id),
- ram_st_bst_mosi => ram_st_bst_mosi_arr(beamset_id),
- ram_st_bst_miso => ram_st_bst_miso_arr(beamset_id),
- reg_stat_enable_mosi => reg_stat_enable_bst_mosi_arr(beamset_id),
- reg_stat_enable_miso => reg_stat_enable_bst_miso_arr(beamset_id),
- reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_mosi_arr(beamset_id),
- reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_miso_arr(beamset_id),
+ ram_ss_ss_wide_mosi => ram_ss_ss_wide_copi_arr(beamset_id),
+ ram_ss_ss_wide_miso => ram_ss_ss_wide_cipo_arr(beamset_id),
+ ram_bf_weights_mosi => ram_bf_weights_copi_arr(beamset_id),
+ ram_bf_weights_miso => ram_bf_weights_cipo_arr(beamset_id),
+ reg_bf_scale_mosi => reg_bf_scale_copi_arr(beamset_id),
+ reg_bf_scale_miso => reg_bf_scale_cipo_arr(beamset_id),
+ reg_hdr_dat_mosi => reg_hdr_dat_copi_arr(beamset_id),
+ reg_hdr_dat_miso => reg_hdr_dat_cipo_arr(beamset_id),
+ reg_dp_xonoff_mosi => reg_dp_xonoff_copi_arr(beamset_id),
+ reg_dp_xonoff_miso => reg_dp_xonoff_cipo_arr(beamset_id),
+ ram_st_bst_mosi => ram_st_bst_copi_arr(beamset_id),
+ ram_st_bst_miso => ram_st_bst_cipo_arr(beamset_id),
+ reg_stat_enable_mosi => reg_stat_enable_bst_copi_arr(beamset_id),
+ reg_stat_enable_miso => reg_stat_enable_bst_cipo_arr(beamset_id),
+ reg_stat_hdr_dat_mosi => reg_stat_hdr_dat_bst_copi_arr(beamset_id),
+ reg_stat_hdr_dat_miso => reg_stat_hdr_dat_bst_cipo_arr(beamset_id),
+ reg_bsn_align_copi => reg_bsn_align_v2_bf_copi_arr(beamset_id),
+ reg_bsn_align_cipo => reg_bsn_align_v2_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_copi => reg_bsn_monitor_v2_rx_align_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_input_cipo => reg_bsn_monitor_v2_rx_align_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_copi => reg_bsn_monitor_v2_aligned_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bsn_align_output_cipo => reg_bsn_monitor_v2_aligned_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_copi => reg_bsn_monitor_v2_bst_offload_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_bst_offload_cipo => reg_bsn_monitor_v2_bst_offload_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_copi => reg_bsn_monitor_v2_beamlet_output_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_beamlet_output_cipo => reg_bsn_monitor_v2_beamlet_output_cipo_arr(beamset_id),
sdp_info => sdp_info,
+ ring_info => ring_info,
gn_id => gn_id,
bdo_eth_src_mac => cep_eth_src_mac,
@@ -866,10 +847,10 @@ BEGIN
g_mult_addr_w => c_addr_w_ram_ss_ss_wide
)
PORT MAP (
- mosi => ram_ss_ss_wide_mosi,
- miso => ram_ss_ss_wide_miso,
- mosi_arr => ram_ss_ss_wide_mosi_arr,
- miso_arr => ram_ss_ss_wide_miso_arr
+ mosi => ram_ss_ss_wide_copi,
+ miso => ram_ss_ss_wide_cipo,
+ mosi_arr => ram_ss_ss_wide_copi_arr,
+ miso_arr => ram_ss_ss_wide_cipo_arr
);
u_mem_mux_ram_bf_weights : ENTITY common_lib.common_mem_mux
@@ -878,22 +859,34 @@ BEGIN
g_mult_addr_w => c_addr_w_ram_bf_weights
)
PORT MAP (
- mosi => ram_bf_weights_mosi,
- miso => ram_bf_weights_miso,
- mosi_arr => ram_bf_weights_mosi_arr,
- miso_arr => ram_bf_weights_miso_arr
+ mosi => ram_bf_weights_copi,
+ miso => ram_bf_weights_cipo,
+ mosi_arr => ram_bf_weights_copi_arr,
+ miso_arr => ram_bf_weights_cipo_arr
);
-
+
+ u_mem_mux_reg_bsn_align_v2_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_align_v2_bf
+ )
+ PORT MAP (
+ mosi => reg_bsn_align_v2_bf_copi,
+ miso => reg_bsn_align_v2_bf_cipo,
+ mosi_arr => reg_bsn_align_v2_bf_copi_arr,
+ miso_arr => reg_bsn_align_v2_bf_cipo_arr
+ );
+
u_mem_mux_reg_bf_scale : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => c_sdp_N_beamsets,
g_mult_addr_w => c_addr_w_reg_bf_scale
)
PORT MAP (
- mosi => reg_bf_scale_mosi,
- miso => reg_bf_scale_miso,
- mosi_arr => reg_bf_scale_mosi_arr,
- miso_arr => reg_bf_scale_miso_arr
+ mosi => reg_bf_scale_copi,
+ miso => reg_bf_scale_cipo,
+ mosi_arr => reg_bf_scale_copi_arr,
+ miso_arr => reg_bf_scale_cipo_arr
);
u_mem_mux_reg_hdr_dat : ENTITY common_lib.common_mem_mux
@@ -902,10 +895,10 @@ BEGIN
g_mult_addr_w => c_addr_w_reg_hdr_dat
)
PORT MAP (
- mosi => reg_hdr_dat_mosi,
- miso => reg_hdr_dat_miso,
- mosi_arr => reg_hdr_dat_mosi_arr,
- miso_arr => reg_hdr_dat_miso_arr
+ mosi => reg_hdr_dat_copi,
+ miso => reg_hdr_dat_cipo,
+ mosi_arr => reg_hdr_dat_copi_arr,
+ miso_arr => reg_hdr_dat_cipo_arr
);
u_mem_mux_reg_dp_xonoff : ENTITY common_lib.common_mem_mux
@@ -914,10 +907,10 @@ BEGIN
g_mult_addr_w => c_addr_w_reg_dp_xonoff
)
PORT MAP (
- mosi => reg_dp_xonoff_mosi,
- miso => reg_dp_xonoff_miso,
- mosi_arr => reg_dp_xonoff_mosi_arr,
- miso_arr => reg_dp_xonoff_miso_arr
+ mosi => reg_dp_xonoff_copi,
+ miso => reg_dp_xonoff_cipo,
+ mosi_arr => reg_dp_xonoff_copi_arr,
+ miso_arr => reg_dp_xonoff_cipo_arr
);
u_mem_mux_ram_st_bst : ENTITY common_lib.common_mem_mux
@@ -926,10 +919,10 @@ BEGIN
g_mult_addr_w => c_addr_w_ram_st_bst
)
PORT MAP (
- mosi => ram_st_bst_mosi,
- miso => ram_st_bst_miso,
- mosi_arr => ram_st_bst_mosi_arr,
- miso_arr => ram_st_bst_miso_arr
+ mosi => ram_st_bst_copi,
+ miso => ram_st_bst_cipo,
+ mosi_arr => ram_st_bst_copi_arr,
+ miso_arr => ram_st_bst_cipo_arr
);
u_mem_mux_reg_stat_enable_bst : ENTITY common_lib.common_mem_mux
@@ -938,10 +931,10 @@ BEGIN
g_mult_addr_w => c_sdp_reg_stat_enable_addr_w
)
PORT MAP (
- mosi => reg_stat_enable_bst_mosi,
- miso => reg_stat_enable_bst_miso,
- mosi_arr => reg_stat_enable_bst_mosi_arr,
- miso_arr => reg_stat_enable_bst_miso_arr
+ mosi => reg_stat_enable_bst_copi,
+ miso => reg_stat_enable_bst_cipo,
+ mosi_arr => reg_stat_enable_bst_copi_arr,
+ miso_arr => reg_stat_enable_bst_cipo_arr
);
u_mem_mux_reg_stat_hdr_dat_bst : ENTITY common_lib.common_mem_mux
@@ -950,12 +943,60 @@ BEGIN
g_mult_addr_w => c_sdp_reg_stat_hdr_dat_addr_w
)
PORT MAP (
- mosi => reg_stat_hdr_dat_bst_mosi,
- miso => reg_stat_hdr_dat_bst_miso,
- mosi_arr => reg_stat_hdr_dat_bst_mosi_arr,
- miso_arr => reg_stat_hdr_dat_bst_miso_arr
+ mosi => reg_stat_hdr_dat_bst_copi,
+ miso => reg_stat_hdr_dat_bst_cipo,
+ mosi_arr => reg_stat_hdr_dat_bst_copi_arr,
+ miso_arr => reg_stat_hdr_dat_bst_cipo_arr
);
-
+
+ u_mem_mux_reg_bsn_monitor_v2_rx_align_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_rx_align_bf
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_rx_align_bf_copi,
+ miso => reg_bsn_monitor_v2_rx_align_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_rx_align_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_rx_align_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_bsn_monitor_v2_aligned_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_aligned_bf_copi,
+ miso => reg_bsn_monitor_v2_aligned_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_aligned_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_aligned_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_bsn_monitor_v2_bst_offload : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_bst_offload_copi,
+ miso => reg_bsn_monitor_v2_bst_offload_cipo,
+ mosi_arr => reg_bsn_monitor_v2_bst_offload_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_bst_offload_cipo_arr
+ );
+
+ u_mem_mux_reg_bsn_monitor_v2_beamlet_output : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_bsn_monitor_v2_addr_w
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_beamlet_output_copi,
+ miso => reg_bsn_monitor_v2_beamlet_output_cipo,
+ mosi_arr => reg_bsn_monitor_v2_beamlet_output_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_beamlet_output_cipo_arr
+ );
+
-----------------------------------------------------------------------------
-- DP MUX
-----------------------------------------------------------------------------
@@ -1008,11 +1049,11 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
- reg_mac_mosi => reg_nw_10GbE_mac_mosi,
- reg_mac_miso => reg_nw_10GbE_mac_miso,
+ reg_mac_mosi => reg_nw_10GbE_mac_copi,
+ reg_mac_miso => reg_nw_10GbE_mac_cipo,
- reg_eth10g_mosi => reg_nw_10GbE_eth10g_mosi,
- reg_eth10g_miso => reg_nw_10GbE_eth10g_miso,
+ reg_eth10g_mosi => reg_nw_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_nw_10GbE_eth10g_cipo,
-- DP interface
dp_rst => dp_rst,
@@ -1033,6 +1074,249 @@ BEGIN
);
END GENERATE;
+ gen_use_ring : IF g_use_ring GENERATE
+ gen_xst_ring : IF g_use_xsub GENERATE
+ u_ring_lane_xst : ENTITY ring_lib.ring_lane
+ GENERIC MAP (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_longword_w,
+ g_lane_packet_length => c_lane_packet_length_xst,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_sdp_N_pn_max,
+ g_nof_tx_monitors => c_sdp_N_pn_max,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => xst_from_ri_sosi,
+ to_lane_sosi => xst_to_ri_sosi,
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(0),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(0),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(0),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(0),
+ bs_sosi => bs_sosi,
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_xst_copi,
+ reg_ring_lane_info_cipo => reg_ring_lane_info_xst_cipo,
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_xst_copi,
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_xst_cipo,
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_xst_copi,
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_xst_cipo,
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_xst_copi,
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_xst_cipo,
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_xst_copi,
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_xst_cipo,
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
+ END GENERATE;
+
+ gen_bf_ring : IF g_use_bf GENERATE
+ gen_beamset_ring : FOR beamset_id IN 0 TO c_sdp_N_beamsets-1 GENERATE
+ u_ring_lane_bf : ENTITY ring_lib.ring_lane
+ GENERIC MAP (
+ g_lane_direction => 1, -- transport in positive direction.
+ g_lane_data_w => c_longword_w,
+ g_lane_packet_length => c_lane_packet_length_bf,
+ g_use_dp_layer => c_use_dp_layer,
+ g_nof_rx_monitors => c_sdp_N_pn_max,
+ g_nof_tx_monitors => c_sdp_N_pn_max,
+ g_err_bi => c_err_bi,
+ g_nof_err_counts => c_nof_err_counts,
+ g_bsn_at_sync_check_channel => c_bsn_at_sync_check_channel,
+ g_validate_channel => c_validate_channel,
+ g_validate_channel_mode => c_validate_channel_mode,
+ g_sync_timeout => c_sync_timeout
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+
+ from_lane_sosi => bf_from_ri_sosi_arr(beamset_id),
+ to_lane_sosi => bf_to_ri_sosi_arr(beamset_id),
+ lane_rx_cable_sosi => lane_rx_cable_sosi_arr(1 + beamset_id),
+ lane_rx_board_sosi => lane_rx_board_sosi_arr(1 + beamset_id),
+ lane_tx_cable_sosi => lane_tx_cable_sosi_arr(1 + beamset_id),
+ lane_tx_board_sosi => lane_tx_board_sosi_arr(1 + beamset_id),
+ bs_sosi => fsub_sosi_arr(0), -- used for bsn and sync
+
+ reg_ring_lane_info_copi => reg_ring_lane_info_bf_copi_arr(beamset_id),
+ reg_ring_lane_info_cipo => reg_ring_lane_info_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_copi => reg_bsn_monitor_v2_ring_rx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_rx_cipo => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_copi => reg_bsn_monitor_v2_ring_tx_bf_copi_arr(beamset_id),
+ reg_bsn_monitor_v2_ring_tx_cipo => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_err_copi => reg_dp_block_validate_err_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_err_cipo => reg_dp_block_validate_err_bf_cipo_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_copi => reg_dp_block_validate_bsn_at_sync_bf_copi_arr(beamset_id),
+ reg_dp_block_validate_bsn_at_sync_cipo => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr(beamset_id),
+
+ this_rn => this_rn,
+ N_rn => ring_info.N_rn,
+ rx_select => ring_info.use_cable_to_previous_rn,
+ tx_select => ring_info.use_cable_to_next_rn
+ );
+ END GENERATE;
+
+
+ u_mem_mux_reg_ring_lane_info_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_ring_lane_info_bf
+ )
+ PORT MAP (
+ mosi => reg_ring_lane_info_bf_copi,
+ miso => reg_ring_lane_info_bf_cipo,
+ mosi_arr => reg_ring_lane_info_bf_copi_arr,
+ miso_arr => reg_ring_lane_info_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_bsn_monitor_v2_ring_rx_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_rx_bf
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_ring_rx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_rx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_rx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_rx_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_bsn_monitor_v2_ring_tx_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_addr_w_reg_bsn_monitor_v2_ring_tx_bf
+ )
+ PORT MAP (
+ mosi => reg_bsn_monitor_v2_ring_tx_bf_copi,
+ miso => reg_bsn_monitor_v2_ring_tx_bf_cipo,
+ mosi_arr => reg_bsn_monitor_v2_ring_tx_bf_copi_arr,
+ miso_arr => reg_bsn_monitor_v2_ring_tx_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_dp_block_validate_err_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_err_addr_w
+ )
+ PORT MAP (
+ mosi => reg_dp_block_validate_err_bf_copi,
+ miso => reg_dp_block_validate_err_bf_cipo,
+ mosi_arr => reg_dp_block_validate_err_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_err_bf_cipo_arr
+ );
+
+ u_mem_mux_reg_dp_block_validate_bsn_at_sync_bf : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => c_sdp_N_beamsets,
+ g_mult_addr_w => c_sdp_reg_dp_block_validate_bsn_at_sync_addr_w
+ )
+ PORT MAP (
+ mosi => reg_dp_block_validate_bsn_at_sync_bf_copi,
+ miso => reg_dp_block_validate_bsn_at_sync_bf_cipo,
+ mosi_arr => reg_dp_block_validate_bsn_at_sync_bf_copi_arr,
+ miso_arr => reg_dp_block_validate_bsn_at_sync_bf_cipo_arr
+ );
+ END GENERATE;
+ -----------------------------------------------------------------------------
+ -- Combine seperate signals into array for tr_10GbE
+ -----------------------------------------------------------------------------
+ gen_lane_wires : FOR I IN 0 TO c_nof_lane-1 GENERATE
+ -- QSFP_RX
+ lane_rx_cable_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_qsfp_if_offset) WHEN ring_info.use_cable_to_previous_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_previous_rn=1 -> even lanes receive from cable
+
+ -- QSFP_TX
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_qsfp_if_offset) <= lane_tx_cable_sosi_arr(I) WHEN ring_info.use_cable_to_next_rn = '1' ELSE c_dp_sosi_rst; -- use_cable_to_next_rn=1 -> even lanes transmit to cable
+
+ -- RING_0_RX even lanes receive from RING_0 (from the left)
+ lane_rx_board_sosi_arr(I) <= tr_10gbe_src_out_arr(c_nof_if * I + c_ring_0_if_offset);
+
+ -- RING_1_TX even lanes transmit to RING_1 (to the right)
+ tr_10gbe_snk_in_arr(c_nof_if * I + c_ring_1_if_offset) <= lane_tx_board_sosi_arr(I);
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- tr_10GbE
+ -----------------------------------------------------------------------------
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_mac,
+ g_direction => "TX_RX",
+ g_tx_fifo_fill => c_xsub_fifo_tx_fill,
+ g_tx_fifo_size => c_xsub_fifo_tx_size
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_644 => SA_CLK,
+ tr_ref_clk_312 => tr_ref_clk_312,
+ tr_ref_clk_156 => tr_ref_clk_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mac_copi,
+ reg_mac_miso => reg_tr_10GbE_mac_cipo,
+
+ reg_eth10g_mosi => reg_tr_10GbE_eth10g_copi,
+ reg_eth10g_miso => reg_tr_10GbE_eth10g_cipo,
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => tr_10gbe_src_out_arr,
+ src_in_arr => tr_10gbe_src_in_arr,
+
+ snk_out_arr => tr_10gbe_snk_out_arr,
+ snk_in_arr => tr_10gbe_snk_in_arr,
+
+ -- Serial IO
+ serial_tx_arr => tr_10gbe_serial_tx_arr,
+ serial_rx_arr => tr_10gbe_serial_rx_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- Seperate serial tx/rx array
+ -----------------------------------------------------------------------------
+ -- Seperating the one large serial tx/rx array from tr_10GbE to the 3 port arrays:
+ -- QSFP port, RING_0 port and RING_1 port.
+ gen_serial_wires : FOR I IN 0 TO c_nof_lane-1 GENERATE
+ -- QSFP_TX
+ unb2_board_front_io_serial_tx_arr(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_qsfp_if_offset);
+ -- QSFP_RX
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_qsfp_if_offset) <= unb2_board_front_io_serial_rx_arr(I);
+
+ -- RING_0_TX
+ RING_0_TX(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_ring_0_if_offset);
+ -- RING_0_RX
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_ring_0_if_offset) <= RING_0_RX(I);
+
+ -- RING_1_TX
+ RING_1_TX(I) <= tr_10gbe_serial_tx_arr(c_nof_if * I + c_ring_1_if_offset);
+ -- RING_1_RX
+ tr_10gbe_serial_rx_arr(c_nof_if * I + c_ring_1_if_offset) <= RING_1_RX(I);
+ END GENERATE;
+ END GENERATE;
+
---------
-- PLL
---------
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index 45f4be06831c117b547a6c89da4c4cdc061fb3f6..934dbb94caddf710fb87cdda18238fa359dc3b2b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -25,10 +25,12 @@
-- Purpose:
-- . SDP statistics offload
-- Description:
--- https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+filterbank
--- . See figure 4.3
--- https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
--- . See 2.9.4 Station Control (L3-SC) - SDP Firmware (L4-SDPFW)
+-- [1] https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+filterbank
+-- . See figure 4.3
+-- [2] https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+Correlator
+-- . See Figure 3.7
+-- [3] https://plm.astron.nl/polarion/#/project/LOFAR2System/wiki/L2%20Interface%20Control%20Documents/SC%20to%20SDP%20ICD
+-- . See 2.9.4 Station Control (L3-SC) - SDP Firmware (L4-SDPFW)
--
-- . endianess
-- Within a 32bit MM word the values are stored with LSByte at lowest byte
@@ -82,6 +84,17 @@
-- BST (Xh, Xl), (Yh, Yl), 2 keep X, Y parts order
-- XST (Rh, Rl), (Ih, Il), 2 keep Re, Im parts order
--
+-- . g_P_sq and nof_used_P_sq
+-- The g_P_sq defines the number of correlator cells that is available in
+-- the SDPFW. Use generic to support P_sq = 1 for one node and P_sq =
+-- c_sdp_P_sq for multiple nodes (with ring).
+-- The nof_used_P_sq is the number of correlator cells that is actually
+-- used and that will output XST packets. Unused correlator cells yield
+-- zero data that should not be output. The nof_used_P_sq is the smallest
+-- of g_P_sq and ring_info.N_rn/2 + 1. In this way the XST offload can work
+-- with g_P_sq = 1 when N_rn > 1 and also in a ring with N_rn < N_pn when
+-- g_P_sq = 9.
+--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, mm_lib, dp_lib, ring_lib;
@@ -99,8 +112,8 @@ ENTITY sdp_statistics_offload IS
g_statistics_type : STRING := "SST";
g_offload_time : NATURAL := c_sdp_offload_time;
g_beamset_id : NATURAL := 0;
- g_P_sq : NATURAL := c_sdp_P_sq; -- use generic to support P_sq = 1 for one node and P_sq = c_sdp_P_sq for multiple nodes (with ring)
- g_crosslets_direction : NATURAL := 1; -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
+ g_P_sq : NATURAL := c_sdp_P_sq; -- number of available correlator cells,
+ g_crosslets_direction : NATURAL := 1; -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
g_reverse_word_order : BOOLEAN := TRUE -- default word order is MSB after LSB, we need to stream LSB after MSB.
);
PORT (
@@ -122,6 +135,10 @@ ENTITY sdp_statistics_offload IS
reg_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_hdr_dat_miso : OUT t_mem_miso;
+ -- Memory access bsn monitor udp offload
+ reg_bsn_monitor_v2_offload_copi : IN t_mem_copi := c_mem_copi_rst;
+ reg_bsn_monitor_v2_offload_cipo : OUT t_mem_cipo;
+
-- Input timing regarding the integration interval of the statistics
in_sosi : IN t_dp_sosi;
@@ -137,7 +154,7 @@ ENTITY sdp_statistics_offload IS
gn_index : IN NATURAL;
ring_info : IN t_ring_info := c_ring_info_rst; -- only needed for XST
sdp_info : IN t_sdp_info;
- subband_calibrated_flag : IN STD_LOGIC := '0';
+ weighted_subbands_flag : IN STD_LOGIC := '0';
nof_crosslets : IN STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0) := (OTHERS => '0');
crosslets_info : IN STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0')
);
@@ -170,6 +187,7 @@ ARCHITECTURE str OF sdp_statistics_offload IS
packet_count : NATURAL RANGE 0 TO c_nof_packets_max;
start_address : NATURAL RANGE 0 TO c_mm_ram_size;
start_pulse : STD_LOGIC;
+ sync : STD_LOGIC;
dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0);
payload_err : STD_LOGIC;
in_sop_cnt : NATURAL;
@@ -184,7 +202,7 @@ ARCHITECTURE str OF sdp_statistics_offload IS
END RECORD;
CONSTANT c_crosslets_info_rst : t_sdp_crosslets_info := (offset_arr => (OTHERS => 0), step => 0);
- CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), '0', 0, 0, 0, 0, 0, 0, 0, 0, c_crosslets_info_rst);
+ CONSTANT c_reg_rst : t_reg := (0, 0, '0', '0', (OTHERS => '0'), '0', 0, 0, 0, 0, 0, 0, 0, 0, c_crosslets_info_rst);
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
@@ -198,7 +216,10 @@ ARCHITECTURE str OF sdp_statistics_offload IS
SIGNAL remote_pn : NATURAL; -- index of remote node in antenna band
SIGNAL remote_si_offset : NATURAL; -- index of first signal input on remote node
SIGNAL nof_cycles_dly : NATURAL; -- trigger_offload delay for this node
- SIGNAL nof_packets : NATURAL; -- nof packets per integration interval
+ SIGNAL offset_rn : NATURAL; -- = ring_info.O_rn, GN index of first ring node
+ SIGNAL nof_rn : NATURAL; -- = ring_info.N_rn, number of GN in the ring
+ SIGNAL nof_used_P_sq : NATURAL; -- number of used correlator cells <= g_P_sq (is number of available correlator cells)
+ SIGNAL nof_packets : NATURAL; -- nof XST offload packets per integration interval
SIGNAL data_id_rec : t_sdp_stat_data_id;
SIGNAL data_id_slv : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
@@ -206,13 +227,16 @@ ARCHITECTURE str OF sdp_statistics_offload IS
SIGNAL trigger_en : STD_LOGIC := '0';
SIGNAL trigger_offload : STD_LOGIC := '0';
SIGNAL mm_done : STD_LOGIC := '0';
+ SIGNAL dp_sop : STD_LOGIC := '0';
SIGNAL dp_block_from_mm_src_out : t_dp_sosi;
SIGNAL dp_block_from_mm_src_in : t_dp_siso;
SIGNAL dp_offload_snk_in : t_dp_sosi;
SIGNAL dp_offload_snk_out : t_dp_siso;
- SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL udp_sosi : t_dp_sosi;
+
+ SIGNAL bsn_at_sync : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL dp_header_info : STD_LOGIC_VECTOR(1023 DOWNTO 0):= (OTHERS => '0');
-- Debug signals for view in Wave window
@@ -229,7 +253,7 @@ ARCHITECTURE str OF sdp_statistics_offload IS
BEGIN
- bsn_at_sync <= RESIZE_UVEC(in_sosi.bsn, 64) WHEN rising_edge(dp_clk) AND in_sosi.sync = '1';
+ bsn_at_sync <= RESIZE_UVEC(in_sosi.bsn, c_dp_stream_bsn_w) WHEN rising_edge(dp_clk) AND in_sosi.sync = '1';
-------------------------------------------------------------------------------
-- Assemble offload header info, for data path fields that are selected by:
@@ -252,7 +276,7 @@ BEGIN
-- sdp_source_info_fsub_type,
-- sdp_source_info_payload_error,
-- sdp_source_info_beam_repositioning_flag,
- -- sdp_source_info_subband_calibrated_flag,
+ -- sdp_source_info_weighted_subbands_flag,
-- sdp_source_info_gn_id,
-- - sdp_integration_interval, sdp_data_id, sdp_nof_signal_inputs,
-- sdp_nof_bytes_per_statistic,
@@ -273,7 +297,7 @@ BEGIN
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_fsub_type" )) <= SLV(sdp_info.fsub_type);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_payload_error" )) <= SLV(r.payload_err);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_beam_repositioning_flag" )) <= SLV(sdp_info.beam_repositioning_flag);
- dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_subband_calibrated_flag" )) <= SLV(subband_calibrated_flag);
+ dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_weighted_subbands_flag" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_weighted_subbands_flag" )) <= SLV(weighted_subbands_flag);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_source_info_gn_id" )) <= TO_UVEC(gn_index, 5);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_integration_interval" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_integration_interval" )) <= TO_UVEC(r.integration_interval, 24);
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id" ) DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id" )) <= data_id_slv;
@@ -293,17 +317,24 @@ BEGIN
END PROCESS;
-- Derive and pipeline dynamic parameters
- gn_index_reg <= gn_index WHEN rising_edge(dp_clk);
- pn_index <= func_sdp_gn_index_to_pn_index(gn_index) WHEN rising_edge(dp_clk);
- rn_index <= gn_index - TO_UINT(ring_info.O_rn) WHEN rising_edge(dp_clk);
- local_si_offset <= pn_index * c_sdp_S_pn WHEN rising_edge(dp_clk);
- nof_cycles_dly <= gn_index * g_offload_time WHEN rising_edge(dp_clk);
- nof_packets <= func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, g_P_sq, r.nof_crosslets) WHEN rising_edge(dp_clk);
-
- remote_rn <= func_ring_nof_hops_to_source_rn(r.instance_count, rn_index, TO_UINT(ring_info.N_rn), g_crosslets_direction);
- remote_gn <= TO_UINT(ring_info.O_rn) + remote_rn;
- remote_pn <= func_sdp_gn_index_to_pn_index(remote_gn) WHEN rising_edge(dp_clk);
- remote_si_offset <= remote_pn * c_sdp_S_pn WHEN rising_edge(dp_clk);
+ p_parameters : PROCESS(dp_clk)
+ BEGIN
+ IF rising_edge(dp_clk) THEN
+ gn_index_reg <= gn_index;
+ pn_index <= func_sdp_gn_index_to_pn_index(gn_index_reg);
+ offset_rn <= TO_UINT(ring_info.O_rn);
+ rn_index <= gn_index_reg - offset_rn;
+ local_si_offset <= pn_index * c_sdp_S_pn;
+ nof_cycles_dly <= gn_index_reg * g_offload_time;
+ nof_rn <= TO_UINT(ring_info.N_rn);
+ nof_used_P_sq <= smallest(nof_rn / 2 + 1, g_P_sq);
+ nof_packets <= func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, nof_used_P_sq, r.nof_crosslets);
+ remote_rn <= func_ring_nof_hops_to_source_rn(r.instance_count, rn_index, nof_rn, g_crosslets_direction);
+ remote_gn <= offset_rn + remote_rn;
+ remote_pn <= func_sdp_gn_index_to_pn_index(remote_gn);
+ remote_si_offset <= remote_pn * c_sdp_S_pn;
+ END IF;
+ END PROCESS;
-- Assign application header data_id for different statistic types, use
-- GENERATE to keep unused fields at 0.
@@ -321,12 +352,13 @@ BEGIN
data_id_slv <= func_sdp_map_stat_data_id(g_statistics_type, data_id_rec);
- p_control_packet_offload : PROCESS(r, in_sosi, local_si_offset, trigger_offload, nof_crosslets, crosslets_info, nof_packets, mm_done, dp_header_info)
+ p_control_packet_offload : PROCESS(r, in_sosi, local_si_offset, trigger_offload, nof_crosslets, crosslets_info, nof_packets, dp_sop, dp_header_info)
VARIABLE v : t_reg;
VARIABLE v_index : NATURAL;
BEGIN
v := r;
v.start_pulse := '0';
+ v.sync := '0';
-- Count number of sop in a sync interval and get payload errors and keep them till next sync.
IF in_sosi.sync = '1' THEN
@@ -343,19 +375,35 @@ BEGIN
END IF;
END IF;
- -- Capture nof_crosslets and crosslets_info at in_sosi.sync, to make sure
- -- they do not change during packets offload. The trigger_offload occurs
- -- after the nof_cycles_dly and the offload will have finished before the
- -- next in_sosi.sync
+
+ -- For XST offload capture nof_crosslets and crosslets_info at in_sosi.sync,
+ -- to make sure they do not change during packets offload.
+ -- . The sdp_crosslets_subband_select.vhd takes in [2] takes care that
+ -- nof_crosslets and crosslets_info are valid at the xsel_sosi.sync. The
+ -- mmp_dp_bsn_align_v2 in [2] then aligns the local xsel_sosi with the
+ -- remote data and passes on the sync. After some latency the sync
+ -- arrives at the sdp_statistics_offload. This latency is very short
+ -- compared to the sync period, so the nof_crosslets and crosslet_info
+ -- are still valid at the in_sosi.sync.
IF in_sosi.sync = '1' THEN
v.nof_crosslets := TO_UINT(nof_crosslets);
v.crosslets_info_rec := func_sdp_map_crosslets_info(crosslets_info);
END IF;
- -- Issue start_pulse per packet offload
+ -- The trigger_offload occurs nof_cycles_dly after the in_sosi.sync and the
+ -- offload will have finished before the next in_sosi.sync, because
+ -- c_sdp_offload_time is such that all offload will finish within 100 ms
+ -- and the integration interval (= sync interval) is 1 s for SST and BST
+ -- and minimal 0.1s (= c_sdp_xst_nof_clk_per_sync_min) for XST.
+ -- The trigger_offload initializes the control for the first packet offload
+ -- in every sync interval.
+ -- . Issue a start_pulse per packet offload. The start_pulse is used by
+ -- u_dp_block_from_mm_dc to read the packet from statistics memory.
IF trigger_offload = '1' THEN
- -- Use trigger_offload to start first packet offload, all g_statistics_type start from start address 0
+ -- Use trigger_offload to start first packet offload, all
+ -- g_statistics_type start from start address 0
v.start_pulse := '1';
+ v.sync := '1';
v.start_address := 0;
v.packet_count := 0;
v.interleave_count := 0; -- only used for SST
@@ -364,8 +412,20 @@ BEGIN
v.instance_count := 0; -- only used for XST
v.instance_address := 0; -- only used for XST
- ELSIF mm_done = '1' THEN
- -- Use mm_done to start next packets offloads.
+ -- The dp_sop = '1' when the packet has been read from statistics memory
+ -- and is about to get out of the dp_fifo_fill_eop in
+ -- u_dp_block_from_mm_dc. The difference between dp_sop and the mm_done
+ -- output of u_dp_block_from_mm_dc, is that dp_sop also includes any
+ -- dp_fifo_fill_eop latency. This ensures that the dp_sop identifies the
+ -- sop of the offload packet. At the dp_sop:
+ -- . the dp_header_info per packet offload can be released
+ -- . the next packet offload can be prepared
+ --
+ ELSIF dp_sop = '1' THEN
+ -- Release dp_header_info for current packet offload
+ v.dp_header_info := dp_header_info;
+
+ -- Start next packets offload.
IF r.packet_count < nof_packets - 1 THEN
IF g_statistics_type = "SST" THEN
-- step step step step step step
@@ -414,10 +474,6 @@ BEGIN
END IF;
END IF;
- -- Release dp_header_info per packet offload
- IF trigger_offload = '1' OR mm_done = '1' THEN
- v.dp_header_info := dp_header_info;
- END IF;
nxt_r <= v;
END PROCESS;
@@ -445,7 +501,8 @@ BEGIN
g_step_size => c_mm_step_size,
g_nof_data => c_mm_nof_data,
g_word_w => c_word_w,
- g_reverse_word_order => g_reverse_word_order
+ g_reverse_word_order => g_reverse_word_order,
+ g_bsn_w => c_dp_stream_bsn_w
)
PORT MAP(
dp_rst => dp_rst,
@@ -453,14 +510,27 @@ BEGIN
mm_rst => mm_rst,
mm_clk => mm_clk,
start_pulse => r.start_pulse,
+ sync_in => r.sync,
+ bsn_at_sync => bsn_at_sync,
start_address => r.start_address,
- done => mm_done,
+ done => mm_done, -- not used, use dp_sop instead
mm_mosi => master_mosi,
mm_miso => master_miso,
out_sosi => dp_block_from_mm_src_out,
out_siso => dp_block_from_mm_src_in
);
+ -- Use dp_block_from_mm_src_out.sop as dp_sop, to include the
+ -- dp_fifo_fill_eop that is in dp_block_from_mm_dc. The dp_sop thus is the
+ -- sop of the packet that is about to be offloaded by u_dp_offload_tx_v3.
+ -- The r.dp_header_info must be available at the dp_offload_snk_in.sop.
+ -- This is guaranteed because:
+ -- . r.dp_header_info is available one clock cycle after dp_sop in
+ -- p_control_packet_offload.
+ -- . The dp_offload_snk_in is delayed also by at least one clock cycle by
+ -- u_dp_pipeline_ready.
+ dp_sop <= dp_block_from_mm_src_out.sop;
+
u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
PORT MAP(
rst => dp_rst,
@@ -491,8 +561,40 @@ BEGIN
reg_hdr_dat_miso => reg_hdr_dat_miso,
snk_in_arr(0) => dp_offload_snk_in,
snk_out_arr(0) => dp_offload_snk_out,
- src_out_arr(0) => out_sosi,
+ src_out_arr(0) => udp_sosi,
src_in_arr(0) => out_siso,
hdr_fields_in_arr(0) => r.dp_header_info
);
+
+ out_sosi <= udp_sosi;
+
+ u_bsn_mon_udp : ENTITY dp_lib.mms_dp_bsn_monitor_v2
+ GENERIC MAP (
+ g_nof_streams => 1,
+ g_cross_clock_domain => TRUE,
+ g_sync_timeout => c_sdp_N_clk_sync_timeout,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_error_bi => 0,
+ g_cnt_sop_w => c_word_w,
+ g_cnt_valid_w => c_word_w,
+ g_cnt_latency_w => c_word_w
+ )
+ PORT MAP (
+ -- Memory-mapped clock domain
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_v2_offload_copi,
+ reg_miso => reg_bsn_monitor_v2_offload_cipo,
+
+ -- Streaming clock domain
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ ref_sync => in_sosi.sync,
+
+ in_sosi_arr(0) => udp_sosi
+ );
+
+
+
+
END str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index 7ae6012f078832edcae802a8e94dec511874f292..05d222f417f158351779bbee469fc7b5543f3124 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -77,30 +77,32 @@ BEGIN
-- fsub[S_pn/Q_fft]_[N_sub][Q_fft]. Therefore the counter in
-- sdp_subband_equalizer.vhd has to account for this difference in order.
p_cnt : PROCESS(dp_clk, dp_rst)
- VARIABLE v_Q_fft, v_N_sub : NATURAL;
+ -- Use short index variables v_Q, v_SUB names in capitals, to ease
+ -- recognizing them as (loop) indices.
+ VARIABLE v_Q, v_SUB : NATURAL;
BEGIN
IF dp_rst = '1' THEN
cnt <= 0;
- v_Q_fft := 0;
- v_N_sub := 0;
+ v_Q := 0;
+ v_SUB := 0;
ELSIF rising_edge(dp_clk) THEN
IF in_sosi_arr(0).valid = '1' THEN
IF in_sosi_arr(0).eop = '1' THEN
- v_Q_fft := 0;
- v_N_sub := 0;
+ v_Q := 0;
+ v_SUB := 0;
ELSE
- IF v_Q_fft >= c_sdp_Q_fft-1 THEN
- v_Q_fft := 0;
- IF v_N_sub >= c_sdp_N_sub-1 THEN
- v_N_sub := 0;
+ IF v_Q >= c_sdp_Q_fft-1 THEN
+ v_Q := 0;
+ IF v_SUB >= c_sdp_N_sub-1 THEN
+ v_SUB := 0;
ELSE
- v_N_sub := v_N_sub + 1;
+ v_SUB := v_SUB + 1;
END IF;
ELSE
- v_Q_fft := v_Q_fft + 1;
+ v_Q := v_Q + 1;
END IF;
END IF;
- cnt <= v_Q_fft * c_sdp_N_sub + v_N_sub;
+ cnt <= v_Q * c_sdp_N_sub + v_SUB;
END IF;
END IF;
END PROCESS;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index 2b6912dc420207a7adb5bd133be40546074c798c..d58cd1b58e1de6fbc64612736e5f3bad2ce48e72 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -55,28 +55,31 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
CONSTANT c_rl : NATURAL := 1;
CONSTANT c_nof_sync : NATURAL := 5;
CONSTANT c_nof_block_per_sync : NATURAL := 4;
- CONSTANT c_nof_ch_in : NATURAL := 1024; -- nof input words per block, identical for all input streams.
CONSTANT c_dsp_data_w : NATURAL := c_sdp_W_subband;
- CONSTANT c_nof_ch_sel_row : NATURAL := c_sdp_P_pfb;
CONSTANT c_N_crosslets : NATURAL := 2;
- CONSTANT c_ch_sel_offsets : t_natural_arr(0 TO c_N_crosslets-1) := (0, 15);
- CONSTANT c_nof_ch_sel_col : NATURAL := c_sdp_Q_fft; -- nof of sequential collums to select per row.
- CONSTANT c_ch_sel_step : NATURAL := 3; -- offset step size to increase per sync interval
+ CONSTANT c_crosslet_offsets : t_natural_arr(0 TO c_N_crosslets-1) := (0, 15);
+ CONSTANT c_crosslet_step : NATURAL := 3; -- offset step size to increase per sync interval
+ CONSTANT c_nof_ch_in : NATURAL := 1024; -- nof input words per block, identical for all input streams.
+ CONSTANT c_nof_ch_sel_row : NATURAL := c_sdp_P_pfb;
+ CONSTANT c_nof_ch_sel_col : NATURAL := c_sdp_Q_fft; -- nof of sequential columns to select per row.
CONSTANT c_nof_ch_sel : NATURAL := c_N_crosslets*c_nof_ch_sel_col*c_nof_ch_sel_row;
+
CONSTANT c_ctrl_interval_size : NATURAL := c_nof_block_per_sync * c_nof_ch_in;
CONSTANT c_scheduled_bsn : NATURAL := 11;
CONSTANT c_nof_block_dly : NATURAL := c_nof_block_per_sync;
+ SIGNAL tb_end : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL mm_clk : STD_LOGIC := '1';
- SIGNAL tb_end : STD_LOGIC;
-
- SIGNAL mm_mosi : t_mem_mosi;
- SIGNAL mm_miso : t_mem_miso;
-
+
+ SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL mm_miso : t_mem_miso;
+ SIGNAL rd_crosslet_offsets : t_natural_arr(0 TO c_N_crosslets-1) := (0, 15);
+ SIGNAL rd_crosslet_step : NATURAL;
+
SIGNAL mm_trigger_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL mm_trigger_miso : t_mem_miso;
@@ -91,32 +94,74 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
SIGNAL out_sosi : t_dp_sosi;
- SIGNAL exp_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL out_crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL exp_crosslets_info_slv : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL out_crosslets_info_slv : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL exp_crosslets_info_rec : t_sdp_crosslets_info;
+ SIGNAL out_crosslets_info_rec : t_sdp_crosslets_info;
+
BEGIN
clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
mm_clk <= (NOT mm_clk) OR tb_end AFTER c_mm_clk_period/2;
rst <= '1', '0' AFTER c_clk_period*7;
- p_select_stimuli : PROCESS
+ p_mm_stimuli : PROCESS
VARIABLE k : NATURAL;
BEGIN
-
proc_common_wait_until_low(mm_clk, rst);
proc_common_wait_some_cycles(mm_clk, 50); -- Give dut some time to start
- -- BSN Scheduler
+
+ -- Set BSN sync scheduler
proc_mem_mm_bus_wr(1, c_ctrl_interval_size, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(2, c_scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(3, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(0, 1, mm_clk, mm_trigger_miso, mm_trigger_mosi); --enable
+ -- Set crosslet info
+ FOR I IN 0 TO c_N_crosslets-1 LOOP
+ proc_mem_mm_bus_wr(I, c_crosslet_offsets(I), mm_clk, mm_miso, mm_mosi); --offsets
+ END LOOP;
+ proc_mem_mm_bus_wr(15, c_crosslet_step, mm_clk, mm_miso, mm_mosi); --step
+ proc_common_wait_cross_clock_domain_latency(c_clk_period, c_mm_clk_period);
- -- crosslet info
+ -- Verify that MM reads the active crosslets_info
+ -- a) Readback crosslet info after rst release
+ FOR I IN 0 TO c_N_crosslets-1 LOOP
+ proc_mem_mm_bus_rd(I, mm_clk, mm_miso, mm_mosi); --offsets
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_crosslet_offsets(I) <= TO_UINT(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ END LOOP;
+ proc_mem_mm_bus_rd(15, mm_clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_crosslet_step <= TO_UINT(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+ -- Verify that readback crosslet info is active crosslets_info
FOR I IN 0 TO c_N_crosslets-1 LOOP
- proc_mem_mm_bus_wr(I, c_ch_sel_offsets(I), mm_clk, mm_miso, mm_mosi); --offsets
+ ASSERT rd_crosslet_offsets(I) = 0 REPORT "Wrong crosslet offset after rst." SEVERITY ERROR;
END LOOP;
- proc_mem_mm_bus_wr(15, c_ch_sel_step, mm_clk, mm_miso, mm_mosi); --step
+ ASSERT rd_crosslet_step = 0 REPORT "Wrong crosslet step after rst." SEVERITY ERROR;
+
+ -- b) Read crosslet_info in every sync interval
+ WHILE TRUE LOOP
+ proc_common_wait_until_hi_lo(clk, out_sosi.sync);
+ proc_common_wait_cross_clock_domain_latency(c_clk_period, c_mm_clk_period);
+ -- Readback crosslet info
+ FOR I IN 0 TO c_N_crosslets-1 LOOP
+ proc_mem_mm_bus_rd(I, mm_clk, mm_miso, mm_mosi); --offsets
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_crosslet_offsets(I) <= TO_UINT(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ END LOOP;
+ proc_mem_mm_bus_rd(15, mm_clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ rd_crosslet_step <= TO_UINT(mm_miso.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+ -- Verify that readback crosslet info is active crosslets_info
+ FOR I IN 0 TO c_N_crosslets-1 LOOP
+ ASSERT rd_crosslet_offsets(I) = exp_crosslets_info_rec.offset_arr(I) REPORT "Wrong active crosslet offset in output sync interval." SEVERITY ERROR;
+ END LOOP;
+ ASSERT rd_crosslet_step = exp_crosslets_info_rec.step REPORT "Wrong active crosslet step in output sync interval." SEVERITY ERROR;
+ END LOOP;
+
WAIT;
END PROCESS;
@@ -179,16 +224,16 @@ BEGIN
exp_sosi <= c_dp_sosi_rst;
WAIT UNTIL rising_edge(out_sosi.sop);
- exp_crosslets_info(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w) <= TO_UVEC(c_ch_sel_step, c_sdp_crosslets_index_w);
+ exp_crosslets_info_slv(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w) <= TO_UVEC(c_crosslet_step, c_sdp_crosslets_index_w);
FOR C IN 0 TO c_nof_ch_sel_col-1 LOOP
- exp_crosslets_info((C+1)*c_sdp_crosslets_index_w-1 DOWNTO C*c_sdp_crosslets_index_w) <= TO_UVEC(c_ch_sel_offsets(C) + v_sync_ix * c_ch_sel_step, c_sdp_crosslets_index_w);
+ exp_crosslets_info_slv((C+1)*c_sdp_crosslets_index_w-1 DOWNTO C*c_sdp_crosslets_index_w) <= TO_UVEC(c_crosslet_offsets(C) + v_sync_ix * c_crosslet_step, c_sdp_crosslets_index_w);
END LOOP;
FOR J IN 0 TO c_nof_ch_sel-1 LOOP
v_offset := J / (c_nof_ch_sel_col*c_nof_ch_sel_row);
v_col := J MOD c_nof_ch_sel_col;
v_row := (J/c_nof_ch_sel_col) MOD c_nof_ch_sel_row;
- v_k := c_nof_ch_sel_col * v_sync_ix * c_ch_sel_step;
+ v_k := c_nof_ch_sel_col * v_sync_ix * c_crosslet_step;
exp_sosi <= c_dp_sosi_rst;
exp_sosi.valid <= '1';
@@ -202,8 +247,8 @@ BEGIN
exp_sosi.eop <= '1';
END IF;
- exp_sosi.re <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
- exp_sosi.im <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
+ exp_sosi.re <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_crosslet_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
+ exp_sosi.im <= RESIZE_DP_DSP_DATA(TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_crosslet_offsets(v_offset) + v_col + v_row*2**5)(c_sdp_W_crosslet-1 DOWNTO 0));
proc_common_wait_some_cycles(clk, 1);
END LOOP;
@@ -219,7 +264,7 @@ BEGIN
ASSERT out_sosi.sop = exp_sosi.sop REPORT "Wrong out_sosi.sop" SEVERITY ERROR;
ASSERT out_sosi.eop = exp_sosi.eop REPORT "Wrong out_sosi.eop" SEVERITY ERROR;
ASSERT out_sosi.sync = exp_sosi.sync REPORT "Wrong out_sosi.sync" SEVERITY ERROR;
- ASSERT out_crosslets_info = exp_crosslets_info REPORT "Wrong out_crosslets_info" SEVERITY ERROR;
+ ASSERT out_crosslets_info_slv = exp_crosslets_info_slv REPORT "Wrong out_crosslets_info_slv" SEVERITY ERROR;
IF exp_sosi.valid = '1' THEN
ASSERT out_sosi.re = exp_sosi.re REPORT "Wrong out_sosi.re" SEVERITY ERROR;
ASSERT out_sosi.im = exp_sosi.im REPORT "Wrong out_sosi.im" SEVERITY ERROR;
@@ -249,7 +294,11 @@ BEGIN
in_sosi_arr => in_sosi_arr,
out_sosi => out_sosi,
- out_crosslets_info => out_crosslets_info
+ out_crosslets_info => out_crosslets_info_slv
);
+ -- Map crosslets_info slv to record for easier view in Wave window
+ exp_crosslets_info_rec <= func_sdp_map_crosslets_info(exp_crosslets_info_slv);
+ out_crosslets_info_rec <= func_sdp_map_crosslets_info(out_crosslets_info_slv);
+
END tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index d905af1d81408584d7240267628053baee46f4a5..7c2e39c5f1af617d757ee4fe815428bedac881ce 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -85,7 +85,7 @@ PACKAGE BODY tb_sdp_pkg IS
ASSERT in_hdr.app.sdp_source_info_fsub_type = exp_hdr.app.sdp_source_info_fsub_type REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_fsub_type" SEVERITY ERROR;
ASSERT in_hdr.app.sdp_source_info_payload_error = exp_hdr.app.sdp_source_info_payload_error REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_payload_error" SEVERITY ERROR;
ASSERT in_hdr.app.sdp_source_info_beam_repositioning_flag = exp_hdr.app.sdp_source_info_beam_repositioning_flag REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_beam_repositioning_flag" SEVERITY ERROR;
- ASSERT in_hdr.app.sdp_source_info_subband_calibrated_flag = exp_hdr.app.sdp_source_info_subband_calibrated_flag REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_subband_calibrated_flag" SEVERITY ERROR;
+ ASSERT in_hdr.app.sdp_source_info_weighted_subbands_flag = exp_hdr.app.sdp_source_info_weighted_subbands_flag REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_weighted_subbands_flag" SEVERITY ERROR;
ASSERT in_hdr.app.sdp_source_info_reserved = exp_hdr.app.sdp_source_info_reserved REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_reserved" SEVERITY ERROR;
ASSERT in_hdr.app.sdp_source_info_gn_id = exp_hdr.app.sdp_source_info_gn_id REPORT "Wrong " & g_statistics_type & " app.sdp_source_info_gn_id" SEVERITY ERROR;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 0c30fa8fb3a9d587e752b79d106fd4715073fec6..99ebd6f839aef1583d421cee33c40dfcca70927a 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -32,7 +32,7 @@
-- Usage:
-- > as 8
-- > run -a
--- . for header: view test_offload_sosi and the rx_sdp_stat_header.app fields
+-- . for header: view rx_offload_sosi and the rx_sdp_stat_header.app fields
-- . for payload: view rx_val, rx_data and exp_data
-------------------------------------------------------------------------------
@@ -54,17 +54,20 @@ USE work.tb_sdp_pkg.ALL;
ENTITY tb_sdp_statistics_offload IS
GENERIC (
-- All
- g_statistics_type : STRING := "SST";
+ g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
+ -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
+ g_statistics_type : STRING := "XST";
g_offload_time : NATURAL := 50;
g_reverse_word_order : BOOLEAN := TRUE; -- when TRUE then stream LSB word after MSB word.
- g_gn_index : NATURAL := 5; -- global node (GN) index, must be in range(O_rn, O_rn + N_rn), use > 0 to see effect of g_offload_time
+ g_gn_index : NATURAL := 4; -- global node (GN) index, must be in range(O_rn, O_rn + N_rn), use > 0 to see effect of g_offload_time
+ g_nof_sync : NATURAL := 3; -- simulate some sync periods, choose >= 3
-- BST
- g_beamset_id : NATURAL := 1; -- < c_sdp_N_beamsets
+ g_beamset_id : NATURAL := 0; -- < c_sdp_N_beamsets
-- XST
- g_O_rn : NATURAL := 4; -- GN index of first ring node (RN)
+ g_O_rn : NATURAL := 0; -- GN index of first ring node (RN)
g_N_rn : NATURAL := 8; -- <= c_sdp_N_rn_max = 16, number of nodes in ring
- g_P_sq : NATURAL := 4; -- <= c_sdp_P_sq
- g_nof_crosslets : NATURAL := 3; -- <= c_sdp_N_crosslets_max
+ g_P_sq : NATURAL := 9; -- <= c_sdp_P_sq, nof available correlator cells
+ g_nof_crosslets : NATURAL := 4; -- <= c_sdp_N_crosslets_max
g_crosslets_direction : NATURAL := 1 -- > 0 for crosslet transport in positive direction (incrementing RN), else 0 for negative direction
);
END tb_sdp_statistics_offload;
@@ -72,7 +75,8 @@ END tb_sdp_statistics_offload;
ARCHITECTURE tb OF tb_sdp_statistics_offload IS
CONSTANT c_dp_clk_period : TIME := 5 ns; -- 200 MHz
- CONSTANT c_mm_clk_period : TIME := 1 ns; -- 1 GHz to speed up simulation
+ CONSTANT c_mm_clk_period : TIME := sel_a_b(g_fast_mm_clk, 1 , 10) * 1 ns;
+ CONSTANT c_mm_dp_clk_ratio : NATURAL := sel_a_b(c_mm_clk_period > c_dp_clk_period, c_mm_clk_period / c_dp_clk_period, 1);
CONSTANT c_cross_clock_domain_latency : NATURAL := 20;
@@ -112,12 +116,14 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
CONSTANT c_beamlet_index : NATURAL := g_beamset_id * c_sdp_S_sub_bf;
- CONSTANT c_crosslets_info_rec : t_sdp_crosslets_info := (offset_arr => (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), step => 16);
+ --CONSTANT c_crosslets_info_rec : t_sdp_crosslets_info := (offset_arr => (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), step => 16);
+ CONSTANT c_crosslets_info_rec : t_sdp_crosslets_info := (offset_arr => (0, 1, 2, 3, 4, 5, 6, 10, 11, 12, 13, 14, 15, 16, 17), step => 7);
CONSTANT c_crosslets_info_slv : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) := func_sdp_map_crosslets_info(c_crosslets_info_rec);
-- Crosslets settings
CONSTANT c_mm_nof_crosslets : STD_LOGIC_VECTOR(c_sdp_nof_crosslets_reg_w-1 DOWNTO 0) := TO_UVEC(g_nof_crosslets, c_sdp_nof_crosslets_reg_w);
- CONSTANT c_mm_nof_packets : NATURAL := func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, g_P_sq, g_nof_crosslets);
+ CONSTANT c_nof_used_P_sq : NATURAL := smallest(g_N_rn / 2 + 1, g_P_sq); -- number of used correlator cells <= g_P_sq
+ CONSTANT c_rx_nof_packets : NATURAL := func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, c_nof_used_P_sq, g_nof_crosslets);
-- payload data
CONSTANT c_packet_size : NATURAL := c_nof_statistics_per_packet * c_sdp_W_statistic_sz;
@@ -142,10 +148,9 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
-- Define block timing.
CONSTANT c_bsn_init : NATURAL := 0;
-- Sufficient c_nof_block_per_sync to fit more than c_nof_packets_max offload packets per sync interval.
- CONSTANT c_nof_block_per_sync : NATURAL := 3 + ceil_div(c_offload_time, c_packet_size) + c_nof_packets_max;
+ CONSTANT c_nof_block_per_sync : NATURAL := 3 + c_mm_dp_clk_ratio * (ceil_div(c_offload_time, c_packet_size) + c_nof_packets_max);
CONSTANT c_nof_clk_per_block : NATURAL := c_packet_size;
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync * c_nof_clk_per_block;
- CONSTANT c_nof_sync : NATURAL := 3;
SIGNAL tb_end : STD_LOGIC := '0';
@@ -171,15 +176,15 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
SIGNAL in_crosslets_info_rec : t_sdp_crosslets_info;
SIGNAL in_crosslets_info_slv : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
- SIGNAL offload_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- 32 bit
- SIGNAL offload_sosi : t_dp_sosi;
- SIGNAL offload_siso : t_dp_siso := c_dp_siso_rst;
+ SIGNAL sdp_offload_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- 32 bit
+ SIGNAL sdp_offload_sosi : t_dp_sosi;
+ SIGNAL sdp_offload_siso : t_dp_siso := c_dp_siso_rst;
- SIGNAL test_offload_en : STD_LOGIC := '0';
- SIGNAL test_offload_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- 32 bit
- SIGNAL test_offload_sosi : t_dp_sosi := c_dp_sosi_rst;
- SIGNAL test_offload_sop_cnt : NATURAL := 0;
- SIGNAL test_offload_eop_cnt : NATURAL := 0;
+ SIGNAL rx_offload_en : STD_LOGIC := '0';
+ SIGNAL rx_offload_data : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- 32 bit
+ SIGNAL rx_offload_sosi : t_dp_sosi := c_dp_sosi_rst;
+ SIGNAL rx_offload_sop_cnt : NATURAL := 0;
+ SIGNAL rx_offload_eop_cnt : NATURAL := 0;
SIGNAL rx_hdr_fields_out : STD_LOGIC_VECTOR(1023 DOWNTO 0);
SIGNAL rx_hdr_fields_raw : STD_LOGIC_VECTOR(1023 DOWNTO 0) := (OTHERS => '0');
@@ -204,7 +209,7 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
SIGNAL source_rn : NATURAL; -- source node RN
SIGNAL source_gn : NATURAL; -- source node GN
- SIGNAL subband_calibrated_flag : STD_LOGIC := '0';
+ SIGNAL weighted_subbands_flag : STD_LOGIC := '0';
-- Signals used for starting processes.
SIGNAL ram_wr_data : STD_LOGIC_VECTOR(c_ram_buf.dat_w-1 DOWNTO 0);
@@ -212,19 +217,19 @@ ARCHITECTURE tb OF tb_sdp_statistics_offload IS
SIGNAL ram_wr_en : STD_LOGIC;
SIGNAL init_ram_done : STD_LOGIC := '0';
- SIGNAL in_sync_cnt : NATURAL := 0;
- SIGNAL test_sync_cnt : INTEGER := 0;
-
+ SIGNAL rx_sync_cnt : INTEGER := 0;
SIGNAL rx_packet_cnt : NATURAL := 0;
SIGNAL rx_valid_cnt : NATURAL := 0;
-- Debug signals, to view in Wave window
+ SIGNAL dbg_c_mm_dp_clk_ratio : NATURAL := c_mm_dp_clk_ratio;
SIGNAL dbg_c_nof_statistics_per_packet : NATURAL := c_nof_statistics_per_packet;
SIGNAL dbg_c_udp_total_length : NATURAL := c_udp_total_length;
SIGNAL dbg_c_ip_total_length : NATURAL := c_ip_total_length;
SIGNAL dbg_c_marker : NATURAL := c_marker;
SIGNAL dbg_c_nof_signal_inputs : NATURAL := c_nof_signal_inputs;
SIGNAL dbg_c_nof_packets_max : NATURAL := c_nof_packets_max;
+ SIGNAL dbg_c_rx_nof_packets : NATURAL := c_rx_nof_packets;
SIGNAL dbg_c_beamlet_index : NATURAL := c_beamlet_index;
SIGNAL dbg_c_packet_size : NATURAL := c_packet_size;
SIGNAL dbg_c_mm_user_size : NATURAL := c_mm_user_size;
@@ -249,7 +254,7 @@ BEGIN
mm_rst <= '1', '0' AFTER c_mm_clk_period*7;
mm_clk <= (NOT mm_clk) OR tb_end AFTER c_mm_clk_period/2;
- -- Fill ram with data, data is same as address number.
+ -- Fill statistics RAM with data, data is same as address number.
p_mm_statistics_ram : PROCESS
BEGIN
ram_wr_en <= '0';
@@ -269,10 +274,10 @@ BEGIN
WAIT;
END PROCESS;
- -- Start the input
+ -- Start the input when statistics RAM is initialized
p_in_sosi : PROCESS
BEGIN
- proc_common_wait_until_low(dp_clk, dp_rst);
+ proc_common_wait_until_high(mm_clk, init_ram_done);
proc_common_wait_some_cycles(dp_clk, 10);
in_sosi.bsn <= TO_DP_BSN(c_bsn_init);
in_sosi.valid <= '1';
@@ -309,12 +314,14 @@ BEGIN
-- Enable the statistics offload when input is running
p_enable_trigger : PROCESS
BEGIN
- proc_common_wait_until_high(mm_clk, init_ram_done);
+ -- Wait at least one sync interval, so that DUT can have measured the integration_interval
+ proc_common_wait_until_hi_lo(dp_clk, in_sosi.sync);
+ proc_common_wait_some_cycles(mm_clk, 10);
-- Enable common variable delay.
proc_mem_mm_bus_wr(c_reg_enable_mm_addr_enable, 1, mm_clk, enable_miso, enable_mosi);
proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
proc_common_wait_some_cycles(dp_clk, 1);
- test_offload_en <= '1';
+ rx_offload_en <= '1';
WAIT;
END PROCESS;
@@ -322,41 +329,39 @@ BEGIN
p_test_counters : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
- -- Count test_offload_sosi packets
- IF test_offload_sosi.sop = '1' THEN
- test_offload_sop_cnt <= test_offload_sop_cnt + 1; -- early count
+ -- Count rx_offload_sosi packets
+ IF rx_offload_sosi.sop = '1' THEN
+ rx_offload_sop_cnt <= rx_offload_sop_cnt + 1; -- early count
END IF;
- IF test_offload_sosi.eop = '1' THEN
- test_offload_eop_cnt <= test_offload_eop_cnt + 1; -- after count
+ IF rx_offload_sosi.eop = '1' THEN
+ rx_offload_eop_cnt <= rx_offload_eop_cnt + 1; -- after count
END IF;
END IF;
END PROCESS;
- -- Count sync intervals using in_sosi.sync, because there is no test_offload_sosi.sync
- in_sync_cnt <= in_sync_cnt + 1 WHEN rising_edge(dp_clk) AND in_sosi.sync = '1';
- test_sync_cnt <= in_sync_cnt - 1; -- optionally adjust to fit test_offload_sosi
+ rx_sync_cnt <= rx_sync_cnt + 1 WHEN rising_edge(dp_clk) AND rx_offload_sosi.sync = '1';
-- derive current X_sq correlator cell index
- cur_X_sq_cell <= (test_offload_eop_cnt / g_nof_crosslets) MOD g_P_sq;
+ cur_X_sq_cell <= (rx_offload_eop_cnt / g_nof_crosslets) MOD c_nof_used_P_sq;
-- derive current N_crosslets index index
- cur_crosslet <= test_offload_eop_cnt MOD g_nof_crosslets;
+ cur_crosslet <= rx_offload_eop_cnt MOD g_nof_crosslets;
-- derive source RN index
source_rn <= func_ring_nof_hops_to_source_rn(cur_X_sq_cell, rn_index, g_N_rn, g_crosslets_direction);
source_gn <= g_O_rn + source_rn;
- -- Prepare exp_sdp_stat_header before test_offload_sosi.eop, so that p_exp_sdp_stat_header can
- -- verify it at test_offload_sosi.eop.
+ -- Prepare exp_sdp_stat_header before rx_offload_sosi.eop, so that p_exp_sdp_stat_header can
+ -- verify it at rx_offload_sosi.eop.
-- For all statistics
- exp_dp_bsn <= TO_SVEC(c_bsn_init + 1 + test_sync_cnt * c_nof_block_per_sync, 64);
+ exp_dp_bsn <= TO_SVEC(c_bsn_init + 1 + rx_sync_cnt * c_nof_block_per_sync, 64);
-- SST
exp_sst_signal_input <= rx_packet_cnt + c_sdp_S_pn * gn_index;
-- BST
exp_bst_beamlet_index <= c_beamlet_index;
-- XST
-- . prepare expected XST subband_index
- exp_subband_index <= (c_crosslets_info_rec.offset_arr(cur_crosslet) + test_sync_cnt * c_crosslets_info_rec.step) MOD c_sdp_N_sub;
+ exp_subband_index <= (c_crosslets_info_rec.offset_arr(cur_crosslet) + rx_sync_cnt * c_crosslets_info_rec.step) MOD c_sdp_N_sub;
-- . prepare expected XST signal_input_A index
exp_xst_signal_input_A <= (gn_index MOD c_sdp_N_pn_max) * c_sdp_S_pn;
@@ -364,7 +369,7 @@ BEGIN
-- . prepare expected XST signal_input_B index, assume crosslet transport in positive direction
exp_xst_signal_input_B <= (source_gn MOD c_sdp_N_pn_max) * c_sdp_S_pn;
- p_exp_sdp_stat_header : PROCESS(subband_calibrated_flag, gn_index, exp_dp_bsn, exp_sst_signal_input, exp_subband_index, exp_xst_signal_input_A, exp_xst_signal_input_B)
+ p_exp_sdp_stat_header : PROCESS(weighted_subbands_flag, gn_index, exp_dp_bsn, exp_sst_signal_input, exp_subband_index, exp_xst_signal_input_A, exp_xst_signal_input_B)
BEGIN
-- eth header
exp_sdp_stat_header.eth.dst_mac <= c_sdp_stat_eth_dst_mac;
@@ -403,7 +408,7 @@ BEGIN
exp_sdp_stat_header.app.sdp_source_info_fsub_type <= slv(c_exp_sdp_info.fsub_type);
exp_sdp_stat_header.app.sdp_source_info_payload_error <= TO_UVEC(0, 1);
exp_sdp_stat_header.app.sdp_source_info_beam_repositioning_flag <= slv(c_exp_sdp_info.beam_repositioning_flag);
- exp_sdp_stat_header.app.sdp_source_info_subband_calibrated_flag <= slv(subband_calibrated_flag);
+ exp_sdp_stat_header.app.sdp_source_info_weighted_subbands_flag <= slv(weighted_subbands_flag);
exp_sdp_stat_header.app.sdp_source_info_reserved <= TO_UVEC(0, 3);
exp_sdp_stat_header.app.sdp_source_info_gn_id <= TO_UVEC(gn_index, 5);
@@ -431,25 +436,22 @@ BEGIN
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
- p_verify_header : PROCESS(test_offload_sosi)
+ p_verify_header : PROCESS(rx_offload_sosi)
VARIABLE v_bool : BOOLEAN;
BEGIN
- -- Prepare exp_sdp_stat_header before test_offload_sosi.eop, so that it can be verified at test_offload_sosi.eop
- IF test_offload_sosi.eop = '1' THEN
+ -- Prepare exp_sdp_stat_header before rx_offload_sosi.eop, so that it can be verified at rx_offload_sosi.eop
+ IF rx_offload_sosi.eop = '1' THEN
v_bool := func_sdp_verify_stat_header(g_statistics_type, rx_sdp_stat_header, exp_sdp_stat_header);
END IF;
END PROCESS;
-- Count number of packets in a sync interval.
- -- There is no active test_offload_sosi.sync to restart the count, therefore
- -- use in_sosi.sync to reset the count for the next test_offload_sosi.sync
- -- interval
p_rx_packet_cnt : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
- IF in_sosi.sync = '1' THEN
+ IF rx_offload_sosi.sync = '1' THEN
rx_packet_cnt <= 0;
- ELSIF test_offload_sosi.eop = '1' THEN
+ ELSIF rx_offload_sosi.eop = '1' THEN
rx_packet_cnt <= rx_packet_cnt + 1;
END IF;
END IF;
@@ -459,8 +461,8 @@ BEGIN
p_verify_nof_packets : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
- IF in_sosi.sync = '1' AND in_sync_cnt > 1 THEN
- ASSERT rx_packet_cnt = c_mm_nof_packets REPORT "Wrong number of packets per sync interval" SEVERITY ERROR;
+ IF rx_offload_sosi.sync = '1' AND rx_sync_cnt > 1 THEN
+ ASSERT rx_packet_cnt = c_rx_nof_packets REPORT "Wrong number of packets per sync interval" SEVERITY ERROR;
END IF;
END IF;
END PROCESS;
@@ -468,10 +470,10 @@ BEGIN
p_verify_nof_valid_per_packet : PROCESS(dp_clk)
BEGIN
IF rising_edge(dp_clk) THEN
- IF test_offload_sosi.eop = '1' THEN
+ IF rx_offload_sosi.eop = '1' THEN
rx_valid_cnt <= 0;
ASSERT rx_valid_cnt = c_packet_size - 1 REPORT "Wrong number of valid per packet" SEVERITY ERROR;
- ELSIF test_offload_sosi.valid = '1' THEN
+ ELSIF rx_offload_sosi.valid = '1' THEN
rx_valid_cnt <= rx_valid_cnt + 1;
END IF;
END IF;
@@ -491,8 +493,8 @@ BEGIN
BEGIN
IF rising_edge(dp_clk) THEN
rx_val <= '0';
- v_rx_data := TO_UINT(test_offload_sosi.data);
- IF test_offload_sosi.valid = '1' THEN
+ v_rx_data := TO_UINT(rx_offload_sosi.data);
+ IF rx_offload_sosi.valid = '1' THEN
IF g_statistics_type = "SST" THEN
-- Indices:
-- W: 0 1 2 3 4 5 ... 1022 1023
@@ -515,7 +517,7 @@ BEGIN
-- c_mm_data_size / c_sdp_W_statistic_sz = 1
U := S; -- range c_sdp_N_sub = 512 SST values
I := W MOD c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
- P := rx_packet_cnt; -- range c_nof_packets_max = 12 = c_sdp_S_pn Packets
+ P := rx_packet_cnt MOD c_rx_nof_packets; -- range c_nof_packets_max = 12 = c_sdp_S_pn packets
J := P MOD c_mm_nof_step; -- range c_mm_nof_step = 2 = c_sdp_Q_fft
v_exp_data := S * 4; -- due to c_mm_step_size = 4 = c_sdp_W_statistic_sz * c_sdp_Q_fft;
@@ -546,7 +548,7 @@ BEGIN
-- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_sdp_N_pol_bf
B := D; -- range c_sdp_S_sub_bf = 488 dual polarization BST values
I := W MOD c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
- P := rx_packet_cnt; -- range c_nof_packets_max = 1
+ P := rx_packet_cnt MOD c_rx_nof_packets; -- range c_nof_packets_max = 1 packet
v_exp_data := S * c_mm_user_size; -- c_mm_user_size = 2
IF g_reverse_word_order = FALSE THEN
@@ -557,7 +559,7 @@ BEGIN
ASSERT v_exp_data = v_rx_data REPORT "Wrong BST payload data Rx" SEVERITY ERROR;
ELSIF g_statistics_type = "XST" THEN
- -- . g_P_sq = 4
+ -- . c_nof_used_P_sq = 4
-- . g_nof_crosslets = 3
-- . c_sdp_N_crosslets_max = 7 --> c_mm_Xsq_span = 2**ceil_log2(7 * 576) = 4096
--
@@ -587,9 +589,9 @@ BEGIN
-- c_mm_data_size / c_sdp_W_statistic_sz = 2 = c_nof_complex
X := D; -- range c_sdp_X_sq = 144 complex XST values
I := W MOD c_mm_user_size; -- range c_mm_user_size = c_sdp_W_statistic_sz = 2 words
- P := rx_packet_cnt; -- range c_mm_nof_packets
+ P := rx_packet_cnt MOD c_rx_nof_packets; -- range c_nof_packets_max = c_nof_used_P_sq * g_nof_crosslets packets
J := P MOD g_nof_crosslets; -- range g_nof_crosslets
- K := P / g_nof_crosslets; -- range g_P_sq
+ K := P / g_nof_crosslets; -- range c_nof_used_P_sq
v_exp_data := S * c_mm_user_size; -- c_mm_user_size = 2
IF g_reverse_word_order = FALSE THEN
@@ -613,7 +615,7 @@ BEGIN
p_dp_end : PROCESS
BEGIN
proc_common_wait_until_high(mm_clk, init_ram_done);
- proc_common_wait_some_cycles(dp_clk, c_nof_sync * c_nof_clk_per_sync); -- will show some sync periods
+ proc_common_wait_some_cycles(dp_clk, g_nof_sync * c_nof_clk_per_sync); -- will show some sync periods
tb_end <= '1';
WAIT;
END PROCESS;
@@ -657,10 +659,10 @@ BEGIN
reg_hdr_dat_mosi => offload_rx_hdr_dat_mosi,
reg_hdr_dat_miso => offload_rx_hdr_dat_miso,
- snk_in_arr(0) => offload_sosi,
- snk_out_arr(0) => offload_siso,
+ snk_in_arr(0) => sdp_offload_sosi,
+ snk_out_arr(0) => sdp_offload_siso,
- src_out_arr(0) => test_offload_sosi,
+ src_out_arr(0) => rx_offload_sosi,
hdr_fields_out_arr(0) => rx_hdr_fields_out,
hdr_fields_raw_arr(0) => rx_hdr_fields_raw
@@ -695,8 +697,8 @@ BEGIN
-- ST
in_sosi => in_sosi,
- out_sosi => offload_sosi,
- out_siso => offload_siso,
+ out_sosi => sdp_offload_sosi,
+ out_siso => sdp_offload_siso,
-- Inputs from other blocks
eth_src_mac => c_eth_src_mac,
@@ -706,7 +708,7 @@ BEGIN
gn_index => gn_index,
ring_info => c_exp_ring_info,
sdp_info => c_exp_sdp_info,
- subband_calibrated_flag => subband_calibrated_flag,
+ weighted_subbands_flag => weighted_subbands_flag,
nof_crosslets => c_mm_nof_crosslets,
crosslets_info => in_crosslets_info_slv
);
@@ -715,7 +717,7 @@ BEGIN
ASSERT c_crosslets_info_rec = func_sdp_map_crosslets_info(c_crosslets_info_slv) REPORT "Error in func_sdp_map_crosslets_info()" SEVERITY FAILURE;
-- To view the 32 bit 1GbE offload data more easily in the Wave window
- offload_data <= offload_sosi.data(c_word_w-1 DOWNTO 0);
- test_offload_data <= test_offload_sosi.data(c_word_w-1 DOWNTO 0);
+ sdp_offload_data <= sdp_offload_sosi.data(c_word_w-1 DOWNTO 0);
+ rx_offload_data <= rx_offload_sosi.data(c_word_w-1 DOWNTO 0);
END tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
index a688d26acd7d88aba8f60ca51f3409710bf0c36e..e017be43252f7e9fc1151b48ae864e896902c597 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
@@ -38,10 +38,13 @@ ARCHITECTURE tb OF tb_tb_sdp_statistics_offload IS
BEGIN
-- -- All
+-- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
+-- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
-- g_statistics_type : STRING := "SST";
-- g_offload_time : NATURAL := 500;
-- g_reverse_word_order : BOOLEAN := TRUE -- when TRUE then stream LSB word after MSB word.
-- g_gn_index : NATURAL := 1; -- global node (GN) index, use > 0 to see effect of g_offload_time
+-- g_nof_sync : NATURAL := 3;
-- -- BST
-- g_beamset_id : NATURAL := 0;
-- -- XST
@@ -51,17 +54,21 @@ BEGIN
-- g_nof_crosslets : NATURAL := 1;
-- g_crosslets_direction : INTEGER := 1; -- +1 or -1
- u_sst : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("SST", 50, TRUE, 3, 0, 0);
- u_sst_no_reverse : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("SST", 50, FALSE, 3, 0, 0);
- u_bst_0 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("BST", 50, TRUE, 1, 0, 0);
- u_bst_0_no_reverse : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("BST", 50, FALSE, 1, 0, 0);
- u_bst_1 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("BST", 50, TRUE, 1, 1, 0);
- u_xst_P1 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 1, 0, 0, 16, 1, 1, 1);
- u_xst_P1_N3 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 1, 0, 0, 16, 1, 3, 1);
- u_xst_P9 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 1, 0, 0, 16, 9, 1, 1);
- u_xst_P9_N3 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 1, 0, 0, 16, 9, 3, 1);
- u_xst_P9_N3_no_reverse : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, FALSE, 1, 0, 0, 16, 9, 3, 1);
- u_xst_P9_N3_neg : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 1, 0, 0, 16, 9, 3, 0);
- u_xst_P8_N7_RN1_15 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP("XST", 50, TRUE, 1, 0, 1, 15, 8, 7, 0);
+ u_sst : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "SST", 50, TRUE, 3, 3);
+ u_sst_no_reverse : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "SST", 50, FALSE, 3, 3);
+ u_bst_0 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "BST", 50, TRUE, 1, 3);
+ u_bst_0_no_reverse : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "BST", 50, FALSE, 1, 3, 0);
+ u_bst_1 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "BST", 50, TRUE, 1, 3, 1);
+ u_xst_P1 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, TRUE, 1, 3, 0, 0, 16, 1, 1, 1);
+ u_xst_P1_N3 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, TRUE, 1, 3, 0, 0, 16, 1, 3, 1);
+ u_xst_P9 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, TRUE, 1, 3, 0, 0, 16, 9, 1, 1);
+ u_xst_P9_N3 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, TRUE, 1, 3, 0, 0, 16, 9, 3, 1);
+ u_xst_P9_N3_no_reverse : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, FALSE, 1, 3, 0, 0, 16, 9, 3, 1);
+ u_xst_P9_N3_neg_dir : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, TRUE, 1, 3, 0, 0, 16, 9, 3, 0);
+ u_xst_P8_N7_RN1_15 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, TRUE, 1, 3, 0, 1, 15, 8, 7, 0);
+ u_xst_P1_N7_RN0_7 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, TRUE, 3, 3, 0, 0, 8, 1, 7, 1); -- P_sq = 1 < N_rn/2+1 = 5
+ u_xst_P9_N7_RN0_7 : ENTITY work.tb_sdp_statistics_offload GENERIC MAP( TRUE, "XST", 50, TRUE, 3, 3, 0, 0, 8, 9, 7, 1); -- P_sq = 9 > N_rn/2+1 = 5
+ u_xst_P9_N4_RN0_7_slow_mm : ENTITY work.tb_sdp_statistics_offload GENERIC MAP(FALSE, "XST", 50, TRUE, 3, 3, 0, 0, 8, 9, 4, 1); -- P_sq = 9 > N_rn/2+1 = 5
+ u_xst_P9_N7_RN0_7_slow_mm : ENTITY work.tb_sdp_statistics_offload GENERIC MAP(FALSE, "XST", 50, TRUE, 3, 3, 0, 0, 8, 9, 7, 1); -- P_sq = 9 > N_rn/2+1 = 5
END tb;
diff --git a/applications/lofar2/model/data/Coefficient_16KHanning_16b.dat b/applications/lofar2/model/data/Coefficient_16KHanning_16b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..20c9f1b27db52abf1b319c9a8ff5cb0388be8aba
--- /dev/null
+++ b/applications/lofar2/model/data/Coefficient_16KHanning_16b.dat
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diff --git a/applications/lofar2/model/data/Coefficient_16KHanning_18b.dat b/applications/lofar2/model/data/Coefficient_16KHanning_18b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..55f5823fa873ae2dd512ced936037f3fac80004e
--- /dev/null
+++ b/applications/lofar2/model/data/Coefficient_16KHanning_18b.dat
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diff --git a/applications/lofar2/model/data/Coefficient_16KKaiser_16b.dat b/applications/lofar2/model/data/Coefficient_16KKaiser_16b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..a7d31bdfc7cd89b2588db0f2afe4f2604718a5a1
--- /dev/null
+++ b/applications/lofar2/model/data/Coefficient_16KKaiser_16b.dat
@@ -0,0 +1,16384 @@
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diff --git a/applications/lofar2/model/data/Coefficient_16KKaiser_18b.dat b/applications/lofar2/model/data/Coefficient_16KKaiser_18b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..694e2ac9d2f8999c1e2fb0adeb2d6ec14f006783
--- /dev/null
+++ b/applications/lofar2/model/data/Coefficient_16KKaiser_18b.dat
@@ -0,0 +1,16384 @@
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diff --git a/applications/lofar2/model/pfs_coeff_final.m b/applications/lofar2/model/pfs_coeff_final.m
index b8bb2d3f196d52abebd5285886a20594b8cd5309..406d47446157e75e96ff5e8c2ba87a3c84ff51c4 100644
--- a/applications/lofar2/model/pfs_coeff_final.m
+++ b/applications/lofar2/model/pfs_coeff_final.m
@@ -97,6 +97,8 @@
% h) Support loading and analysing LOFAR1 coefficients for comparison
% i) Support changing the half power subband band width via relative_bw = 1
% j) Save plots in plots/
+% k) Create FIR coefficients for 16b, 18b, 20b Kaiser (has sharp band edge)
+% and Hanning (has almost flat DC response for all poly phases)
close all;
clear all;
@@ -118,9 +120,13 @@ if not(reproduce_ftf)
relative_bw = 1;
% word size for coefficients
nof_bits = 16;
+ nof_bits = 18;
+ nof_bits = 20;
% window function for coefficients
kaiser_beta = 1;
- use_window = 'kaiser';
+ use_window = 'Kaiser';
+ %use_window = 'Hanning';
+ %use_window = 'Blackman';
% quantization method
use_uencode = false;
% support analysing LOFAR1 coefficients
@@ -132,7 +138,7 @@ else
relative_bw = 1;
nof_bits = 16;
kaiser_beta = 1;
- use_window = 'kaiser';
+ use_window = 'Kaiser';
use_uencode = true;
use_lofar1 = false;
end
@@ -190,16 +196,16 @@ phase_comp = unwrap(angle(fftshift_comp));
%% Compute windowed filter
-if strcmp(use_window, 'blackman')
+if strcmp(use_window, 'Blackman')
disp(sprintf('NOTE: use blackman window'));
h_window = blackman(M1);
-elseif strcmp(use_window, 'hanning')
+elseif strcmp(use_window, 'Hanning')
disp(sprintf('NOTE: use hanning window'));
h_window = hanning(M1);
-elseif strcmp(use_window, 'kaiser')
+elseif strcmp(use_window, 'Kaiser')
disp(sprintf('NOTE: use kaiser window (beta = %4.2f)', kaiser_beta));
h_window = kaiser(M1, kaiser_beta);
-else % default 'none'
+else % default 'None'
disp(sprintf('NOTE: use no window'));
h_window = ones(M1, 1); % no window is rectangular window
end
@@ -288,7 +294,12 @@ end
%% Save the coefficients
-fid = fopen('data/Coefficient_16KKaiser.dat','w');
+if reproduce_ftf
+ file_name = ['data/Coefficient_16KKaiser.dat'];
+else
+ file_name = ['data/Coefficient_16K', use_window, sprintf('_%db', nof_bits), '.dat']
+end
+fid = fopen(file_name,'w');
fprintf(fid,'%i\n', h_quant);
fclose(fid);
diff --git a/applications/lofar2/model/quantize.m b/applications/lofar2/model/quantize.m
new file mode 100644
index 0000000000000000000000000000000000000000..b404d54cca81fbecaa0fd90d0f803b7d52de6d7a
--- /dev/null
+++ b/applications/lofar2/model/quantize.m
@@ -0,0 +1,119 @@
+%-----------------------------------------------------------------------------
+%
+% Copyright (C) 2016
+% ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+% P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+%
+% This program is free software: you can redistribute it and/or modify
+% it under the terms of the GNU General Public License as published by
+% the Free Software Foundation, either version 3 of the License, or
+% (at your option) any later version.
+%
+% This program is distributed in the hope that it will be useful,
+% but WITHOUT ANY WARRANTY; without even the implied warranty of
+% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+% GNU General Public License for more details.
+%
+% You should have received a copy of the GNU General Public License
+% along with this program. If not, see <http://www.gnu.org/licenses/>.
+%
+%-----------------------------------------------------------------------------
+% Author: E. Kooistra, 2016
+%
+% quantize - quantize two's-complement input data
+% The output has nof_bits. Definitions:
+% . w = nof_bits (output data width)
+% . q_full_scale = 2**(w-1)
+% . q_max = q_full_scale - 1
+% . q_min = -q_full_scale
+% Magnitude and amplitude are synonyms for full scale.
+%
+% The quantization process involves the following steps:
+%
+% 1 scale the input data magnitude
+% 2 round the data
+% 3 handle overflow
+% 4 scale back to the original input data magnitude
+%
+% The in_full_scale internally maps to in_q_max. Choose in_q_max =
+% . q_full_scale : default, implies that in_data = in_full_scale will
+% just clip to q_max (or just wrap dependent on the
+% overflow option) and in_data = -in_full_scale will
+% map to q_min.
+% . q_max : in_data = in_full_scale will map to q_max, so no
+% overflow.
+% Typically use in_q_max = q_full_scale for data and use in_q_max =
+% q_max for coefficients. Use in_q_max < q_max if more backoff is
+% needed for some other reason.
+%
+% The 'rounding' determines how -0.5 is rounded:
+% . 'half_away': Round half away from zero, so +0.5 --> 1, -0.5 --> -1.
+% . 'half_up' : Round half up to +infinity, so +0.5 --> 1, -0.5 --> 0.
+%
+% Quantized data that is out of range -q_min : q_max gets treated
+% dependent on 'overflow':
+% . 'clip' : Clip to -q_min or q_max
+% . 'clip_sym' : Clip symmetrical to -q_max or q_max
+% . 'wrap' : Wrap within nof_bits signed integer range
+% . 'no_limit' : No range limit, so allow quantized data to get out
+% of range -q_min : q_max
+%
+% The output data range is scaled back to the original in_full_scale.
+
+function out_data = quantize(in_data, in_full_scale, nof_bits, rounding, overflow, in_q_max)
+
+q_bit = 1;
+q_full_scale = 2^(nof_bits-1); % maximum amplitude, magnitude
+q_max = q_full_scale-1;
+q_min = -q_full_scale;
+q_period = 2^nof_bits;
+
+% Default options
+if ~exist('rounding', 'var'); rounding = 'half_away'; end;
+if ~exist('overflow', 'var'); overflow = 'clip'; end;
+if ~exist('in_q_max', 'var'); in_q_max = q_full_scale; end;
+
+% Scale
+q_data = in_q_max * in_data/in_full_scale;
+
+% Round
+if strcmp(rounding, 'half_away')
+ q_data = round(q_data);
+else
+ q_data = floor(q_data + q_bit/2);
+end
+
+% Overflow
+if isreal(q_data)
+ q_re = q_data;
+else
+ q_re = real(q_data);
+ q_im = imag(q_data);
+end
+if strcmp(overflow, 'clip')
+ q_re(q_re>q_max) = q_max;
+ q_re(q_re<q_min) = q_min;
+ if ~isreal(q_data)
+ q_im(q_im>q_max) = q_max;
+ q_im(q_im<q_min) = q_min;
+ end
+elseif strcmp(overflow, 'clip_sym')
+ q_re(q_re> q_max) = q_max;
+ q_re(q_re<-q_max) = -q_max;
+ if ~isreal(q_data)
+ q_im(q_im> q_max) = q_max;
+ q_im(q_im<-q_max) = -q_max;
+ end
+elseif strcmp(overflow, 'wrap')
+ q_re = mod(q_re - q_min, q_period) + q_min;
+ if ~isreal(q_data)
+ q_im = mod(q_im - q_min, q_period) + q_min;
+ end
+end
+if isreal(q_data)
+ q_data = q_re;
+else
+ q_data = complex(q_re, q_im);
+end
+% Back to original full scale
+out_data = in_full_scale * q_data/q_full_scale;
diff --git a/applications/lofar2/model/run_pfir_coeff.m b/applications/lofar2/model/run_pfir_coeff.m
index 5c77cd51d8f3d7c2795968b922afa16543f6a87d..da526ae98a499551c2da7d7118a905e98da34fb8 100644
--- a/applications/lofar2/model/run_pfir_coeff.m
+++ b/applications/lofar2/model/run_pfir_coeff.m
@@ -127,8 +127,8 @@ elseif strcmp(application, 'lofar_subband')
L = 16;
coeff_w = 16;
q_full_scale = 2^(coeff_w-1);
- coeffLoad = load('data/Coefficient_16KKaiser.dat'); % column
- %coeffLoad = load('data/Coeffs16384Kaiser-quant.dat'); % column
+ %coeffLoad = load('data/Coefficient_16KKaiser.gold'); % column, created with pfs_coeff_final.m, DC gain = 0.995714
+ coeffLoad = load('data/Coeffs16384Kaiser-quant.dat'); % column, used in LOFAR1, DC gain = 0.994817
coeffLoad = coeffLoad'; % row with integer coefficients from file
config.dc_adjust = false;
if config.dc_adjust==false
@@ -379,6 +379,8 @@ end
title(['FIR filter coefficients for ', config.design, strNL]);
xlabel(['Taps 1:', num2str(L)]);
ylabel(['Channels 1:', num2str(N)]);
+file_name = ['plots/', file_name_prefix, '_coefficients.jpg'];
+print(file_name, '-djpeg')
%% Plot FIR-filter DC response per polyphase
if coeff_w>0
@@ -402,6 +404,8 @@ if coeff_w>0
xlabel(['Polyphase 1:', num2str(N)]);
ylabel(['Sum of taps (with median at zero is ', num2str(dc_polyphases_median), ')']);
grid on;
+ file_name = ['plots/', file_name_prefix, '_dc_response_per_polyphase.jpg'];
+ print(file_name, '-djpeg')
end
% Plot DC adjustment for LOFAR subband FIR-filter coefficients
@@ -433,7 +437,8 @@ grid on;
title(['Full FIR filter transfer function for ', config.design, strNL]);
xlabel('Frequency [channels]');
ylabel('Power [dB]');
-file_name = ['plots/', file_name_prefix, '_fir_transfer_function.jpg'];
+file_name = ['plots/', file_name_prefix, '_transfer_function_full.jpg'];
+print(file_name, '-djpeg')
% . zoomed plot in power
fig=fig+1;
@@ -447,7 +452,7 @@ grid on;
title(['Zoomed FIR filter transfer function for ', config.design, strNL]);
xlabel('Frequency [channels]');
ylabel('Power');
-file_name = ['plots/', file_name_prefix, '_fir_transfer_function.jpg'];
+file_name = ['plots/', file_name_prefix, '_transfer_function_zoom.jpg'];
print(file_name, '-djpeg')
% Plot FIR-filter amplitude and phase characteristic using freqz()
@@ -491,3 +496,6 @@ title(['FIR filter sum of power responses between channels for ', config.design,
xlabel('Frequency [channels]');
ylabel('Power');
+file_name = ['plots/', file_name_prefix, '_transfer_function_two_channels.jpg'];
+print(file_name, '-djpeg')
+
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index f7b14794bd4dc60e705c2263a5187d3c0239b101..b6a3ffaa8bd1bc4b4f2d08943836d6116f4872cd 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -78,7 +78,7 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
CONSTANT c_nof_stamp_regs : NATURAL := 2; -- date, time
CONSTANT c_nof_revision_id_regs : NATURAL := 3; -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
- CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
+ CONSTANT c_nof_design_note_regs : NATURAL := 12; -- note
CONSTANT c_info_reg : NATURAL := 0;
CONSTANT c_use_phy_reg : NATURAL := 1;
@@ -87,7 +87,7 @@ ARCHITECTURE rtl OF unb2b_board_system_info_reg IS
CONSTANT c_stamp_time_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
CONSTANT c_revision_id_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
CONSTANT c_design_note_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
- CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+ CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
diff --git a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
index fc5f4ccbf3e156fe51d24ed3009ccc25029f53c2..155cb99047c012ad57a0591c91e646438bde15ca 100644
--- a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+++ b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
@@ -130,7 +130,7 @@ peripherals:
access_mode: RO
- - field_name: design_note
field_description: "FPGA FW design note string."
- number_of_fields: 52
+ number_of_fields: 48
address_offset: 0x50
mm_width: 32
user_width: 8
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 20c4278e6951dfa1f2b727784a5ee751ebf87523..ccf97cf6edcd7345fea47e80d8c0b5727798a64b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -106,7 +106,7 @@ ENTITY ctrl_unb2c_board IS
----------------------------------------------------------------------------
-- Auxiliary Interface
----------------------------------------------------------------------------
- g_fpga_temp_high : NATURAL := 85;
+ g_fpga_temp_high : NATURAL := 100;
g_app_led_red : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_red
g_app_led_green : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_green
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
index d126fa5669ae9ee868f43c8490cf7106d9b23573..d4c6adc30d7d44a3b30c0703e58cebaeee452324 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
@@ -34,7 +34,7 @@ ENTITY mms_unb2c_fpga_sens IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_technology : NATURAL := c_tech_arria10;
- g_temp_high : NATURAL := 85
+ g_temp_high : NATURAL := 100
);
PORT (
-- Clocks and reset
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 303690fe7c0ea7c84fdda2821e70c589077f84e4..504a41b01ef2a995c716807d30ff72fb9808c380 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -78,7 +78,7 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
CONSTANT c_nof_design_name_regs : NATURAL := 13; -- design_name
CONSTANT c_nof_stamp_regs : NATURAL := 2; -- date, time
CONSTANT c_nof_revision_id_regs : NATURAL := 3; -- revision id, commit hash or id (hash: first 9 chars of the 40chars commit hash)
- CONSTANT c_nof_design_note_regs : NATURAL := 13; -- note
+ CONSTANT c_nof_design_note_regs : NATURAL := 12; -- note
CONSTANT c_info_reg : NATURAL := 0;
CONSTANT c_use_phy_reg : NATURAL := 1;
@@ -87,7 +87,7 @@ ARCHITECTURE rtl OF unb2c_board_system_info_reg IS
CONSTANT c_stamp_time_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + 1;
CONSTANT c_revision_id_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs;
CONSTANT c_design_note_offset : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs;
- CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs;
+ CONSTANT c_nof_regs : NATURAL := c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_revision_id_regs + c_nof_design_note_regs; -- = 2+13+2+3+12 = 32
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_regs),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
diff --git a/boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml b/boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml
index 067556ecdeea650ee7e6283d1fba4b61136e8df0..804d7b4d8636163eebd213560e9b81b650cb64b6 100644
--- a/boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml
+++ b/boards/uniboard2c/libraries/unb2c_board/unb2c_board.peripheral.yaml
@@ -130,7 +130,7 @@ peripherals:
access_mode: RO
- - field_name: design_note
field_description: "FPGA FW design note string."
- number_of_fields: 52
+ number_of_fields: 48
address_offset: 0x50
mm_width: 32
user_width: 8
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index 331c88ad51e35af98694cc004c3bb75a84cc4a16..3da862a891f2babd981d398dfe9ad1169de2ea42 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -19,6 +19,7 @@
* ICT diensten
* Python
* Jupyter
+* Graphana
* Zenodo DOI
@@ -94,6 +95,15 @@ source also radiohdl tools
Questasim had Exit code 5 = "Cannot create/open/find/read/write a design library"
during tb simulation load --> fixed by "sudo chmod a+w -R modelsim_altera_libs/18.0".
+> run_quartus unb1 &
+
+# Run command line synthesis
+run_qsys_pro unb2c lofar2_unb2c_sdp_station_full;
+gen_rom_mmap.py --avalon -d lofar2_unb2c_sdp_station -r lofar2_unb2c_sdp_station_full;
+run_reg unb2c lofar2_unb2c_sdp_station_full;
+run_qcomp unb2c lofar2_unb2c_sdp_station_full --clk=CLK;
+run_rbf unb2c lofar2_unb2c_sdp_station_full
+
*******************************************************************************
* RadioHDL with SVN
*******************************************************************************
@@ -150,6 +160,8 @@ gen_doc.py --fpga unb2b_minimal # result in build/unb2b/args/unb2b_minimal/doc/
* GIT references
*******************************************************************************
+https://ohshitgit.com/
+
difftool ?
mergetool ?
@@ -835,6 +847,24 @@ Works from home in VPN:
* LTS --> http://test-lcu2.astron.nl:8888/notebooks/ # = dop81
* DTS --> http://dts-lcu.astron.nl:8888/notebooks/
+XST indices:
+* DTS --> http://dts-lcu.astron.nl:8888/tree/python_test_scripts/XST_test/XSTs
+* DTS --> http://dts-lcu.astron.nl:8888/notebooks/python_test_scripts/XST_test/XST_index_test.ipynb
+
+
+Get XST results h5 file per crosslet on local machine from LCU2
+> ls22-statistics-writer -a dts-lcu.astron.nl
+
+Check of SDPTR op dop369 actief is met:
+> uals -u 10.87.2.36:4840 -p "0:Objects"
+
+
+*******************************************************************************
+* Graphana
+*******************************************************************************
+
+http://dts-lcu.astron.nl:3000/?orgId=1
+
*******************************************************************************
* Zenodo DOI
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 6153caf04a8c55f7cfdb2b77674b7407161229a4..d57813bc9a4de02174e449cce1cf367fc7049baa 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -41,6 +41,7 @@ PACKAGE common_pkg IS
CONSTANT c_1 : NATURAL := 1;
CONSTANT c_one : NATURAL := 1;
CONSTANT c_2 : NATURAL := 2;
+ CONSTANT c_dual : NATURAL := 2;
CONSTANT c_4 : NATURAL := 4;
CONSTANT c_quad : NATURAL := 4;
CONSTANT c_8 : NATURAL := 8;
@@ -386,6 +387,10 @@ PACKAGE common_pkg IS
FUNCTION func_slv_extract( a_w, b_w, c_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
FUNCTION func_slv_extract( a_w, b_w : NATURAL; vec : STD_LOGIC_VECTOR; sel : NATURAL) RETURN STD_LOGIC_VECTOR;
+ -- Number formats, see:
+ -- . https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
+ -- . https://support.astron.nl/confluence/display/L2M/L4+SDPFW+Decision%3A+Number+representation%2C+resizing+and+rounding
+
FUNCTION TO_UINT(vec : STD_LOGIC_VECTOR) RETURN NATURAL; -- beware: NATURAL'HIGH = 2**31-1, not 2*32-1, use TO_SINT to avoid warning
FUNCTION TO_SINT(vec : STD_LOGIC_VECTOR) RETURN INTEGER;
@@ -470,10 +475,31 @@ PACKAGE common_pkg IS
FUNCTION COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
FUNCTION COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
-
+
+ -- Convert between polar and rectangular coordinates
+ FUNCTION COMPLEX_RADIUS(re, im : REAL) RETURN REAL;
+ FUNCTION COMPLEX_RADIUS(re, im : INTEGER) RETURN REAL;
+
+ FUNCTION COMPLEX_PHASE( re, im : REAL; radians : BOOLEAN) RETURN REAL; -- phase in radians or degrees
+ FUNCTION COMPLEX_PHASE( re, im : INTEGER; radians : BOOLEAN) RETURN REAL; -- phase in radians or degrees
+ FUNCTION COMPLEX_PHASE( re, im : REAL) RETURN REAL; -- phase in degrees
+ FUNCTION COMPLEX_PHASE( re, im : INTEGER) RETURN REAL; -- phase in degrees
+
+ FUNCTION COMPLEX_RE(ampl, phase : REAL; radians : BOOLEAN) RETURN REAL; -- phase in radians or degrees
+ FUNCTION COMPLEX_RE(ampl, phase : INTEGER; radians : BOOLEAN) RETURN REAL; -- phase in radians or degrees
+ FUNCTION COMPLEX_RE(ampl, phase : REAL) RETURN REAL; -- phase in degrees
+ FUNCTION COMPLEX_RE(ampl, phase : INTEGER) RETURN REAL; -- phase in degrees
+
+ FUNCTION COMPLEX_IM(ampl, phase : REAL; radians : BOOLEAN) RETURN REAL; -- phase in radians or degrees
+ FUNCTION COMPLEX_IM(ampl, phase : INTEGER; radians : BOOLEAN) RETURN REAL; -- phase in radians or degrees
+ FUNCTION COMPLEX_IM(ampl, phase : REAL) RETURN REAL; -- phase in degrees
+ FUNCTION COMPLEX_IM(ampl, phase : INTEGER) RETURN REAL; -- phase in degrees
+
FUNCTION SHIFT_UVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR; -- < 0 shift left, > 0 shift right
FUNCTION SHIFT_SVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR; -- < 0 shift left, > 0 shift right
-
+
+ FUNCTION ROTATE_UVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR; -- < 0 rotate left, > 0 rotate right
+
FUNCTION offset_binary(a : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR;
FUNCTION truncate( vec : STD_LOGIC_VECTOR; n : NATURAL) RETURN STD_LOGIC_VECTOR; -- remove n LSBits from vec, so result has width vec'LENGTH-n
@@ -2051,6 +2077,9 @@ PACKAGE BODY common_pkg IS
RETURN sel_a_b(c_pos, c_real, -c_real);
END;
+ -- Fixed point format
+ -- . https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+Definition+of+fixed+point+numbers
+
FUNCTION TO_UREAL(uvec : STD_LOGIC_VECTOR; resolution_w : INTEGER) RETURN REAL IS
BEGIN
-- First convert as unsigned integer, then scale to real. See TO_SREAL()
@@ -2252,7 +2281,94 @@ PACKAGE BODY common_pkg IS
BEGIN
RETURN (a_im*b_re + a_re*b_im);
END;
+
+ FUNCTION COMPLEX_RADIUS(re, im : REAL) RETURN REAL IS
+ BEGIN
+ -- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0.
+ -- Must must use brackets (ABS()) to avoid compile error.
+ -- Alternative equivalent code would be: SQRT(re * re + im * im).
+ RETURN SQRT((ABS(re))**2.0 + (ABS(im))**2.0);
+ END;
+
+ FUNCTION COMPLEX_RADIUS(re, im : INTEGER) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_RADIUS(REAL(re), REAL(im));
+ END;
+
+ FUNCTION COMPLEX_PHASE(re, im : REAL; radians : BOOLEAN) RETURN REAL IS
+ BEGIN
+ IF radians = TRUE THEN
+ RETURN ATAN2(Y => im, X => re);
+ ELSE
+ RETURN ATAN2(Y => im, X => re) * 360.0 / MATH_2_PI;
+ END IF;
+ END;
+
+ FUNCTION COMPLEX_PHASE(re, im : INTEGER; radians : BOOLEAN) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_PHASE(REAL(re), REAL(im), radians);
+ END;
+
+ FUNCTION COMPLEX_PHASE(re, im : REAL) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_PHASE(re, im, FALSE);
+ END;
+
+ FUNCTION COMPLEX_PHASE(re, im : INTEGER) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_PHASE(REAL(re), REAL(im), FALSE);
+ END;
+
+ FUNCTION COMPLEX_RE(ampl, phase : REAL; radians : BOOLEAN) RETURN REAL IS
+ BEGIN
+ IF radians = TRUE THEN
+ RETURN ampl * COS(phase);
+ ELSE
+ RETURN ampl * COS(phase * MATH_2_PI / 360.0);
+ END IF;
+ END;
+
+ FUNCTION COMPLEX_RE(ampl, phase : INTEGER; radians : BOOLEAN) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_RE(REAL(ampl), REAL(phase), radians);
+ END;
+
+ FUNCTION COMPLEX_RE(ampl, phase : REAL) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_RE(ampl, phase, FALSE);
+ END;
+
+ FUNCTION COMPLEX_RE(ampl, phase : INTEGER) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_RE(REAL(ampl), REAL(phase), FALSE);
+ END;
+
+ FUNCTION COMPLEX_IM(ampl, phase : REAL; radians : BOOLEAN) RETURN REAL IS
+ BEGIN
+ IF radians = TRUE THEN
+ RETURN ampl * SIN(phase);
+ ELSE
+ RETURN ampl * SIN(phase * MATH_2_PI / 360.0);
+ END IF;
+ END;
+
+ FUNCTION COMPLEX_IM(ampl, phase : INTEGER; radians : BOOLEAN) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_IM(REAL(ampl), REAL(phase), radians);
+ END;
+
+ FUNCTION COMPLEX_IM(ampl, phase : REAL) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_IM(ampl, phase, FALSE);
+ END;
+
+ FUNCTION COMPLEX_IM(ampl, phase : INTEGER) RETURN REAL IS
+ BEGIN
+ RETURN COMPLEX_IM(REAL(ampl), REAL(phase), FALSE);
+ END;
+
+
FUNCTION SHIFT_UVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF shift < 0 THEN
@@ -2271,6 +2387,17 @@ PACKAGE BODY common_pkg IS
END IF;
END;
+ FUNCTION ROTATE_UVEC(vec : STD_LOGIC_VECTOR; shift : INTEGER) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ IF shift < 0 THEN
+ RETURN STD_LOGIC_VECTOR(ROTATE_LEFT(UNSIGNED(vec), -shift)); -- /<-- vec <--\
+ -- \---------->/
+ ELSE
+ RETURN STD_LOGIC_VECTOR(ROTATE_RIGHT(UNSIGNED(vec), shift)); -- /--> vec -->\
+ -- \<----------/
+ END IF;
+ END;
+
--
-- offset_binary() : maps offset binary to or from two-complement binary.
--
@@ -2385,7 +2512,8 @@ PACKAGE BODY common_pkg IS
END;
-------------------------------------------------------------------------------------------------
- -- Rounding schemes:
+ -- Rounding schemes
+ -- . https://support.astron.nl/confluence/display/L2M/L4+SDPFW+Decision%3A+Number+representation%2C+resizing+and+rounding
-------------------------------------------------------------------------------------------------
--
-- From https://en.wikipedia.org/wiki/Rounding it follows that there are three main
diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index cd704a27386792c8c272453232a1d58e996f5ce3..cecbb7dd0bbad81eac9217211dc4aecca805cf7a 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -59,7 +59,7 @@ ENTITY common_requantize IS
-- when 0 then no effect
g_lsb_round : BOOLEAN := TRUE; -- when TRUE round else truncate the input LSbits
g_lsb_round_clip : BOOLEAN := FALSE; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
- g_lsb_round_even : BOOLEAN := FALSE; -- when TRUE round to even, else round away from zero
+ g_lsb_round_even : BOOLEAN := TRUE; -- when TRUE round half to even, else round half away from zero
g_msb_clip : BOOLEAN := TRUE; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : BOOLEAN := FALSE; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
diff --git a/libraries/base/diag/src/vhdl/diag_wg.vhd b/libraries/base/diag/src/vhdl/diag_wg.vhd
index 53ab3a2a5daf43706991a4e810991280920e5dc8..a30ec8a8608aa3fce0021d2829869ddaf3116558 100644
--- a/libraries/base/diag/src/vhdl/diag_wg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg.vhd
@@ -21,7 +21,12 @@
-- Purpose: Sine waveform generator
-- Description:
--- . Based on diag_waveproc from LOFAR.
+-- . Based on diag_waveproc from LOFAR1.
+-- . Monitor the active WG ctrl:
+-- - WG ctrl.mode = off takes effect immediately
+-- - WG ctrl.ampl takes effect immediately
+-- - Changing WG ctrl.phase and ctrl.freq require a restart to take effect,
+-- to have synchronous phase relation between different WG.
-- Remarks:
-- . For WG sine periods that integer fit in the WG buffer size the carrier
-- wWave (CW) frequency is exact. For fractional WG frequencies, for which
@@ -73,6 +78,7 @@ ENTITY diag_wg IS
buf_rdval : IN STD_LOGIC;
ctrl : IN t_diag_wg;
+ mon_ctrl : OUT t_diag_wg;
out_ovr : OUT STD_LOGIC;
out_dat : OUT STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
@@ -117,8 +123,11 @@ ARCHITECTURE rtl OF diag_wg IS
SIGNAL state : state_enum;
SIGNAL nxt_state : state_enum;
+ SIGNAL prev_state : state_enum;
SIGNAL idle : STD_LOGIC;
+ SIGNAL i_mon_ctrl : t_diag_wg;
+ SIGNAL nxt_mon_ctrl : t_diag_wg;
SIGNAL nof_samples : STD_LOGIC_VECTOR(g_buf_addr_w DOWNTO 0); -- only use effective range of nof_samples+1
SIGNAL nxt_nof_samples : STD_LOGIC_VECTOR(g_buf_addr_w DOWNTO 0);
SIGNAL sample_cnt : NATURAL RANGE 0 TO 2**g_buf_addr_w-1;
@@ -126,7 +135,7 @@ ARCHITECTURE rtl OF diag_wg IS
SIGNAL sample_step : NATURAL RANGE 0 TO g_rate_factor;
SIGNAL nxt_sample_step : NATURAL;
SIGNAL init_repeat_done : STD_LOGIC;
-
+
SIGNAL phase : STD_LOGIC_VECTOR(ctrl.freq'LENGTH-1 DOWNTO 0);
SIGNAL nxt_phase : STD_LOGIC_VECTOR(phase'RANGE);
SIGNAL phase_step : STD_LOGIC_VECTOR(phase'RANGE);
@@ -159,12 +168,15 @@ ARCHITECTURE rtl OF diag_wg IS
BEGIN
+ mon_ctrl <= i_mon_ctrl;
+
registers : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
-- Internal registers.
nof_samples <= (OTHERS => '0');
state <= s_off;
+ prev_state <= s_off;
sample_cnt <= 0;
sample_step <= 0;
phase <= (OTHERS => '0');
@@ -172,6 +184,7 @@ BEGIN
init_phase_cnt <= 0;
init_sync <= '0';
-- Output registers.
+ i_mon_ctrl <= c_diag_wg_rst;
buf_addr <= (OTHERS => '0');
buf_rden <= '0';
out_ovr <= '0';
@@ -182,6 +195,7 @@ BEGIN
-- Internal registers.
nof_samples <= nxt_nof_samples;
state <= nxt_state;
+ prev_state <= state;
sample_cnt <= nxt_sample_cnt;
sample_step <= nxt_sample_step;
phase <= nxt_phase;
@@ -189,6 +203,7 @@ BEGIN
init_phase_cnt <= nxt_init_phase_cnt;
init_sync <= nxt_init_sync;
-- Output registers.
+ i_mon_ctrl <= nxt_mon_ctrl;
buf_addr <= nxt_buf_addr;
buf_rden <= nxt_buf_rden;
out_ovr <= nxt_out_ovr;
@@ -317,9 +332,23 @@ BEGIN
END IF;
END PROCESS;
-
ctrl_ampl <= '0' & ctrl.ampl;
+ p_mon_ctrl : PROCESS(i_mon_ctrl, ctrl, prev_state, state)
+ BEGIN
+ nxt_mon_ctrl <= i_mon_ctrl;
+ IF TO_UINT(ctrl.mode) = c_diag_wg_mode_off THEN
+ -- WG immediately goes into off state
+ nxt_mon_ctrl <= ctrl;
+ ELSIF prev_state = s_init AND prev_state /= state THEN
+ -- WG holds ctrl, when it goes into active state (s_single, s_repeat, or s_calc)
+ nxt_mon_ctrl <= ctrl;
+ END IF;
+ -- These MM ctrl fields always take effect immediately in all WG states
+ nxt_mon_ctrl.ampl <= ctrl.ampl;
+ nxt_mon_ctrl.nof_samples <= ctrl.nof_samples;
+ END PROCESS;
+
mult : ENTITY common_mult_lib.common_mult
GENERIC MAP (
g_technology => g_technology,
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index 63d02e992cb7517fae7ddb83bbaf8649f71e3e3d..0f4384df6182b31988bb8090ab3bcd95b4835b9b 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -66,6 +66,7 @@ ENTITY diag_wg_wideband IS
st_restart : IN STD_LOGIC;
st_ctrl : IN t_diag_wg;
+ st_mon_ctrl : OUT t_diag_wg;
out_ovr : OUT STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0); -- big endian, so first output sample in MSBit, MSData
out_dat : OUT STD_LOGIC_VECTOR(g_wideband_factor*g_buf_dat_w-1 DOWNTO 0);
@@ -88,7 +89,9 @@ ARCHITECTURE str OF diag_wg_wideband IS
TYPE t_buf_dat_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
TYPE t_buf_adr_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_addr_w-1 DOWNTO 0);
-
+
+ SIGNAL st_mon_ctrl_arr : t_diag_wg_arr(0 TO g_wideband_factor-1);
+
-- Use same address and data widths for both MM side and ST side memory ports
SIGNAL buf_rdval : STD_LOGIC_VECTOR(0 TO g_wideband_factor-1);
SIGNAL buf_rddata : t_buf_dat_arr(0 TO g_wideband_factor-1);
@@ -107,6 +110,8 @@ BEGIN
mm_rdval <= buf_rdval(0);
mm_rddata <= buf_rddata(0);
+ st_mon_ctrl <= st_mon_ctrl_arr(0); -- same for all g_wideband_factor waveform generators
+
gen_wg : FOR I IN 0 TO g_wideband_factor-1 GENERATE
-- Waveform buffer
u_buf : ENTITY common_lib.common_ram_crw_crw
@@ -157,7 +162,8 @@ BEGIN
buf_rden => st_rd(I),
ctrl => st_ctrl,
-
+ mon_ctrl => st_mon_ctrl_arr(I),
+
out_ovr => out_ovr( g_wideband_factor-I-1),
out_dat => out_dat((g_wideband_factor-I)*g_buf_dat_w-1 DOWNTO (g_wideband_factor-I-1)*g_buf_dat_w),
out_val => out_val( g_wideband_factor-I-1),
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
index 4043c51e1efa6bb2bcbf672b4f52ae97dba203a3..c6db7329b6ea11c94d3918d8b6f728518c06230e 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
@@ -62,7 +62,8 @@ ENTITY diag_wg_wideband_reg IS
sla_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
-- MM registers in st_clk domain
- st_wg_ctrl : OUT t_diag_wg -- WG control port
+ st_wg_ctrl : OUT t_diag_wg; -- WG control write port
+ st_mon_ctrl : IN t_diag_wg -- WG control read port, for currently active control
);
END diag_wg_wideband_reg;
@@ -80,6 +81,8 @@ ARCHITECTURE rtl OF diag_wg_wideband_reg IS
SIGNAL mm_wg_ctrl : t_diag_wg;
SIGNAL mm_wg_ctrl_mode_wr : STD_LOGIC;
+ SIGNAL mm_mon_ctrl : t_diag_wg;
+
-- Registers in st_clk domain
BEGIN
@@ -129,14 +132,14 @@ BEGIN
sla_out.rdval <= '1'; -- c_mm_reg.latency = 1
CASE TO_UINT(sla_in.address(c_mm_reg.adr_w-1 DOWNTO 0)) IS
WHEN 0 =>
- sla_out.rddata( 7 DOWNTO 0) <= mm_wg_ctrl.mode; -- = 8 = c_diag_wg_mode_w
- sla_out.rddata(31 DOWNTO 16) <= mm_wg_ctrl.nof_samples; -- = 16 = c_diag_wg_nof_samples_w
+ sla_out.rddata( 7 DOWNTO 0) <= mm_mon_ctrl.mode; -- = 8 = c_diag_wg_mode_w
+ sla_out.rddata(31 DOWNTO 16) <= mm_mon_ctrl.nof_samples; -- = 16 = c_diag_wg_nof_samples_w
WHEN 1 =>
- sla_out.rddata(15 DOWNTO 0) <= mm_wg_ctrl.phase; -- = 16 = c_diag_wg_phase_w
+ sla_out.rddata(15 DOWNTO 0) <= mm_mon_ctrl.phase; -- = 16 = c_diag_wg_phase_w
WHEN 2 =>
- sla_out.rddata(30 DOWNTO 0) <= mm_wg_ctrl.freq; -- = 31 = c_diag_wg_freq_w
+ sla_out.rddata(30 DOWNTO 0) <= mm_mon_ctrl.freq; -- = 31 = c_diag_wg_freq_w
WHEN 3 =>
- sla_out.rddata(16 DOWNTO 0) <= mm_wg_ctrl.ampl; -- = 17 = c_diag_wg_ampl_w
+ sla_out.rddata(16 DOWNTO 0) <= mm_mon_ctrl.ampl; -- = 17 = c_diag_wg_ampl_w
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
END IF;
@@ -161,6 +164,7 @@ BEGIN
------------------------------------------------------------------------------
no_cross : IF g_cross_clock_domain = FALSE GENERATE -- so mm_clk = st_clk
+ -- Write: MM to ST clock domain
p_st_clk : PROCESS(st_rst, st_clk)
BEGIN
IF st_rst='1' THEN
@@ -171,9 +175,13 @@ BEGIN
END IF;
END IF;
END PROCESS;
- END GENERATE; -- no_cross
- gen_cross : IF g_cross_clock_domain = TRUE GENERATE
+ -- Read: ST to MM clock domain
+ mm_mon_ctrl <= st_mon_ctrl;
+ END GENERATE;
+
+ -- Write: MM to ST clock domain
+ gen_cross_wr : IF g_cross_clock_domain = TRUE GENERATE
-- Assume diag WG mode gets written last, so when diag WG mode is transfered properly to the st_clk domain, then
-- the other diag WG control fields are stable as well
u_mode : ENTITY common_lib.common_reg_cross_domain
@@ -188,7 +196,7 @@ BEGIN
out_dat => st_wg_ctrl.mode,
out_new => OPEN -- when '1' then the out_dat was updated with in_dat due to in_new
);
- END GENERATE; -- gen_cross
+ END GENERATE;
-- The other wg_ctrl only take effect in diag_wg after the mode has been set
st_wg_ctrl.nof_samples <= mm_wg_ctrl.nof_samples;
@@ -196,4 +204,57 @@ BEGIN
st_wg_ctrl.phase <= mm_wg_ctrl.phase;
st_wg_ctrl.ampl <= mm_wg_ctrl.ampl;
+ -- Read: ST to MM clock domain
+ gen_cross_rd : IF g_cross_clock_domain = TRUE GENERATE
+ u_mode : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.mode,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.mode
+ );
+
+ u_nof_samples : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.nof_samples,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.nof_samples
+ );
+
+ u_freq : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.freq,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.freq
+ );
+
+ u_phase : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.phase,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.phase
+ );
+
+ u_ampl : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_dat => st_mon_ctrl.ampl,
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_mon_ctrl.ampl
+ );
+ END GENERATE;
+
END rtl;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
index 6c6b912bde048cc3c7897963943bbc0c694ae430..e2f291106471290e27750fb6485d82002f149158 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
@@ -80,7 +80,8 @@ END mms_diag_wg_wideband;
ARCHITECTURE str OF mms_diag_wg_wideband IS
- SIGNAL st_wg_ctrl : t_diag_wg;
+ SIGNAL st_wg_ctrl : t_diag_wg; -- write
+ SIGNAL st_mon_ctrl : t_diag_wg; -- read
BEGIN
@@ -100,7 +101,8 @@ BEGIN
sla_out => reg_miso,
-- MM registers in st_clk domain
- st_wg_ctrl => st_wg_ctrl
+ st_wg_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl
);
u_wg_wideband : ENTITY work.diag_wg_wideband
@@ -137,6 +139,7 @@ BEGIN
st_restart => st_restart,
st_ctrl => st_wg_ctrl,
+ st_mon_ctrl => st_mon_ctrl,
out_ovr => out_ovr,
out_dat => out_dat,
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index 47474faa2976ab7ae41a01136cecd27f837299cf..790e7d959bb6fba217a07a32f776ad3f01ffe029 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -566,7 +566,7 @@ PACKAGE BODY tb_diag_pkg IS
CONSTANT c_Q : REAL := COS(c_angle); -- Q = quadrature reference
CONSTANT c_dat : REAL := REAL(TO_SINT(in_dat));
CONSTANT c_phase : REAL := ARCTAN(accum_Q, accum_I + c_eps);
- CONSTANT c_ampl : REAL := SQRT((ABS(accum_I))**2.0 + (ABS(accum_Q))**2.0) * 2.0 / c_Nsamples;
+ CONSTANT c_ampl : REAL := COMPLEX_RADIUS(accum_I, accum_Q) * 2.0 / c_Nsamples;
BEGIN
IF rising_edge(dp_clk) THEN
-- Output reference I and Q for debugging in wave window
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
index ca3ba5ef9857a8cd8b962bf3fb7aa4f4a450445f..520bf017d12372c674ac709130a7c0fc01bde844 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
@@ -19,7 +19,7 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-
+
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -49,7 +49,7 @@ ARCHITECTURE tb OF tb_diag_wg IS
CONSTANT c_clk_freq : NATURAL := 200*10**6; -- Hz
CONSTANT c_clk_period : TIME := (10**9 / c_clk_freq) * 1 ns;
-
+
-- Default settings
CONSTANT c_buf : t_c_mem := (latency => 1,
adr_w => g_buf_adr_w,
@@ -59,86 +59,86 @@ ARCHITECTURE tb OF tb_diag_wg IS
CONSTANT c_buf_file : STRING := sel_a_b(c_buf.adr_w=11 AND c_buf.dat_w=18, "data/diag_sin_2048x18.hex",
sel_a_b(c_buf.adr_w=10 AND c_buf.dat_w=18, "data/diag_sin_1024x18.hex",
sel_a_b(c_buf.adr_w=10 AND c_buf.dat_w= 8, "data/diag_sin_1024x8.hex", "UNUSED")));
-
-
+
+
CONSTANT c_wg_nof_samples : NATURAL := c_buf.nof_dat; -- must be <= c_buf.nof_dat
CONSTANT c_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
-
+
CONSTANT c_buf_full_scale : NATURAL := 2**(g_buf_dat_w-1)-1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
CONSTANT c_wg_full_scale : NATURAL := 2**(g_wg_dat_w-1)-1;
CONSTANT c_ampl_norm : REAL := sel_a_b(g_wg_dat_w < g_buf_dat_w, REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
--CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
-
+
CONSTANT c_freq_unit : REAL := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
CONSTANT c_ampl_unit : REAL := c_diag_wg_ampl_unit*c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
CONSTANT c_phase_unit : REAL := c_diag_wg_phase_unit; -- ^= 1 degree
-
+
SIGNAL tb_end : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL restart : STD_LOGIC;
-
+
SIGNAL buf_rddat : STD_LOGIC_VECTOR(c_buf.dat_w-1 DOWNTO 0);
SIGNAL buf_rdval : STD_LOGIC;
SIGNAL buf_addr : STD_LOGIC_VECTOR(c_buf.adr_w-1 DOWNTO 0);
SIGNAL buf_rden : STD_LOGIC;
-
+
SIGNAL wg_ctrl : t_diag_wg;
-
+
SIGNAL wg_mode : NATURAL;
SIGNAL wg_freq : NATURAL;
SIGNAL wg_ampl : NATURAL;
SIGNAL wg_nof_samples : NATURAL;
SIGNAL wg_phase : NATURAL;
-
+
SIGNAL wg_ovr : STD_LOGIC;
SIGNAL wg_dat : STD_LOGIC_VECTOR(c_buf.dat_w-1 DOWNTO 0);
SIGNAL wg_val : STD_LOGIC;
SIGNAL wg_sync : STD_LOGIC;
-
+
BEGIN
rst <= '1', '0' AFTER c_clk_period/10;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
-
+
wg_ctrl.mode <= TO_UVEC(wg_mode, c_diag_wg_mode_w);
wg_ctrl.freq <= TO_UVEC(wg_freq, c_diag_wg_freq_w);
wg_ctrl.ampl <= TO_UVEC(wg_ampl, c_diag_wg_ampl_w);
wg_ctrl.nof_samples <= TO_UVEC(wg_nof_samples, c_diag_wg_nofsamples_w);
wg_ctrl.phase <= TO_UVEC(wg_phase, c_diag_wg_phase_w);
-
+
p_mm : PROCESS
BEGIN
tb_end <= '0';
restart <= '0';
wg_mode <= c_diag_wg_mode_off;
-
+
---------------------------------------------------------------------------
-- >>> Single, repeat mode
wg_nof_samples <= c_wg_nof_samples;
-
+
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
-- wg_freq <= INTEGER(0.5 * c_freq_unit);
-- wg_phase <= INTEGER(90.0 * c_phase_unit);
-
+
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
- -- this also applies to 2.0, 3.0, 4.0 etc
+ -- this also applies to 2.0, 3.0, 4.0 etc
-- wg_freq <= INTEGER(1.0 * c_freq_unit);
-- wg_phase <= INTEGER(45.0 * c_phase_unit);
-
+
-- Sinus Fs/16
wg_freq <= INTEGER(0.0625 * c_freq_unit);
--wg_freq <= INTEGER(511.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0); -- minimum value, yields Fs/c_freq_unit Hz sinus
wg_phase <= INTEGER(0.0 * c_phase_unit);
-
+
-- Sinus Fs/17
-- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
-- wg_phase <= INTEGER(0.0 * c_phase_unit);
@@ -146,13 +146,13 @@ BEGIN
wg_ampl <= INTEGER(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
-- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
-- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
-
+
WAIT UNTIL rising_edge(clk); -- align to rising edge
WAIT FOR c_clk_period*200;
-
+
---------------------------------------------------------------------------
-- >>> Select the different modes
-
+
-- CALC mode
wg_mode <= c_diag_wg_mode_calc;
restart <= '1';
@@ -164,14 +164,14 @@ BEGIN
restart <= '0';
WAIT FOR c_clk_period*3000;
--WAIT FOR 1 sec;
-
+
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
WAIT FOR c_clk_period*200;
-
+
-- SINGLE mode
wg_mode <= c_diag_wg_mode_single;
FOR I IN 0 TO 1 LOOP
@@ -181,7 +181,7 @@ BEGIN
WAIT FOR c_clk_period*c_buf.nof_dat;
WAIT FOR c_clk_period*300;
END LOOP;
-
+
-- REPEAT mode
wg_mode <= c_diag_wg_mode_repeat;
restart <= '1';
@@ -194,19 +194,19 @@ BEGIN
restart <= '0';
WAIT FOR c_clk_period*c_buf.nof_dat*5;
WAIT FOR c_clk_period*200;
-
+
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
WAIT FOR c_clk_period*200;
-
+
WAIT FOR c_clk_period*100;
tb_end <= '1';
WAIT;
END PROCESS;
-
+
-- Waveform buffer
u_buf : ENTITY common_lib.common_ram_crw_crw
GENERIC MAP (
@@ -231,7 +231,7 @@ BEGIN
rd_val_a => OPEN,
rd_val_b => buf_rdval
);
-
+
-- Waveform generator
u_wg : ENTITY work.diag_wg
GENERIC MAP (
@@ -258,6 +258,6 @@ BEGIN
out_val => wg_val,
out_sync => wg_sync
);
-
+
END tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index 5fe5307223af3b54807bffcd691fe80b30ea4130..3727020eac42f779201e4a94f5d043d0b93ec80d 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -19,7 +19,15 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-
+-- Purpose: Tb for WG
+-- Description: Verifies all WG modes.
+-- Usage:
+-- > as 10
+-- > run -all
+-- . Use select rigth mouse in Wave window on wg_dat and choose radix -->
+-- decimal and format --> analogue (automatic)
+-- . Observe state in diag_wg(0).
+
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
@@ -27,15 +35,6 @@ USE IEEE.MATH_REAL.ALL;
USE common_lib.common_pkg.ALL;
USE work.diag_pkg.ALL;
--- Usage:
--- > do wave_diag_wg_wideband.do
--- > run -all
---
--- . Use select rigth mouse in wave window on wg_dat and choose 'format --> analogue (automatic)'
--- . run 10 us to see CALC mode waveform output at proper automatic scale
--- . run 100 us to see SINGLE and REPEAT mode waveform output at proper automatic scale
-
-
ENTITY tb_diag_wg_wideband IS
GENERIC (
-- Wideband parameters
@@ -52,49 +51,51 @@ ARCHITECTURE tb OF tb_diag_wg_wideband IS
CONSTANT c_clk_freq : NATURAL := 200; -- MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
-
+
-- Default WG settings
CONSTANT c_buf_nof_dat : NATURAL := 2**g_buf_addr_w;
-
+
CONSTANT c_wg_gain_w : NATURAL := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
-- . use gain 2**0 = 1 to have fulle scale without clipping
-- . use gain 2**g_calc_gain_w > 1 to cause clipping
-
+
CONSTANT c_buf_full_scale : NATURAL := 2**(g_buf_dat_w-1)-1; -- The stored waveform range should also be [-c_buf_full_scale +c_buf_full_scale], so not including -c_buf_full_scale-1
CONSTANT c_wg_full_scale : NATURAL := 2**(g_wg_dat_w-1)-1;
CONSTANT c_ampl_norm : REAL := sel_a_b(g_wg_dat_w < g_buf_dat_w, REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1), 1.0);
--CONSTANT c_ampl_norm : REAL := REAL(c_wg_full_scale)/REAL(c_wg_full_scale+1); -- Use this if g_wg_dat_w < g_buf_dat_w, to avoid clipping
--CONSTANT c_ampl_norm : REAL := 1.0; -- Use this if g_wg_dat_w = g_buf_dat_w, because the stored waveform range is already -+c_buf_full_scale
--CONSTANT c_ampl_norm : REAL := REAL(c_buf_full_scale)/REAL(c_buf_full_scale+1); -- No need to use this, because the stored waveform range is already -+c_buf_full_scale
-
+
CONSTANT c_freq_unit : REAL := c_diag_wg_freq_unit; -- ^= c_clk_freq = Fs (sample frequency), assuming one sinus waveform in the buffer
CONSTANT c_ampl_unit : REAL := c_diag_wg_ampl_unit*c_ampl_norm; -- ^= Full Scale range [-c_wg_full_scale +c_wg_full_scale] without clipping
CONSTANT c_phase_unit : REAL := c_diag_wg_phase_unit; -- ^= 1 degree
-
+
-- Wideband WG settings
CONSTANT c_sample_period : TIME := (10**6 / (c_clk_freq*g_wideband_factor)) * 1 ps;
-
+
TYPE t_buf_dat_arr IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
-
+
SIGNAL tb_end : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL restart : STD_LOGIC;
-
+
SIGNAL wg_ctrl : t_diag_wg;
-
+ SIGNAL cur_ctrl : t_diag_wg;
+ SIGNAL mon_ctrl : t_diag_wg;
+
SIGNAL wg_mode : NATURAL;
SIGNAL wg_freq : NATURAL;
SIGNAL wg_ampl : NATURAL;
SIGNAL wg_nof_samples : NATURAL;
SIGNAL wg_phase : NATURAL;
-
+
-- Wideband WG output is big endian, so first output sample in MSBit, MSData
SIGNAL out_ovr : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
SIGNAL out_dat : STD_LOGIC_VECTOR(g_wideband_factor*g_buf_dat_w-1 DOWNTO 0);
SIGNAL out_val : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
SIGNAL out_sync : STD_LOGIC_VECTOR(g_wideband_factor -1 DOWNTO 0);
-
+
SIGNAL wg_ovr : STD_LOGIC_VECTOR(0 TO g_wideband_factor-1);
SIGNAL wg_dat : t_buf_dat_arr(0 TO g_wideband_factor-1);
SIGNAL wg_val : STD_LOGIC_VECTOR(0 TO g_wideband_factor-1);
@@ -106,47 +107,47 @@ ARCHITECTURE tb OF tb_diag_wg_wideband IS
SIGNAL sample_dat : STD_LOGIC_VECTOR(g_buf_dat_w-1 DOWNTO 0);
SIGNAL sample_val : STD_LOGIC;
SIGNAL sample_sync : STD_LOGIC;
-
+
BEGIN
rst <= '1', '0' AFTER c_clk_period/10;
clk <= NOT clk OR tb_end AFTER c_clk_period/2;
-
+
sample_clk <= NOT sample_clk OR tb_end AFTER c_sample_period/2;
-
+
wg_ctrl.mode <= TO_UVEC(wg_mode, c_diag_wg_mode_w);
wg_ctrl.freq <= TO_UVEC(wg_freq, c_diag_wg_freq_w);
wg_ctrl.ampl <= TO_UVEC(wg_ampl, c_diag_wg_ampl_w);
wg_ctrl.nof_samples <= TO_UVEC(wg_nof_samples, c_diag_wg_nofsamples_w);
wg_ctrl.phase <= TO_UVEC(wg_phase, c_diag_wg_phase_w);
-
+
p_mm : PROCESS
BEGIN
tb_end <= '0';
restart <= '0';
wg_mode <= c_diag_wg_mode_off;
-
+
---------------------------------------------------------------------------
-- >>> Single, repeat mode
wg_nof_samples <= c_buf_nof_dat; -- must be <= c_buf_nof_dat
-
+
-- >>> CALC mode
-- Cosinus with frequency Fs/2 (note sinus Fs/2 yields DC = 0)
-- wg_freq <= INTEGER(0.5 * c_freq_unit);
-- wg_phase <= INTEGER(90.0 * c_phase_unit);
-
+
-- Choosing 1.0*Fs to select Fs which is equivalent to DC, hence the DC value is then determined by phase
- -- this also applies to 2.0, 3.0, 4.0 etc
+ -- this also applies to 2.0, 3.0, 4.0 etc
-- wg_freq <= INTEGER(1.0 * c_freq_unit);
-- wg_phase <= INTEGER(45.0 * c_phase_unit);
-
+
-- Sinus Fs/16
wg_freq <= INTEGER(0.0625 * c_freq_unit);
--wg_freq <= INTEGER(511.0/512.0 * c_freq_unit);
wg_freq <= INTEGER(1.0/512.0 * c_freq_unit);
--wg_freq <= INTEGER(1.0); -- minimum value, yields Fs/c_freq_unit Hz sinus
wg_phase <= INTEGER(0.0 * c_phase_unit);
-
+
-- Sinus Fs/17
-- wg_freq <= INTEGER(1.0/17.0 * c_freq_unit);
-- wg_phase <= INTEGER(0.0 * c_phase_unit);
@@ -154,68 +155,115 @@ BEGIN
wg_ampl <= INTEGER(1.0 * c_ampl_unit); -- yields amplitude of c_wg_full_scale
-- wg_ampl <= INTEGER(1.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 1
-- wg_ampl <= INTEGER(3.0/REAL(c_wg_full_scale) * c_ampl_unit); -- yields amplitude of 3
-
+
WAIT UNTIL rising_edge(clk); -- align to rising edge
+ cur_ctrl <= wg_ctrl;
WAIT FOR c_clk_period*200;
-
+
---------------------------------------------------------------------------
-- >>> Select the different modes
-
+
-- CALC mode
wg_mode <= c_diag_wg_mode_calc;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected hold OFF)" SEVERITY ERROR;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new CALC)" SEVERITY ERROR;
+
WAIT FOR c_clk_period*3000;
+
+ wg_ampl <= INTEGER(0.5 * c_ampl_unit); -- change ampl immediately
+ WAIT FOR c_clk_period*1;
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new CALC ampl)" SEVERITY ERROR;
+
+ WAIT FOR c_clk_period*3000;
+
+ wg_phase <= INTEGER(90.0 * c_phase_unit); -- no change phase without restart
+ wg_freq <= INTEGER(0.5/512.0 * c_freq_unit); -- no change freq without restart
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected hold CALC phase and freq)" SEVERITY ERROR;
+
+ WAIT FOR c_clk_period*3000;
+
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new CALC phase and freq)" SEVERITY ERROR;
+
WAIT FOR c_clk_period*3000;
- --WAIT FOR 1 sec;
-
+
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
+ WAIT FOR c_clk_period*1;
+ cur_ctrl <= wg_ctrl; -- OFF mode takes effect immediately
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected immediately OFF)" SEVERITY ERROR;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected still OFF)" SEVERITY ERROR;
+
WAIT FOR c_clk_period*200;
-
+
-- SINGLE mode
wg_mode <= c_diag_wg_mode_single;
- FOR I IN 0 TO 1 LOOP
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected hold OFF)" SEVERITY ERROR;
+ FOR I IN 0 TO 3 LOOP
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new SINGLE)" SEVERITY ERROR;
WAIT FOR c_clk_period*c_buf_nof_dat;
WAIT FOR c_clk_period*300;
END LOOP;
-
+
-- REPEAT mode
wg_mode <= c_diag_wg_mode_repeat;
- restart <= '1';
- WAIT FOR c_clk_period*1;
- restart <= '0';
- WAIT FOR c_clk_period*c_buf_nof_dat*5;
- WAIT FOR c_clk_period*200;
- restart <= '1';
- WAIT FOR c_clk_period*1;
- restart <= '0';
- WAIT FOR c_clk_period*c_buf_nof_dat*5;
- WAIT FOR c_clk_period*200;
-
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected hold SINGLE)" SEVERITY ERROR;
+ FOR I IN 0 TO 1 LOOP
+ restart <= '1';
+ WAIT FOR c_clk_period*1;
+ restart <= '0';
+ cur_ctrl <= wg_ctrl;
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected new REPEAT)" SEVERITY ERROR;
+ WAIT FOR c_clk_period*c_buf_nof_dat*5;
+ WAIT FOR c_clk_period*200;
+ END LOOP;
+
-- OFF mode
wg_mode <= c_diag_wg_mode_off;
+ WAIT FOR c_clk_period*1;
+ cur_ctrl <= wg_ctrl; -- OFF mode takes effect immediately, no need for restart
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected immediately OFF)" SEVERITY ERROR;
restart <= '1';
WAIT FOR c_clk_period*1;
restart <= '0';
+ WAIT FOR c_clk_period*10;
+ ASSERT mon_ctrl = cur_ctrl REPORT "Wrong mon_ctrl (expected still OFF)" SEVERITY ERROR;
+
WAIT FOR c_clk_period*200;
-
+
WAIT FOR c_clk_period*100;
tb_end <= '1';
WAIT;
END PROCESS;
-
-
+
+
u_wideband_wg : ENTITY work.diag_wg_wideband
GENERIC MAP (
-- Wideband parameters
@@ -231,7 +279,7 @@ BEGIN
-- Memory-mapped clock domain
mm_rst => '0',
mm_clk => '0',
-
+
mm_wrdata => (OTHERS=>'0'),
mm_address => (OTHERS=>'0'),
mm_wr => '0',
@@ -243,15 +291,16 @@ BEGIN
st_rst => rst,
st_clk => clk,
st_restart => restart,
-
+
st_ctrl => wg_ctrl,
+ st_mon_ctrl => mon_ctrl,
out_ovr => out_ovr,
out_dat => out_dat,
out_val => out_val,
out_sync => out_sync
);
-
+
-- Map wideband WG out_* slv to wg_* arrays to ease interpretation in wave window
gen_wires : FOR I IN 0 TO g_wideband_factor-1 GENERATE
wg_ovr(I) <= out_ovr( g_wideband_factor-I-1);
@@ -259,8 +308,8 @@ BEGIN
wg_val(I) <= out_val( g_wideband_factor-I-1);
wg_sync(I) <= out_sync( g_wideband_factor-I-1);
END GENERATE;
-
- -- View WG output at the sample rate
+
+ -- View WG output at the sample rate
p_sample : PROCESS(sample_clk)
BEGIN
IF rising_edge(sample_clk) THEN
@@ -275,6 +324,6 @@ BEGIN
sample_sync <= wg_sync(sample_cnt);
END IF;
END PROCESS;
-
+
END tb;
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 34a2c49f89a64e30918443ee012c44e85d40f1d5..fdead4ddbcbdaa5a5e5274ef6dbb2a49e688a1da 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -300,6 +300,7 @@ test_bench_files =
tb/vhdl/tb_tb_dp_block_validate_channel.vhd
tb/vhdl/tb_tb_dp_bsn_align.vhd
tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+ tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
tb/vhdl/tb_tb_dp_concat.vhd
@@ -357,7 +358,6 @@ regression_test_vhdl =
tb/vhdl/tb_dp_latency_adapter.vhd
tb/vhdl/tb_dp_shiftreg.vhd
tb/vhdl/tb_dp_bsn_source.vhd
- tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_mms_dp_bsn_source.vhd
tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -372,6 +372,7 @@ regression_test_vhdl =
tb/vhdl/tb_tb_dp_block_from_mm.vhd
tb/vhdl/tb_tb_dp_block_validate_channel.vhd
tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+ tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
tb/vhdl/tb_tb_dp_concat.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 462d489dce2291ffc9e2e82d5603d9bba517bbb4..839b6eee681665af5afb5b3a144169868fc309c5 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -54,6 +54,12 @@
-- to preserve the order of the user parts (e.g. real and imag, X and Y
-- polarization) in a data block.
--
+-- . sync_in is an optional sync pulse to generate a sync signal at out_sosi.
+-- sync_in is not equal to start_pulse as start pulse indicates the start
+-- of a packet and not the start of a sync period.
+-- . For generating a bsn at out_sosi, the bsn_at_sync should contain the
+-- desired bsn at sync_in pulse. The bsn is increased in this component at
+-- every start_pulse.
-- --------------------------------------------------------------------------
LIBRARY IEEE,common_lib;
@@ -71,12 +77,15 @@ ENTITY dp_block_from_mm IS
g_nof_data : NATURAL;
g_word_w : NATURAL := c_word_w;
g_mm_rd_latency : NATURAL := 1; -- default 1 from rd_en to rd_val, use 2 to ease timing closure
- g_reverse_word_order : BOOLEAN := FALSE
+ g_reverse_word_order : BOOLEAN := FALSE;
+ g_bsn_w : NATURAL := 1
);
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
start_pulse : IN STD_LOGIC;
+ sync_in : IN STD_LOGIC := '0'; -- Must be syncronous with start_pulse.
+ bsn_at_sync : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
start_address : IN NATURAL;
mm_done : OUT STD_LOGIC;
mm_mosi : OUT t_mem_mosi;
@@ -92,16 +101,19 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
CONSTANT c_mem_size : NATURAL := g_step_size * g_nof_data;
TYPE t_reg IS RECORD
- busy : STD_LOGIC;
- sop : STD_LOGIC;
- eop : STD_LOGIC;
- user_index : NATURAL RANGE 0 TO g_user_size; -- word index in g_user_size
- data_index : NATURAL RANGE 0 TO g_data_size; -- default word order index in g_data_size
- word_index : NATURAL RANGE 0 TO g_data_size; -- default or reversed word order index in g_data_size
- step_address : NATURAL RANGE 0 TO c_mem_size; -- step address offset
+ busy : STD_LOGIC;
+ sync : STD_LOGIC;
+ sop : STD_LOGIC;
+ eop : STD_LOGIC;
+ sync_in_detected : STD_LOGIC;
+ bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ user_index : NATURAL RANGE 0 TO g_user_size; -- word index in g_user_size
+ data_index : NATURAL RANGE 0 TO g_data_size; -- default word order index in g_data_size
+ word_index : NATURAL RANGE 0 TO g_data_size; -- default or reversed word order index in g_data_size
+ step_address : NATURAL RANGE 0 TO c_mem_size; -- step address offset
END RECORD;
- CONSTANT c_reg_rst : t_reg := ('0', '0', '0', 0, 0, 0, 0);
+ CONSTANT c_reg_rst : t_reg := ('0', '0', '0', '0', '0', (OTHERS => '0'), 0, 0, 0, 0);
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
@@ -112,8 +124,12 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
SIGNAL r_sop_p : STD_LOGIC;
SIGNAL r_eop_p : STD_LOGIC;
+ SIGNAL r_sync_p : STD_LOGIC;
+ SIGNAL r_bsn_p : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
SIGNAL out_sop : STD_LOGIC;
SIGNAL out_eop : STD_LOGIC;
+ SIGNAL out_sync : STD_LOGIC;
+ SIGNAL out_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
BEGIN
@@ -122,18 +138,24 @@ BEGIN
mm_address_rev <= start_address + r.word_index + r.step_address; -- reverse word order per g_user_size
-- Take care of g_mm_rd_latency for out_sosi.sop and out_sosi.eop
- r_sop_p <= r.sop WHEN rising_edge(clk);
- r_eop_p <= r.eop WHEN rising_edge(clk);
- out_sop <= r.sop WHEN g_mm_rd_latency = 1 ELSE r_sop_p;
- out_eop <= r.eop WHEN g_mm_rd_latency = 1 ELSE r_eop_p;
-
- u_sosi : PROCESS(r, mm_miso, out_sop, out_eop)
+ r_sop_p <= r.sop WHEN rising_edge(clk);
+ r_eop_p <= r.eop WHEN rising_edge(clk);
+ r_sync_p <= r.sync WHEN rising_edge(clk);
+ r_bsn_p <= r.bsn WHEN rising_edge(clk);
+ out_sop <= r.sop WHEN g_mm_rd_latency = 1 ELSE r_sop_p;
+ out_eop <= r.eop WHEN g_mm_rd_latency = 1 ELSE r_eop_p;
+ out_sync <= r.sync WHEN g_mm_rd_latency = 1 ELSE r_sync_p;
+ out_bsn <= r.bsn WHEN g_mm_rd_latency = 1 ELSE r_bsn_p;
+
+ p_out_sosi : PROCESS(mm_miso, out_sop, out_eop, out_sync, out_bsn)
BEGIN
out_sosi <= c_dp_sosi_rst; -- To avoid Modelsim warnings on conversion to integer from unused fields.
out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(g_word_w-1 DOWNTO 0));
out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
out_sosi.sop <= out_sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
out_sosi.eop <= out_eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
+ out_sosi.sync <= out_sync; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sync can be used for output sync
+ out_sosi.bsn <= RESIZE_DP_BSN(out_bsn); -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.bsn can be used for output bsn
END PROCESS;
mm_done <= r.eop;
@@ -147,14 +169,15 @@ BEGIN
END IF;
END PROCESS;
- p_comb : PROCESS(r, start_pulse, out_siso, mm_address, mm_address_rev, last_mm_address)
+ p_comb : PROCESS(r, start_pulse, sync_in, bsn_at_sync, out_siso, mm_address, mm_address_rev, last_mm_address)
VARIABLE v : t_reg;
VARIABLE v_base : NATURAL;
VARIABLE v_reverse : NATURAL;
BEGIN
v := r;
- v.sop := '0';
- v.eop := '0';
+ v.sop := '0';
+ v.eop := '0';
+ v.sync := '0';
-- Use default c_mem_mosi_rst to avoid Warning: (vsim-8684) No drivers exist on out port .wr, .wrdata
mm_mosi <= c_mem_mosi_rst;
@@ -162,6 +185,10 @@ BEGIN
IF r.busy = '0' AND start_pulse = '1' THEN
-- initiate next output block
v.busy := '1';
+ IF sync_in = '1' THEN
+ v.sync_in_detected := '1';
+ v.bsn := bsn_at_sync;
+ END IF;
END IF;
-- use v.busy, instead of r.busy, to allow start_pulse at mm_done, to
@@ -189,6 +216,12 @@ BEGIN
-- check start of output block
IF r.data_index = 0 AND r.step_address = 0 THEN
v.sop := '1';
+ IF v.sync_in_detected = '1' THEN
+ v.sync := '1';
+ v.sync_in_detected := '0';
+ ELSE
+ v.bsn := INCR_UVEC(r.bsn, 1);
+ END IF;
END IF;
-- check end of output block
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index 0ac01ec489d22cf6d3e2843e7df9e9e6243e2150..86189e162cc1f7c9ccc80c94795eac7f32d9a7f4 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -41,7 +41,8 @@ ENTITY dp_block_from_mm_dc IS
g_step_size : NATURAL;
g_nof_data : NATURAL;
g_word_w : NATURAL := c_word_w;
- g_reverse_word_order : BOOLEAN := FALSE
+ g_reverse_word_order : BOOLEAN := FALSE;
+ g_bsn_w : NATURAL := 1
);
PORT (
-- mm_clk domain
@@ -53,6 +54,8 @@ ENTITY dp_block_from_mm_dc IS
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
start_pulse : IN STD_LOGIC;
+ sync_in : IN STD_LOGIC := '0'; -- Must be syncronous with start_pulse.
+ bsn_at_sync : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
start_address : IN NATURAL;
done : OUT STD_LOGIC;
out_sosi : OUT t_dp_sosi;
@@ -62,25 +65,35 @@ END dp_block_from_mm_dc;
ARCHITECTURE str OF dp_block_from_mm_dc IS
- CONSTANT c_packet_size : NATURAL := g_nof_data * g_data_size; -- 512 * 2 = 1024 words.
- CONSTANT c_fifo_size : NATURAL := c_packet_size * 2;
+ CONSTANT c_packet_size : NATURAL := g_nof_data * g_data_size;
+
+ -- Fit one packet in FIFO, and less than two, to avoid filling the FIFO with
+ -- multiple packets in case writing FIFO (mm_clk) is faster than reading
+ -- FIFO (dp_clk).
+ CONSTANT c_fifo_fill : NATURAL := c_packet_size;
+ CONSTANT c_fifo_size : NATURAL := c_packet_size + c_packet_size/2;
CONSTANT c_start_addr_w : NATURAL := c_natural_w;
CONSTANT c_delay_len : NATURAL := c_meta_delay_len;
SIGNAL mm_fifo_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL mm_fifo_siso : t_dp_siso;
SIGNAL start_pulse_dly : STD_LOGIC_VECTOR(0 TO c_delay_len) := (OTHERS => '0');
+ SIGNAL sync_dly : STD_LOGIC_VECTOR(0 TO c_delay_len) := (OTHERS => '0');
SIGNAL mm_start_pulse : STD_LOGIC := '0';
+ SIGNAL mm_sync : STD_LOGIC := '0';
SIGNAL mm_done : STD_LOGIC := '0';
+ SIGNAL mm_bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL start_address_slv : STD_LOGIC_VECTOR(c_start_addr_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL mm_start_address_slv : STD_LOGIC_VECTOR(c_start_addr_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL mm_start_address : NATURAL := 0;
BEGIN
- -- Use start_pulse_dly to make sure mm_start_address_slv is stable before
+ -- Use sync/start_pulse_dly to make sure mm_start_address_slv is stable before
-- mm_start_pulse, also when mm_clk is faster than dp_clk (e.g. in sim).
start_pulse_dly(0) <= start_pulse;
start_pulse_dly(1 TO c_delay_len) <= start_pulse_dly(0 TO c_delay_len-1) WHEN rising_edge(dp_clk);
+ sync_dly(0) <= sync_in;
+ sync_dly(1 TO c_delay_len) <= sync_dly(0 TO c_delay_len-1) WHEN rising_edge(dp_clk);
u_common_spulse_start_pulse : ENTITY common_lib.common_spulse
PORT MAP (
@@ -92,6 +105,16 @@ BEGIN
out_pulse => mm_start_pulse
);
+ u_common_spulse_sync : ENTITY common_lib.common_spulse
+ PORT MAP (
+ in_rst => dp_rst,
+ in_clk => dp_clk,
+ in_pulse => sync_dly(c_delay_len),
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_pulse => mm_sync
+ );
+
u_common_spulse_mm_done : ENTITY common_lib.common_spulse
PORT MAP (
in_rst => mm_rst,
@@ -110,17 +133,31 @@ BEGIN
g_delay_len => c_meta_delay_len
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
+ rst => mm_rst,
+ clk => mm_clk,
din => start_address_slv,
dout => mm_start_address_slv
);
+ u_common_async_slv_bsn : ENTITY common_lib.common_async_slv
+ GENERIC MAP (
+ g_delay_len => c_meta_delay_len
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ din => bsn_at_sync,
+ dout => mm_bsn_at_sync
+ );
+
u_dp_fifo_fill_eop : ENTITY work.dp_fifo_fill_eop
GENERIC MAP (
g_use_dual_clock => TRUE,
g_data_w => c_word_w,
- g_fifo_fill => c_packet_size,
+ g_bsn_w => g_bsn_w,
+ g_use_bsn => TRUE,
+ g_use_sync => TRUE,
+ g_fifo_fill => c_fifo_fill,
g_fifo_size => c_fifo_size
)
PORT MAP (
@@ -143,13 +180,16 @@ BEGIN
g_step_size => g_step_size,
g_nof_data => g_nof_data,
g_word_w => g_word_w,
- g_reverse_word_order => g_reverse_word_order
+ g_reverse_word_order => g_reverse_word_order,
+ g_bsn_w => g_bsn_w
)
PORT MAP (
clk => mm_clk,
rst => mm_rst,
start_pulse => mm_start_pulse,
+ sync_in => mm_sync,
+ bsn_at_sync => mm_bsn_at_sync,
start_address => mm_start_address,
mm_done => mm_done,
mm_mosi => mm_mosi,
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index 3f83496de73c2a7b8d9d07ff013ebffd164be04a..125a82f533fd942e12b3da0f7331e7a7973881c7 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -118,7 +118,7 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
TYPE t_bsn_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
TYPE t_channel_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_channel_w-1 DOWNTO 0);
- TYPE t_adr_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_mem_ram.adr_w-1 DOWNTO 0);
+ TYPE t_adr_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_ram_buf.adr_w-1 DOWNTO 0);
TYPE t_filled_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_buffer_nof_blocks-1 DOWNTO 0);
-- State
@@ -136,7 +136,7 @@ ARCHITECTURE rtl OF dp_bsn_align_v2 IS
dp_sosi : t_dp_sosi;
-- p_read
rd_blk_pointer : INTEGER; -- use integer to detect need to wrap to natural
- rd_offset : STD_LOGIC_VECTOR(c_mem_ram.adr_w-1 DOWNTO 0);
+ rd_offset : STD_LOGIC_VECTOR(c_ram_buf.adr_w-1 DOWNTO 0);
rd_copi : t_mem_copi;
fill_cipo_arr : t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0); -- used combinatorial to contain rd_cipo_arr from buffer or replacement data
out_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0); -- hold BSN until next sop, for easy view in Wave window
@@ -251,7 +251,7 @@ BEGIN
-- p_write
IF in_sosi_arr_p(I).valid = '1' THEN
-- . increment address during block
- v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(INCR_UVEC(r.wr_copi_arr(I).address(c_mem_ram.adr_w-1 DOWNTO 0), 1));
+ v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(INCR_UVEC(r.wr_copi_arr(I).address(c_ram_buf.adr_w-1 DOWNTO 0), 1));
v.wr_copi_arr(I).wr := '1';
v.wr_copi_arr(I).wrdata := RESIZE_MEM_SDATA(in_sosi_arr_p(I).data);
END IF;
@@ -260,8 +260,8 @@ BEGIN
-- . set address at start of block
w.blk_pointer_slv := in_sosi_arr_p(I).bsn(c_blk_pointer_w-1 DOWNTO 0);
w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv);
- -- . resize to c_mem_ram.adr_w
- v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(RESIZE_UVEC(w.product_slv, c_mem_ram.adr_w));
+ -- . resize to c_ram_buf.adr_w
+ v.wr_copi_arr(I).address := RESIZE_MEM_ADDRESS(RESIZE_UVEC(w.product_slv, c_ram_buf.adr_w));
-- . set filled flag at sop, so assume rest of block will follow in time
v.filled_arr(I)(TO_UINT(w.blk_pointer_slv)) := '1';
@@ -292,7 +292,7 @@ BEGIN
-- . update read address of read block pointer
w.blk_pointer_slv := TO_UVEC(v.rd_blk_pointer, c_blk_pointer_w);
w.product_slv := MULT_UVEC(w.blk_pointer_slv, c_block_size_slv);
- v.rd_offset := RESIZE_UVEC(w.product_slv, c_mem_ram.adr_w);
+ v.rd_offset := RESIZE_UVEC(w.product_slv, c_ram_buf.adr_w);
-- . issue mm_sosi, if there is output ready to be read, indicated by filled reference block
IF r.filled_arr(0)(v.rd_blk_pointer) = '1' THEN
@@ -343,7 +343,7 @@ BEGIN
-- Do the output via the MM interface
--------------------------------------------------------------------------
-- . adjust the rd address to the current buffer output block
- -- sum yields c_mem_ram.adr_w bits, because left operand in ADD_UVECdetermines width
+ -- sum yields c_ram_buf.adr_w bits, because left operand in ADD_UVECdetermines width
v.rd_copi := mm_copi;
v.rd_copi.address := RESIZE_MEM_ADDRESS(ADD_UVEC(r.rd_offset, mm_copi.address));
@@ -357,7 +357,7 @@ BEGIN
-- Do the output via the DP streaming interface
--------------------------------------------------------------------------
-- . adjust the rd address
- -- sum yields c_mem_ram.adr_w bits, because left operand in ADD_UVECdetermines width
+ -- sum yields c_ram_buf.adr_w bits, because left operand in ADD_UVECdetermines width
v.rd_copi := dp_copi;
v.rd_copi.address := RESIZE_MEM_ADDRESS(ADD_UVEC(r.rd_offset, dp_copi.address));
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index 0d5b21ea615ec19a28357937cc811b4c43b23ddc..22099bf168a065ce4064308f9e30c4a84b12f1e0 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -111,29 +111,31 @@ USE work.dp_stream_pkg.ALL;
ENTITY dp_bsn_sync_scheduler IS
GENERIC (
- g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
- g_pipeline : NATURAL := 1 -- use '1' on HW, use '0' for easier debugging in Wave window
+ g_bsn_w : NATURAL := c_dp_stream_bsn_w;
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_ctrl_interval_size_min : NATURAL := 1; -- Minimum interval size to use if MM write interval size is set too small.
+ g_pipeline : NATURAL := 1 -- use '1' on HW, use '0' for easier debugging in Wave window
);
PORT (
- rst : IN STD_LOGIC;
- clk : IN STD_LOGIC;
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
-- M&C
- ctrl_enable : IN STD_LOGIC;
- ctrl_enable_evt : IN STD_LOGIC;
- ctrl_interval_size : IN NATURAL;
- ctrl_start_bsn : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
- mon_current_input_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- mon_input_bsn_at_sync : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- mon_output_enable : OUT STD_LOGIC;
- mon_output_sync_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ ctrl_enable : IN STD_LOGIC;
+ ctrl_enable_evt : IN STD_LOGIC;
+ ctrl_interval_size : IN NATURAL;
+ ctrl_start_bsn : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ mon_current_input_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ mon_input_bsn_at_sync : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ mon_output_enable : OUT STD_LOGIC;
+ mon_output_interval_size : OUT NATURAL;
+ mon_output_sync_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
-- Streaming
- in_sosi : IN t_dp_sosi;
- out_sosi : OUT t_dp_sosi;
- out_start : OUT STD_LOGIC; -- pulse at out_sosi.sync at ctrl_start_bsn
- out_enable : OUT STD_LOGIC -- for tb verification purposes
+ in_sosi : IN t_dp_sosi;
+ out_sosi : OUT t_dp_sosi;
+ out_start : OUT STD_LOGIC; -- pulse at out_sosi.sync at ctrl_start_bsn
+ out_enable : OUT STD_LOGIC -- for tb verification purposes
);
END dp_bsn_sync_scheduler;
@@ -158,7 +160,7 @@ ARCHITECTURE rtl OF dp_bsn_sync_scheduler IS
output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
END RECORD;
- CONSTANT c_reg_rst : t_reg := ('0', '0', 0, 0, (OTHERS=>'0'), (OTHERS=>'0'), 0, 0, 0, 0, 0, '1', '0', '0', (OTHERS=>'0'));
+ CONSTANT c_reg_rst : t_reg := ('0', '0', 0, g_ctrl_interval_size_min, (OTHERS=>'0'), (OTHERS=>'0'), 0, 0, 0, 0, 0, '1', '0', '0', (OTHERS=>'0'));
-- Local registers
SIGNAL r : t_reg;
@@ -173,10 +175,11 @@ BEGIN
ASSERT g_block_size >= 2 REPORT "g_block_size must be >= 2." SEVERITY FAILURE;
-- Capture monitoring info
- mon_current_input_bsn <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sop = '1';
- mon_input_bsn_at_sync <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sync = '1';
- mon_output_enable <= r.output_enable;
- mon_output_sync_bsn <= r.output_sync_bsn;
+ mon_current_input_bsn <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sop = '1';
+ mon_input_bsn_at_sync <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sync = '1';
+ mon_output_enable <= r.output_enable;
+ mon_output_interval_size <= g_ctrl_interval_size_min WHEN rst='1' ELSE r.interval_size WHEN rising_edge(clk) AND output_start = '1';
+ mon_output_sync_bsn <= r.output_sync_bsn;
p_clk : PROCESS(rst, clk)
BEGIN
diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index 77a3a2dd6b0e5c090398d6099a6c720ca92a97e1..986bcb5c21ebdde4b60dd928b5de99bcfb4e6f90 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -201,6 +201,7 @@ ARCHITECTURE rtl OF dp_packet_merge IS
pkt_cnt : NATURAL RANGE 0 TO g_nof_pkt+1;
align_cnt : NATURAL RANGE 0 TO g_nof_pkt+1;
busy : STD_LOGIC;
+ sync : STD_LOGIC;
src_out : t_dp_sosi;
END RECORD;
@@ -324,9 +325,17 @@ BEGIN
IF snk_in.sop = '1' THEN
IF r.pkt_cnt = 0 THEN
v.src_out.sop := '1';
- v.src_out.sync := snk_in.sync; -- only preserve sync when sync interval and nof_pkt interval are aligned, else sync gets lost but could still be recovered from BSN
+ v.src_out.sync := r.sync; -- use sync from previous merged packet if it occurred on pkt_cnt /= 0.
v.src_out.bsn := snk_in.bsn; -- use BSN of first packet for merged packet
v.src_out.channel := snk_in.channel; -- use channel of first packet for merged packet
+ v.sync := '0'; -- reset captured sync.
+ IF snk_in.sync = '1' THEN
+ v.src_out.sync := '1'; -- set out sync to '1' if this first block contains the sync.
+ END IF;
+ ELSE
+ IF snk_in.sync = '1' THEN
+ v.sync := '1'; -- Capture sync if it occurs on a pkt_cnt /= 0 so we can use it in the next merged packet
+ END IF;
END IF;
END IF;
@@ -359,6 +368,7 @@ BEGIN
v.pkt_cnt := 0;
v.align_cnt := 0;
v.busy := '0';
+ v.sync := '0';
v.src_out := c_dp_sosi_rst;
END IF;
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index 31d63241e128df435401ce5e9a9bba5a41adf732..dd80feef650afcfedee1fbe0466ff305e3b093a4 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -41,7 +41,7 @@ ENTITY dp_requantize IS
-- when 0 then no effect
g_lsb_round : BOOLEAN := TRUE; -- when TRUE round else truncate the input LSbits
g_lsb_round_clip : BOOLEAN := FALSE; -- when TRUE round clip to +max to avoid wrapping to output -min (signed) or 0 (unsigned) due to rounding
- g_lsb_round_even : BOOLEAN := FALSE; -- when TRUE round to even, else round away from zero
+ g_lsb_round_even : BOOLEAN := TRUE; -- when TRUE round half to even, else round half away from zero
g_msb_clip : BOOLEAN := TRUE; -- when TRUE CLIP else WRAP the input MSbits
g_msb_clip_symmetric : BOOLEAN := FALSE; -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
-- for wrapping when g_msb_clip=FALSE the g_msb_clip_symmetric is ignored, so signed wrapping is done asymmetric
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
index 77d8f531a1c4c94b0fdbdf82dbead54e8dfac78d..2d74ca00ed1f890a0f16bbdac6636450a8427d17 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
@@ -89,7 +89,7 @@ ENTITY mmp_dp_bsn_align_v2 IS
mm_copi : IN t_mem_copi := c_mem_copi_rst; -- read access to output block, all output streams share same mm_copi
mm_cipo_arr : OUT t_mem_cipo_arr(g_nof_streams-1 DOWNTO 0);
- -- Output via streaming DP interface, when g_use_mm_output = TRUE.
+ -- Output via streaming DP interface, when g_use_mm_output = FALSE.
out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
);
END mmp_dp_bsn_align_v2;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 75b42316d077b32591da03f6a12aff7ee6da26d9..9cfe48f8dba79806999f160015e2e625b4753190 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -22,7 +22,8 @@
--
-- wi Bits Access Type Name
-- 0 [0] RW boolean ctrl_enable, '1' is on, '0' is FALSE is off
--- 1 [31:0] RW uint32 ctrl_interval_size
+-- 1 [31:0] RW uint32 W: ctrl_interval_size
+-- R: mon_output_interval_size
-- 2 [31:0] RW uint64 ctrl_start_bsn[31:0]
-- 3 [31:0] RW ctrl_start_bsn[63:32]
-- 4 [31:0] RO uint64 mon_current_input_bsn[31:0]
@@ -63,7 +64,7 @@ USE work.dp_stream_pkg.ALL;
ENTITY mmp_dp_bsn_sync_scheduler IS
GENERIC (
g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
);
PORT (
@@ -95,20 +96,21 @@ ARCHITECTURE str OF mmp_dp_bsn_sync_scheduler IS
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
CONSTANT c_mm_reg : t_c_mem := (1, 4, c_word_w, 12, '0');
- SIGNAL reg_wr_arr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat -1 DOWNTO 0);
- SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
- SIGNAL reg_rd : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
-
- SIGNAL wr_ctrl_enable : STD_LOGIC;
- SIGNAL wr_ctrl_enable_evt : STD_LOGIC;
- SIGNAL ctrl_enable : STD_LOGIC := '0';
- SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
- SIGNAL ctrl_interval_size : NATURAL;
- SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL mon_current_input_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- SIGNAL mon_input_bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- SIGNAL mon_output_enable : STD_LOGIC;
- SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL reg_wr_arr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat -1 DOWNTO 0);
+ SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
+ SIGNAL reg_rd : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL wr_ctrl_enable : STD_LOGIC;
+ SIGNAL wr_ctrl_enable_evt : STD_LOGIC;
+ SIGNAL ctrl_enable : STD_LOGIC := '0';
+ SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
+ SIGNAL ctrl_interval_size : NATURAL;
+ SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL mon_current_input_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL mon_input_bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL mon_output_enable : STD_LOGIC;
+ SIGNAL mon_output_interval_size : NATURAL;
+ SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
-- Resize BSN values to 64 bit
SIGNAL wr_start_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
@@ -151,7 +153,7 @@ BEGIN
-- . Read
reg_rd( 0) <= ctrl_enable; -- read back internal ctrl_enable
- reg_rd( 2*c_word_w-1 DOWNTO 1*c_word_w) <= TO_UVEC(ctrl_interval_size, c_word_w);
+ reg_rd( 2*c_word_w-1 DOWNTO 1*c_word_w) <= TO_UVEC(mon_output_interval_size, c_word_w);
reg_rd( 3*c_word_w-1 DOWNTO 2*c_word_w) <= wr_start_bsn_64( c_word_w-1 DOWNTO 0); -- low word
reg_rd( 4*c_word_w-1 DOWNTO 3*c_word_w) <= wr_start_bsn_64( 2*c_word_w-1 DOWNTO c_word_w); -- high word
reg_rd( 5*c_word_w-1 DOWNTO 4*c_word_w) <= rd_current_input_bsn_64( c_word_w-1 DOWNTO 0); -- low word
@@ -189,29 +191,31 @@ BEGIN
u_dp_bsn_sync_scheduler : ENTITY work.dp_bsn_sync_scheduler
GENERIC MAP (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_pipeline => 1
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min,
+ g_pipeline => 1
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
+ rst => dp_rst,
+ clk => dp_clk,
-- M&C
- ctrl_enable => ctrl_enable,
- ctrl_enable_evt => ctrl_enable_evt,
- ctrl_interval_size => ctrl_interval_size,
- ctrl_start_bsn => ctrl_start_bsn,
- mon_current_input_bsn => mon_current_input_bsn,
- mon_input_bsn_at_sync => mon_input_bsn_at_sync,
- mon_output_enable => mon_output_enable,
- mon_output_sync_bsn => mon_output_sync_bsn,
+ ctrl_enable => ctrl_enable,
+ ctrl_enable_evt => ctrl_enable_evt,
+ ctrl_interval_size => ctrl_interval_size,
+ ctrl_start_bsn => ctrl_start_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
+ mon_input_bsn_at_sync => mon_input_bsn_at_sync,
+ mon_output_enable => mon_output_enable,
+ mon_output_interval_size => mon_output_interval_size,
+ mon_output_sync_bsn => mon_output_sync_bsn,
-- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_enable => out_enable
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_enable => out_enable
);
END str;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
index f37dab7d34f6a13a485ea7a1fd91c31110fd13ed..d3821177509f80c9ee2e0d4134f6eda890c7907e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
@@ -238,9 +238,6 @@ BEGIN
proc_dp_verify_data("verify_snk_in.bsn", c_rl, c_unsigned_0, TO_UNSIGNED(c_verify_data_gap,32), clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, TO_UNSIGNED(c_verify_data_gap,32), clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.channel, prev_verify_snk_in.channel);
- -- Verify that the output sync occurs when expected
- proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en_sop, verify_snk_in.sync, verify_snk_in.sop, verify_snk_in.bsn);
-
-- Verify output packet ctrl
proc_dp_verify_sop_and_eop(clk, verify_snk_in.valid, verify_snk_in.sop, verify_snk_in.eop, verify_hold_sop);
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index a7b2234a79a41c7fb71c5250e2a999c8d3cbb43e..d9fd975a4eb30877fd101260a963134aab754ba7 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -45,6 +45,9 @@ USE work.dp_stream_pkg.ALL;
USE work.tb_dp_pkg.ALL;
ENTITY tb_mmp_dp_bsn_align_v2 IS
+ GENERIC (
+ g_lost_input : BOOLEAN := TRUE -- when TRUE use c_nof_streams-1 as lost input
+ );
END tb_mmp_dp_bsn_align_v2;
@@ -60,11 +63,12 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
-- Fixed dut generics
-- . for dp_bsn_align_v2
- CONSTANT c_nof_streams : NATURAL := 3;
+ CONSTANT c_nof_streams : NATURAL := 5;
CONSTANT c_bsn_latency_max : NATURAL := 1;
CONSTANT c_nof_aligners_max : POSITIVE := 1; -- fixed in this tb
CONSTANT c_block_size : NATURAL := 11;
CONSTANT c_block_period : NATURAL := 11;
+ CONSTANT c_block_per_sync : NATURAL := 7;
CONSTANT c_bsn_w : NATURAL := c_dp_stream_bsn_w;
CONSTANT c_data_w : NATURAL := 16;
CONSTANT c_data_replacement_value : INTEGER := 17;
@@ -73,7 +77,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
CONSTANT c_pipeline_output : NATURAL := 1;
CONSTANT c_rd_latency : NATURAL := 2;
-- . for mms_dp_bsn_monitor_v2
- CONSTANT c_nof_clk_per_sync : NATURAL := 200*10**6;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_block_per_sync * c_block_period;
CONSTANT c_nof_input_bsn_monitors : NATURAL := c_nof_streams;
CONSTANT c_use_bsn_output_monitor : BOOLEAN := TRUE;
@@ -96,8 +100,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
CONSTANT c_bsn_init : NATURAL := 3;
CONSTANT c_channel_init : INTEGER := 0;
CONSTANT c_err_init : NATURAL := 247;
- CONSTANT c_sync_period : NATURAL := 7;
- CONSTANT c_sync_offset : NATURAL := 2;
+ CONSTANT c_sync_bsn_offset : NATURAL := 2;
CONSTANT c_gap_size : NATURAL := c_block_period - c_block_size;
-- DUT latency
@@ -138,8 +141,8 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
SIGNAL reg_output_monitor_copi : t_mem_copi := c_mem_copi_rst;
SIGNAL reg_output_monitor_cipo : t_mem_cipo;
- SIGNAL mon_latency_input_arr : t_nat_natural_arr(c_nof_streams-1 DOWNTO 0);
- SIGNAL mon_latency_output : NATURAL;
+ SIGNAL mon_latency_input_arr : t_integer_arr(c_nof_streams-1 DOWNTO 0);
+ SIGNAL mon_latency_output : INTEGER;
-- DP clock domain
SIGNAL dp_clk : STD_LOGIC := '1';
@@ -173,7 +176,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
SIGNAL out_err_arr : t_err_arr;
SIGNAL verify_done_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
- SIGNAL verify_done : STD_LOGIC;
+ SIGNAL verify_done : STD_LOGIC := '0';
SIGNAL hold_out_sop_arr : STD_LOGIC_VECTOR(c_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL expected_out_bsn_arr : t_bsn_arr;
@@ -257,15 +260,19 @@ BEGIN
FOR I IN 0 TO c_nof_streams-1 LOOP
proc_mem_mm_bus_rd(6 + I*c_reg_bsn_monitor_span, mm_clk, reg_input_monitor_cipo, reg_input_monitor_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- mon_latency_input_arr(I) <= TO_UINT(reg_input_monitor_cipo.rddata);
+ mon_latency_input_arr(I) <= TO_SINT(reg_input_monitor_cipo.rddata(31 DOWNTO 0));
proc_common_wait_some_cycles(mm_clk, 1);
- ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) SEVERITY ERROR;
+ IF g_lost_input = TRUE AND I = c_nof_streams-1 THEN
+ ASSERT mon_latency_input_arr(I) = -1 REPORT "Wrong input BSN monitor latency timeout for input " & int_to_str(I) SEVERITY ERROR;
+ ELSE
+ ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) SEVERITY ERROR;
+ END IF;
END LOOP;
-- Read output BSN monitor
proc_mem_mm_bus_rd(6, mm_clk, reg_output_monitor_cipo, reg_output_monitor_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
- mon_latency_output <= TO_UINT(reg_output_monitor_cipo.rddata);
+ mon_latency_output <= TO_SINT(reg_output_monitor_cipo.rddata(31 DOWNTO 0));
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_latency_output = c_total_latency REPORT "Wrong output BSN monitor latency" SEVERITY ERROR;
@@ -299,14 +306,14 @@ BEGIN
FOR S IN 0 TO c_tb_nof_restart-1 LOOP
v_bsn := c_bsn_init;
FOR R IN 0 TO c_tb_nof_blocks-1 LOOP
- v_sync := sel_a_b(v_bsn MOD c_sync_period = c_sync_offset, '1', '0');
+ v_sync := sel_a_b(v_bsn MOD c_block_per_sync = c_sync_bsn_offset, '1', '0');
proc_dp_gen_block_data(c_rl, TRUE, c_data_w, c_data_w, v_data, 0, 0, c_block_size, v_channel, v_err, v_sync, TO_UVEC(v_bsn, c_bsn_w), dp_clk, sl1, ref_siso_arr(I), ref_sosi_arr(I));
v_bsn := v_bsn + 1;
v_data := v_data + c_block_size;
proc_common_wait_some_cycles(dp_clk, c_gap_size); -- create gap between frames
END LOOP;
-- Create gap between restarts
- proc_common_wait_some_cycles(dp_clk, 100);
+ proc_common_wait_some_cycles(dp_clk, 10);
restart_cnt_arr(I) <= restart_cnt_arr(I) + 1;
END LOOP;
@@ -314,10 +321,15 @@ BEGIN
-- . default c_bsn_latency_max blocks remain in DUT buffer
expected_out_bsn_arr(I) <= TO_UVEC(v_bsn-1 - c_align_latency_nof_blocks, c_bsn_w);
expected_out_data_arr(I) <= TO_UVEC(v_data-1 - c_align_latency_nof_valid, c_data_w);
- -- . default no data is lost, so all channel(0) lost data flags are 0
+ -- . default no data is lost, so all channel(bit 0) lost data flags are 0
expected_out_channel_arr(I) <= TO_DP_CHANNEL(0);
-
- proc_common_wait_some_cycles(dp_clk, 100);
+ IF g_lost_input = TRUE THEN
+ IF I = c_nof_streams-1 THEN
+ expected_out_data_arr(I) <= TO_UVEC(c_data_replacement_value, c_data_w);
+ expected_out_channel_arr(I) <= TO_DP_CHANNEL(1);
+ END IF;
+ END IF;
+ proc_common_wait_some_cycles(dp_clk, 10);
verify_done_arr(I) <= '1';
proc_common_wait_some_cycles(dp_clk, 1);
verify_done_arr(I) <= '0';
@@ -329,15 +341,25 @@ BEGIN
END PROCESS;
END GENERATE;
- verify_done <= verify_done_arr(0);
+ verify_done <= '1' WHEN verify_done_arr(0) = '1';
restart_cnt <= restart_cnt_arr(0);
dp_end <= vector_and(dp_end_arr);
-- Model misalignment latency between the input streams to have different
-- input BSN monitor latencies
- gen_rx_sosi_arr : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE
- in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ no_lost_input : IF g_lost_input = FALSE GENERATE
+ gen_in_sosi_arr : FOR I IN c_nof_streams-1 DOWNTO 0 GENERATE
+ in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ END GENERATE;
+ END GENERATE;
+
+ one_lost_input : IF g_lost_input = TRUE GENERATE
+ -- Model missing enabled input stream at index c_lost_input = c_nof_streams-1
+ in_sosi_arr(c_nof_streams-1) <= c_dp_sosi_rst;
+ gen_in_sosi_arr : FOR I IN c_nof_streams-2 DOWNTO 0 GENERATE
+ in_sosi_arr(I) <= TRANSPORT ref_sosi_arr(I) AFTER func_input_delay(I) * c_dp_clk_period;
+ END GENERATE;
END GENERATE;
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index ce4e5f605e7efbba13cb3ec7a972a5d9b9548805..43162d9c6df7dd1b3e4b768e0353f9f65d51e791 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -52,6 +52,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
CONSTANT c_nof_block_per_input_sync : NATURAL := 17;
CONSTANT c_nof_block_per_output_sync : NATURAL := 5;
CONSTANT c_block_size : NATURAL := 10;
+ CONSTANT c_ctrl_interval_size_min : NATURAL := 19; -- Minimum interval size to use if MM write interval size is set too small.
CONSTANT c_input_gap_size : NATURAL := 3;
CONSTANT c_sim_nof_blocks : NATURAL := c_nof_block_per_input_sync * c_nof_input_sync;
@@ -75,6 +76,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
SIGNAL ctrl_start_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_output_enable : STD_LOGIC;
+ SIGNAL mon_output_interval_size : NATURAL;
SIGNAL mon_current_input_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_input_bsn_at_sync_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_output_sync_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
@@ -118,6 +120,13 @@ BEGIN
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_block_size = c_block_size REPORT "Wrong block_size." SEVERITY ERROR;
+ -- . Read mon_output_interval_size
+ proc_mem_mm_bus_rd(1, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ mon_output_interval_size <= TO_UINT(reg_miso.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+ ASSERT mon_output_interval_size = c_ctrl_interval_size_min REPORT "Wrong minimum output interval_size." SEVERITY ERROR;
+
-- . Read mon_output_enable
proc_mem_mm_bus_rd(8, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -214,10 +223,16 @@ BEGIN
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_output_enable <= reg_miso.rddata(0);
+ -- . Read mon_output_interval_size
+ proc_mem_mm_bus_rd(1, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ mon_output_interval_size <= TO_UINT(reg_miso.rddata(c_word_w-1 DOWNTO 0));
+
-- Verify output is on and running
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_output_enable = '1' REPORT "mon_output_enable is not enabled." SEVERITY ERROR;
ASSERT out_enable = '1' REPORT "output_enable is not enabled." SEVERITY ERROR;
+ ASSERT mon_output_interval_size = c_ctrl_interval_size REPORT "mon_output_interval_size is not ctrl_interval_size." SEVERITY ERROR;
---------------------------------------------------------------------------
-- Check that monitor BSN are incrementing
@@ -381,8 +396,9 @@ BEGIN
u_mmp_dp_bsn_sync_scheduler : ENTITY work.mmp_dp_bsn_sync_scheduler
GENERIC MAP (
- g_bsn_w => c_bsn_w,
- g_block_size => c_block_size
+ g_bsn_w => c_bsn_w,
+ g_block_size => c_block_size,
+ g_ctrl_interval_size_min => c_ctrl_interval_size_min
)
PORT MAP (
-- Clocks and reset
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7eea68cc3bdd53a99d18a3334f5df6d2a1fa3f16
--- /dev/null
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
@@ -0,0 +1,46 @@
+-- --------------------------------------------------------------------------
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+-- --------------------------------------------------------------------------
+--
+-- Author: E. Kooistra, 2 march 2022
+-- Purpose: Regression multi tb for mmp_dp_bsn_align_v2
+-- Description:
+-- Usage:
+-- > as 3
+-- > run -all
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.tb_dp_pkg.ALL;
+
+
+ENTITY tb_tb_mmp_dp_bsn_align_v2 IS
+END tb_tb_mmp_dp_bsn_align_v2;
+
+
+ARCHITECTURE tb OF tb_tb_mmp_dp_bsn_align_v2 IS
+
+ SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
+
+BEGIN
+
+ -- g_lost_input : BOOLEAN := FALSE
+
+ u_no_lost_input : ENTITY work.tb_mmp_dp_bsn_align_v2 GENERIC MAP (FALSE);
+ u_one_lost_input : ENTITY work.tb_mmp_dp_bsn_align_v2 GENERIC MAP (TRUE);
+
+END tb;
diff --git a/libraries/dsp/fft/hdllib.cfg b/libraries/dsp/fft/hdllib.cfg
index a75778467bbdea6b49354de1f431115a5b5dd9d8..aee1489da150feebf22084542d8ebd71b86484e8 100644
--- a/libraries/dsp/fft/hdllib.cfg
+++ b/libraries/dsp/fft/hdllib.cfg
@@ -21,7 +21,8 @@ synth_files =
test_bench_files =
tb/vhdl/tb_fft_pkg.vhd
- tb/vhdl/tb_fft_functions.vhd
+ tb/vhdl/tb_fft_functions.vhd
+ tb/vhdl/tb_fft_lfsr.vhd
tb/vhdl/tb_fft_switch.vhd
tb/vhdl/tb_fft_sepa.vhd
tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
@@ -32,11 +33,12 @@ test_bench_files =
tb/vhdl/tb_fft_wide_unit.vhd
tb/vhdl/tb_mmf_fft_r2.vhd
tb/vhdl/tb_mmf_fft_wide_unit.vhd
- tb/vhdl/tb_tb_fft_r2_pipe.vhd
+ tb/vhdl/tb_tb_fft_r2_pipe.vhd
tb/vhdl/tb_tb_fft_r2_par.vhd
tb/vhdl/tb_tb_fft_r2_wide.vhd
regression_test_vhdl =
+ tb/vhdl/tb_fft_lfsr.vhd
tb/vhdl/tb_fft_switch.vhd
tb/vhdl/tb_tb_fft_r2_pipe.vhd
tb/vhdl/tb_tb_fft_r2_par.vhd
diff --git a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
index 56f5b5e453f9a2e009a05c2418f6890ee6aa22e3..7f53b0a398f8dddef39cc056eb7225767d53362b 100644
--- a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
@@ -21,12 +21,20 @@
-- Author: ported by E. Kooistra, original 2004 by W. Lubberhuizen / W. Poeisz
-- Purpose: Scramble quantization noise crosstalk between two real inputs
-- Description: Ported from LOFAR1, see readme_lofar1.txt
--- Remark: Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+-- Remark:
+-- . Copy from applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+-- . The g_seed must be > 0 for LFSR period is 2**c_fft_lfsr_len - 1. Value
+-- g_seed = 0 causes the LFSR to remain stuck at 0.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
+USE work.fft_pkg.ALL;
ENTITY fft_lfsr IS
+ GENERIC (
+ g_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed1;
+ g_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed2
+ );
PORT (
in_en : IN STD_LOGIC;
out_bit1 : OUT STD_LOGIC;
@@ -43,23 +51,23 @@ ARCHITECTURE rtl OF fft_lfsr IS
-- x^41 + x^20 + 1 and x^41 + x^3 + 1
-- see XAPP217
- CONSTANT c_max : NATURAL := 41;
+ CONSTANT c_len : NATURAL := c_fft_lfsr_len; -- = 41, same for both trinomials
CONSTANT c1 : NATURAL := 20;
CONSTANT c2 : NATURAL := 3;
- SIGNAL s1 : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
- SIGNAL nxt_s1 : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
-
- SIGNAL s2 : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
- SIGNAL nxt_s2 : STD_LOGIC_VECTOR(c_max-1 DOWNTO 0);
-
+ SIGNAL s1 : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0);
+ SIGNAL nxt_s1 : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0);
+ SIGNAL s2 : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0);
+ SIGNAL nxt_s2 : STD_LOGIC_VECTOR(c_len-1 DOWNTO 0);
+
BEGIN
+
p_reg : PROCESS(rst,clk)
BEGIN
IF rst='1' THEN
- s1 <= "01000101011101110101001011111000101100001";
- s2 <= "11011001000101001011011001110101100101100";
+ s1 <= g_seed1;
+ s2 <= g_seed2;
ELSIF rising_edge(clk) THEN
s1 <= nxt_s1;
s2 <= nxt_s2;
@@ -69,22 +77,22 @@ BEGIN
out_bit1 <= s1(s1'HIGH);
out_bit2 <= s2(s2'HIGH);
- p_seed : PROCESS(in_en,s1,s2)
+ p_seed : PROCESS(in_en, s1, s2)
BEGIN
nxt_s1 <= s1;
nxt_s2 <= s2;
- IF in_en='1' THEN
+ IF in_en = '1' THEN
-- shift
- nxt_s1(c_max-1 DOWNTO 1) <= s1(c_max-2 DOWNTO 0);
- nxt_s2(c_max-1 DOWNTO 1) <= s2(c_max-2 DOWNTO 0);
+ nxt_s1(c_len-1 DOWNTO 1) <= s1(c_len-2 DOWNTO 0);
+ nxt_s2(c_len-1 DOWNTO 1) <= s2(c_len-2 DOWNTO 0);
-- feedback 1
- nxt_s1(0) <= s1(c_max-1);
- nxt_s2(0) <= s2(c_max-1);
+ nxt_s1(0) <= s1(c_len-1);
+ nxt_s2(0) <= s2(c_len-1);
-- feedback 2
- nxt_s1(c1) <= s1(c_max-1) xor s1(c1-1);
- nxt_s2(c2) <= s2(c_max-1) xor s2(c2-1);
+ nxt_s1(c1) <= s1(c_len-1) xor s1(c1-1);
+ nxt_s2(c2) <= s2(c_len-1) xor s2(c2-1);
END IF;
END PROCESS;
diff --git a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
index 4b4a00f80ba00c619efabaf1b8c5be9995588636..a177c9b2360167cb6ca9a00f118b3f452a61de4c 100644
--- a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
@@ -25,6 +25,23 @@ use common_lib.common_pkg.all;
package fft_pkg is
+ -- Default FFT switch and unswitch seeds from LOFAR1
+ constant c_fft_lfsr_len : natural := 41;
+ constant c_fft_switch_seed1 : std_logic_vector(c_fft_lfsr_len-1 DOWNTO 0) := "01000101011101110101001011111000101100001";
+ constant c_fft_switch_seed2 : std_logic_vector(c_fft_lfsr_len-1 DOWNTO 0) := "11011001000101001011011001110101100101100";
+
+ function fft_switch_new_seed(seed : std_logic_vector; offset : natural) return std_logic_vector;
+
+ -- The FFT gain for an real input sinus signal is 0.5, because a real input
+ -- sinus with amplitude A yields two subband phasors each with amplitude
+ -- A/2, one at -f_bin and one at +f_bin. The power stays the same, because
+ -- the power of an real input sinus is A**2 / 2 and the power of the f_bin
+ -- signal complex phasors is (A/2)**2 + (A/2)**2 = A**2 / 2.
+ -- For DC at bin 0 the real input gain is 1.0, because DC has only one
+ -- phasor component of frequency 0.
+ CONSTANT c_fft_real_input_gain_sine : REAL := 0.5;
+ CONSTANT c_fft_real_input_gain_dc : REAL := 1.0;
+
-- FFT parameters for pipelined FFT (fft_pipe), parallel FFT (fft_par) and wideband FFT (fft_wide)
type t_fft is record
use_reorder : boolean; -- = false for bit-reversed output, true for normal output
@@ -68,6 +85,11 @@ end package fft_pkg;
package body fft_pkg is
+ function fft_switch_new_seed(seed : std_logic_vector; offset : natural) return std_logic_vector is
+ begin
+ return INCR_UVEC(seed, offset); -- make new unique seed
+ end;
+
function fft_r2_parameter_asserts(g_fft : t_fft) return boolean is
begin
-- nof_points
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
index c9089c8de041e6d5786deecbbceaa535d8516041..02bf10f3cdc378575e093c4651fad58d5891f3ff 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
@@ -125,30 +125,37 @@ architecture str of fft_r2_par is
constant c_pipeline_add_sub : natural := 1;
constant c_pipeline_remove_lsb : natural := 1;
- constant c_sepa_round : boolean := true; -- must be true, because separate should round the 1 bit growth
-
+
constant c_nof_stages : natural := ceil_log2(g_fft.nof_points);
constant c_nof_bf_per_stage : natural := g_fft.nof_points/2;
constant c_in_scale_w_tester : integer := g_fft.stage_dat_w - g_fft.in_dat_w - sel_a_b(g_fft.guard_enable, g_fft.guard_w, 0);
constant c_in_scale_w : natural := sel_a_b(c_in_scale_w_tester > 0, c_in_scale_w_tester, 0); -- Only scale when in_dat_w is not too big.
constant c_out_scale_w : integer := g_fft.stage_dat_w - g_fft.out_dat_w - g_fft.out_gain_w; -- Estimate number of LSBs to throw away when > 0 or insert when < 0
+
+ constant c_sepa_growth_w : natural := sel_a_b(g_fft.use_separate, 1, 0); -- add one bit for add sub growth in separate
+ constant c_raw_dat_w : natural := g_fft.stage_dat_w + c_sepa_growth_w;
type t_stage_dat_arr is array (integer range <>) of std_logic_vector(g_fft.stage_dat_w-1 downto 0);
- type t_stage_sum_arr is array (integer range <>) of std_logic_vector(g_fft.stage_dat_w downto 0);
+ type t_stage_raw_arr is array (integer range <>) of std_logic_vector(c_raw_dat_w-1 downto 0);
type t_data_arr2 is array(c_nof_stages downto 0) of t_stage_dat_arr(g_fft.nof_points-1 downto 0);
type t_val_arr is array(c_nof_stages downto 0) of std_logic_vector( g_fft.nof_points-1 downto 0);
signal data_re : t_data_arr2;
signal data_im : t_data_arr2;
signal data_val : t_val_arr;
+
signal int_re_arr : t_stage_dat_arr(g_fft.nof_points-1 downto 0);
signal int_im_arr : t_stage_dat_arr(g_fft.nof_points-1 downto 0);
- signal fft_re_arr : t_stage_dat_arr(g_fft.nof_points-1 downto 0);
- signal fft_im_arr : t_stage_dat_arr(g_fft.nof_points-1 downto 0);
- signal add_arr : t_stage_sum_arr(g_fft.nof_points-1 downto 0);
- signal sub_arr : t_stage_sum_arr(g_fft.nof_points-1 downto 0);
signal int_val : std_logic;
+ signal int_a_dc : std_logic_vector(g_fft.stage_dat_w-1 downto 0);
+ signal int_b_dc : std_logic_vector(g_fft.stage_dat_w-1 downto 0);
+
+ signal add_arr : t_stage_raw_arr(g_fft.nof_points-1 downto 0);
+ signal sub_arr : t_stage_raw_arr(g_fft.nof_points-1 downto 0);
+
+ signal fft_re_arr : t_stage_raw_arr(g_fft.nof_points-1 downto 0);
+ signal fft_im_arr : t_stage_raw_arr(g_fft.nof_points-1 downto 0);
signal fft_val : std_logic;
begin
@@ -235,7 +242,7 @@ begin
g_pipeline_input => 0,
g_pipeline_output => c_pipeline_add_sub,
g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => g_fft.stage_dat_w+1
+ g_out_dat_w => c_raw_dat_w
)
port map (
clk => clk,
@@ -251,7 +258,7 @@ begin
g_pipeline_input => 0,
g_pipeline_output => c_pipeline_add_sub,
g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => g_fft.stage_dat_w+1
+ g_out_dat_w => c_raw_dat_w
)
port map (
clk => clk,
@@ -267,7 +274,7 @@ begin
g_pipeline_input => 0,
g_pipeline_output => c_pipeline_add_sub,
g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => g_fft.stage_dat_w+1
+ g_out_dat_w => c_raw_dat_w
)
port map (
clk => clk,
@@ -283,7 +290,7 @@ begin
g_pipeline_input => 0,
g_pipeline_output => c_pipeline_add_sub,
g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => g_fft.stage_dat_w+1
+ g_out_dat_w => c_raw_dat_w
)
port map (
clk => clk,
@@ -292,84 +299,14 @@ begin
result => sub_arr(2*I+1)
);
- gen_sepa_truncate : IF c_sepa_round=false GENERATE
- -- truncate the one LSbit
- fft_re_arr(2*I ) <= add_arr(2*I )(g_fft.stage_dat_w DOWNTO 1); -- A real
- fft_re_arr(2*I+1) <= add_arr(2*I+1)(g_fft.stage_dat_w DOWNTO 1); -- B real
- fft_im_arr(2*I ) <= sub_arr(2*I )(g_fft.stage_dat_w DOWNTO 1); -- A imag
- fft_im_arr(2*I+1) <= sub_arr(2*I+1)(g_fft.stage_dat_w DOWNTO 1); -- B imag
- end generate;
-
- gen_sepa_round : IF c_sepa_round=true GENERATE
- -- round the one LSbit
- round_re_a : ENTITY common_lib.common_round
- GENERIC MAP (
- g_representation => "SIGNED", -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_round => TRUE, -- when TRUE round the input, else truncate the input
- g_round_clip => FALSE, -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_pipeline_input => 0, -- >= 0
- g_pipeline_output => 0, -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
- g_in_dat_w => g_fft.stage_dat_w+1,
- g_out_dat_w => g_fft.stage_dat_w
- )
- PORT MAP (
- clk => clk,
- in_dat => add_arr(2*I),
- out_dat => fft_re_arr(2*I)
- );
-
- round_re_b : ENTITY common_lib.common_round
- GENERIC MAP (
- g_representation => "SIGNED", -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_round => TRUE, -- when TRUE round the input, else truncate the input
- g_round_clip => FALSE, -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_pipeline_input => 0, -- >= 0
- g_pipeline_output => 0, -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
- g_in_dat_w => g_fft.stage_dat_w+1,
- g_out_dat_w => g_fft.stage_dat_w
- )
- PORT MAP (
- clk => clk,
- in_dat => add_arr(2*I+1),
- out_dat => fft_re_arr(2*I+1)
- );
-
- round_im_a : ENTITY common_lib.common_round
- GENERIC MAP (
- g_representation => "SIGNED", -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_round => TRUE, -- when TRUE round the input, else truncate the input
- g_round_clip => FALSE, -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_pipeline_input => 0, -- >= 0
- g_pipeline_output => 0, -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
- g_in_dat_w => g_fft.stage_dat_w+1,
- g_out_dat_w => g_fft.stage_dat_w
- )
- PORT MAP (
- clk => clk,
- in_dat => sub_arr(2*I),
- out_dat => fft_im_arr(2*I)
- );
-
- round_im_b : ENTITY common_lib.common_round
- GENERIC MAP (
- g_representation => "SIGNED", -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_round => TRUE, -- when TRUE round the input, else truncate the input
- g_round_clip => FALSE, -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_pipeline_input => 0, -- >= 0
- g_pipeline_output => 0, -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
- g_in_dat_w => g_fft.stage_dat_w+1,
- g_out_dat_w => g_fft.stage_dat_w
- )
- PORT MAP (
- clk => clk,
- in_dat => sub_arr(2*I+1),
- out_dat => fft_im_arr(2*I+1)
- );
- end generate;
+ fft_re_arr(2*I ) <= add_arr(2*I )(c_raw_dat_w-1 DOWNTO 0); -- A real
+ fft_re_arr(2*I+1) <= add_arr(2*I+1)(c_raw_dat_w-1 DOWNTO 0); -- B real
+ fft_im_arr(2*I ) <= sub_arr(2*I )(c_raw_dat_w-1 DOWNTO 0); -- A imag
+ fft_im_arr(2*I+1) <= sub_arr(2*I+1)(c_raw_dat_w-1 DOWNTO 0); -- B imag
end generate;
---------------------------------------------------------------------------
- -- Generate bin 0 directly
+ -- Generate bin 0 = DC directly
---------------------------------------------------------------------------
-- Index N=g_fft.nof_points wraps to index 0:
-- . fft_re_arr(0) = (int_re_arr(0) + int_re_arr(N)) / 2 = int_re_arr(0)
@@ -379,28 +316,34 @@ begin
u_pipeline_a_re_0 : entity common_lib.common_pipeline
generic map (
- g_pipeline => c_pipeline_add_sub,
- g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => g_fft.stage_dat_w
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_add_sub,
+ g_in_dat_w => g_fft.stage_dat_w,
+ g_out_dat_w => g_fft.stage_dat_w
)
port map (
clk => clk,
in_dat => int_re_arr(0),
- out_dat => fft_re_arr(0)
+ out_dat => int_a_dc
);
u_pipeline_b_re_0 : entity common_lib.common_pipeline
generic map (
- g_pipeline => c_pipeline_add_sub,
- g_in_dat_w => g_fft.stage_dat_w,
- g_out_dat_w => g_fft.stage_dat_w
+ g_representation => "SIGNED",
+ g_pipeline => c_pipeline_add_sub,
+ g_in_dat_w => g_fft.stage_dat_w,
+ g_out_dat_w => g_fft.stage_dat_w
)
port map (
clk => clk,
in_dat => int_im_arr(0),
- out_dat => fft_re_arr(1)
+ out_dat => int_b_dc
);
+ -- The real outputs of A(0) and B(0) are scaled by shift left is * 2 for separate add
+ fft_re_arr(0) <= int_a_dc & '0';
+ fft_re_arr(1) <= int_b_dc & '0';
+
-- The imaginary outputs of A(0) and B(0) are always zero in case two real inputs are provided
fft_im_arr(0) <= (others=>'0');
fft_im_arr(1) <= (others=>'0');
@@ -421,6 +364,7 @@ begin
no_separate : if g_fft.use_separate=false generate
assign_outputs : for I in 0 to g_fft.nof_points-1 generate
+ -- c_raw_dat_w = g_fft.stage_dat_w, because g_fft.use_separate=false
fft_re_arr(I) <= int_re_arr(I);
fft_im_arr(I) <= int_im_arr(I);
end generate;
@@ -434,14 +378,14 @@ begin
u_requantize_re : entity common_lib.common_requantize
generic map (
g_representation => "SIGNED",
- g_lsb_w => c_out_scale_w,
+ g_lsb_w => c_out_scale_w + c_sepa_growth_w,
g_lsb_round => TRUE,
g_lsb_round_clip => FALSE,
g_msb_clip => FALSE,
g_msb_clip_symmetric => FALSE,
g_pipeline_remove_lsb => c_pipeline_remove_lsb,
g_pipeline_remove_msb => 0,
- g_in_dat_w => g_fft.stage_dat_w,
+ g_in_dat_w => c_raw_dat_w,
g_out_dat_w => g_fft.out_dat_w
)
port map (
@@ -454,14 +398,14 @@ begin
u_requantize_im : entity common_lib.common_requantize
generic map (
g_representation => "SIGNED",
- g_lsb_w => c_out_scale_w,
+ g_lsb_w => c_out_scale_w + c_sepa_growth_w,
g_lsb_round => TRUE,
g_lsb_round_clip => FALSE,
g_msb_clip => FALSE,
g_msb_clip_symmetric => FALSE,
g_pipeline_remove_lsb => c_pipeline_remove_lsb,
g_pipeline_remove_msb => 0,
- g_in_dat_w => g_fft.stage_dat_w,
+ g_in_dat_w => c_raw_dat_w,
g_out_dat_w => g_fft.out_dat_w
)
port map (
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
index c9ed7f72c558ac588935c3670265363a810f4b5f..8f3d64e600c1f9e10a087cd2d92210f3aef931aa 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
@@ -66,11 +66,10 @@ use work.fft_pkg.all;
entity fft_r2_pipe is
generic (
+ g_instance_index : natural := 0; -- used for FFT switch seed
g_fft : t_fft := c_fft; -- generics for the FFT
g_pipeline : t_fft_pipeline := c_fft_pipeline; -- generics for pipelining in each stage, defined in rTwoSDF_lib.rTwoSDFPkg
- g_dont_flip_channels : boolean := false; -- generic to prevent re-ordering of the channels
- g_r2_mul_extra_w : natural := 0; -- extra bits at rTwoWMul output in rTwoSDFStage to improve rTwoSDFStage output requantization
- g_sepa_extra_w : natural := 0 -- extra LSbits in output of last rTwoSDFStage to improve two real separate requantization
+ g_dont_flip_channels : boolean := false -- generic to prevent re-ordering of the channels
);
port (
clk : in std_logic;
@@ -92,12 +91,14 @@ architecture str of fft_r2_pipe is
constant c_switch_sz_w : natural := ceil_log2(g_fft.nof_points) + g_fft.nof_chan;
constant c_switch_dat_w : natural := g_fft.in_dat_w + 1; -- add 1 extra bit to fit negation of most negative value per real input switch function
constant c_unswitch_dat_w : natural := g_fft.out_dat_w; -- no need for extra bit, because most negative value cannot occur in output
+ constant c_switch_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := fft_switch_new_seed(c_fft_switch_seed1, g_instance_index);
+ constant c_switch_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := fft_switch_new_seed(c_fft_switch_seed2, g_instance_index);
constant c_nof_stages : natural := ceil_log2(g_fft.nof_points);
constant c_stage_offset : natural := true_log2(g_fft.wb_factor); -- Stage offset is required for twiddle generation in wideband fft
constant c_in_scale_w : natural := g_fft.stage_dat_w - g_fft.in_dat_w - sel_a_b(g_fft.guard_enable, g_fft.guard_w, 0);
constant c_out_scale_w : integer := g_fft.stage_dat_w - g_fft.out_dat_w - g_fft.out_gain_w; -- Estimate number of LSBs to throw throw away when > 0 or insert when < 0
- constant c_raw_dat_extra_w : natural := sel_a_b(g_fft.use_separate, g_sepa_extra_w, 0);
- constant c_raw_dat_w : natural := g_fft.stage_dat_w + c_raw_dat_extra_w;
+ constant c_sepa_growth_w : natural := sel_a_b(g_fft.use_separate, 1, 0); -- add one bit for add sub growth in separate
+ constant c_raw_dat_w : natural := g_fft.stage_dat_w + c_sepa_growth_w;
-- number the stage instances from c_nof_stages:1
-- . the data input for the first stage has index c_nof_stages
@@ -114,12 +115,10 @@ architecture str of fft_r2_pipe is
signal data_re : t_data_arr;
signal data_im : t_data_arr;
- signal last_re : std_logic_vector(c_raw_dat_w-1 downto 0);
- signal last_im : std_logic_vector(c_raw_dat_w-1 downto 0);
signal data_val : std_logic_vector(c_nof_stages downto 0):= (others=>'0');
+ signal in_cplx : std_logic_vector(c_nof_complex*g_fft.stage_dat_w-1 downto 0);
signal out_cplx : std_logic_vector(c_nof_complex*c_raw_dat_w-1 downto 0);
- signal in_cplx : std_logic_vector(c_nof_complex*c_raw_dat_w-1 downto 0);
signal raw_out_re : std_logic_vector(c_raw_dat_w-1 downto 0);
signal raw_out_im : std_logic_vector(c_raw_dat_w-1 downto 0);
signal raw_out_val : std_logic;
@@ -143,6 +142,8 @@ begin
u_switch : ENTITY work.fft_switch
GENERIC MAP (
g_switch_en => c_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
g_fft_sz_w => c_switch_sz_w,
g_dat_w => c_switch_dat_w
)
@@ -172,8 +173,7 @@ begin
g_stage_offset => c_stage_offset,
g_twiddle_offset => g_fft.twiddle_offset,
g_scale_enable => sel_a_b(stage <= g_fft.guard_w, FALSE, TRUE),
- g_pipeline => g_pipeline,
- g_r2_mul_extra_w => g_r2_mul_extra_w
+ g_pipeline => g_pipeline
)
port map (
clk => clk,
@@ -195,8 +195,7 @@ begin
g_stage_offset => c_stage_offset,
g_twiddle_offset => g_fft.twiddle_offset,
g_scale_enable => sel_a_b(1 <= g_fft.guard_w, FALSE, TRUE),
- g_pipeline => g_pipeline,
- g_r2_mul_extra_w => g_r2_mul_extra_w
+ g_pipeline => g_pipeline
)
port map (
clk => clk,
@@ -204,16 +203,16 @@ begin
in_re => data_re(1),
in_im => data_im(1),
in_val => data_val(1),
- out_re => last_re, -- = data_re(0), but may instead have c_raw_dat_w bits
- out_im => last_im, -- = data_im(0), but may instead have c_raw_dat_w bits
+ out_re => data_re(0),
+ out_im => data_im(0),
out_val => data_val(0)
);
------------------------------------------------------------------------------
-- Optional output reorder and separation
------------------------------------------------------------------------------
- gen_reorder_and_separate : if(g_fft.use_separate or g_fft.use_reorder) generate
- in_cplx <= last_im & last_re;
+ gen_reorder_and_separate : if g_fft.use_separate or g_fft.use_reorder generate
+ in_cplx <= data_im(0) & data_re(0);
u_reorder_sep : entity work.fft_reorder_sepa_pipe
generic map (
@@ -227,20 +226,23 @@ begin
port map (
clk => clk,
rst => rst,
- in_dat => in_cplx,
+ in_dat => in_cplx, -- c_nof_complex * g_fft.stage_dat_w
in_val => data_val(0),
- out_dat => out_cplx,
+ out_dat => out_cplx, -- c_nof_complex * c_raw_dat_w
out_val => raw_out_val
);
+ -- c_raw_dat_w = g_fft.stage_dat_w when g_fft.use_separate = false
+ -- c_raw_dat_w = g_fft.stage_dat_w + 1 when g_fft.use_separate = true
raw_out_re <= out_cplx( c_raw_dat_w-1 downto 0);
raw_out_im <= out_cplx(2*c_raw_dat_w-1 downto c_raw_dat_w);
end generate;
- no_reorder_no_seperate : if(g_fft.use_separate=false and g_fft.use_reorder=false) generate
- raw_out_re <= last_re;
- raw_out_im <= last_im;
+ no_reorder_no_seperate : if g_fft.use_separate=false and g_fft.use_reorder=false generate
+ -- c_raw_dat_w = g_fft.stage_dat_w because g_fft.use_separate = false
+ raw_out_re <= data_re(0);
+ raw_out_im <= data_im(0);
raw_out_val <= data_val(0);
end generate;
@@ -250,7 +252,7 @@ begin
u_requantize_re : entity common_lib.common_requantize
generic map (
g_representation => "SIGNED",
- g_lsb_w => c_out_scale_w + c_raw_dat_extra_w,
+ g_lsb_w => c_out_scale_w + c_sepa_growth_w,
g_lsb_round => TRUE,
g_lsb_round_clip => FALSE,
g_msb_clip => FALSE,
@@ -270,7 +272,7 @@ begin
u_requantize_im : entity common_lib.common_requantize
generic map (
g_representation => "SIGNED",
- g_lsb_w => c_out_scale_w + c_raw_dat_extra_w,
+ g_lsb_w => c_out_scale_w + c_sepa_growth_w,
g_lsb_round => TRUE,
g_lsb_round_clip => FALSE,
g_msb_clip => FALSE,
@@ -303,6 +305,8 @@ begin
u_unswitch : ENTITY work.fft_unswitch
GENERIC MAP (
g_switch_en => c_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
g_fft_sz_w => c_switch_sz_w,
g_dat_w => c_unswitch_dat_w
)
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
index da55a674b03786958fe8ee3f4545643f0664232d..017e5b1384983d66a423fe605f4259e54fc1d4ae 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
@@ -77,8 +77,7 @@ entity fft_r2_wide is
generic (
g_fft : t_fft := c_fft; -- generics for the FFT
g_pft_pipeline : t_fft_pipeline := c_fft_pipeline; -- For the pipelined part, from rTwoSDF_lib.rTwoSDFPkg
- g_fft_pipeline : t_fft_pipeline := c_fft_pipeline; -- For the parallel part, from rTwoSDF_lib.rTwoSDFPkg
- g_r2_mul_extra_w : natural := 0 -- extra bits at rTwoWMul output in rTwoSDFStage to improve rTwoSDFStage output requantization in fft_r2_pipe
+ g_fft_pipeline : t_fft_pipeline := c_fft_pipeline -- For the parallel part, from rTwoSDF_lib.rTwoSDFPkg
);
port (
clk : in std_logic;
@@ -153,18 +152,25 @@ architecture rtl of fft_r2_wide is
constant c_out_scale_w : integer := c_fft_r2_par.out_dat_w - g_fft.out_dat_w - g_fft.out_gain_w; -- Estimate number of LSBs to throw away when > 0 or insert when < 0
+ constant c_sepa_growth_w : natural := sel_a_b(g_fft.use_separate, 1, 0); -- add one bit for add sub growth in separate
+ constant c_raw_dat_w : natural := g_fft.stage_dat_w + c_sepa_growth_w;
+
+ -- g_fft.wb_factor = 1
+ signal fft_pipe_out_re : std_logic_vector(g_fft.out_dat_w-1 downto 0);
+ signal fft_pipe_out_im : std_logic_vector(g_fft.out_dat_w-1 downto 0);
+
+ -- g_fft.wb_factor > 1 and < g_fft.nof_points
signal in_fft_pipe_re_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
signal in_fft_pipe_im_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
signal out_fft_pipe_re_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
signal out_fft_pipe_im_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
+ signal out_fft_pipe_val : std_logic_vector(g_fft.wb_factor-1 downto 0);
+ signal in_fft_par : std_logic; -- = out_fft_pipe_val(0)
signal in_fft_par_re_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
signal in_fft_par_im_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
- signal fft_pipe_out_re : std_logic_vector(g_fft.out_dat_w-1 downto 0);
- signal fft_pipe_out_im : std_logic_vector(g_fft.out_dat_w-1 downto 0);
-
signal fft_out_re_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
signal fft_out_im_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
signal fft_out_val : std_logic;
@@ -173,11 +179,6 @@ architecture rtl of fft_r2_wide is
signal sep_out_im_arr : t_fft_slv_arr(g_fft.wb_factor-1 downto 0);
signal sep_out_val : std_logic;
- signal int_val : std_logic_vector(g_fft.wb_factor-1 downto 0);
-
- signal out_cplx : std_logic_vector(c_nof_complex*g_fft.stage_dat_w-1 downto 0);
- signal in_cplx : std_logic_vector(c_nof_complex*g_fft.stage_dat_w-1 downto 0);
-
begin
-- Default to fft_r2_pipe when g_fft.wb_factor=1
@@ -185,8 +186,7 @@ begin
u_fft_r2_pipe : entity work.fft_r2_pipe
generic map (
g_fft => g_fft,
- g_pipeline => g_pft_pipeline,
- g_r2_mul_extra_w => g_r2_mul_extra_w
+ g_pipeline => g_pft_pipeline
)
port map (
clk => clk,
@@ -241,8 +241,7 @@ begin
u_pft : entity work.fft_r2_pipe
generic map (
g_fft => c_fft_r2_pipe_arr(I), -- generics for the pipelined FFTs
- g_pipeline => g_pft_pipeline, -- pipeline generics for the pipelined FFTs
- g_r2_mul_extra_w => g_r2_mul_extra_w
+ g_pipeline => g_pft_pipeline -- pipeline generics for the pipelined FFTs
)
port map (
clk => clk,
@@ -252,7 +251,7 @@ begin
in_val => in_val,
out_re => out_fft_pipe_re_arr(I)(c_fft_r2_pipe_arr(I).out_dat_w-1 downto 0),
out_im => out_fft_pipe_im_arr(I)(c_fft_r2_pipe_arr(I).out_dat_w-1 downto 0),
- out_val => int_val(I)
+ out_val => out_fft_pipe_val(I)
);
end generate;
@@ -261,6 +260,8 @@ begin
-- PARALLEL FFT STAGE
---------------------------------------------------------------
+ in_fft_par <= out_fft_pipe_val(0);
+
-- Create input for parallel FFT
gen_inputs_for_par : for I in g_fft.wb_factor-1 downto 0 generate
in_fft_par_re_arr(I) <= resize_fft_svec(out_fft_pipe_re_arr(I)(c_fft_r2_pipe_arr(I).out_dat_w-1 downto 0));
@@ -279,7 +280,7 @@ begin
rst => rst,
in_re_arr => in_fft_par_re_arr,
in_im_arr => in_fft_par_im_arr,
- in_val => int_val(0),
+ in_val => in_fft_par,
out_re_arr => fft_out_re_arr,
out_im_arr => fft_out_im_arr,
out_val => fft_out_val
@@ -320,14 +321,14 @@ begin
u_requantize_output_re : entity common_lib.common_requantize
generic map (
g_representation => "SIGNED",
- g_lsb_w => c_out_scale_w,
+ g_lsb_w => c_out_scale_w + c_sepa_growth_w,
g_lsb_round => TRUE,
g_lsb_round_clip => FALSE,
g_msb_clip => FALSE,
g_msb_clip_symmetric => FALSE,
g_pipeline_remove_lsb => c_pipeline_remove_lsb,
g_pipeline_remove_msb => 0,
- g_in_dat_w => g_fft.stage_dat_w,
+ g_in_dat_w => c_raw_dat_w,
g_out_dat_w => g_fft.out_dat_w
)
port map (
@@ -340,14 +341,14 @@ begin
u_requantize_output_im : entity common_lib.common_requantize
generic map (
g_representation => "SIGNED",
- g_lsb_w => c_out_scale_w,
+ g_lsb_w => c_out_scale_w + c_sepa_growth_w,
g_lsb_round => TRUE,
g_lsb_round_clip => FALSE,
g_msb_clip => FALSE,
g_msb_clip_symmetric => FALSE,
g_pipeline_remove_lsb => c_pipeline_remove_lsb,
g_pipeline_remove_msb => 0,
- g_in_dat_w => g_fft.stage_dat_w,
+ g_in_dat_w => c_raw_dat_w,
g_out_dat_w => g_fft.out_dat_w
)
port map (
diff --git a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
index 89d056fb82dfdf09df5302911545fc375820e9d5..b363745caf022d3cf0e9716eef1cfcaea424c8e5 100644
--- a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
@@ -51,9 +51,9 @@ entity fft_reorder_sepa_pipe is
port (
clk : in std_logic;
rst : in std_logic;
- in_dat : in std_logic_vector;
+ in_dat : in std_logic_vector; -- c_dat_w
in_val : in std_logic;
- out_dat : out std_logic_vector;
+ out_dat : out std_logic_vector; -- c_dat_w when g_separate = false, else c_dat_w + 2
out_val : out std_logic
);
end entity fft_reorder_sepa_pipe;
@@ -323,9 +323,9 @@ begin
port map (
clk => clk,
rst => rst,
- in_dat => out_dat_i,
+ in_dat => out_dat_i, -- c_dat_w
in_val => out_val_i,
- out_dat => out_dat,
+ out_dat => out_dat, -- c_dat_w + 2
out_val => out_val
);
end generate;
@@ -335,8 +335,8 @@ begin
-- the output signals are directly driven.
gen_no_separate : if g_separate=false generate
rd_adr <= TO_UVEC(r.count_up, c_adr_tot_w);
- out_dat <= out_dat_i;
- out_val <= out_val_i;
+ out_dat <= out_dat_i; -- c_dat_w
+ out_val <= out_val_i;
end generate;
end rtl;
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
index 5bf2423a8595c65f9e3218c48f4ab6fc01906049..65da081cd733226a48086dbffdc5be08e4499516 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
@@ -41,17 +41,9 @@
-- B.imag(m) = (X.real(N-m) - X.real(m))/2
--
-- Remarks:
--- . The add and sub output of the separate have 1 bit growth that needs to be
--- rounded. Simply skipping 1 LSbit is not suitable, because it yields
--- asymmetry around 0 and thus a DC offset. For example for N = 3-bit data:
--- x = -4 -3 -2 -1 0 1 2 3
--- round(x/2) = -2 -2 -1 -1 0 1 1 2 = common_round for signed
--- floor(x/2) = -2 -2 -1 -1 0 0 1 1 = truncation
--- The most negative value can be ignored:
--- x : mean(-3 -2 -1 0 1 2 3) = 0
--- . round(x/2) : mean(-2 -1 -1 0 1 1 2) = 0
--- . floor(x/2) : mean(-2 -1 -1 0 0 1 1) = -2/8 = -0.25 = -2^(N-1)/2 / 2^N
--- So the DC offset due to truncation is -0.25 LSbit, independent of N.
+-- . The A, B outputs are scaled by factor 2 due to separate add and sub.
+-- Therefore in_dat re, im have c_in_data_w bits and out_dat re, im have
+-- c_out_data_w = c_in_data_w + 1 bits, to avoid overflow.
library IEEE, common_lib;
use IEEE.std_logic_1164.ALL;
@@ -62,40 +54,40 @@ entity fft_sepa is
port (
clk : in std_logic;
rst : in std_logic;
- in_dat : in std_logic_vector;
+ in_dat : in std_logic_vector; -- c_nof_complex * c_in_data_w
in_val : in std_logic;
- out_dat : out std_logic_vector;
+ out_dat : out std_logic_vector; -- c_nof_complex * c_out_data_w = c_nof_complex * (c_in_data_w + 1)
out_val : out std_logic
);
end entity fft_sepa;
architecture rtl of fft_sepa is
- constant c_sepa_round : boolean := true; -- must be true, because separate should round the 1 bit growth
-
- constant c_data_w : natural := in_dat'length/c_nof_complex;
- constant c_c_data_w : natural := c_nof_complex*c_data_w;
- constant c_pipeline : natural := 3;
+ constant c_in_data_w : natural := in_dat'length / c_nof_complex;
+ constant c_in_complex_w : natural := c_nof_complex * c_in_data_w;
+ constant c_out_data_w : natural := c_in_data_w + 1;
+ constant c_out_complex_w : natural := c_nof_complex * c_out_data_w;
+ constant c_pipeline : natural := 3;
- type reg_type is record
- switch : std_logic; -- Register used to toggle between A & B definitionn
- val_dly : std_logic_vector(c_pipeline-1 downto 0); -- Register that delays the incoming valid signal
- xn_m_reg : std_logic_vector(c_c_data_w-1 downto 0); -- Register to hold the X(N-m) value for one cycle
- xm_reg : std_logic_vector(c_c_data_w-1 downto 0); -- Register to hold the X(m) value for one cycle
- add_reg_a : std_logic_vector(c_data_w-1 downto 0); -- Input register A for the adder
- add_reg_b : std_logic_vector(c_data_w-1 downto 0); -- Input register B for the adder
- sub_reg_a : std_logic_vector(c_data_w-1 downto 0); -- Input register A for the subtractor
- sub_reg_b : std_logic_vector(c_data_w-1 downto 0); -- Input register B for the subtractor
- out_dat : std_logic_vector(c_c_data_w-1 downto 0); -- Registered output value
- out_val : std_logic; -- Registered data valid signal
+ type t_reg is record
+ switch : std_logic; -- Register used to toggle between A & B definitionn
+ val_dly : std_logic_vector(c_pipeline-1 downto 0); -- Register that delays the incoming valid signal
+ xn_m_reg : std_logic_vector(c_in_complex_w-1 downto 0); -- Register to hold the X(N-m) value for one cycle
+ xm_reg : std_logic_vector(c_in_complex_w-1 downto 0); -- Register to hold the X(m) value for one cycle
+ add_reg_a : std_logic_vector(c_in_data_w-1 downto 0); -- Input register A for the adder
+ add_reg_b : std_logic_vector(c_in_data_w-1 downto 0); -- Input register B for the adder
+ sub_reg_a : std_logic_vector(c_in_data_w-1 downto 0); -- Input register A for the subtractor
+ sub_reg_b : std_logic_vector(c_in_data_w-1 downto 0); -- Input register B for the subtractor
+ out_dat : std_logic_vector(c_out_complex_w-1 downto 0); -- Registered output value
+ out_val : std_logic; -- Registered data valid signal
end record;
+
+ constant c_reg_init : t_reg := ('0', (others=>'0'), (others=>'0'), (others=>'0'), (others=>'0'), (others=>'0'), (others=>'0'), (others=>'0'), (others=>'0'), '0');
- signal r, rin : reg_type;
- signal sub_result : std_logic_vector(c_data_w downto 0); -- Result of the subtractor
- signal add_result : std_logic_vector(c_data_w downto 0); -- Result of the adder
-
- signal sub_result_q : std_logic_vector(c_data_w-1 downto 0); -- Requantized result of the subtractor
- signal add_result_q : std_logic_vector(c_data_w-1 downto 0); -- Requantized result of the adder
+ signal r : t_reg := c_reg_init;
+ signal rin : t_reg;
+ signal sub_result : std_logic_vector(c_out_data_w-1 downto 0); -- Result of the subtractor
+ signal add_result : std_logic_vector(c_out_data_w-1 downto 0); -- Result of the adder
begin
@@ -108,8 +100,8 @@ begin
g_representation => "SIGNED",
g_pipeline_input => 0,
g_pipeline_output => 1,
- g_in_dat_w => c_data_w,
- g_out_dat_w => c_data_w + 1
+ g_in_dat_w => c_in_data_w,
+ g_out_dat_w => c_out_data_w -- = c_in_data_w + 1
)
port map (
clk => clk,
@@ -124,8 +116,8 @@ begin
g_representation => "SIGNED",
g_pipeline_input => 0,
g_pipeline_output => 1,
- g_in_dat_w => c_data_w,
- g_out_dat_w => c_data_w + 1
+ g_in_dat_w => c_in_data_w,
+ g_out_dat_w => c_out_data_w -- = c_in_data_w + 1
)
port map (
clk => clk,
@@ -134,52 +126,11 @@ begin
result => sub_result
);
- gen_sepa_truncate : IF c_sepa_round=FALSE GENERATE
- -- truncate the one LSbit
- add_result_q <= add_result(c_data_w downto 1);
- sub_result_q <= sub_result(c_data_w downto 1);
- end generate;
-
- gen_sepa_round : IF c_sepa_round=TRUE GENERATE
- -- round the one LSbit
- round_add : ENTITY common_lib.common_round
- GENERIC MAP (
- g_representation => "SIGNED", -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_round => TRUE, -- when TRUE round the input, else truncate the input
- g_round_clip => FALSE, -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_pipeline_input => 0, -- >= 0
- g_pipeline_output => 0, -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
- g_in_dat_w => c_data_w+1,
- g_out_dat_w => c_data_w
- )
- PORT MAP (
- clk => clk,
- in_dat => add_result,
- out_dat => add_result_q
- );
-
- round_sub : ENTITY common_lib.common_round
- GENERIC MAP (
- g_representation => "SIGNED", -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
- g_round => TRUE, -- when TRUE round the input, else truncate the input
- g_round_clip => FALSE, -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
- g_pipeline_input => 0, -- >= 0
- g_pipeline_output => 0, -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
- g_in_dat_w => c_data_w+1,
- g_out_dat_w => c_data_w
- )
- PORT MAP (
- clk => clk,
- in_dat => sub_result,
- out_dat => sub_result_q
- );
- end generate;
-
---------------------------------------------------------------
-- CONTROL PROCESS
---------------------------------------------------------------
- comb : process(r, rst, in_val, in_dat, add_result_q, sub_result_q)
- variable v : reg_type;
+ comb : process(r, rst, in_val, in_dat, add_result, sub_result)
+ variable v : t_reg;
begin
v := r;
@@ -188,7 +139,7 @@ begin
v.val_dly(0) := in_val;
-- Composition of the output registers:
- v.out_dat := sub_result_q & add_result_q;
+ v.out_dat := sub_result & add_result;
v.out_val := r.val_dly(c_pipeline-1);
-- Compose the inputs for the adder and subtractor
@@ -196,16 +147,16 @@ begin
if in_val = '1' or r.val_dly(0) = '1' then
if r.switch = '0' then
v.xm_reg := in_dat;
- v.add_reg_a := r.xm_reg(c_c_data_w-1 downto c_data_w); -- Xm imag
- v.add_reg_b := r.xn_m_reg(c_c_data_w-1 downto c_data_w); -- Xn-m imag
- v.sub_reg_a := r.xn_m_reg(c_data_w-1 downto 0); -- Xn-m real
- v.sub_reg_b := r.xm_reg(c_data_w-1 downto 0); -- Xm real
+ v.add_reg_a := r.xm_reg(c_in_complex_w-1 downto c_in_data_w); -- Xm imag
+ v.add_reg_b := r.xn_m_reg(c_in_complex_w-1 downto c_in_data_w); -- Xn-m imag
+ v.sub_reg_a := r.xn_m_reg(c_in_data_w-1 downto 0); -- Xn-m real
+ v.sub_reg_b := r.xm_reg(c_in_data_w-1 downto 0); -- Xm real
else
v.xn_m_reg := in_dat;
- v.add_reg_a := r.xm_reg(c_data_w-1 downto 0); -- Xm real
- v.add_reg_b := in_dat(c_data_w-1 downto 0); -- Xn-m real
- v.sub_reg_a := r.xm_reg(c_c_data_w-1 downto c_data_w); -- Xm imag
- v.sub_reg_b := in_dat(c_c_data_w-1 downto c_data_w); -- Xn-m imag
+ v.add_reg_a := r.xm_reg(c_in_data_w-1 downto 0); -- Xm real
+ v.add_reg_b := in_dat(c_in_data_w-1 downto 0); -- Xn-m real
+ v.sub_reg_a := r.xm_reg(c_in_complex_w-1 downto c_in_data_w); -- Xm imag
+ v.sub_reg_b := in_dat(c_in_complex_w-1 downto c_in_data_w); -- Xn-m imag
end if;
end if;
@@ -213,16 +164,10 @@ begin
v.switch := not r.switch;
end if;
- if(rst = '1') then
+ if rst = '1' then
+ -- Only need to reset the control signals
v.switch := '0';
v.val_dly := (others => '0');
- v.xn_m_reg := (others => '0');
- v.xm_reg := (others => '0');
- v.add_reg_a := (others => '0');
- v.add_reg_b := (others => '0');
- v.sub_reg_a := (others => '0');
- v.sub_reg_b := (others => '0');
- v.out_dat := (others => '0');
v.out_val := '0';
end if;
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
index a950206d5e537f7f015195ad88cbe668f4f5951d..0af4993aee9dfc7d3db23ba938b08ad8ecc42863 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
@@ -67,11 +67,17 @@ architecture rtl of fft_sepa_wide is
constant c_page_size : natural := g_fft.nof_points/g_fft.wb_factor; -- Size of the memories
constant c_nof_pages : natural := 2; -- The number of pages in each ram.
- constant c_dat_w : natural := c_nof_complex*g_fft.stage_dat_w; -- Data width for the internal vectors where real and imag are combined.
+ constant c_in_w : natural := g_fft.stage_dat_w;
+ constant c_dat_w : natural := c_nof_complex*c_in_w; -- Data width for the internal vectors where real and imag are combined.
constant c_adr_w : natural := ceil_log2(c_page_size); -- Address width of the rams
constant c_nof_streams : natural := 2; -- Number of inputstreams for the zip units
- type t_dat_arr is array(integer range <> ) of std_logic_vector(c_dat_w-1 downto 0);
+ constant c_sepa_growth_w : natural := sel_a_b(g_fft.use_separate, 1, 0); -- add one bit for add sub growth in separate
+ constant c_out_w : natural := c_in_w + c_sepa_growth_w;
+ constant c_raw_dat_w : natural := c_nof_complex*c_out_w; -- = c_dat_w or c_dat_w + 2
+
+ type t_dat_arr is array(integer range <> ) of std_logic_vector(c_dat_w-1 downto 0);
+ type t_raw_dat_arr is array(integer range <> ) of std_logic_vector(c_raw_dat_w-1 downto 0);
type t_rd_adr_arr is array(integer range <> ) of std_logic_vector(c_adr_w-1 downto 0);
type t_zip_in_matrix is array(integer range <> ) of t_slv_64_arr(1 downto 0); -- Every Zip unit has two inputs.
@@ -85,24 +91,27 @@ architecture rtl of fft_sepa_wide is
signal zip_in_matrix : t_zip_in_matrix(g_fft.wb_factor-1 downto 0); -- Matrix that contains the inputs for zip units
signal zip_in_val : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector that holds the data input valids for the zip units
- signal zip_out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the outputs of all zip units.
+ signal zip_out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the outputs of all zip units.
signal zip_out_val : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector that holds the output valids of the zip units
- signal sep_out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the outputs of the separation blocks
+ signal sep_out_dat_arr : t_raw_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the outputs of the separation blocks
signal sep_out_val_vec : std_logic_vector(g_fft.wb_factor-1 downto 0); -- Vector containing the datavalids from the separation blocks
- signal out_dat_arr : t_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the ouput values, where real and imag are concatenated
+ signal out_dat_arr : t_raw_dat_arr(g_fft.wb_factor-1 downto 0); -- Array that holds the ouput values, where real and imag are concatenated
- type state_type is (s_idle, s_read);
- type reg_type is record
+ type t_state is (s_idle, s_read);
+ type t_reg is record
switch : std_logic; -- Toggle register used for separate functionalilty
count_up : natural range 0 to c_page_size; -- An upwards counter for read addressing
count_down : natural range 0 to c_page_size; -- A downwards counter for read addressing
val_odd : std_logic; -- Register that drives the in_valid of the odd zip units
val_even : std_logic; -- Register that drives the in_valid of the even zip units
- state : state_type; -- The state machine.
+ state : t_state; -- The state machine.
end record;
- signal r, rin : reg_type;
+ constant c_reg_init : t_reg := ('0', 0, 0, '0', '0', s_idle);
+
+ signal r : t_reg := c_reg_init;
+ signal rin : t_reg;
begin
@@ -111,7 +120,7 @@ begin
---------------------------------------------------------------
-- Prepare the data for the dual paged memory. Real and imaginary part are concatenated into one vector.
gen_prep_write_data : for I in 0 to g_fft.wb_factor-1 generate
- wr_dat(I) <= in_im_arr(I)(g_fft.stage_dat_w-1 downto 0) & in_re_arr(I)(g_fft.stage_dat_w-1 downto 0);
+ wr_dat(I) <= in_im_arr(I)(c_in_w-1 downto 0) & in_re_arr(I)(c_in_w-1 downto 0);
end generate;
-- Prepare the write control signals for the memories.
@@ -204,9 +213,9 @@ begin
port map (
clk => clk,
rst => rst,
- in_dat => zip_out_dat_arr(I),
+ in_dat => zip_out_dat_arr(I), -- c_dat_w
in_val => zip_out_val(I),
- out_dat => sep_out_dat_arr(I),
+ out_dat => sep_out_dat_arr(I), -- c_dat_w + 2
out_val => sep_out_val_vec(I)
);
end generate;
@@ -218,13 +227,13 @@ begin
-- the fellow toggle signals. It also controls the starting and stopping
-- of the data stream.
comb : process(r, rst, next_page)
- variable v : reg_type;
+ variable v : t_reg;
begin
v := r;
case r.state is
- when s_idle =>
+ when s_idle =>
v.switch := '0';
v.val_odd := '0';
v.val_even := '0';
@@ -234,7 +243,7 @@ begin
v.state := s_read;
end if;
- when s_read =>
+ when s_read =>
if(r.switch = '0') then -- Toggle the switch register from 0 to 1
v.switch := '1';
end if;
@@ -255,22 +264,17 @@ begin
v.val_odd := r.switch; -- Assignment of the odd and even markers
v.val_even := not(r.switch);
- when others =>
- v.state := s_idle;
+ when others =>
+ v.state := s_idle;
- end case;
+ end case;
- if(rst = '1') then
- v.switch := '0';
- v.count_up := 0;
- v.count_down := 0;
- v.val_odd := '0';
- v.val_even := '0';
- v.state := s_idle;
+ if rst = '1' then
+ v := c_reg_init;
end if;
rin <= v;
-
+
end process comb;
regs : process(clk)
@@ -287,8 +291,8 @@ begin
u_output_pipeline_align : entity common_lib.common_pipeline
generic map (
g_pipeline => c_pipeline_output + 1, -- Pipeline + one stage for allignment
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => c_raw_dat_w
)
port map (
clk => clk,
@@ -299,8 +303,8 @@ begin
u_output_pipeline : entity common_lib.common_pipeline
generic map (
g_pipeline => c_pipeline_output, -- Only pipeline stage
- g_in_dat_w => c_dat_w,
- g_out_dat_w => c_dat_w
+ g_in_dat_w => c_raw_dat_w,
+ g_out_dat_w => c_raw_dat_w
)
port map (
clk => clk,
@@ -321,8 +325,8 @@ begin
-- Split the concatenated array into a real and imaginary array for the output
gen_output_arrays : for I in g_fft.wb_factor-1 downto 0 generate
- out_re_arr(I) <= resize_fft_svec(out_dat_arr(I)( g_fft.stage_dat_w-1 downto 0));
- out_im_arr(I) <= resize_fft_svec(out_dat_arr(I)(c_nof_complex*g_fft.stage_dat_w-1 downto g_fft.stage_dat_w));
+ out_re_arr(I) <= resize_fft_svec(out_dat_arr(I)( c_out_w-1 downto 0));
+ out_im_arr(I) <= resize_fft_svec(out_dat_arr(I)(c_nof_complex*c_out_w-1 downto c_out_w));
end generate;
end rtl;
diff --git a/libraries/dsp/fft/src/vhdl/fft_switch.vhd b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
index cad57405ab3b2c03ed84834171fab082b2ed6b51..9da13b566ede8834d55739437b8515417fac3bf5 100644
--- a/libraries/dsp/fft/src/vhdl/fft_switch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
@@ -46,10 +46,13 @@
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
+USE work.fft_pkg.ALL;
ENTITY fft_switch IS
GENERIC (
g_switch_en : BOOLEAN := FALSE;
+ g_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed1;
+ g_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed2;
g_fft_sz_w : NATURAL;
g_dat_w : NATURAL
);
@@ -156,6 +159,10 @@ BEGIN
END PROCESS;
u_fft_lfsr: ENTITY work.fft_lfsr
+ GENERIC MAP (
+ g_seed1 => g_seed1,
+ g_seed2 => g_seed2
+ )
PORT MAP (
clk => clk,
rst => rst,
diff --git a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
index 6d9f561a15e7ca184f70c418810bd85f9b1ac6d6..f94f12e7f0954a3b6af011504a33052e471bef90 100644
--- a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
@@ -31,10 +31,13 @@
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
+USE work.fft_pkg.ALL;
ENTITY fft_unswitch IS
GENERIC (
g_switch_en : BOOLEAN := FALSE;
+ g_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed1;
+ g_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := c_fft_switch_seed2;
g_fft_sz_w : NATURAL;
g_dat_w : NATURAL
);
@@ -147,6 +150,10 @@ BEGIN
END PROCESS;
u_fft_lfsr: ENTITY work.fft_lfsr
+ GENERIC MAP (
+ g_seed1 => g_seed1,
+ g_seed2 => g_seed2
+ )
PORT MAP (
clk => clk,
rst => rst,
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..23791ba61bcdf56d68adae81c6b3d1672fb22166
--- /dev/null
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
@@ -0,0 +1,92 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Verify fft_lsfr for different seeds
+-- Description:
+-- Check that after c_fft_lfsr_len = 41 blocks the LFSR1 and LFSR2 bits of
+-- the two instances u0 and u1 indeed start to differ.
+--
+-- Usage:
+-- > as 4
+-- > run -all
+-- # Not self checking, manually compare that u0_lfsr_bit1 and u1_lfsr_bit1
+-- start to differ after about c_fft_lfsr_len blocks. Similar for
+-- u0_lfsr_bit1 and u1_lfsr_bit1.
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.fft_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_fft_lfsr IS
+END tb_fft_lfsr;
+
+ARCHITECTURE tb OF tb_fft_lfsr IS
+
+ CONSTANT clk_period : TIME := 10 ns;
+
+ CONSTANT c_block_period : NATURAL := 10;
+ CONSTANT c_nof_block : NATURAL := 1000;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC := '1';
+ SIGNAL clk : STD_LOGIC := '0';
+
+ SIGNAL in_en : STD_LOGIC := '0';
+ SIGNAL u0_lfsr_bit1 : STD_LOGIC;
+ SIGNAL u1_lfsr_bit1 : STD_LOGIC;
+ SIGNAL u0_lfsr_bit2 : STD_LOGIC;
+ SIGNAL u1_lfsr_bit2 : STD_LOGIC;
+
+BEGIN
+
+ clk <= NOT clk OR tb_end AFTER clk_period/2;
+ rst <= '1', '0' AFTER 10 * clk_period;
+ tb_end <= '0', '1' AFTER c_nof_block * c_block_period * clk_period;
+
+ proc_common_gen_pulse(1, c_block_period, '1', rst, clk, in_en);
+
+ u0 : ENTITY work.fft_lfsr
+ GENERIC MAP (
+ g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 0),
+ g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 0)
+ )
+ PORT MAP (
+ in_en => in_en,
+ out_bit1 => u0_lfsr_bit1,
+ out_bit2 => u0_lfsr_bit2,
+ clk => clk,
+ rst => rst
+ );
+
+ u1 : ENTITY work.fft_lfsr
+ GENERIC MAP (
+ g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 1),
+ g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 1)
+ )
+ PORT MAP (
+ in_en => in_en,
+ out_bit1 => u1_lfsr_bit1,
+ out_bit2 => u1_lfsr_bit2,
+ clk => clk,
+ rst => rst
+ );
+
+END tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
index 08d04ee3e9bae1ffaea762e535be0d38d97395f6..981f017da2af2a9125e6155283168f6e17d83542 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
@@ -52,9 +52,11 @@ LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
+USE work.fft_pkg.ALL;
ENTITY tb_fft_switch IS
GENERIC (
+ g_instance_index : NATURAL := 0;
g_switch_en : BOOLEAN := TRUE;
g_in_val_gaps : BOOLEAN := TRUE;
g_increment_at_val : BOOLEAN := TRUE;
@@ -66,9 +68,9 @@ END tb_fft_switch;
ARCHITECTURE tb OF tb_fft_switch IS
- CONSTANT clk_period : TIME := 10 ns;
+ CONSTANT clk_period : TIME := 10 ns;
- CONSTANT c_dat_w : NATURAL := 16;
+ CONSTANT c_dat_w : NATURAL := 16;
CONSTANT c_nof_clk_per_block : NATURAL := 2**g_fft_size_w;
CONSTANT c_nof_block_per_sync_max : NATURAL := ceil_div(g_nof_clk_per_sync, c_nof_clk_per_block);
@@ -76,6 +78,9 @@ ARCHITECTURE tb OF tb_fft_switch IS
CONSTANT c_dly : NATURAL := 4; -- pipeling in fft_switch, mux, fft_unswitch and demux
+ constant c_switch_seed1 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := fft_switch_new_seed(c_fft_switch_seed1, g_instance_index);
+ constant c_switch_seed2 : STD_LOGIC_VECTOR(c_fft_lfsr_len-1 DOWNTO 0) := fft_switch_new_seed(c_fft_switch_seed2, g_instance_index);
+
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL rst : STD_LOGIC := '1';
SIGNAL clk : STD_LOGIC := '0';
@@ -185,6 +190,8 @@ BEGIN
u_fft_switch : ENTITY work.fft_switch
GENERIC MAP (
g_switch_en => g_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
g_fft_sz_w => g_fft_size_w,
g_dat_w => c_dat_w
)
@@ -227,6 +234,8 @@ BEGIN
u_fft_unswitch : ENTITY work.fft_unswitch
GENERIC MAP (
g_switch_en => g_switch_en,
+ g_seed1 => c_switch_seed1,
+ g_seed2 => c_switch_seed2,
g_fft_sz_w => g_fft_size_w,
g_dat_w => c_dat_w
)
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b.dat b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..20c9f1b27db52abf1b319c9a8ff5cb0388be8aba
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b.dat
@@ -0,0 +1,16384 @@
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new file mode 100644
index 0000000000000000000000000000000000000000..d170e2c22b177d4a00d6c4cfc43894f0fbdbf192
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_0.mif
@@ -0,0 +1,1030 @@
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+ 3ff : 0 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_1.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_1.mif
new file mode 100644
index 0000000000000000000000000000000000000000..2cc0a0370beaeaefc4c317ce4dea2d06e126b787
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_1.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fa : 14 ;
+ 3fb : 14 ;
+ 3fc : 14 ;
+ 3fd : 14 ;
+ 3fe : 14 ;
+ 3ff : 14 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_10.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_10.mif
new file mode 100644
index 0000000000000000000000000000000000000000..bea45867565063964b736b1d99b83fc96cfbf72c
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_10.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : f0 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_11.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_11.mif
new file mode 100644
index 0000000000000000000000000000000000000000..103581ed6c6b2dc86e29d8b20d496f9f7c87cab0
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_11.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fe : ff69 ;
+ 3ff : ff6e ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_12.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_12.mif
new file mode 100644
index 0000000000000000000000000000000000000000..158121871cc48b2b9f01860ee88baac4b2f3751d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_12.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 1a ;
+ 1 : 1c ;
+ 2 : 1d ;
+ 3 : 1e ;
+ 4 : 1f ;
+ 5 : 20 ;
+ 6 : 21 ;
+ 7 : 22 ;
+ 8 : 24 ;
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+ 3f9 : 40 ;
+ 3fa : 3d ;
+ 3fb : 3a ;
+ 3fc : 38 ;
+ 3fd : 35 ;
+ 3fe : 32 ;
+ 3ff : 30 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_13.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_13.mif
new file mode 100644
index 0000000000000000000000000000000000000000..2cc0f975ccd95fa8b5492d43760067bdb9f2fc25
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_13.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : ffcf ;
+ 1 : ffcf ;
+ 2 : ffce ;
+ 3 : ffce ;
+ 4 : ffce ;
+ 5 : ffcd ;
+ 6 : ffcd ;
+ 7 : ffcc ;
+ 8 : ffcc ;
+ 9 : ffcc ;
+ a : ffcb ;
+ b : ffcb ;
+ c : ffcb ;
+ d : ffca ;
+ e : ffca ;
+ f : ffca ;
+ 10 : ffc9 ;
+ 11 : ffc9 ;
+ 12 : ffc8 ;
+ 13 : ffc8 ;
+ 14 : ffc8 ;
+ 15 : ffc7 ;
+ 16 : ffc7 ;
+ 17 : ffc7 ;
+ 18 : ffc6 ;
+ 19 : ffc6 ;
+ 1a : ffc5 ;
+ 1b : ffc5 ;
+ 1c : ffc5 ;
+ 1d : ffc4 ;
+ 1e : ffc4 ;
+ 1f : ffc4 ;
+ 20 : ffc3 ;
+ 21 : ffc3 ;
+ 22 : ffc2 ;
+ 23 : ffc2 ;
+ 24 : ffc2 ;
+ 25 : ffc1 ;
+ 26 : ffc1 ;
+ 27 : ffc1 ;
+ 28 : ffc0 ;
+ 29 : ffc0 ;
+ 2a : ffbf ;
+ 2b : ffbf ;
+ 2c : ffbf ;
+ 2d : ffbe ;
+ 2e : ffbe ;
+ 2f : ffbd ;
+ 30 : ffbd ;
+ 31 : ffbd ;
+ 32 : ffbc ;
+ 33 : ffbc ;
+ 34 : ffbc ;
+ 35 : ffbb ;
+ 36 : ffbb ;
+ 37 : ffba ;
+ 38 : ffba ;
+ 39 : ffba ;
+ 3a : ffb9 ;
+ 3b : ffb9 ;
+ 3c : ffb8 ;
+ 3d : ffb8 ;
+ 3e : ffb8 ;
+ 3f : ffb7 ;
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+ 41 : ffb6 ;
+ 42 : ffb6 ;
+ 43 : ffb6 ;
+ 44 : ffb5 ;
+ 45 : ffb5 ;
+ 46 : ffb4 ;
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+ 48 : ffb4 ;
+ 49 : ffb3 ;
+ 4a : ffb3 ;
+ 4b : ffb2 ;
+ 4c : ffb2 ;
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+ 4e : ffb1 ;
+ 4f : ffb1 ;
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+ 59 : ffad ;
+ 5a : ffad ;
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+ 7d : ff9e ;
+ 7e : ff9e ;
+ 7f : ff9d ;
+ 80 : ff9d ;
+ 81 : ff9d ;
+ 82 : ff9c ;
+ 83 : ff9c ;
+ 84 : ff9b ;
+ 85 : ff9b ;
+ 86 : ff9b ;
+ 87 : ff9a ;
+ 88 : ff9a ;
+ 89 : ff99 ;
+ 8a : ff99 ;
+ 8b : ff99 ;
+ 8c : ff98 ;
+ 8d : ff98 ;
+ 8e : ff97 ;
+ 8f : ff97 ;
+ 90 : ff96 ;
+ 91 : ff96 ;
+ 92 : ff96 ;
+ 93 : ff95 ;
+ 94 : ff95 ;
+ 95 : ff94 ;
+ 96 : ff94 ;
+ 97 : ff94 ;
+ 98 : ff93 ;
+ 99 : ff93 ;
+ 9a : ff92 ;
+ 9b : ff92 ;
+ 9c : ff91 ;
+ 9d : ff91 ;
+ 9e : ff91 ;
+ 9f : ff90 ;
+ a0 : ff90 ;
+ a1 : ff8f ;
+ a2 : ff8f ;
+ a3 : ff8f ;
+ a4 : ff8e ;
+ a5 : ff8e ;
+ a6 : ff8d ;
+ a7 : ff8d ;
+ a8 : ff8d ;
+ a9 : ff8c ;
+ aa : ff8c ;
+ ab : ff8b ;
+ ac : ff8b ;
+ ad : ff8a ;
+ ae : ff8a ;
+ af : ff8a ;
+ b0 : ff89 ;
+ b1 : ff89 ;
+ b2 : ff88 ;
+ b3 : ff88 ;
+ b4 : ff88 ;
+ b5 : ff87 ;
+ b6 : ff87 ;
+ b7 : ff86 ;
+ b8 : ff86 ;
+ b9 : ff85 ;
+ ba : ff85 ;
+ bb : ff85 ;
+ bc : ff84 ;
+ bd : ff84 ;
+ be : ff83 ;
+ bf : ff83 ;
+ c0 : ff83 ;
+ c1 : ff82 ;
+ c2 : ff82 ;
+ c3 : ff81 ;
+ c4 : ff81 ;
+ c5 : ff81 ;
+ c6 : ff80 ;
+ c7 : ff80 ;
+ c8 : ff7f ;
+ c9 : ff7f ;
+ ca : ff7e ;
+ cb : ff7e ;
+ cc : ff7e ;
+ cd : ff7d ;
+ ce : ff7d ;
+ cf : ff7c ;
+ d0 : ff7c ;
+ d1 : ff7c ;
+ d2 : ff7b ;
+ d3 : ff7b ;
+ d4 : ff7a ;
+ d5 : ff7a ;
+ d6 : ff79 ;
+ d7 : ff79 ;
+ d8 : ff79 ;
+ d9 : ff78 ;
+ da : ff78 ;
+ db : ff77 ;
+ dc : ff77 ;
+ dd : ff77 ;
+ de : ff76 ;
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+ e0 : ff75 ;
+ e1 : ff75 ;
+ e2 : ff75 ;
+ e3 : ff74 ;
+ e4 : ff74 ;
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+ e7 : ff73 ;
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+ ea : ff71 ;
+ eb : ff71 ;
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+ ef : ff6f ;
+ f0 : ff6f ;
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+ f3 : ff6e ;
+ f4 : ff6d ;
+ f5 : ff6d ;
+ f6 : ff6c ;
+ f7 : ff6c ;
+ f8 : ff6c ;
+ f9 : ff6b ;
+ fa : ff6b ;
+ fb : ff6a ;
+ fc : ff6a ;
+ fd : ff6a ;
+ fe : ff69 ;
+ ff : ff69 ;
+ 100 : ff68 ;
+ 101 : ff68 ;
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+ 10a : ff64 ;
+ 10b : ff64 ;
+ 10c : ff64 ;
+ 10d : ff63 ;
+ 10e : ff63 ;
+ 10f : ff63 ;
+ 110 : ff62 ;
+ 111 : ff62 ;
+ 112 : ff61 ;
+ 113 : ff61 ;
+ 114 : ff61 ;
+ 115 : ff60 ;
+ 116 : ff60 ;
+ 117 : ff5f ;
+ 118 : ff5f ;
+ 119 : ff5f ;
+ 11a : ff5e ;
+ 11b : ff5e ;
+ 11c : ff5d ;
+ 11d : ff5d ;
+ 11e : ff5d ;
+ 11f : ff5c ;
+ 120 : ff5c ;
+ 121 : ff5c ;
+ 122 : ff5b ;
+ 123 : ff5b ;
+ 124 : ff5a ;
+ 125 : ff5a ;
+ 126 : ff5a ;
+ 127 : ff59 ;
+ 128 : ff59 ;
+ 129 : ff58 ;
+ 12a : ff58 ;
+ 12b : ff58 ;
+ 12c : ff57 ;
+ 12d : ff57 ;
+ 12e : ff57 ;
+ 12f : ff56 ;
+ 130 : ff56 ;
+ 131 : ff55 ;
+ 132 : ff55 ;
+ 133 : ff55 ;
+ 134 : ff54 ;
+ 135 : ff54 ;
+ 136 : ff54 ;
+ 137 : ff53 ;
+ 138 : ff53 ;
+ 139 : ff53 ;
+ 13a : ff52 ;
+ 13b : ff52 ;
+ 13c : ff51 ;
+ 13d : ff51 ;
+ 13e : ff51 ;
+ 13f : ff50 ;
+ 140 : ff50 ;
+ 141 : ff50 ;
+ 142 : ff4f ;
+ 143 : ff4f ;
+ 144 : ff4f ;
+ 145 : ff4e ;
+ 146 : ff4e ;
+ 147 : ff4d ;
+ 148 : ff4d ;
+ 149 : ff4d ;
+ 14a : ff4c ;
+ 14b : ff4c ;
+ 14c : ff4c ;
+ 14d : ff4b ;
+ 14e : ff4b ;
+ 14f : ff4b ;
+ 150 : ff4a ;
+ 151 : ff4a ;
+ 152 : ff4a ;
+ 153 : ff49 ;
+ 154 : ff49 ;
+ 155 : ff48 ;
+ 156 : ff48 ;
+ 157 : ff48 ;
+ 158 : ff47 ;
+ 159 : ff47 ;
+ 15a : ff47 ;
+ 15b : ff46 ;
+ 15c : ff46 ;
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+ 161 : ff44 ;
+ 162 : ff44 ;
+ 163 : ff44 ;
+ 164 : ff43 ;
+ 165 : ff43 ;
+ 166 : ff43 ;
+ 167 : ff42 ;
+ 168 : ff42 ;
+ 169 : ff42 ;
+ 16a : ff41 ;
+ 16b : ff41 ;
+ 16c : ff41 ;
+ 16d : ff40 ;
+ 16e : ff40 ;
+ 16f : ff40 ;
+ 170 : ff3f ;
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+ 178 : ff3d ;
+ 179 : ff3d ;
+ 17a : ff3c ;
+ 17b : ff3c ;
+ 17c : ff3c ;
+ 17d : ff3b ;
+ 17e : ff3b ;
+ 17f : ff3b ;
+ 180 : ff3a ;
+ 181 : ff3a ;
+ 182 : ff3a ;
+ 183 : ff3a ;
+ 184 : ff39 ;
+ 185 : ff39 ;
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+ 188 : ff38 ;
+ 189 : ff38 ;
+ 18a : ff37 ;
+ 18b : ff37 ;
+ 18c : ff37 ;
+ 18d : ff37 ;
+ 18e : ff36 ;
+ 18f : ff36 ;
+ 190 : ff36 ;
+ 191 : ff35 ;
+ 192 : ff35 ;
+ 193 : ff35 ;
+ 194 : ff35 ;
+ 195 : ff34 ;
+ 196 : ff34 ;
+ 197 : ff34 ;
+ 198 : ff33 ;
+ 199 : ff33 ;
+ 19a : ff33 ;
+ 19b : ff33 ;
+ 19c : ff32 ;
+ 19d : ff32 ;
+ 19e : ff32 ;
+ 19f : ff32 ;
+ 1a0 : ff31 ;
+ 1a1 : ff31 ;
+ 1a2 : ff31 ;
+ 1a3 : ff30 ;
+ 1a4 : ff30 ;
+ 1a5 : ff30 ;
+ 1a6 : ff30 ;
+ 1a7 : ff2f ;
+ 1a8 : ff2f ;
+ 1a9 : ff2f ;
+ 1aa : ff2f ;
+ 1ab : ff2e ;
+ 1ac : ff2e ;
+ 1ad : ff2e ;
+ 1ae : ff2e ;
+ 1af : ff2d ;
+ 1b0 : ff2d ;
+ 1b1 : ff2d ;
+ 1b2 : ff2d ;
+ 1b3 : ff2c ;
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+ 2ca : ff32 ;
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+ 3e8 : 0 ;
+ 3e9 : 1 ;
+ 3ea : 2 ;
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+ 3ed : 5 ;
+ 3ee : 6 ;
+ 3ef : 8 ;
+ 3f0 : 9 ;
+ 3f1 : a ;
+ 3f2 : b ;
+ 3f3 : c ;
+ 3f4 : d ;
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+ 3f9 : 13 ;
+ 3fa : 14 ;
+ 3fb : 15 ;
+ 3fc : 16 ;
+ 3fd : 17 ;
+ 3fe : 18 ;
+ 3ff : 19 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_14.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_14.mif
new file mode 100644
index 0000000000000000000000000000000000000000..5a92e5dfc5dae4bdfa695f58f37cc0d766535cd2
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_14.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 14 ;
+ 1 : 14 ;
+ 2 : 14 ;
+ 3 : 14 ;
+ 4 : 14 ;
+ 5 : 14 ;
+ 6 : 14 ;
+ 7 : 14 ;
+ 8 : 14 ;
+ 9 : 14 ;
+ a : 14 ;
+ b : 14 ;
+ c : 14 ;
+ d : 14 ;
+ e : 14 ;
+ f : 14 ;
+ 10 : 15 ;
+ 11 : 15 ;
+ 12 : 15 ;
+ 13 : 15 ;
+ 14 : 15 ;
+ 15 : 15 ;
+ 16 : 15 ;
+ 17 : 15 ;
+ 18 : 15 ;
+ 19 : 15 ;
+ 1a : 15 ;
+ 1b : 15 ;
+ 1c : 15 ;
+ 1d : 15 ;
+ 1e : 15 ;
+ 1f : 15 ;
+ 20 : 16 ;
+ 21 : 16 ;
+ 22 : 16 ;
+ 23 : 16 ;
+ 24 : 16 ;
+ 25 : 16 ;
+ 26 : 16 ;
+ 27 : 16 ;
+ 28 : 16 ;
+ 29 : 16 ;
+ 2a : 16 ;
+ 2b : 16 ;
+ 2c : 16 ;
+ 2d : 16 ;
+ 2e : 16 ;
+ 2f : 16 ;
+ 30 : 17 ;
+ 31 : 17 ;
+ 32 : 17 ;
+ 33 : 17 ;
+ 34 : 17 ;
+ 35 : 17 ;
+ 36 : 17 ;
+ 37 : 17 ;
+ 38 : 17 ;
+ 39 : 17 ;
+ 3a : 17 ;
+ 3b : 17 ;
+ 3c : 17 ;
+ 3d : 17 ;
+ 3e : 17 ;
+ 3f : 18 ;
+ 40 : 18 ;
+ 41 : 18 ;
+ 42 : 18 ;
+ 43 : 18 ;
+ 44 : 18 ;
+ 45 : 18 ;
+ 46 : 18 ;
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+ 48 : 18 ;
+ 49 : 18 ;
+ 4a : 18 ;
+ 4b : 18 ;
+ 4c : 18 ;
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+ 4f : 19 ;
+ 50 : 19 ;
+ 51 : 19 ;
+ 52 : 19 ;
+ 53 : 19 ;
+ 54 : 19 ;
+ 55 : 19 ;
+ 56 : 19 ;
+ 57 : 19 ;
+ 58 : 19 ;
+ 59 : 19 ;
+ 5a : 19 ;
+ 5b : 19 ;
+ 5c : 19 ;
+ 5d : 1a ;
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+ 5f : 1a ;
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+ 99 : 1e ;
+ 9a : 1e ;
+ 9b : 1e ;
+ 9c : 1e ;
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+ a0 : 1e ;
+ a1 : 1e ;
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+ a3 : 1e ;
+ a4 : 1e ;
+ a5 : 1e ;
+ a6 : 1e ;
+ a7 : 1f ;
+ a8 : 1f ;
+ a9 : 1f ;
+ aa : 1f ;
+ ab : 1f ;
+ ac : 1f ;
+ ad : 1f ;
+ ae : 1f ;
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+ b0 : 1f ;
+ b1 : 1f ;
+ b2 : 1f ;
+ b3 : 1f ;
+ b4 : 1f ;
+ b5 : 1f ;
+ b6 : 20 ;
+ b7 : 20 ;
+ b8 : 20 ;
+ b9 : 20 ;
+ ba : 20 ;
+ bb : 20 ;
+ bc : 20 ;
+ bd : 20 ;
+ be : 20 ;
+ bf : 20 ;
+ c0 : 20 ;
+ c1 : 20 ;
+ c2 : 20 ;
+ c3 : 20 ;
+ c4 : 20 ;
+ c5 : 21 ;
+ c6 : 21 ;
+ c7 : 21 ;
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+ ca : 21 ;
+ cb : 21 ;
+ cc : 21 ;
+ cd : 21 ;
+ ce : 21 ;
+ cf : 21 ;
+ d0 : 21 ;
+ d1 : 21 ;
+ d2 : 21 ;
+ d3 : 21 ;
+ d4 : 22 ;
+ d5 : 22 ;
+ d6 : 22 ;
+ d7 : 22 ;
+ d8 : 22 ;
+ d9 : 22 ;
+ da : 22 ;
+ db : 22 ;
+ dc : 22 ;
+ dd : 22 ;
+ de : 22 ;
+ df : 22 ;
+ e0 : 22 ;
+ e1 : 22 ;
+ e2 : 22 ;
+ e3 : 22 ;
+ e4 : 23 ;
+ e5 : 23 ;
+ e6 : 23 ;
+ e7 : 23 ;
+ e8 : 23 ;
+ e9 : 23 ;
+ ea : 23 ;
+ eb : 23 ;
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+ ef : 23 ;
+ f0 : 23 ;
+ f1 : 23 ;
+ f2 : 23 ;
+ f3 : 23 ;
+ f4 : 24 ;
+ f5 : 24 ;
+ f6 : 24 ;
+ f7 : 24 ;
+ f8 : 24 ;
+ f9 : 24 ;
+ fa : 24 ;
+ fb : 24 ;
+ fc : 24 ;
+ fd : 24 ;
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+ 10b : 25 ;
+ 10c : 25 ;
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+ 12a : 27 ;
+ 12b : 27 ;
+ 12c : 27 ;
+ 12d : 27 ;
+ 12e : 27 ;
+ 12f : 27 ;
+ 130 : 27 ;
+ 131 : 27 ;
+ 132 : 27 ;
+ 133 : 27 ;
+ 134 : 27 ;
+ 135 : 27 ;
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_15.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_15.mif
new file mode 100644
index 0000000000000000000000000000000000000000..fa29e6a821bf25556f105268a2bc48783c58404d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_15.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_2.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_2.mif
new file mode 100644
index 0000000000000000000000000000000000000000..db082680b6cb4ae82b28386cc66f1a917a95b401
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_2.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3d5 : ffbf ;
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+ 3d8 : ffc1 ;
+ 3d9 : ffc1 ;
+ 3da : ffc1 ;
+ 3db : ffc2 ;
+ 3dc : ffc2 ;
+ 3dd : ffc2 ;
+ 3de : ffc3 ;
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+ 3e0 : ffc4 ;
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+ 3e4 : ffc5 ;
+ 3e5 : ffc5 ;
+ 3e6 : ffc6 ;
+ 3e7 : ffc6 ;
+ 3e8 : ffc7 ;
+ 3e9 : ffc7 ;
+ 3ea : ffc7 ;
+ 3eb : ffc8 ;
+ 3ec : ffc8 ;
+ 3ed : ffc8 ;
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+ 3ef : ffc9 ;
+ 3f0 : ffca ;
+ 3f1 : ffca ;
+ 3f2 : ffca ;
+ 3f3 : ffcb ;
+ 3f4 : ffcb ;
+ 3f5 : ffcb ;
+ 3f6 : ffcc ;
+ 3f7 : ffcc ;
+ 3f8 : ffcc ;
+ 3f9 : ffcd ;
+ 3fa : ffcd ;
+ 3fb : ffce ;
+ 3fc : ffce ;
+ 3fd : ffce ;
+ 3fe : ffcf ;
+ 3ff : ffcf ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_3.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_3.mif
new file mode 100644
index 0000000000000000000000000000000000000000..ea6f0d96792e99c38132050ba0bf4ef49461d8cd
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_3.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 30 ;
+ 1 : 32 ;
+ 2 : 35 ;
+ 3 : 38 ;
+ 4 : 3a ;
+ 5 : 3d ;
+ 6 : 40 ;
+ 7 : 42 ;
+ 8 : 45 ;
+ 9 : 48 ;
+ a : 4a ;
+ b : 4d ;
+ c : 50 ;
+ d : 52 ;
+ e : 55 ;
+ f : 58 ;
+ 10 : 5a ;
+ 11 : 5d ;
+ 12 : 60 ;
+ 13 : 62 ;
+ 14 : 65 ;
+ 15 : 67 ;
+ 16 : 6a ;
+ 17 : 6d ;
+ 18 : 6f ;
+ 19 : 72 ;
+ 1a : 74 ;
+ 1b : 77 ;
+ 1c : 79 ;
+ 1d : 7c ;
+ 1e : 7f ;
+ 1f : 81 ;
+ 20 : 84 ;
+ 21 : 86 ;
+ 22 : 89 ;
+ 23 : 8b ;
+ 24 : 8e ;
+ 25 : 90 ;
+ 26 : 93 ;
+ 27 : 95 ;
+ 28 : 98 ;
+ 29 : 9a ;
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+ 3fc : 1e ;
+ 3fd : 1d ;
+ 3fe : 1c ;
+ 3ff : 1a ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_4.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_4.mif
new file mode 100644
index 0000000000000000000000000000000000000000..0394c4527e784a41f64dbcba0498852ba80cafb0
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_4.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fa : 1f ;
+ 3fb : 22 ;
+ 3fc : 25 ;
+ 3fd : 28 ;
+ 3fe : 2a ;
+ 3ff : 2d ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_5.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_5.mif
new file mode 100644
index 0000000000000000000000000000000000000000..7c1872dbcb348ba453075776fb162292d78179d1
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_5.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : f0 ;
+ 1 : fc ;
+ 2 : 108 ;
+ 3 : 114 ;
+ 4 : 120 ;
+ 5 : 12d ;
+ 6 : 139 ;
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+ 8 : 151 ;
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_6.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_6.mif
new file mode 100644
index 0000000000000000000000000000000000000000..73ba26830318c23d4c179c88c2a993b51b4b5c29
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_6.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : e4 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_7.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_7.mif
new file mode 100644
index 0000000000000000000000000000000000000000..227c6ecd94134349abf3928c611c3a20593c0d0d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_7.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_8.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_8.mif
new file mode 100644
index 0000000000000000000000000000000000000000..52d873d1e232431640cf281a15f20f40b25b6b90
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_8.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 7fff ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_9.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_9.mif
new file mode 100644
index 0000000000000000000000000000000000000000..ab8ffdc575796f4260be60e2a0288ba99856ef66
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_16b_1wb_9.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : e4 ;
+ 1 : d8 ;
+ 2 : cc ;
+ 3 : bf ;
+ 4 : b3 ;
+ 5 : a7 ;
+ 6 : 9b ;
+ 7 : 8e ;
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+ 3da : fab0 ;
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+ 3f0 : fd13 ;
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+ 3f9 : fe18 ;
+ 3fa : fe35 ;
+ 3fb : fe52 ;
+ 3fc : fe6f ;
+ 3fd : fe8d ;
+ 3fe : feaa ;
+ 3ff : fec8 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b.dat b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..55f5823fa873ae2dd512ced936037f3fac80004e
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b.dat
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diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_0.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_0.mif
new file mode 100644
index 0000000000000000000000000000000000000000..4a32e54e81e3339fed8ce5d261e6d08932837323
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_0.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_1.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_1.mif
new file mode 100644
index 0000000000000000000000000000000000000000..2187ea619609b4d5bf4cbab9455bc44477806d8e
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_1.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_10.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_10.mif
new file mode 100644
index 0000000000000000000000000000000000000000..40b6fdf41f1c47f3f3e157e7f4992848f3fdf251
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_10.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_11.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_11.mif
new file mode 100644
index 0000000000000000000000000000000000000000..d79cd97d63ce699abb582e728731f8ad62739370
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_11.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fc : 3fd74 ;
+ 3fd : 3fd8b ;
+ 3fe : 3fda2 ;
+ 3ff : 3fdb9 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_12.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_12.mif
new file mode 100644
index 0000000000000000000000000000000000000000..cae98f690ba350b4d98339427a96a9c935288a76
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_12.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_13.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_13.mif
new file mode 100644
index 0000000000000000000000000000000000000000..234c7cbf2bea7ed8261ba876959b70ea72583b3f
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_13.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fc : 58 ;
+ 3fd : 5c ;
+ 3fe : 61 ;
+ 3ff : 65 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_14.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_14.mif
new file mode 100644
index 0000000000000000000000000000000000000000..1cddfc9b303050089d0d69d08ac4a8fe4e9d3693
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_14.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 4e ;
+ 1 : 4e ;
+ 2 : 4f ;
+ 3 : 4f ;
+ 4 : 4f ;
+ 5 : 4f ;
+ 6 : 50 ;
+ 7 : 50 ;
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diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_15.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_15.mif
new file mode 100644
index 0000000000000000000000000000000000000000..4ab568fc35f4a14f28f481cb09fc8b1849c73b88
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_15.mif
@@ -0,0 +1,1030 @@
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_2.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_2.mif
new file mode 100644
index 0000000000000000000000000000000000000000..4cde602863aedd33b87c9d3a5c887b6bb1da5889
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_2.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fe : 3ff3b ;
+ 3ff : 3ff3c ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_3.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_3.mif
new file mode 100644
index 0000000000000000000000000000000000000000..46cd3ab4b5b92ba139b9f17cbd212f0363d605e8
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_3.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : bf ;
+ 1 : c9 ;
+ 2 : d4 ;
+ 3 : df ;
+ 4 : ea ;
+ 5 : f4 ;
+ 6 : ff ;
+ 7 : 10a ;
+ 8 : 115 ;
+ 9 : 11f ;
+ a : 12a ;
+ b : 134 ;
+ c : 13f ;
+ d : 14a ;
+ e : 154 ;
+ f : 15f ;
+ 10 : 169 ;
+ 11 : 174 ;
+ 12 : 17e ;
+ 13 : 188 ;
+ 14 : 193 ;
+ 15 : 19d ;
+ 16 : 1a8 ;
+ 17 : 1b2 ;
+ 18 : 1bc ;
+ 19 : 1c7 ;
+ 1a : 1d1 ;
+ 1b : 1db ;
+ 1c : 1e6 ;
+ 1d : 1f0 ;
+ 1e : 1fa ;
+ 1f : 204 ;
+ 20 : 20e ;
+ 21 : 219 ;
+ 22 : 223 ;
+ 23 : 22d ;
+ 24 : 237 ;
+ 25 : 241 ;
+ 26 : 24b ;
+ 27 : 255 ;
+ 28 : 25f ;
+ 29 : 269 ;
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+ 3fa : 80 ;
+ 3fb : 7c ;
+ 3fc : 77 ;
+ 3fd : 73 ;
+ 3fe : 6e ;
+ 3ff : 6a ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_4.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_4.mif
new file mode 100644
index 0000000000000000000000000000000000000000..48e506d4ddc7e2ad6c8f835a01ba0c031b7202fc
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_4.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fc : 93 ;
+ 3fd : 9e ;
+ 3fe : a9 ;
+ 3ff : b4 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_5.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_5.mif
new file mode 100644
index 0000000000000000000000000000000000000000..ac5320b77b7b39dcdae634e420889cd7bf765254
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_5.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_6.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_6.mif
new file mode 100644
index 0000000000000000000000000000000000000000..e2ecd51fb120ce498e35ca8791f1a1f2feda771b
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_6.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fb : 2cc ;
+ 3fc : 2fd ;
+ 3fd : 32e ;
+ 3fe : 35f ;
+ 3ff : 390 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_7.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_7.mif
new file mode 100644
index 0000000000000000000000000000000000000000..88a1201055d483286cc97e3465cffa2189ff5a13
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_7.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 1ffff ;
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+ 3ff : 3fb97 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_8.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_8.mif
new file mode 100644
index 0000000000000000000000000000000000000000..a1decd202425656bb64ebdfb2aac222cc291974e
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_8.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fc : 1fffc ;
+ 3fd : 1fffe ;
+ 3fe : 1ffff ;
+ 3ff : 1ffff ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_9.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_9.mif
new file mode 100644
index 0000000000000000000000000000000000000000..9e10e8f1e1465c473dcf2d9eaa8ff737f6a06929
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_18b_1wb_9.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 390 ;
+ 1 : 35f ;
+ 2 : 32e ;
+ 3 : 2fd ;
+ 4 : 2cc ;
+ 5 : 29b ;
+ 6 : 26a ;
+ 7 : 239 ;
+ 8 : 208 ;
+ 9 : 1d6 ;
+ a : 1a5 ;
+ b : 174 ;
+ c : 142 ;
+ d : 110 ;
+ e : df ;
+ f : ad ;
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+ 3fc : 3f9be ;
+ 3fd : 3fa34 ;
+ 3fe : 3faaa ;
+ 3ff : 3fb20 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b.dat b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..2faf3e1372763b52f6cb7996e8b3bca695b86bb8
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b.dat
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diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_0.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_0.mif
new file mode 100644
index 0000000000000000000000000000000000000000..70cb9a1f82d67c28e4d38f21adc8382b32ce0658
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_0.mif
@@ -0,0 +1,1030 @@
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_1.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_1.mif
new file mode 100644
index 0000000000000000000000000000000000000000..777a619e9f8028d48b93fd1a03f50ff173adac25
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_1.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_10.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_10.mif
new file mode 100644
index 0000000000000000000000000000000000000000..e3f6d4d154bb8fa0e4905169d235d94972d02d9e
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_10.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fe : fc3 ;
+ 3ff : f01 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_11.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_11.mif
new file mode 100644
index 0000000000000000000000000000000000000000..dd460eb1a43bb1db7ab1bc8e326de4831d3d459d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_11.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_12.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_12.mif
new file mode 100644
index 0000000000000000000000000000000000000000..9027e0e82c38f549d18ea5c80b5abce0d415f61d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_12.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fe : 326 ;
+ 3ff : 2fb ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_13.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_13.mif
new file mode 100644
index 0000000000000000000000000000000000000000..e3afc43096d87593851e74f4cd04ed44a0a1b771
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_13.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : ffcf0 ;
+ 1 : ffcea ;
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+ 5 : ffcd3 ;
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+ 3fa : 13c ;
+ 3fb : 14e ;
+ 3fc : 15f ;
+ 3fd : 171 ;
+ 3fe : 183 ;
+ 3ff : 195 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_14.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_14.mif
new file mode 100644
index 0000000000000000000000000000000000000000..834907fbffedba3dc35ffd3190106b615d988386
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_14.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 138 ;
+ 1 : 139 ;
+ 2 : 13a ;
+ 3 : 13b ;
+ 4 : 13c ;
+ 5 : 13d ;
+ 6 : 13e ;
+ 7 : 13f ;
+ 8 : 140 ;
+ 9 : 141 ;
+ a : 142 ;
+ b : 143 ;
+ c : 144 ;
+ d : 145 ;
+ e : 146 ;
+ f : 147 ;
+ 10 : 148 ;
+ 11 : 149 ;
+ 12 : 14a ;
+ 13 : 14b ;
+ 14 : 14c ;
+ 15 : 14d ;
+ 16 : 14e ;
+ 17 : 14f ;
+ 18 : 150 ;
+ 19 : 151 ;
+ 1a : 152 ;
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+ 25 : 15e ;
+ 26 : 15f ;
+ 27 : 160 ;
+ 28 : 161 ;
+ 29 : 162 ;
+ 2a : 163 ;
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+ 31 : 16a ;
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+ 38 : 171 ;
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_15.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_15.mif
new file mode 100644
index 0000000000000000000000000000000000000000..d6b1a87a10114b97bb8d289d1b96d4c0ec040f9b
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_15.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
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+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fe : 136 ;
+ 3ff : 137 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_2.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_2.mif
new file mode 100644
index 0000000000000000000000000000000000000000..0b65ded2484c79ec172be5f4b66465c85dc58015
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_2.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 195 ;
+ 1 : 183 ;
+ 2 : 171 ;
+ 3 : 15f ;
+ 4 : 14e ;
+ 5 : 13c ;
+ 6 : 12a ;
+ 7 : 118 ;
+ 8 : 106 ;
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+ 21d : ff22a ;
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+ 221 : ff235 ;
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+ 22a : ff250 ;
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+ 22c : ff256 ;
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+ 22e : ff25d ;
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+ 236 : ff277 ;
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+ 23b : ff288 ;
+ 23c : ff28b ;
+ 23d : ff28f ;
+ 23e : ff293 ;
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+ 240 : ff29a ;
+ 241 : ff29d ;
+ 242 : ff2a1 ;
+ 243 : ff2a5 ;
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+ 245 : ff2ac ;
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+ 250 : ff2d6 ;
+ 251 : ff2da ;
+ 252 : ff2de ;
+ 253 : ff2e2 ;
+ 254 : ff2e6 ;
+ 255 : ff2ea ;
+ 256 : ff2ee ;
+ 257 : ff2f3 ;
+ 258 : ff2f7 ;
+ 259 : ff2fb ;
+ 25a : ff2ff ;
+ 25b : ff303 ;
+ 25c : ff307 ;
+ 25d : ff30c ;
+ 25e : ff310 ;
+ 25f : ff314 ;
+ 260 : ff318 ;
+ 261 : ff31d ;
+ 262 : ff321 ;
+ 263 : ff325 ;
+ 264 : ff32a ;
+ 265 : ff32e ;
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+ 268 : ff33c ;
+ 269 : ff340 ;
+ 26a : ff344 ;
+ 26b : ff349 ;
+ 26c : ff34d ;
+ 26d : ff352 ;
+ 26e : ff357 ;
+ 26f : ff35b ;
+ 270 : ff360 ;
+ 271 : ff364 ;
+ 272 : ff369 ;
+ 273 : ff36e ;
+ 274 : ff372 ;
+ 275 : ff377 ;
+ 276 : ff37c ;
+ 277 : ff381 ;
+ 278 : ff385 ;
+ 279 : ff38a ;
+ 27a : ff38f ;
+ 27b : ff394 ;
+ 27c : ff398 ;
+ 27d : ff39d ;
+ 27e : ff3a2 ;
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+ 28a : ff3de ;
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+ 292 : ff407 ;
+ 293 : ff40c ;
+ 294 : ff411 ;
+ 295 : ff417 ;
+ 296 : ff41c ;
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+ 298 : ff426 ;
+ 299 : ff42c ;
+ 29a : ff431 ;
+ 29b : ff436 ;
+ 29c : ff43c ;
+ 29d : ff441 ;
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+ 2a0 : ff451 ;
+ 2a1 : ff457 ;
+ 2a2 : ff45c ;
+ 2a3 : ff461 ;
+ 2a4 : ff467 ;
+ 2a5 : ff46c ;
+ 2a6 : ff472 ;
+ 2a7 : ff477 ;
+ 2a8 : ff47d ;
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+ 2aa : ff488 ;
+ 2ab : ff48d ;
+ 2ac : ff493 ;
+ 2ad : ff499 ;
+ 2ae : ff49e ;
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+ 2b0 : ff4a9 ;
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+ 2c4 : ff51c ;
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+ 2ca : ff540 ;
+ 2cb : ff546 ;
+ 2cc : ff54c ;
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+ 2dc : ff5ac ;
+ 2dd : ff5b2 ;
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+ 2df : ff5bf ;
+ 2e0 : ff5c5 ;
+ 2e1 : ff5cb ;
+ 2e2 : ff5d1 ;
+ 2e3 : ff5d7 ;
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+ 2e5 : ff5e4 ;
+ 2e6 : ff5ea ;
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+ 2fa : ff667 ;
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+ 3b0 : ffb0e ;
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+ 3b2 : ffb1b ;
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+ 3b4 : ffb28 ;
+ 3b5 : ffb2e ;
+ 3b6 : ffb34 ;
+ 3b7 : ffb3b ;
+ 3b8 : ffb41 ;
+ 3b9 : ffb47 ;
+ 3ba : ffb4e ;
+ 3bb : ffb54 ;
+ 3bc : ffb5a ;
+ 3bd : ffb61 ;
+ 3be : ffb67 ;
+ 3bf : ffb6d ;
+ 3c0 : ffb73 ;
+ 3c1 : ffb7a ;
+ 3c2 : ffb80 ;
+ 3c3 : ffb86 ;
+ 3c4 : ffb8d ;
+ 3c5 : ffb93 ;
+ 3c6 : ffb99 ;
+ 3c7 : ffb9f ;
+ 3c8 : ffba5 ;
+ 3c9 : ffbac ;
+ 3ca : ffbb2 ;
+ 3cb : ffbb8 ;
+ 3cc : ffbbe ;
+ 3cd : ffbc4 ;
+ 3ce : ffbcb ;
+ 3cf : ffbd1 ;
+ 3d0 : ffbd7 ;
+ 3d1 : ffbdd ;
+ 3d2 : ffbe3 ;
+ 3d3 : ffbe9 ;
+ 3d4 : ffbf0 ;
+ 3d5 : ffbf6 ;
+ 3d6 : ffbfc ;
+ 3d7 : ffc02 ;
+ 3d8 : ffc08 ;
+ 3d9 : ffc0e ;
+ 3da : ffc14 ;
+ 3db : ffc1a ;
+ 3dc : ffc20 ;
+ 3dd : ffc26 ;
+ 3de : ffc2d ;
+ 3df : ffc33 ;
+ 3e0 : ffc39 ;
+ 3e1 : ffc3f ;
+ 3e2 : ffc45 ;
+ 3e3 : ffc4b ;
+ 3e4 : ffc51 ;
+ 3e5 : ffc57 ;
+ 3e6 : ffc5d ;
+ 3e7 : ffc63 ;
+ 3e8 : ffc69 ;
+ 3e9 : ffc6f ;
+ 3ea : ffc75 ;
+ 3eb : ffc7b ;
+ 3ec : ffc81 ;
+ 3ed : ffc87 ;
+ 3ee : ffc8d ;
+ 3ef : ffc92 ;
+ 3f0 : ffc98 ;
+ 3f1 : ffc9e ;
+ 3f2 : ffca4 ;
+ 3f3 : ffcaa ;
+ 3f4 : ffcb0 ;
+ 3f5 : ffcb6 ;
+ 3f6 : ffcbc ;
+ 3f7 : ffcc2 ;
+ 3f8 : ffcc7 ;
+ 3f9 : ffccd ;
+ 3fa : ffcd3 ;
+ 3fb : ffcd9 ;
+ 3fc : ffcdf ;
+ 3fd : ffce5 ;
+ 3fe : ffcea ;
+ 3ff : ffcf0 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_3.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_3.mif
new file mode 100644
index 0000000000000000000000000000000000000000..110595d7ff667ed6a61b326b155e2b30ed8bbea4
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_3.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 2fb ;
+ 1 : 326 ;
+ 2 : 351 ;
+ 3 : 37c ;
+ 4 : 3a7 ;
+ 5 : 3d2 ;
+ 6 : 3fd ;
+ 7 : 427 ;
+ 8 : 452 ;
+ 9 : 47d ;
+ a : 4a7 ;
+ b : 4d2 ;
+ c : 4fc ;
+ d : 526 ;
+ e : 550 ;
+ f : 57a ;
+ 10 : 5a4 ;
+ 11 : 5ce ;
+ 12 : 5f8 ;
+ 13 : 622 ;
+ 14 : 64c ;
+ 15 : 675 ;
+ 16 : 69f ;
+ 17 : 6c8 ;
+ 18 : 6f2 ;
+ 19 : 71b ;
+ 1a : 744 ;
+ 1b : 76d ;
+ 1c : 796 ;
+ 1d : 7bf ;
+ 1e : 7e8 ;
+ 1f : 811 ;
+ 20 : 83a ;
+ 21 : 862 ;
+ 22 : 88b ;
+ 23 : 8b3 ;
+ 24 : 8db ;
+ 25 : 904 ;
+ 26 : 92c ;
+ 27 : 954 ;
+ 28 : 97c ;
+ 29 : 9a4 ;
+ 2a : 9cc ;
+ 2b : 9f4 ;
+ 2c : a1b ;
+ 2d : a43 ;
+ 2e : a6a ;
+ 2f : a92 ;
+ 30 : ab9 ;
+ 31 : ae0 ;
+ 32 : b07 ;
+ 33 : b2e ;
+ 34 : b55 ;
+ 35 : b7c ;
+ 36 : ba3 ;
+ 37 : bca ;
+ 38 : bf0 ;
+ 39 : c17 ;
+ 3a : c3d ;
+ 3b : c63 ;
+ 3c : c8a ;
+ 3d : cb0 ;
+ 3e : cd6 ;
+ 3f : cfc ;
+ 40 : d21 ;
+ 41 : d47 ;
+ 42 : d6d ;
+ 43 : d92 ;
+ 44 : db8 ;
+ 45 : ddd ;
+ 46 : e03 ;
+ 47 : e28 ;
+ 48 : e4d ;
+ 49 : e72 ;
+ 4a : e97 ;
+ 4b : ebc ;
+ 4c : ee0 ;
+ 4d : f05 ;
+ 4e : f29 ;
+ 4f : f4e ;
+ 50 : f72 ;
+ 51 : f96 ;
+ 52 : fbb ;
+ 53 : fdf ;
+ 54 : 1003 ;
+ 55 : 1026 ;
+ 56 : 104a ;
+ 57 : 106e ;
+ 58 : 1091 ;
+ 59 : 10b5 ;
+ 5a : 10d8 ;
+ 5b : 10fc ;
+ 5c : 111f ;
+ 5d : 1142 ;
+ 5e : 1165 ;
+ 5f : 1188 ;
+ 60 : 11aa ;
+ 61 : 11cd ;
+ 62 : 11f0 ;
+ 63 : 1212 ;
+ 64 : 1234 ;
+ 65 : 1257 ;
+ 66 : 1279 ;
+ 67 : 129b ;
+ 68 : 12bd ;
+ 69 : 12df ;
+ 6a : 1300 ;
+ 6b : 1322 ;
+ 6c : 1344 ;
+ 6d : 1365 ;
+ 6e : 1387 ;
+ 6f : 13a8 ;
+ 70 : 13c9 ;
+ 71 : 13ea ;
+ 72 : 140b ;
+ 73 : 142c ;
+ 74 : 144c ;
+ 75 : 146d ;
+ 76 : 148e ;
+ 77 : 14ae ;
+ 78 : 14ce ;
+ 79 : 14ef ;
+ 7a : 150f ;
+ 7b : 152f ;
+ 7c : 154f ;
+ 7d : 156e ;
+ 7e : 158e ;
+ 7f : 15ae ;
+ 80 : 15cd ;
+ 81 : 15ed ;
+ 82 : 160c ;
+ 83 : 162b ;
+ 84 : 164a ;
+ 85 : 1669 ;
+ 86 : 1688 ;
+ 87 : 16a7 ;
+ 88 : 16c5 ;
+ 89 : 16e4 ;
+ 8a : 1702 ;
+ 8b : 1721 ;
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_4.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_4.mif
new file mode 100644
index 0000000000000000000000000000000000000000..db619dc2c1bdaf85b8791815a90898ae864e9e76
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_4.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
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+ 3fe : 2a4 ;
+ 3ff : 2cf ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_5.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_5.mif
new file mode 100644
index 0000000000000000000000000000000000000000..b2570935a279ab7a3c7d94c209ebbf3c35460b3e
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_5.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_6.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_6.mif
new file mode 100644
index 0000000000000000000000000000000000000000..75fbd56621b76b4b63268563ddee3331d8cd9e89
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_6.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : e3f ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_7.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_7.mif
new file mode 100644
index 0000000000000000000000000000000000000000..f69f2553e17cb196914835aa663a3f920d9b9015
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_7.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fe : ff037 ;
+ 3ff : fee5b ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_8.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_8.mif
new file mode 100644
index 0000000000000000000000000000000000000000..25b48bf05429c245a5d2582c257f5a42594d0b78
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_8.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_9.mif b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_9.mif
new file mode 100644
index 0000000000000000000000000000000000000000..0f6897c46dc632279fac0d57ae29100689c9b3e4
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KHanning_20b_1wb_9.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b.dat b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..a7d31bdfc7cd89b2588db0f2afe4f2604718a5a1
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b.dat
@@ -0,0 +1,16384 @@
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diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_0.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_0.mif
new file mode 100644
index 0000000000000000000000000000000000000000..74319e0999882f0a11453f898efb6334f0932f7d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_0.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 28 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_1.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_1.mif
new file mode 100644
index 0000000000000000000000000000000000000000..8b912cbda10bdf3b2163ae927232cfe21a287bda
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_1.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 1a7 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_10.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_10.mif
new file mode 100644
index 0000000000000000000000000000000000000000..b6559b7ee6fe96aa287fd8de8e81a10ac255dcf8
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_10.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 115 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_11.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_11.mif
new file mode 100644
index 0000000000000000000000000000000000000000..13f550b84755c0029952f102613246a33b593af6
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_11.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 55 ;
+ 1 : 50 ;
+ 2 : 4b ;
+ 3 : 45 ;
+ 4 : 40 ;
+ 5 : 3b ;
+ 6 : 36 ;
+ 7 : 31 ;
+ 8 : 2c ;
+ 9 : 26 ;
+ a : 21 ;
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+ 3fc : ff1c ;
+ 3fd : ff24 ;
+ 3fe : ff2c ;
+ 3ff : ff34 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_12.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_12.mif
new file mode 100644
index 0000000000000000000000000000000000000000..c93d6108e5f46b82cb85188bb19c4feb5d40eb68
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_12.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 4e ;
+ 1 : 51 ;
+ 2 : 55 ;
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+ 3fa : 74 ;
+ 3fb : 6e ;
+ 3fc : 69 ;
+ 3fd : 64 ;
+ 3fe : 5f ;
+ 3ff : 5a ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_13.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_13.mif
new file mode 100644
index 0000000000000000000000000000000000000000..d083bc245d99fad736c779d4555b63db655eabdf
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_13.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : fedc ;
+ 1 : feda ;
+ 2 : fed8 ;
+ 3 : fed6 ;
+ 4 : fed4 ;
+ 5 : fed2 ;
+ 6 : fed1 ;
+ 7 : fecf ;
+ 8 : fecd ;
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+ a : fec9 ;
+ b : fec7 ;
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+ 3fd : 44 ;
+ 3fe : 48 ;
+ 3ff : 4b ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_14.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_14.mif
new file mode 100644
index 0000000000000000000000000000000000000000..1f088073ebccd0241cd56ed6875965ff26508d2e
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_14.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_15.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_15.mif
new file mode 100644
index 0000000000000000000000000000000000000000..e4421573acea5da7a413478ec18246e757cbc0d2
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_15.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_2.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_2.mif
new file mode 100644
index 0000000000000000000000000000000000000000..d8091c23615782ce88ac9b174d4fc49e71f34e11
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_2.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3a0 : fe2a ;
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+ 3a3 : fe2f ;
+ 3a4 : fe31 ;
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+ 3a9 : fe3a ;
+ 3aa : fe3c ;
+ 3ab : fe3e ;
+ 3ac : fe40 ;
+ 3ad : fe42 ;
+ 3ae : fe44 ;
+ 3af : fe45 ;
+ 3b0 : fe47 ;
+ 3b1 : fe49 ;
+ 3b2 : fe4b ;
+ 3b3 : fe4d ;
+ 3b4 : fe4f ;
+ 3b5 : fe51 ;
+ 3b6 : fe52 ;
+ 3b7 : fe54 ;
+ 3b8 : fe56 ;
+ 3b9 : fe58 ;
+ 3ba : fe5a ;
+ 3bb : fe5c ;
+ 3bc : fe5e ;
+ 3bd : fe5f ;
+ 3be : fe61 ;
+ 3bf : fe63 ;
+ 3c0 : fe65 ;
+ 3c1 : fe67 ;
+ 3c2 : fe69 ;
+ 3c3 : fe6b ;
+ 3c4 : fe6c ;
+ 3c5 : fe6e ;
+ 3c6 : fe70 ;
+ 3c7 : fe72 ;
+ 3c8 : fe74 ;
+ 3c9 : fe76 ;
+ 3ca : fe78 ;
+ 3cb : fe7a ;
+ 3cc : fe7b ;
+ 3cd : fe7d ;
+ 3ce : fe7f ;
+ 3cf : fe81 ;
+ 3d0 : fe83 ;
+ 3d1 : fe85 ;
+ 3d2 : fe87 ;
+ 3d3 : fe89 ;
+ 3d4 : fe8b ;
+ 3d5 : fe8c ;
+ 3d6 : fe8e ;
+ 3d7 : fe90 ;
+ 3d8 : fe92 ;
+ 3d9 : fe94 ;
+ 3da : fe96 ;
+ 3db : fe98 ;
+ 3dc : fe9a ;
+ 3dd : fe9b ;
+ 3de : fe9d ;
+ 3df : fe9f ;
+ 3e0 : fea1 ;
+ 3e1 : fea3 ;
+ 3e2 : fea5 ;
+ 3e3 : fea7 ;
+ 3e4 : fea9 ;
+ 3e5 : feab ;
+ 3e6 : feac ;
+ 3e7 : feae ;
+ 3e8 : feb0 ;
+ 3e9 : feb2 ;
+ 3ea : feb4 ;
+ 3eb : feb6 ;
+ 3ec : feb8 ;
+ 3ed : feba ;
+ 3ee : febc ;
+ 3ef : febe ;
+ 3f0 : febf ;
+ 3f1 : fec1 ;
+ 3f2 : fec3 ;
+ 3f3 : fec5 ;
+ 3f4 : fec7 ;
+ 3f5 : fec9 ;
+ 3f6 : fecb ;
+ 3f7 : fecd ;
+ 3f8 : fecf ;
+ 3f9 : fed1 ;
+ 3fa : fed2 ;
+ 3fb : fed4 ;
+ 3fc : fed6 ;
+ 3fd : fed8 ;
+ 3fe : feda ;
+ 3ff : fedc ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_3.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_3.mif
new file mode 100644
index 0000000000000000000000000000000000000000..6c0853418cc02ac4e8580b8af77400814ca714b7
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_3.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 5a ;
+ 1 : 5f ;
+ 2 : 64 ;
+ 3 : 69 ;
+ 4 : 6e ;
+ 5 : 74 ;
+ 6 : 79 ;
+ 7 : 7e ;
+ 8 : 83 ;
+ 9 : 88 ;
+ a : 8d ;
+ b : 92 ;
+ c : 97 ;
+ d : 9c ;
+ e : a1 ;
+ f : a6 ;
+ 10 : ab ;
+ 11 : b0 ;
+ 12 : b5 ;
+ 13 : ba ;
+ 14 : bf ;
+ 15 : c4 ;
+ 16 : c9 ;
+ 17 : ce ;
+ 18 : d3 ;
+ 19 : d8 ;
+ 1a : dd ;
+ 1b : e2 ;
+ 1c : e7 ;
+ 1d : ec ;
+ 1e : f1 ;
+ 1f : f6 ;
+ 20 : fb ;
+ 21 : 100 ;
+ 22 : 105 ;
+ 23 : 10a ;
+ 24 : 10f ;
+ 25 : 114 ;
+ 26 : 119 ;
+ 27 : 11e ;
+ 28 : 123 ;
+ 29 : 127 ;
+ 2a : 12c ;
+ 2b : 131 ;
+ 2c : 136 ;
+ 2d : 13b ;
+ 2e : 140 ;
+ 2f : 145 ;
+ 30 : 149 ;
+ 31 : 14e ;
+ 32 : 153 ;
+ 33 : 158 ;
+ 34 : 15d ;
+ 35 : 161 ;
+ 36 : 166 ;
+ 37 : 16b ;
+ 38 : 170 ;
+ 39 : 175 ;
+ 3a : 179 ;
+ 3b : 17e ;
+ 3c : 183 ;
+ 3d : 188 ;
+ 3e : 18c ;
+ 3f : 191 ;
+ 40 : 196 ;
+ 41 : 19a ;
+ 42 : 19f ;
+ 43 : 1a4 ;
+ 44 : 1a8 ;
+ 45 : 1ad ;
+ 46 : 1b2 ;
+ 47 : 1b6 ;
+ 48 : 1bb ;
+ 49 : 1c0 ;
+ 4a : 1c4 ;
+ 4b : 1c9 ;
+ 4c : 1ce ;
+ 4d : 1d2 ;
+ 4e : 1d7 ;
+ 4f : 1db ;
+ 50 : 1e0 ;
+ 51 : 1e5 ;
+ 52 : 1e9 ;
+ 53 : 1ee ;
+ 54 : 1f2 ;
+ 55 : 1f7 ;
+ 56 : 1fb ;
+ 57 : 200 ;
+ 58 : 204 ;
+ 59 : 209 ;
+ 5a : 20d ;
+ 5b : 212 ;
+ 5c : 216 ;
+ 5d : 21b ;
+ 5e : 21f ;
+ 5f : 224 ;
+ 60 : 228 ;
+ 61 : 22d ;
+ 62 : 231 ;
+ 63 : 236 ;
+ 64 : 23a ;
+ 65 : 23e ;
+ 66 : 243 ;
+ 67 : 247 ;
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+ 3fe : 51 ;
+ 3ff : 4e ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_4.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_4.mif
new file mode 100644
index 0000000000000000000000000000000000000000..7f6f8492266126284cb7a575c741f920c16ea8d5
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_4.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : ff34 ;
+ 1 : ff2c ;
+ 2 : ff24 ;
+ 3 : ff1c ;
+ 4 : ff13 ;
+ 5 : ff0b ;
+ 6 : ff03 ;
+ 7 : fefb ;
+ 8 : fef3 ;
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+ 3fc : 45 ;
+ 3fd : 4b ;
+ 3fe : 50 ;
+ 3ff : 55 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_5.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_5.mif
new file mode 100644
index 0000000000000000000000000000000000000000..004cdc57781d6e161ee8ece2a466b5373a2f61b6
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_5.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 115 ;
+ 1 : 123 ;
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_6.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_6.mif
new file mode 100644
index 0000000000000000000000000000000000000000..e7ea0a360ebf1180a0322c1f7974a76d1273d250
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_6.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_7.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_7.mif
new file mode 100644
index 0000000000000000000000000000000000000000..d935da4c0fda14a6a2e119ee3d4176f2d0646454
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_7.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : fedc ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_8.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_8.mif
new file mode 100644
index 0000000000000000000000000000000000000000..5b19e35ee5804b3f43c284b18a94a7b89f11514b
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_8.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_9.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_9.mif
new file mode 100644
index 0000000000000000000000000000000000000000..28271d09caa09f28223e925f5d5c4a058b8653c5
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_16b_1wb_9.mif
@@ -0,0 +1,1030 @@
+WIDTH=16;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 107 ;
+ 1 : f9 ;
+ 2 : eb ;
+ 3 : dd ;
+ 4 : cf ;
+ 5 : c1 ;
+ 6 : b2 ;
+ 7 : a4 ;
+ 8 : 96 ;
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+ a : 79 ;
+ b : 6b ;
+ c : 5d ;
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b.dat b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..694e2ac9d2f8999c1e2fb0adeb2d6ec14f006783
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b.dat
@@ -0,0 +1,16384 @@
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diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_0.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_0.mif
new file mode 100644
index 0000000000000000000000000000000000000000..3e66dd979a0be6791249fde9df7397fafd366c0f
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_0.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 69a ;
+ 1 : 698 ;
+ 2 : 695 ;
+ 3 : 693 ;
+ 4 : 691 ;
+ 5 : 68f ;
+ 6 : 68d ;
+ 7 : 68a ;
+ 8 : 688 ;
+ 9 : 686 ;
+ a : 684 ;
+ b : 681 ;
+ c : 67f ;
+ d : 67d ;
+ e : 67b ;
+ f : 678 ;
+ 10 : 676 ;
+ 11 : 674 ;
+ 12 : 672 ;
+ 13 : 66f ;
+ 14 : 66d ;
+ 15 : 66b ;
+ 16 : 669 ;
+ 17 : 666 ;
+ 18 : 664 ;
+ 19 : 662 ;
+ 1a : 660 ;
+ 1b : 65d ;
+ 1c : 65b ;
+ 1d : 659 ;
+ 1e : 656 ;
+ 1f : 654 ;
+ 20 : 652 ;
+ 21 : 650 ;
+ 22 : 64d ;
+ 23 : 64b ;
+ 24 : 649 ;
+ 25 : 646 ;
+ 26 : 644 ;
+ 27 : 642 ;
+ 28 : 63f ;
+ 29 : 63d ;
+ 2a : 63b ;
+ 2b : 638 ;
+ 2c : 636 ;
+ 2d : 634 ;
+ 2e : 631 ;
+ 2f : 62f ;
+ 30 : 62d ;
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+ 3fb : 98 ;
+ 3fc : 9c ;
+ 3fd : 9e ;
+ 3fe : a0 ;
+ 3ff : a1 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_1.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_1.mif
new file mode 100644
index 0000000000000000000000000000000000000000..695f3b34e1d18c4c16ed94db8bd347141e299ee7
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_1.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 69c ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_10.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_10.mif
new file mode 100644
index 0000000000000000000000000000000000000000..73823d4e2e458c9b495fd04328cb1e90d6879798
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_10.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 455 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_11.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_11.mif
new file mode 100644
index 0000000000000000000000000000000000000000..019c46b3cb8aaba21924230bb1e8143a4be05bb8
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_11.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 3fcd0 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_12.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_12.mif
new file mode 100644
index 0000000000000000000000000000000000000000..359a1c941a677a2c7bfba5b4bb6e0b18465338ce
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_12.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_13.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_13.mif
new file mode 100644
index 0000000000000000000000000000000000000000..05b06357c7228af42c505ada336684b8e3f9d6b3
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_13.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 12b ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_14.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_14.mif
new file mode 100644
index 0000000000000000000000000000000000000000..d9ab539c05596132395faca5fa2941a7d7480651
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_14.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 3fb77 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_15.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_15.mif
new file mode 100644
index 0000000000000000000000000000000000000000..20c2700692089d13791c803112cf756bc02d798f
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_15.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_2.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_2.mif
new file mode 100644
index 0000000000000000000000000000000000000000..c98595d9a7ad942cf4c110024aaf3e939040647d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_2.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fe : 3fb68 ;
+ 3ff : 3fb70 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_3.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_3.mif
new file mode 100644
index 0000000000000000000000000000000000000000..6a8a89fc906f59c4b74c552c639a339f9735e3ae
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_3.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_4.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_4.mif
new file mode 100644
index 0000000000000000000000000000000000000000..6a742c820ab7a57622eced5455baa674a3e0cf5e
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_4.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fe : 13f ;
+ 3ff : 153 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_5.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_5.mif
new file mode 100644
index 0000000000000000000000000000000000000000..c765d0b2fe350eaca956b19dfd230c4be7f9cfda
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_5.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_6.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_6.mif
new file mode 100644
index 0000000000000000000000000000000000000000..9e8f5404bbb412e0a4e239531d132fa9edfb0035
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_6.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fd : 3ac ;
+ 3fe : 3e4 ;
+ 3ff : 41d ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_7.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_7.mif
new file mode 100644
index 0000000000000000000000000000000000000000..9a44758b01cbd143ef1ed68a99bd2393baf7adf6
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_7.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_8.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_8.mif
new file mode 100644
index 0000000000000000000000000000000000000000..1ef55131d9b76e0e0f155c5719c754254dd8726d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_8.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
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+ 3fd : 1fffe ;
+ 3fe : 1ffff ;
+ 3ff : 1ffff ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_9.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_9.mif
new file mode 100644
index 0000000000000000000000000000000000000000..d7f894ab9d58b99573e363dc3591f84524578db1
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_18b_1wb_9.mif
@@ -0,0 +1,1030 @@
+WIDTH=18;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 41d ;
+ 1 : 3e4 ;
+ 2 : 3ac ;
+ 3 : 373 ;
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+ 5 : 302 ;
+ 6 : 2c9 ;
+ 7 : 290 ;
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b.dat b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b.dat
new file mode 100644
index 0000000000000000000000000000000000000000..2b4d69d3dac33e6daba3d0db689e4def4e35e4b0
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b.dat
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diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_0.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_0.mif
new file mode 100644
index 0000000000000000000000000000000000000000..0302c4058a56ec17bcaa6be22bcdbff7dd86ae11
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_0.mif
@@ -0,0 +1,1030 @@
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+ 3ff : 285 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_1.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_1.mif
new file mode 100644
index 0000000000000000000000000000000000000000..709b86c9b8ba5c86ed56e5b97a69d6dbebc48ef7
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_1.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_10.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_10.mif
new file mode 100644
index 0000000000000000000000000000000000000000..7f681e936835334918a2d24f7cd926a9524b2b51
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_10.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : ff3c3 ;
+ 1 : ff446 ;
+ 2 : ff4c9 ;
+ 3 : ff54c ;
+ 4 : ff5d0 ;
+ 5 : ff653 ;
+ 6 : ff6d7 ;
+ 7 : ff75b ;
+ 8 : ff7df ;
+ 9 : ff863 ;
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+ 3fe : 1235 ;
+ 3ff : 1154 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_11.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_11.mif
new file mode 100644
index 0000000000000000000000000000000000000000..9bc15ad0dc82c75320719f3e59b38d6d5293ac9f
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_11.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : ff340 ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_12.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_12.mif
new file mode 100644
index 0000000000000000000000000000000000000000..fa5dda33dfc44b4f417b4cd58d4c06cc5dc634fe
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_12.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_13.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_13.mif
new file mode 100644
index 0000000000000000000000000000000000000000..4f46dd69088b80b2f95c22631ea6789d31728301
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_13.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3d8 : ffccb ;
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+ 3da : ffd31 ;
+ 3db : ffd64 ;
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+ 3de : ffdfd ;
+ 3df : ffe30 ;
+ 3e0 : ffe64 ;
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+ 3e2 : ffeca ;
+ 3e3 : ffefe ;
+ 3e4 : fff31 ;
+ 3e5 : fff65 ;
+ 3e6 : fff98 ;
+ 3e7 : fffcc ;
+ 3e8 : fffff ;
+ 3e9 : 33 ;
+ 3ea : 67 ;
+ 3eb : 9a ;
+ 3ec : ce ;
+ 3ed : 102 ;
+ 3ee : 136 ;
+ 3ef : 16a ;
+ 3f0 : 19e ;
+ 3f1 : 1d2 ;
+ 3f2 : 206 ;
+ 3f3 : 23a ;
+ 3f4 : 26e ;
+ 3f5 : 2a2 ;
+ 3f6 : 2d6 ;
+ 3f7 : 30b ;
+ 3f8 : 33f ;
+ 3f9 : 373 ;
+ 3fa : 3a8 ;
+ 3fb : 3dc ;
+ 3fc : 410 ;
+ 3fd : 445 ;
+ 3fe : 479 ;
+ 3ff : 4ae ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_14.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_14.mif
new file mode 100644
index 0000000000000000000000000000000000000000..2c01bfaea9535b83d597d367280e1fecf170217b
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_14.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
+ 0 : 1a70 ;
+ 1 : 1a78 ;
+ 2 : 1a81 ;
+ 3 : 1a8a ;
+ 4 : 1a93 ;
+ 5 : 1a9b ;
+ 6 : 1aa4 ;
+ 7 : 1aad ;
+ 8 : 1ab5 ;
+ 9 : 1abe ;
+ a : 1ac6 ;
+ b : 1acf ;
+ c : 1ad8 ;
+ d : 1ae0 ;
+ e : 1ae9 ;
+ f : 1af1 ;
+ 10 : 1afa ;
+ 11 : 1b02 ;
+ 12 : 1b0b ;
+ 13 : 1b13 ;
+ 14 : 1b1c ;
+ 15 : 1b24 ;
+ 16 : 1b2c ;
+ 17 : 1b35 ;
+ 18 : 1b3d ;
+ 19 : 1b46 ;
+ 1a : 1b4e ;
+ 1b : 1b56 ;
+ 1c : 1b5e ;
+ 1d : 1b67 ;
+ 1e : 1b6f ;
+ 1f : 1b77 ;
+ 20 : 1b7f ;
+ 21 : 1b88 ;
+ 22 : 1b90 ;
+ 23 : 1b98 ;
+ 24 : 1ba0 ;
+ 25 : 1ba8 ;
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+ 3ff : feddd ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_15.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_15.mif
new file mode 100644
index 0000000000000000000000000000000000000000..d1c4897044ca20965904c1f068beb126905ed534
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_15.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_2.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_2.mif
new file mode 100644
index 0000000000000000000000000000000000000000..153b9fef5d086faec1c0ec1e17d8e9be2cfc340a
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_2.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_3.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_3.mif
new file mode 100644
index 0000000000000000000000000000000000000000..8bc607b0e46db4737c834fb7f99f37cf71ec6e9d
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_3.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_4.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_4.mif
new file mode 100644
index 0000000000000000000000000000000000000000..a1ec1775981e86c3be7275e4c6352731e4836932
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_4.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3ff : 54d ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_5.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_5.mif
new file mode 100644
index 0000000000000000000000000000000000000000..8097c9d52ff2137a4eb0ee9306090a37ca77625c
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_5.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_6.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_6.mif
new file mode 100644
index 0000000000000000000000000000000000000000..f37204e1f8ee61baa8ce8c4542e1466579d1fbc0
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_6.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_7.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_7.mif
new file mode 100644
index 0000000000000000000000000000000000000000..5f2affed5a96a397534d1112a5796aad6c49eb86
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_7.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_8.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_8.mif
new file mode 100644
index 0000000000000000000000000000000000000000..2b48e7fbcb090eee12b2e5283fd09a80187478f0
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_8.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 3fb : 7ffee ;
+ 3fc : 7fff5 ;
+ 3fd : 7fffa ;
+ 3fe : 7fffd ;
+ 3ff : 7ffff ;
+END;
diff --git a/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_9.mif b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_9.mif
new file mode 100644
index 0000000000000000000000000000000000000000..16581b5ed0bb4c3eb57104fbe8cc0f042feb5dd3
--- /dev/null
+++ b/libraries/dsp/filter/src/hex/Coefficient_16KKaiser_20b_1wb_9.mif
@@ -0,0 +1,1030 @@
+WIDTH=20;
+DEPTH=1024;
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+CONTENT BEGIN
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+ 2d4 : e7a92 ;
+ 2d5 : e7b19 ;
+ 2d6 : e7ba1 ;
+ 2d7 : e7c2b ;
+ 2d8 : e7cb5 ;
+ 2d9 : e7d41 ;
+ 2da : e7dce ;
+ 2db : e7e5d ;
+ 2dc : e7eec ;
+ 2dd : e7f7d ;
+ 2de : e800f ;
+ 2df : e80a2 ;
+ 2e0 : e8136 ;
+ 2e1 : e81cb ;
+ 2e2 : e8262 ;
+ 2e3 : e82fa ;
+ 2e4 : e8393 ;
+ 2e5 : e842d ;
+ 2e6 : e84c9 ;
+ 2e7 : e8566 ;
+ 2e8 : e8603 ;
+ 2e9 : e86a3 ;
+ 2ea : e8743 ;
+ 2eb : e87e4 ;
+ 2ec : e8887 ;
+ 2ed : e892b ;
+ 2ee : e89d0 ;
+ 2ef : e8a77 ;
+ 2f0 : e8b1e ;
+ 2f1 : e8bc7 ;
+ 2f2 : e8c71 ;
+ 2f3 : e8d1d ;
+ 2f4 : e8dc9 ;
+ 2f5 : e8e77 ;
+ 2f6 : e8f26 ;
+ 2f7 : e8fd6 ;
+ 2f8 : e9087 ;
+ 2f9 : e913a ;
+ 2fa : e91ed ;
+ 2fb : e92a2 ;
+ 2fc : e9359 ;
+ 2fd : e9410 ;
+ 2fe : e94c9 ;
+ 2ff : e9583 ;
+ 300 : e963e ;
+ 301 : e96fa ;
+ 302 : e97b8 ;
+ 303 : e9876 ;
+ 304 : e9936 ;
+ 305 : e99f8 ;
+ 306 : e9aba ;
+ 307 : e9b7e ;
+ 308 : e9c43 ;
+ 309 : e9d09 ;
+ 30a : e9dd0 ;
+ 30b : e9e99 ;
+ 30c : e9f63 ;
+ 30d : ea02e ;
+ 30e : ea0fa ;
+ 30f : ea1c8 ;
+ 310 : ea296 ;
+ 311 : ea366 ;
+ 312 : ea437 ;
+ 313 : ea50a ;
+ 314 : ea5de ;
+ 315 : ea6b2 ;
+ 316 : ea789 ;
+ 317 : ea860 ;
+ 318 : ea938 ;
+ 319 : eaa12 ;
+ 31a : eaaed ;
+ 31b : eabca ;
+ 31c : eaca7 ;
+ 31d : ead86 ;
+ 31e : eae66 ;
+ 31f : eaf47 ;
+ 320 : eb029 ;
+ 321 : eb10d ;
+ 322 : eb1f2 ;
+ 323 : eb2d8 ;
+ 324 : eb3c0 ;
+ 325 : eb4a8 ;
+ 326 : eb592 ;
+ 327 : eb67d ;
+ 328 : eb769 ;
+ 329 : eb857 ;
+ 32a : eb946 ;
+ 32b : eba36 ;
+ 32c : ebb27 ;
+ 32d : ebc1a ;
+ 32e : ebd0d ;
+ 32f : ebe02 ;
+ 330 : ebef8 ;
+ 331 : ebff0 ;
+ 332 : ec0e9 ;
+ 333 : ec1e2 ;
+ 334 : ec2de ;
+ 335 : ec3da ;
+ 336 : ec4d8 ;
+ 337 : ec5d6 ;
+ 338 : ec6d7 ;
+ 339 : ec7d8 ;
+ 33a : ec8da ;
+ 33b : ec9de ;
+ 33c : ecae3 ;
+ 33d : ecbe9 ;
+ 33e : eccf1 ;
+ 33f : ecdfa ;
+ 340 : ecf04 ;
+ 341 : ed00f ;
+ 342 : ed11b ;
+ 343 : ed229 ;
+ 344 : ed338 ;
+ 345 : ed448 ;
+ 346 : ed55a ;
+ 347 : ed66c ;
+ 348 : ed780 ;
+ 349 : ed895 ;
+ 34a : ed9ab ;
+ 34b : edac3 ;
+ 34c : edbdc ;
+ 34d : edcf6 ;
+ 34e : ede11 ;
+ 34f : edf2e ;
+ 350 : ee04b ;
+ 351 : ee16a ;
+ 352 : ee28b ;
+ 353 : ee3ac ;
+ 354 : ee4cf ;
+ 355 : ee5f3 ;
+ 356 : ee718 ;
+ 357 : ee83e ;
+ 358 : ee966 ;
+ 359 : eea8f ;
+ 35a : eebb9 ;
+ 35b : eece4 ;
+ 35c : eee10 ;
+ 35d : eef3e ;
+ 35e : ef06d ;
+ 35f : ef19d ;
+ 360 : ef2cf ;
+ 361 : ef402 ;
+ 362 : ef535 ;
+ 363 : ef66b ;
+ 364 : ef7a1 ;
+ 365 : ef8d9 ;
+ 366 : efa11 ;
+ 367 : efb4b ;
+ 368 : efc87 ;
+ 369 : efdc3 ;
+ 36a : eff01 ;
+ 36b : f0040 ;
+ 36c : f0180 ;
+ 36d : f02c1 ;
+ 36e : f0404 ;
+ 36f : f0548 ;
+ 370 : f068d ;
+ 371 : f07d3 ;
+ 372 : f091b ;
+ 373 : f0a63 ;
+ 374 : f0bad ;
+ 375 : f0cf9 ;
+ 376 : f0e45 ;
+ 377 : f0f93 ;
+ 378 : f10e1 ;
+ 379 : f1232 ;
+ 37a : f1383 ;
+ 37b : f14d5 ;
+ 37c : f1629 ;
+ 37d : f177e ;
+ 37e : f18d4 ;
+ 37f : f1a2b ;
+ 380 : f1b84 ;
+ 381 : f1cde ;
+ 382 : f1e39 ;
+ 383 : f1f95 ;
+ 384 : f20f2 ;
+ 385 : f2251 ;
+ 386 : f23b1 ;
+ 387 : f2512 ;
+ 388 : f2674 ;
+ 389 : f27d8 ;
+ 38a : f293c ;
+ 38b : f2aa2 ;
+ 38c : f2c09 ;
+ 38d : f2d72 ;
+ 38e : f2edb ;
+ 38f : f3046 ;
+ 390 : f31b2 ;
+ 391 : f331f ;
+ 392 : f348d ;
+ 393 : f35fd ;
+ 394 : f376e ;
+ 395 : f38df ;
+ 396 : f3a53 ;
+ 397 : f3bc7 ;
+ 398 : f3d3c ;
+ 399 : f3eb3 ;
+ 39a : f402b ;
+ 39b : f41a4 ;
+ 39c : f431e ;
+ 39d : f449a ;
+ 39e : f4617 ;
+ 39f : f4794 ;
+ 3a0 : f4914 ;
+ 3a1 : f4a94 ;
+ 3a2 : f4c15 ;
+ 3a3 : f4d98 ;
+ 3a4 : f4f1c ;
+ 3a5 : f50a1 ;
+ 3a6 : f5227 ;
+ 3a7 : f53ae ;
+ 3a8 : f5537 ;
+ 3a9 : f56c1 ;
+ 3aa : f584b ;
+ 3ab : f59d8 ;
+ 3ac : f5b65 ;
+ 3ad : f5cf3 ;
+ 3ae : f5e83 ;
+ 3af : f6014 ;
+ 3b0 : f61a6 ;
+ 3b1 : f6339 ;
+ 3b2 : f64cd ;
+ 3b3 : f6663 ;
+ 3b4 : f67f9 ;
+ 3b5 : f6991 ;
+ 3b6 : f6b2a ;
+ 3b7 : f6cc4 ;
+ 3b8 : f6e60 ;
+ 3b9 : f6ffc ;
+ 3ba : f719a ;
+ 3bb : f7339 ;
+ 3bc : f74d9 ;
+ 3bd : f767a ;
+ 3be : f781c ;
+ 3bf : f79c0 ;
+ 3c0 : f7b64 ;
+ 3c1 : f7d0a ;
+ 3c2 : f7eb1 ;
+ 3c3 : f8059 ;
+ 3c4 : f8203 ;
+ 3c5 : f83ad ;
+ 3c6 : f8558 ;
+ 3c7 : f8705 ;
+ 3c8 : f88b3 ;
+ 3c9 : f8a62 ;
+ 3ca : f8c12 ;
+ 3cb : f8dc4 ;
+ 3cc : f8f76 ;
+ 3cd : f912a ;
+ 3ce : f92de ;
+ 3cf : f9494 ;
+ 3d0 : f964b ;
+ 3d1 : f9803 ;
+ 3d2 : f99bc ;
+ 3d3 : f9b77 ;
+ 3d4 : f9d32 ;
+ 3d5 : f9eef ;
+ 3d6 : fa0ad ;
+ 3d7 : fa26c ;
+ 3d8 : fa42c ;
+ 3d9 : fa5ed ;
+ 3da : fa7af ;
+ 3db : fa973 ;
+ 3dc : fab37 ;
+ 3dd : facfd ;
+ 3de : faec4 ;
+ 3df : fb08c ;
+ 3e0 : fb255 ;
+ 3e1 : fb41f ;
+ 3e2 : fb5ea ;
+ 3e3 : fb7b6 ;
+ 3e4 : fb984 ;
+ 3e5 : fbb52 ;
+ 3e6 : fbd22 ;
+ 3e7 : fbef3 ;
+ 3e8 : fc0c5 ;
+ 3e9 : fc298 ;
+ 3ea : fc46c ;
+ 3eb : fc641 ;
+ 3ec : fc817 ;
+ 3ed : fc9ef ;
+ 3ee : fcbc7 ;
+ 3ef : fcda1 ;
+ 3f0 : fcf7b ;
+ 3f1 : fd157 ;
+ 3f2 : fd334 ;
+ 3f3 : fd512 ;
+ 3f4 : fd6f1 ;
+ 3f5 : fd8d1 ;
+ 3f6 : fdab2 ;
+ 3f7 : fdc95 ;
+ 3f8 : fde78 ;
+ 3f9 : fe05c ;
+ 3fa : fe242 ;
+ 3fb : fe428 ;
+ 3fc : fe610 ;
+ 3fd : fe7f9 ;
+ 3fe : fe9e2 ;
+ 3ff : febcd ;
+END;
diff --git a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
index d1e0789f8d04a3f8026c19282b2b02922a1907ef..12635199691be8a1a64d07aaf742685746306b5c 100644
--- a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
@@ -61,6 +61,11 @@ package fil_pkg is
constant c_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
+ -- DC gain of FIR filter with Coeffs16384Kaiser-quant.dat used in LOFAR1.
+ -- . Calculated with applications/lofar2/model/run_pfir_coef.m using application = 'lofar_subband'
+ -- . Not used in RTL, only used in test benches to verify expected subband levels
+ constant c_fil_lofar1_fir_filter_dc_gain : real := 0.994817;
+
end package fil_pkg;
package body fil_pkg is
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
index 5734acbf56ec8985eb7a303c0082faf763e5cc2d..feaaa25f8c9cc5948cfd4f8742fa9600912eda48 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
@@ -43,9 +43,8 @@ entity rTwoSDF is
g_stage_dat_w : natural := 18; -- number of bits used between the stages
g_guard_w : natural := 2; -- guard bits are used to avoid overflow in single FFT stage.
g_nof_points : natural := 1024; -- N point FFT
+ g_round_even : boolean := true;
-- generics for rTwoSDFStage
- g_r2_mul_extra_w : natural := 0; -- extra bits at rTwoWMult output in rTwoSDFStage to improve rTwoSDFStage output requantization,
- -- proper value is 2, default use 0 to fit original tb_rTwoSDF.vhd golden results file
g_pipeline : t_fft_pipeline := c_fft_pipeline
);
port (
@@ -106,7 +105,7 @@ begin
g_stage_offset => c_stage_offset,
g_twiddle_offset => c_twiddle_offset,
g_scale_enable => sel_a_b(stage <= g_guard_w, FALSE, TRUE), -- On average all stages have a gain factor of 2 therefore each stage needs to round 1 bit except for the last g_guard_w nof stages due to the input c_in_scale_w
- g_r2_mul_extra_w => g_r2_mul_extra_w,
+ g_round_even => g_round_even,
g_pipeline => g_pipeline
)
port map (
@@ -160,7 +159,8 @@ begin
g_representation => "SIGNED",
g_lsb_w => c_out_scale_w,
g_lsb_round => TRUE,
- g_lsb_round_clip => FALSE,
+ g_lsb_round_clip => FALSE,
+ g_lsb_round_even => g_round_even,
g_msb_clip => FALSE,
g_msb_clip_symmetric => FALSE,
g_pipeline_remove_lsb => 0,
@@ -182,7 +182,8 @@ begin
g_lsb_w => c_out_scale_w,
g_lsb_round => TRUE,
g_lsb_round_clip => FALSE,
- g_msb_clip => FALSE,
+ g_lsb_round_even => g_round_even,
+ g_msb_clip => FALSE,
g_msb_clip_symmetric => FALSE,
g_pipeline_remove_lsb => 0,
g_pipeline_remove_msb => 0,
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
index 932023200fe50de75d6122566343d292bfae8aac..389aca4cd7e11836ed355d843ebb4aab0a4e9ebb 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
@@ -31,8 +31,8 @@ entity rTwoSDFStage is
g_stage : natural := 8;
g_stage_offset : natural := 0; -- The Stage offset: 0 for normal FFT. Other than 0 in wideband FFT
g_twiddle_offset : natural := 0; -- The twiddle offset: 0 for normal FFT. Other than 0 in wideband FFT
- g_scale_enable : boolean := TRUE; --
- g_r2_mul_extra_w : natural := 0; -- extra bits at rTwoMult output to improve FFT stage output requantization
+ g_scale_enable : boolean := TRUE;
+ g_round_even : boolean := TRUE;
g_pipeline : t_fft_pipeline := c_fft_pipeline -- internal pipeline settings
);
port (
@@ -70,8 +70,8 @@ architecture str of rTwoSDFStage is
signal weight_re : wTyp;
signal weight_im : wTyp;
- signal mul_out_re : std_logic_vector(out_re'length-1 + g_r2_mul_extra_w downto 0);
- signal mul_out_im : std_logic_vector(out_im'length-1 + g_r2_mul_extra_w downto 0);
+ signal mul_out_re : std_logic_vector(out_re'length-1 downto 0);
+ signal mul_out_im : std_logic_vector(out_im'length-1 downto 0);
signal mul_out_val : std_logic;
signal quant_out_re : std_logic_vector(out_re'range);
@@ -147,8 +147,9 @@ begin
------------------------------------------------------------------------------
u_TwiddleMult: entity work.rTwoWMul
generic map (
- g_stage => g_stage,
- g_lat => g_pipeline.mul_lat
+ g_stage => g_stage,
+ g_round_even => g_round_even,
+ g_lat => g_pipeline.mul_lat
)
port map (
clk => clk,
@@ -170,9 +171,10 @@ begin
u_requantize_re : entity common_lib.common_requantize
generic map (
g_representation => "SIGNED",
- g_lsb_w => c_r2_stage_bit_growth + g_r2_mul_extra_w,
+ g_lsb_w => c_r2_stage_bit_growth,
g_lsb_round => TRUE,
- g_lsb_round_clip => FALSE,
+ g_lsb_round_clip => FALSE,
+ g_lsb_round_even => g_round_even,
g_msb_clip => FALSE,
g_msb_clip_symmetric => FALSE,
g_pipeline_remove_lsb => 0,
@@ -191,10 +193,11 @@ begin
u_requantize_im : entity common_lib.common_requantize
generic map (
g_representation => "SIGNED",
- g_lsb_w => c_r2_stage_bit_growth + g_r2_mul_extra_w,
+ g_lsb_w => c_r2_stage_bit_growth,
g_lsb_round => TRUE,
g_lsb_round_clip => FALSE,
- g_msb_clip => FALSE,
+ g_lsb_round_even => g_round_even,
+ g_msb_clip => FALSE,
g_msb_clip_symmetric => FALSE,
g_pipeline_remove_lsb => 0,
g_pipeline_remove_msb => 0,
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
index ead344fece9b262abc3641dabb2795592cf2041c..a508eda63d047b44df34e3ed4c2896216e114c69 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
@@ -29,6 +29,7 @@ entity rTwoWMul is
generic (
g_technology : NATURAL := c_tech_select_default;
g_stage : natural := 1;
+ g_round_even : boolean := true;
g_lat : natural := 3+1 -- 3 for mult, 1 for round
);
port (
@@ -184,17 +185,47 @@ begin
gen_sround : if c_use_truncate=false GENERATE
- -- Use resize_svec(s_round()) instead of truncate_and_resize_svec() to have symmetrical rounding around 0
- -- Rounding takes logic due to adding 0.5 therefore need to use c_round_lat=1 to achieve timing
- gen_comb : if c_round_lat=0 generate
- ASSERT false REPORT "rTwoWMul: can probably not achieve timing for sround without pipeline" SEVERITY FAILURE;
- round_re <= RESIZE_SVEC(s_round(product_re, c_round_w), c_out_dat_w);
- round_im <= RESIZE_SVEC(s_round(product_im, c_round_w), c_out_dat_w);
- end generate;
- gen_reg : if c_round_lat=1 generate
- round_re <= RESIZE_SVEC(s_round(product_re, c_round_w), c_out_dat_w) when rising_edge(clk);
- round_im <= RESIZE_SVEC(s_round(product_im, c_round_w), c_out_dat_w) when rising_edge(clk);
- end generate;
+ u_requantize_re : entity common_lib.common_requantize
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_round_w,
+ g_lsb_round => TRUE,
+ g_lsb_round_clip => FALSE,
+ g_lsb_round_even => g_round_even,
+ g_msb_clip => FALSE,
+ g_msb_clip_symmetric => FALSE,
+ g_pipeline_remove_lsb => c_round_lat,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_prod_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => product_re,
+ out_dat => round_re,
+ out_ovr => open
+ );
+
+ u_requantize_im : entity common_lib.common_requantize
+ generic map (
+ g_representation => "SIGNED",
+ g_lsb_w => c_round_w,
+ g_lsb_round => TRUE,
+ g_lsb_round_clip => FALSE,
+ g_lsb_round_even => g_round_even,
+ g_msb_clip => FALSE,
+ g_msb_clip_symmetric => FALSE,
+ g_pipeline_remove_lsb => c_round_lat,
+ g_pipeline_remove_msb => 0,
+ g_in_dat_w => c_prod_w,
+ g_out_dat_w => c_out_dat_w
+ )
+ port map (
+ clk => clk,
+ in_dat => product_im,
+ out_dat => round_im,
+ out_ovr => open
+ );
end generate;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg.vhd b/libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg.vhd
index c7a71f0b7f92a250c0e90746c471937c871616ba..e397b942e0c0aed3ea19d460e759994ae16b2896 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg.vhd
@@ -3,9 +3,9 @@
--DO NOT EDIT THIS FILE !!!
-------------------------------------
--Author :R.T.Rajan
---Date :05-Mar-2013
+--Date :21-Dec-2020
--Npoints :4096
---Nbits :18
+--Nbits :20
-------------------------------------
@@ -17,4112 +17,4112 @@ use ieee.numeric_std.all;
constant copyRightNotice: string
:= "Copyright 2009 , ASTRON. All rights reserved.";
- subtype wTyp is std_logic_vector(17 downto 0);
+ subtype wTyp is std_logic_vector(19 downto 0);
type wRowTyp is array( 1 to 2048 ) of wTyp;
type wMapTyp is array( integer range 0 to 2047, integer range 12 downto 1) of natural;
constant wRe: wRowTyp :=
(
- b"011111111111111111",
- b"011111111111111110",
- b"011111111111111110",
- b"011111111111111101",
- b"011111111111111100",
- b"011111111111111011",
- b"011111111111111001",
- b"011111111111110111",
- b"011111111111110101",
- b"011111111111110010",
- b"011111111111101111",
- b"011111111111101100",
- b"011111111111101000",
- b"011111111111100100",
- b"011111111111100000",
- b"011111111111011100",
- b"011111111111010111",
- b"011111111111010010",
- b"011111111111001101",
- b"011111111111000111",
- b"011111111111000001",
- b"011111111110111010",
- b"011111111110110100",
- b"011111111110101101",
- b"011111111110100110",
- b"011111111110011110",
- b"011111111110010110",
- b"011111111110001110",
- b"011111111110000110",
- b"011111111101111101",
- b"011111111101110100",
- b"011111111101101010",
- b"011111111101100001",
- b"011111111101010111",
- b"011111111101001100",
- b"011111111101000010",
- b"011111111100110111",
- b"011111111100101011",
- b"011111111100100000",
- b"011111111100010100",
- b"011111111100001000",
- b"011111111011111011",
- b"011111111011101111",
- b"011111111011100001",
- b"011111111011010100",
- b"011111111011000110",
- b"011111111010111000",
- b"011111111010101010",
- b"011111111010011011",
- b"011111111010001100",
- b"011111111001111101",
- b"011111111001101110",
- b"011111111001011110",
- b"011111111001001110",
- b"011111111000111101",
- b"011111111000101100",
- b"011111111000011011",
- b"011111111000001010",
- b"011111110111111000",
- b"011111110111100110",
- b"011111110111010100",
- b"011111110111000001",
- b"011111110110101110",
- b"011111110110011011",
- b"011111110110000111",
- b"011111110101110011",
- b"011111110101011111",
- b"011111110101001011",
- b"011111110100110110",
- b"011111110100100001",
- b"011111110100001100",
- b"011111110011110110",
- b"011111110011100000",
- b"011111110011001010",
- b"011111110010110011",
- b"011111110010011100",
- b"011111110010000101",
- b"011111110001101101",
- b"011111110001010101",
- b"011111110000111101",
- b"011111110000100101",
- b"011111110000001100",
- b"011111101111110011",
- b"011111101111011010",
- b"011111101111000000",
- b"011111101110100110",
- b"011111101110001100",
- b"011111101101110001",
- b"011111101101010110",
- b"011111101100111011",
- b"011111101100011111",
- b"011111101100000100",
- b"011111101011100111",
- b"011111101011001011",
- b"011111101010101110",
- b"011111101010010001",
- b"011111101001110100",
- b"011111101001010110",
- b"011111101000111000",
- b"011111101000011010",
- b"011111100111111011",
- b"011111100111011101",
- b"011111100110111101",
- b"011111100110011110",
- b"011111100101111110",
- b"011111100101011110",
- b"011111100100111110",
- b"011111100100011101",
- b"011111100011111100",
- b"011111100011011011",
- b"011111100010111001",
- b"011111100010010111",
- b"011111100001110101",
- b"011111100001010010",
- b"011111100000101111",
- b"011111100000001100",
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+ b"10101111110111010110",
+ b"10101111101101100011",
+ b"10101111100011110001",
+ b"10101111011010000000",
+ b"10101111010000001111",
+ b"10101111000110100000",
+ b"10101110111100110001",
+ b"10101110110011000011",
+ b"10101110101001010110",
+ b"10101110011111101001",
+ b"10101110010101111101",
+ b"10101110001100010010",
+ b"10101110000010101000",
+ b"10101101111000111111",
+ b"10101101101111010110",
+ b"10101101100101101110",
+ b"10101101011100001000",
+ b"10101101010010100001",
+ b"10101101001000111100",
+ b"10101100111111010111",
+ b"10101100110101110100",
+ b"10101100101100010001",
+ b"10101100100010101110",
+ b"10101100011001001101",
+ b"10101100001111101100",
+ b"10101100000110001101",
+ b"10101011111100101110",
+ b"10101011110011010000",
+ b"10101011101001110010",
+ b"10101011100000010110",
+ b"10101011010110111010",
+ b"10101011001101011111",
+ b"10101011000100000101",
+ b"10101010111010101100",
+ b"10101010110001010011",
+ b"10101010100111111100",
+ b"10101010011110100101",
+ b"10101010010101001111",
+ b"10101010001011111010",
+ b"10101010000010100101",
+ b"10101001111001010010",
+ b"10101001101111111111",
+ b"10101001100110101101",
+ b"10101001011101011100",
+ b"10101001010100001100",
+ b"10101001001010111101",
+ b"10101001000001101110",
+ b"10101000111000100001",
+ b"10101000101111010100",
+ b"10101000100110001000",
+ b"10101000011100111101",
+ b"10101000010011110011",
+ b"10101000001010101001",
+ b"10101000000001100001",
+ b"10100111111000011001",
+ b"10100111101111010010",
+ b"10100111100110001100",
+ b"10100111011101000111",
+ b"10100111010100000010",
+ b"10100111001010111111",
+ b"10100111000001111100",
+ b"10100110111000111010",
+ b"10100110101111111001",
+ b"10100110100110111001",
+ b"10100110011101111010",
+ b"10100110010100111100",
+ b"10100110001011111110",
+ b"10100110000011000010",
+ b"10100101111010000110",
+ b"10100101110001001011",
+ b"10100101101000010001",
+ b"10100101011111011000",
+ b"10100101010110100000",
+ b"10100101001101101000",
+ b"10100101000100110010",
+ b"10100100111011111100",
+ b"10100100110011001000",
+ b"10100100101010010100",
+ b"10100100100001100001",
+ b"10100100011000101111",
+ b"10100100001111111101",
+ b"10100100000111001101",
+ b"10100011111110011110",
+ b"10100011110101101111",
+ b"10100011101101000001",
+ b"10100011100100010101",
+ b"10100011011011101001",
+ b"10100011010010111110",
+ b"10100011001010010100",
+ b"10100011000001101010",
+ b"10100010111001000010",
+ b"10100010110000011011",
+ b"10100010100111110100",
+ b"10100010011111001110",
+ b"10100010010110101010",
+ b"10100010001110000110",
+ b"10100010000101100011",
+ b"10100001111101000001",
+ b"10100001110100100000",
+ b"10100001101100000000",
+ b"10100001100011100000",
+ b"10100001011011000010",
+ b"10100001010010100101",
+ b"10100001001010001000",
+ b"10100001000001101100",
+ b"10100000111001010010",
+ b"10100000110000111000",
+ b"10100000101000011111",
+ b"10100000100000000111",
+ b"10100000010111110000",
+ b"10100000001111011010",
+ b"10100000000111000101",
+ b"10011111111110110000",
+ b"10011111110110011101",
+ b"10011111101110001010",
+ b"10011111100101111001",
+ b"10011111011101101000",
+ b"10011111010101011001",
+ b"10011111001101001010",
+ b"10011111000100111100",
+ b"10011110111100101111",
+ b"10011110110100100011",
+ b"10011110101100011001",
+ b"10011110100100001110",
+ b"10011110011100000101",
+ b"10011110010011111101",
+ b"10011110001011110110",
+ b"10011110000011110000",
+ b"10011101111011101010",
+ b"10011101110011100110",
+ b"10011101101011100011",
+ b"10011101100011100000",
+ b"10011101011011011111",
+ b"10011101010011011110",
+ b"10011101001011011110",
+ b"10011101000011100000",
+ b"10011100111011100010",
+ b"10011100110011100101",
+ b"10011100101011101001",
+ b"10011100100011101110",
+ b"10011100011011110101",
+ b"10011100010011111100",
+ b"10011100001100000100",
+ b"10011100000100001101",
+ b"10011011111100010111",
+ b"10011011110100100001",
+ b"10011011101100101101",
+ b"10011011100100111010",
+ b"10011011011101001000",
+ b"10011011010101010111",
+ b"10011011001101100111",
+ b"10011011000101110111",
+ b"10011010111110001001",
+ b"10011010110110011100",
+ b"10011010101110101111",
+ b"10011010100111000100",
+ b"10011010011111011001",
+ b"10011010010111110000",
+ b"10011010010000001000",
+ b"10011010001000100000",
+ b"10011010000000111010",
+ b"10011001111001010100",
+ b"10011001110001110000",
+ b"10011001101010001100",
+ b"10011001100010101001",
+ b"10011001011011001000",
+ b"10011001010011100111",
+ b"10011001001100001000",
+ b"10011001000100101001",
+ b"10011000111101001100",
+ b"10011000110101101111",
+ b"10011000101110010011",
+ b"10011000100110111001",
+ b"10011000011111011111",
+ b"10011000011000000110",
+ b"10011000010000101111",
+ b"10011000001001011000",
+ b"10011000000010000011",
+ b"10010111111010101110",
+ b"10010111110011011010",
+ b"10010111101100001000",
+ b"10010111100100110110",
+ b"10010111011101100110",
+ b"10010111010110010110",
+ b"10010111001111000111",
+ b"10010111000111111010",
+ b"10010111000000101101",
+ b"10010110111001100010",
+ b"10010110110010010111",
+ b"10010110101011001110",
+ b"10010110100100000101",
+ b"10010110011100111110",
+ b"10010110010101110111",
+ b"10010110001110110010",
+ b"10010110000111101101",
+ b"10010110000000101010",
+ b"10010101111001100111",
+ b"10010101110010100110",
+ b"10010101101011100110",
+ b"10010101100100100110",
+ b"10010101011101101000",
+ b"10010101010110101011",
+ b"10010101001111101110",
+ b"10010101001000110011",
+ b"10010101000001111001",
+ b"10010100111011000000",
+ b"10010100110100001000",
+ b"10010100101101010001",
+ b"10010100100110011011",
+ b"10010100011111100110",
+ b"10010100011000110010",
+ b"10010100010001111111",
+ b"10010100001011001101",
+ b"10010100000100011100",
+ b"10010011111101101100",
+ b"10010011110110111101",
+ b"10010011110000010000",
+ b"10010011101001100011",
+ b"10010011100010110111",
+ b"10010011011100001101",
+ b"10010011010101100011",
+ b"10010011001110111010",
+ b"10010011001000010011",
+ b"10010011000001101101",
+ b"10010010111011000111",
+ b"10010010110100100011",
+ b"10010010101110000000",
+ b"10010010100111011101",
+ b"10010010100000111100",
+ b"10010010011010011100",
+ b"10010010010011111101",
+ b"10010010001101011111",
+ b"10010010000111000010",
+ b"10010010000000100110",
+ b"10010001111010001011",
+ b"10010001110011110010",
+ b"10010001101101011001",
+ b"10010001100111000001",
+ b"10010001100000101011",
+ b"10010001011010010101",
+ b"10010001010100000001",
+ b"10010001001101101101",
+ b"10010001000111011011",
+ b"10010001000001001010",
+ b"10010000111010111010",
+ b"10010000110100101011",
+ b"10010000101110011101",
+ b"10010000101000010000",
+ b"10010000100010000100",
+ b"10010000011011111001",
+ b"10010000010101101111",
+ b"10010000001111100111",
+ b"10010000001001011111",
+ b"10010000000011011001",
+ b"10001111111101010011",
+ b"10001111110111001111",
+ b"10001111110001001100",
+ b"10001111101011001001",
+ b"10001111100101001000",
+ b"10001111011111001000",
+ b"10001111011001001001",
+ b"10001111010011001100",
+ b"10001111001101001111",
+ b"10001111000111010011",
+ b"10001111000001011001",
+ b"10001110111011011111",
+ b"10001110110101100111",
+ b"10001110101111101111",
+ b"10001110101001111001",
+ b"10001110100100000100",
+ b"10001110011110010000",
+ b"10001110011000011101",
+ b"10001110010010101011",
+ b"10001110001100111011",
+ b"10001110000111001011",
+ b"10001110000001011100",
+ b"10001101111011101111",
+ b"10001101110110000011",
+ b"10001101110000010111",
+ b"10001101101010101101",
+ b"10001101100101000100",
+ b"10001101011111011100",
+ b"10001101011001110101",
+ b"10001101010100010000",
+ b"10001101001110101011",
+ b"10001101001001000111",
+ b"10001101000011100101",
+ b"10001100111110000100",
+ b"10001100111000100011",
+ b"10001100110011000100",
+ b"10001100101101100110",
+ b"10001100101000001010",
+ b"10001100100010101110",
+ b"10001100011101010011",
+ b"10001100010111111010",
+ b"10001100010010100001",
+ b"10001100001101001010",
+ b"10001100000111110100",
+ b"10001100000010011111",
+ b"10001011111101001011",
+ b"10001011110111111000",
+ b"10001011110010100110",
+ b"10001011101101010110",
+ b"10001011101000000110",
+ b"10001011100010111000",
+ b"10001011011101101010",
+ b"10001011011000011110",
+ b"10001011010011010011",
+ b"10001011001110001010",
+ b"10001011001001000001",
+ b"10001011000011111001",
+ b"10001010111110110011",
+ b"10001010111001101101",
+ b"10001010110100101001",
+ b"10001010101111100110",
+ b"10001010101010100100",
+ b"10001010100101100011",
+ b"10001010100000100100",
+ b"10001010011011100101",
+ b"10001010010110101000",
+ b"10001010010001101011",
+ b"10001010001100110000",
+ b"10001010000111110110",
+ b"10001010000010111101",
+ b"10001001111110000101",
+ b"10001001111001001111",
+ b"10001001110100011001",
+ b"10001001101111100101",
+ b"10001001101010110010",
+ b"10001001100110000000",
+ b"10001001100001001111",
+ b"10001001011100011111",
+ b"10001001010111110000",
+ b"10001001010011000011",
+ b"10001001001110010111",
+ b"10001001001001101011",
+ b"10001001000101000001",
+ b"10001001000000011000",
+ b"10001000111011110001",
+ b"10001000110111001010",
+ b"10001000110010100101",
+ b"10001000101110000000",
+ b"10001000101001011101",
+ b"10001000100100111011",
+ b"10001000100000011010",
+ b"10001000011011111010",
+ b"10001000010111011100",
+ b"10001000010010111110",
+ b"10001000001110100010",
+ b"10001000001010000111",
+ b"10001000000101101101",
+ b"10001000000001010100",
+ b"10000111111100111101",
+ b"10000111111000100110",
+ b"10000111110100010001",
+ b"10000111101111111101",
+ b"10000111101011101010",
+ b"10000111100111011000",
+ b"10000111100011000111",
+ b"10000111011110111000",
+ b"10000111011010101001",
+ b"10000111010110011100",
+ b"10000111010010010000",
+ b"10000111001110000101",
+ b"10000111001001111100",
+ b"10000111000101110011",
+ b"10000111000001101100",
+ b"10000110111101100101",
+ b"10000110111001100000",
+ b"10000110110101011100",
+ b"10000110110001011010",
+ b"10000110101101011000",
+ b"10000110101001011000",
+ b"10000110100101011001",
+ b"10000110100001011011",
+ b"10000110011101011110",
+ b"10000110011001100010",
+ b"10000110010101101000",
+ b"10000110010001101110",
+ b"10000110001101110110",
+ b"10000110001001111111",
+ b"10000110000110001001",
+ b"10000110000010010101",
+ b"10000101111110100001",
+ b"10000101111010101111",
+ b"10000101110110111110",
+ b"10000101110011001110",
+ b"10000101101111011111",
+ b"10000101101011110001",
+ b"10000101101000000101",
+ b"10000101100100011010",
+ b"10000101100000110000",
+ b"10000101011101000111",
+ b"10000101011001011111",
+ b"10000101010101111001",
+ b"10000101010010010011",
+ b"10000101001110101111",
+ b"10000101001011001100",
+ b"10000101000111101010",
+ b"10000101000100001010",
+ b"10000101000000101010",
+ b"10000100111101001100",
+ b"10000100111001101111",
+ b"10000100110110010011",
+ b"10000100110010111001",
+ b"10000100101111011111",
+ b"10000100101100000111",
+ b"10000100101000110000",
+ b"10000100100101011010",
+ b"10000100100010000101",
+ b"10000100011110110010",
+ b"10000100011011011111",
+ b"10000100011000001110",
+ b"10000100010100111110",
+ b"10000100010001101111",
+ b"10000100001110100010",
+ b"10000100001011010101",
+ b"10000100001000001010",
+ b"10000100000101000000",
+ b"10000100000001110111",
+ b"10000011111110110000",
+ b"10000011111011101001",
+ b"10000011111000100100",
+ b"10000011110101100000",
+ b"10000011110010011101",
+ b"10000011101111011100",
+ b"10000011101100011011",
+ b"10000011101001011100",
+ b"10000011100110011110",
+ b"10000011100011100001",
+ b"10000011100000100110",
+ b"10000011011101101011",
+ b"10000011011010110010",
+ b"10000011010111111010",
+ b"10000011010101000011",
+ b"10000011010010001110",
+ b"10000011001111011001",
+ b"10000011001100100110",
+ b"10000011001001110100",
+ b"10000011000111000011",
+ b"10000011000100010011",
+ b"10000011000001100101",
+ b"10000010111110111000",
+ b"10000010111100001100",
+ b"10000010111001100001",
+ b"10000010110110110111",
+ b"10000010110100001111",
+ b"10000010110001101000",
+ b"10000010101111000010",
+ b"10000010101100011101",
+ b"10000010101001111010",
+ b"10000010100111010111",
+ b"10000010100100110110",
+ b"10000010100010010110",
+ b"10000010011111111000",
+ b"10000010011101011010",
+ b"10000010011010111110",
+ b"10000010011000100011",
+ b"10000010010110001001",
+ b"10000010010011110000",
+ b"10000010010001011001",
+ b"10000010001111000010",
+ b"10000010001100101101",
+ b"10000010001010011010",
+ b"10000010001000000111",
+ b"10000010000101110110",
+ b"10000010000011100101",
+ b"10000010000001010110",
+ b"10000001111111001001",
+ b"10000001111100111100",
+ b"10000001111010110001",
+ b"10000001111000100111",
+ b"10000001110110011110",
+ b"10000001110100010110",
+ b"10000001110010010000",
+ b"10000001110000001010",
+ b"10000001101110000110",
+ b"10000001101100000100",
+ b"10000001101010000010",
+ b"10000001101000000010",
+ b"10000001100110000011",
+ b"10000001100100000101",
+ b"10000001100010001000",
+ b"10000001100000001100",
+ b"10000001011110010010",
+ b"10000001011100011001",
+ b"10000001011010100001",
+ b"10000001011000101011",
+ b"10000001010110110101",
+ b"10000001010101000001",
+ b"10000001010011001110",
+ b"10000001010001011100",
+ b"10000001001111101100",
+ b"10000001001101111101",
+ b"10000001001100001110",
+ b"10000001001010100010",
+ b"10000001001000110110",
+ b"10000001000111001100",
+ b"10000001000101100010",
+ b"10000001000011111010",
+ b"10000001000010010100",
+ b"10000001000000101110",
+ b"10000000111111001010",
+ b"10000000111101100111",
+ b"10000000111100000101",
+ b"10000000111010100100",
+ b"10000000111001000101",
+ b"10000000110111100111",
+ b"10000000110110001010",
+ b"10000000110100101110",
+ b"10000000110011010100",
+ b"10000000110001111010",
+ b"10000000110000100010",
+ b"10000000101111001100",
+ b"10000000101101110110",
+ b"10000000101100100010",
+ b"10000000101011001111",
+ b"10000000101001111101",
+ b"10000000101000101100",
+ b"10000000100111011101",
+ b"10000000100110001110",
+ b"10000000100101000001",
+ b"10000000100011110110",
+ b"10000000100010101011",
+ b"10000000100001100010",
+ b"10000000100000011010",
+ b"10000000011111010011",
+ b"10000000011110001101",
+ b"10000000011101001001",
+ b"10000000011100000110",
+ b"10000000011011000100",
+ b"10000000011010000011",
+ b"10000000011001000100",
+ b"10000000011000000101",
+ b"10000000010111001000",
+ b"10000000010110001101",
+ b"10000000010101010010",
+ b"10000000010100011001",
+ b"10000000010011100001",
+ b"10000000010010101010",
+ b"10000000010001110100",
+ b"10000000010001000000",
+ b"10000000010000001101",
+ b"10000000001111011011",
+ b"10000000001110101010",
+ b"10000000001101111010",
+ b"10000000001101001100",
+ b"10000000001100011111",
+ b"10000000001011110011",
+ b"10000000001011001001",
+ b"10000000001010100000",
+ b"10000000001001111000",
+ b"10000000001001010001",
+ b"10000000001000101011",
+ b"10000000001000000111",
+ b"10000000000111100100",
+ b"10000000000111000010",
+ b"10000000000110100001",
+ b"10000000000110000001",
+ b"10000000000101100011",
+ b"10000000000101000110",
+ b"10000000000100101011",
+ b"10000000000100010000",
+ b"10000000000011110111",
+ b"10000000000011011111",
+ b"10000000000011001000",
+ b"10000000000010110010",
+ b"10000000000010011110",
+ b"10000000000010001011",
+ b"10000000000001111001",
+ b"10000000000001101000",
+ b"10000000000001011001",
+ b"10000000000001001011",
+ b"10000000000000111110",
+ b"10000000000000110010",
+ b"10000000000000100111",
+ b"10000000000000011110",
+ b"10000000000000010110",
+ b"10000000000000001111",
+ b"10000000000000001010",
+ b"10000000000000000110",
+ b"10000000000000000010",
+ b"10000000000000000001"
);
constant wIm: wRowTyp :=
(
- b"000000000000000000",
- b"111111111100110110",
- b"111111111001101101",
- b"111111110110100100",
- b"111111110011011011",
- b"111111110000010010",
- b"111111101101001001",
- b"111111101010000000",
- b"111111100110110111",
- b"111111100011101110",
- b"111111100000100100",
- b"111111011101011011",
- b"111111011010010010",
- b"111111010111001001",
- b"111111010100000000",
- b"111111010000110111",
- b"111111001101101110",
- b"111111001010100101",
- b"111111000111011100",
- b"111111000100010011",
- b"111111000001001010",
- b"111110111110000001",
- b"111110111010111001",
- b"111110110111110000",
- b"111110110100100111",
- b"111110110001011110",
- b"111110101110010101",
- b"111110101011001100",
- b"111110101000000011",
- b"111110100100111010",
- b"111110100001110001",
- b"111110011110101000",
- b"111110011011100000",
- b"111110011000010111",
- b"111110010101001110",
- b"111110010010000101",
- b"111110001110111101",
- b"111110001011110100",
- b"111110001000101011",
- b"111110000101100010",
- b"111110000010011010",
- b"111101111111010001",
- b"111101111100001000",
- b"111101111001000000",
- b"111101110101110111",
- b"111101110010101110",
- b"111101101111100110",
- b"111101101100011101",
- b"111101101001010101",
- b"111101100110001100",
- b"111101100011000100",
- b"111101011111111011",
- b"111101011100110011",
- b"111101011001101011",
- b"111101010110100010",
- b"111101010011011010",
- b"111101010000010001",
- b"111101001101001001",
- b"111101001010000001",
- b"111101000110111001",
- b"111101000011110000",
- b"111101000000101000",
- b"111100111101100000",
- b"111100111010011000",
- b"111100110111010000",
- b"111100110100001000",
- b"111100110001000000",
- b"111100101101111000",
- b"111100101010110000",
- b"111100100111101000",
- b"111100100100100000",
- b"111100100001011000",
- b"111100011110010000",
- b"111100011011001000",
- b"111100011000000000",
- b"111100010100111001",
- b"111100010001110001",
- b"111100001110101001",
- b"111100001011100010",
- b"111100001000011010",
- b"111100000101010011",
- b"111100000010001011",
- b"111011111111000011",
- b"111011111011111100",
- b"111011111000110101",
- b"111011110101101101",
- b"111011110010100110",
- b"111011101111011111",
- b"111011101100010111",
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+ b"10011101000011100000",
+ b"10011101001011011110",
+ b"10011101010011011110",
+ b"10011101011011011111",
+ b"10011101100011100000",
+ b"10011101101011100011",
+ b"10011101110011100110",
+ b"10011101111011101010",
+ b"10011110000011110000",
+ b"10011110001011110110",
+ b"10011110010011111101",
+ b"10011110011100000101",
+ b"10011110100100001110",
+ b"10011110101100011001",
+ b"10011110110100100011",
+ b"10011110111100101111",
+ b"10011111000100111100",
+ b"10011111001101001010",
+ b"10011111010101011001",
+ b"10011111011101101000",
+ b"10011111100101111001",
+ b"10011111101110001010",
+ b"10011111110110011101",
+ b"10011111111110110000",
+ b"10100000000111000101",
+ b"10100000001111011010",
+ b"10100000010111110000",
+ b"10100000100000000111",
+ b"10100000101000011111",
+ b"10100000110000111000",
+ b"10100000111001010010",
+ b"10100001000001101100",
+ b"10100001001010001000",
+ b"10100001010010100101",
+ b"10100001011011000010",
+ b"10100001100011100000",
+ b"10100001101100000000",
+ b"10100001110100100000",
+ b"10100001111101000001",
+ b"10100010000101100011",
+ b"10100010001110000110",
+ b"10100010010110101010",
+ b"10100010011111001110",
+ b"10100010100111110100",
+ b"10100010110000011011",
+ b"10100010111001000010",
+ b"10100011000001101010",
+ b"10100011001010010100",
+ b"10100011010010111110",
+ b"10100011011011101001",
+ b"10100011100100010101",
+ b"10100011101101000001",
+ b"10100011110101101111",
+ b"10100011111110011110",
+ b"10100100000111001101",
+ b"10100100001111111101",
+ b"10100100011000101111",
+ b"10100100100001100001",
+ b"10100100101010010100",
+ b"10100100110011001000",
+ b"10100100111011111100",
+ b"10100101000100110010",
+ b"10100101001101101000",
+ b"10100101010110100000",
+ b"10100101011111011000",
+ b"10100101101000010001",
+ b"10100101110001001011",
+ b"10100101111010000110",
+ b"10100110000011000010",
+ b"10100110001011111110",
+ b"10100110010100111100",
+ b"10100110011101111010",
+ b"10100110100110111001",
+ b"10100110101111111001",
+ b"10100110111000111010",
+ b"10100111000001111100",
+ b"10100111001010111111",
+ b"10100111010100000010",
+ b"10100111011101000111",
+ b"10100111100110001100",
+ b"10100111101111010010",
+ b"10100111111000011001",
+ b"10101000000001100001",
+ b"10101000001010101001",
+ b"10101000010011110011",
+ b"10101000011100111101",
+ b"10101000100110001000",
+ b"10101000101111010100",
+ b"10101000111000100001",
+ b"10101001000001101110",
+ b"10101001001010111101",
+ b"10101001010100001100",
+ b"10101001011101011100",
+ b"10101001100110101101",
+ b"10101001101111111111",
+ b"10101001111001010010",
+ b"10101010000010100101",
+ b"10101010001011111010",
+ b"10101010010101001111",
+ b"10101010011110100101",
+ b"10101010100111111100",
+ b"10101010110001010011",
+ b"10101010111010101100",
+ b"10101011000100000101",
+ b"10101011001101011111",
+ b"10101011010110111010",
+ b"10101011100000010110",
+ b"10101011101001110010",
+ b"10101011110011010000",
+ b"10101011111100101110",
+ b"10101100000110001101",
+ b"10101100001111101100",
+ b"10101100011001001101",
+ b"10101100100010101110",
+ b"10101100101100010001",
+ b"10101100110101110100",
+ b"10101100111111010111",
+ b"10101101001000111100",
+ b"10101101010010100001",
+ b"10101101011100001000",
+ b"10101101100101101110",
+ b"10101101101111010110",
+ b"10101101111000111111",
+ b"10101110000010101000",
+ b"10101110001100010010",
+ b"10101110010101111101",
+ b"10101110011111101001",
+ b"10101110101001010110",
+ b"10101110110011000011",
+ b"10101110111100110001",
+ b"10101111000110100000",
+ b"10101111010000001111",
+ b"10101111011010000000",
+ b"10101111100011110001",
+ b"10101111101101100011",
+ b"10101111110111010110",
+ b"10110000000001001001",
+ b"10110000001010111110",
+ b"10110000010100110011",
+ b"10110000011110101000",
+ b"10110000101000011111",
+ b"10110000110010010110",
+ b"10110000111100001111",
+ b"10110001000110000111",
+ b"10110001010000000001",
+ b"10110001011001111011",
+ b"10110001100011110111",
+ b"10110001101101110011",
+ b"10110001110111101111",
+ b"10110010000001101101",
+ b"10110010001011101011",
+ b"10110010010101101010",
+ b"10110010011111101001",
+ b"10110010101001101010",
+ b"10110010110011101011",
+ b"10110010111101101101",
+ b"10110011000111110000",
+ b"10110011010001110011",
+ b"10110011011011110111",
+ b"10110011100101111100",
+ b"10110011110000000010",
+ b"10110011111010001000",
+ b"10110100000100001111",
+ b"10110100001110010111",
+ b"10110100011000011111",
+ b"10110100100010101001",
+ b"10110100101100110011",
+ b"10110100110110111101",
+ b"10110101000001001001",
+ b"10110101001011010101",
+ b"10110101010101100010",
+ b"10110101011111101111",
+ b"10110101101001111110",
+ b"10110101110100001101",
+ b"10110101111110011101",
+ b"10110110001000101101",
+ b"10110110010010111110",
+ b"10110110011101010000",
+ b"10110110100111100011",
+ b"10110110110001110110",
+ b"10110110111100001010",
+ b"10110111000110011111",
+ b"10110111010000110100",
+ b"10110111011011001010",
+ b"10110111100101100001",
+ b"10110111101111111001",
+ b"10110111111010010001",
+ b"10111000000100101010",
+ b"10111000001111000011",
+ b"10111000011001011110",
+ b"10111000100011111001",
+ b"10111000101110010100",
+ b"10111000111000110001",
+ b"10111001000011001110",
+ b"10111001001101101100",
+ b"10111001011000001010",
+ b"10111001100010101001",
+ b"10111001101101001001",
+ b"10111001110111101001",
+ b"10111010000010001010",
+ b"10111010001100101100",
+ b"10111010010111001111",
+ b"10111010100001110010",
+ b"10111010101100010110",
+ b"10111010110110111010",
+ b"10111011000001011111",
+ b"10111011001100000101",
+ b"10111011010110101100",
+ b"10111011100001010011",
+ b"10111011101011111011",
+ b"10111011110110100011",
+ b"10111100000001001100",
+ b"10111100001011110110",
+ b"10111100010110100000",
+ b"10111100100001001011",
+ b"10111100101011110111",
+ b"10111100110110100011",
+ b"10111101000001010000",
+ b"10111101001011111110",
+ b"10111101010110101100",
+ b"10111101100001011011",
+ b"10111101101100001011",
+ b"10111101110110111011",
+ b"10111110000001101100",
+ b"10111110001100011110",
+ b"10111110010111010000",
+ b"10111110100010000011",
+ b"10111110101100110110",
+ b"10111110110111101010",
+ b"10111111000010011111",
+ b"10111111001101010100",
+ b"10111111011000001010",
+ b"10111111100011000000",
+ b"10111111101101111000",
+ b"10111111111000101111",
+ b"11000000000011101000",
+ b"11000000001110100001",
+ b"11000000011001011010",
+ b"11000000100100010101",
+ b"11000000101111001111",
+ b"11000000111010001011",
+ b"11000001000101000111",
+ b"11000001010000000100",
+ b"11000001011011000001",
+ b"11000001100101111111",
+ b"11000001110000111101",
+ b"11000001111011111100",
+ b"11000010000110111100",
+ b"11000010010001111100",
+ b"11000010011100111101",
+ b"11000010100111111111",
+ b"11000010110011000001",
+ b"11000010111110000011",
+ b"11000011001001000111",
+ b"11000011010100001010",
+ b"11000011011111001111",
+ b"11000011101010010100",
+ b"11000011110101011001",
+ b"11000100000000100000",
+ b"11000100001011100110",
+ b"11000100010110101110",
+ b"11000100100001110101",
+ b"11000100101100111110",
+ b"11000100111000000111",
+ b"11000101000011010001",
+ b"11000101001110011011",
+ b"11000101011001100101",
+ b"11000101100100110001",
+ b"11000101101111111101",
+ b"11000101111011001001",
+ b"11000110000110010110",
+ b"11000110010001100100",
+ b"11000110011100110010",
+ b"11000110101000000000",
+ b"11000110110011001111",
+ b"11000110111110011111",
+ b"11000111001001110000",
+ b"11000111010101000000",
+ b"11000111100000010010",
+ b"11000111101011100100",
+ b"11000111110110110110",
+ b"11001000000010001001",
+ b"11001000001101011101",
+ b"11001000011000110001",
+ b"11001000100100000110",
+ b"11001000101111011011",
+ b"11001000111010110000",
+ b"11001001000110000111",
+ b"11001001010001011101",
+ b"11001001011100110101",
+ b"11001001101000001101",
+ b"11001001110011100101",
+ b"11001001111110111110",
+ b"11001010001010010111",
+ b"11001010010101110001",
+ b"11001010100001001011",
+ b"11001010101100100110",
+ b"11001010111000000010",
+ b"11001011000011011110",
+ b"11001011001110111010",
+ b"11001011011010010111",
+ b"11001011100101110101",
+ b"11001011110001010011",
+ b"11001011111100110001",
+ b"11001100001000010000",
+ b"11001100010011110000",
+ b"11001100011111010000",
+ b"11001100101010110000",
+ b"11001100110110010001",
+ b"11001101000001110011",
+ b"11001101001101010101",
+ b"11001101011000110111",
+ b"11001101100100011010",
+ b"11001101101111111110",
+ b"11001101111011100001",
+ b"11001110000111000110",
+ b"11001110010010101011",
+ b"11001110011110010000",
+ b"11001110101001110110",
+ b"11001110110101011100",
+ b"11001111000001000011",
+ b"11001111001100101010",
+ b"11001111011000010010",
+ b"11001111100011111010",
+ b"11001111101111100011",
+ b"11001111111011001100",
+ b"11010000000110110110",
+ b"11010000010010100000",
+ b"11010000011110001010",
+ b"11010000101001110101",
+ b"11010000110101100001",
+ b"11010001000001001101",
+ b"11010001001100111001",
+ b"11010001011000100110",
+ b"11010001100100010011",
+ b"11010001110000000001",
+ b"11010001111011101111",
+ b"11010010000111011101",
+ b"11010010010011001100",
+ b"11010010011110111100",
+ b"11010010101010101100",
+ b"11010010110110011100",
+ b"11010011000010001101",
+ b"11010011001101111110",
+ b"11010011011001110000",
+ b"11010011100101100010",
+ b"11010011110001010100",
+ b"11010011111101000111",
+ b"11010100001000111010",
+ b"11010100010100101110",
+ b"11010100100000100010",
+ b"11010100101100010111",
+ b"11010100111000001100",
+ b"11010101000100000001",
+ b"11010101001111110111",
+ b"11010101011011101110",
+ b"11010101100111100100",
+ b"11010101110011011011",
+ b"11010101111111010011",
+ b"11010110001011001011",
+ b"11010110010111000011",
+ b"11010110100010111100",
+ b"11010110101110110101",
+ b"11010110111010101110",
+ b"11010111000110101000",
+ b"11010111010010100011",
+ b"11010111011110011101",
+ b"11010111101010011000",
+ b"11010111110110010100",
+ b"11011000000010010000",
+ b"11011000001110001100",
+ b"11011000011010001000",
+ b"11011000100110000101",
+ b"11011000110010000011",
+ b"11011000111110000001",
+ b"11011001001001111111",
+ b"11011001010101111101",
+ b"11011001100001111100",
+ b"11011001101101111011",
+ b"11011001111001111011",
+ b"11011010000101111011",
+ b"11011010010001111011",
+ b"11011010011101111100",
+ b"11011010101001111101",
+ b"11011010110101111111",
+ b"11011011000010000000",
+ b"11011011001110000010",
+ b"11011011011010000101",
+ b"11011011100110001000",
+ b"11011011110010001011",
+ b"11011011111110001111",
+ b"11011100001010010010",
+ b"11011100010110010111",
+ b"11011100100010011011",
+ b"11011100101110100000",
+ b"11011100111010100110",
+ b"11011101000110101011",
+ b"11011101010010110001",
+ b"11011101011110110111",
+ b"11011101101010111110",
+ b"11011101110111000101",
+ b"11011110000011001100",
+ b"11011110001111010100",
+ b"11011110011011011100",
+ b"11011110100111100100",
+ b"11011110110011101101",
+ b"11011110111111110110",
+ b"11011111001011111111",
+ b"11011111011000001000",
+ b"11011111100100010010",
+ b"11011111110000011100",
+ b"11011111111100100111",
+ b"11100000001000110001",
+ b"11100000010100111101",
+ b"11100000100001001000",
+ b"11100000101101010100",
+ b"11100000111001100000",
+ b"11100001000101101100",
+ b"11100001010001111001",
+ b"11100001011110000101",
+ b"11100001101010010011",
+ b"11100001110110100000",
+ b"11100010000010101110",
+ b"11100010001110111100",
+ b"11100010011011001010",
+ b"11100010100111011001",
+ b"11100010110011101000",
+ b"11100010111111110111",
+ b"11100011001100000110",
+ b"11100011011000010110",
+ b"11100011100100100110",
+ b"11100011110000110110",
+ b"11100011111101000111",
+ b"11100100001001011000",
+ b"11100100010101101001",
+ b"11100100100001111010",
+ b"11100100101110001100",
+ b"11100100111010011110",
+ b"11100101000110110000",
+ b"11100101010011000011",
+ b"11100101011111010101",
+ b"11100101101011101000",
+ b"11100101110111111011",
+ b"11100110000100001111",
+ b"11100110010000100010",
+ b"11100110011100110110",
+ b"11100110101001001011",
+ b"11100110110101011111",
+ b"11100111000001110100",
+ b"11100111001110001001",
+ b"11100111011010011110",
+ b"11100111100110110011",
+ b"11100111110011001001",
+ b"11100111111111011111",
+ b"11101000001011110101",
+ b"11101000011000001011",
+ b"11101000100100100010",
+ b"11101000110000111000",
+ b"11101000111101001111",
+ b"11101001001001100111",
+ b"11101001010101111110",
+ b"11101001100010010110",
+ b"11101001101110101110",
+ b"11101001111011000110",
+ b"11101010000111011110",
+ b"11101010010011110110",
+ b"11101010100000001111",
+ b"11101010101100101000",
+ b"11101010111001000001",
+ b"11101011000101011011",
+ b"11101011010001110100",
+ b"11101011011110001110",
+ b"11101011101010101000",
+ b"11101011110111000010",
+ b"11101100000011011100",
+ b"11101100001111110111",
+ b"11101100011100010001",
+ b"11101100101000101100",
+ b"11101100110101000111",
+ b"11101101000001100011",
+ b"11101101001101111110",
+ b"11101101011010011010",
+ b"11101101100110110110",
+ b"11101101110011010010",
+ b"11101101111111101110",
+ b"11101110001100001010",
+ b"11101110011000100111",
+ b"11101110100101000011",
+ b"11101110110001100000",
+ b"11101110111101111101",
+ b"11101111001010011010",
+ b"11101111010110111000",
+ b"11101111100011010101",
+ b"11101111101111110011",
+ b"11101111111100010001",
+ b"11110000001000101111",
+ b"11110000010101001101",
+ b"11110000100001101011",
+ b"11110000101110001001",
+ b"11110000111010101000",
+ b"11110001000111000111",
+ b"11110001010011100110",
+ b"11110001100000000101",
+ b"11110001101100100100",
+ b"11110001111001000011",
+ b"11110010000101100010",
+ b"11110010010010000010",
+ b"11110010011110100010",
+ b"11110010101011000001",
+ b"11110010110111100001",
+ b"11110011000100000001",
+ b"11110011010000100010",
+ b"11110011011101000010",
+ b"11110011101001100010",
+ b"11110011110110000011",
+ b"11110100000010100100",
+ b"11110100001111000100",
+ b"11110100011011100101",
+ b"11110100101000000110",
+ b"11110100110100100111",
+ b"11110101000001001001",
+ b"11110101001101101010",
+ b"11110101011010001011",
+ b"11110101100110101101",
+ b"11110101110011001111",
+ b"11110101111111110000",
+ b"11110110001100010010",
+ b"11110110011000110100",
+ b"11110110100101010110",
+ b"11110110110001111000",
+ b"11110110111110011010",
+ b"11110111001010111101",
+ b"11110111010111011111",
+ b"11110111100100000001",
+ b"11110111110000100100",
+ b"11110111111101000111",
+ b"11111000001001101001",
+ b"11111000010110001100",
+ b"11111000100010101111",
+ b"11111000101111010010",
+ b"11111000111011110101",
+ b"11111001001000011000",
+ b"11111001010100111011",
+ b"11111001100001011110",
+ b"11111001101110000001",
+ b"11111001111010100101",
+ b"11111010000111001000",
+ b"11111010010011101100",
+ b"11111010100000001111",
+ b"11111010101100110011",
+ b"11111010111001010110",
+ b"11111011000101111010",
+ b"11111011010010011101",
+ b"11111011011111000001",
+ b"11111011101011100101",
+ b"11111011111000001001",
+ b"11111100000100101101",
+ b"11111100010001010000",
+ b"11111100011101110100",
+ b"11111100101010011000",
+ b"11111100110110111100",
+ b"11111101000011100000",
+ b"11111101010000000100",
+ b"11111101011100101000",
+ b"11111101101001001101",
+ b"11111101110101110001",
+ b"11111110000010010101",
+ b"11111110001110111001",
+ b"11111110011011011101",
+ b"11111110101000000001",
+ b"11111110110100100110",
+ b"11111111000001001010",
+ b"11111111001101101110",
+ b"11111111011010010010",
+ b"11111111100110110111",
+ b"11111111110011011011"
);
constant wMap: wMapTyp :=
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg_wb.vhd b/libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg_wb.vhd
deleted file mode 100644
index d2e8b898b43314e22d2416b33215550a6370490c..0000000000000000000000000000000000000000
--- a/libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg_wb.vhd
+++ /dev/null
@@ -1,139 +0,0 @@
--------------------------------------
---FILE GENERATED BY TWIDDLE GENERATOR
---DO NOT EDIT THIS FILE !!!
--------------------------------------
---Author :R.T.Rajan
---Date :09-Nov-2011
---N :17 # of FFT points
---B :16 # of twiddle bits
---P :4 over clocking rate
--------------------------------------
-
-
-Library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
- package twiddlesPkg_wb is
- constant copyRightNotice: string
- := "Copyright 2009-2011 , ASTRON. All rights reserved.";
-
- subtype wTyp is std_logic_vector(15 downto 0);
- type wRowTyp is array( 1 to 17 ) of wTyp;
- type wMapTyp is array( integer range 0 to 31, integer range 4 downto 1) of natural;
-
- constant wRe: wRowTyp :=
- (
- b"0111111111111111",
- b"0111110110001001",
- b"0111011001000001",
- b"0110101001101101",
- b"0101101010000010",
- b"0100011100011100",
- b"0011000011111011",
- b"0001100011111001",
- b"0000000000000000",
- b"1110011100000110",
- b"1100111100000100",
- b"1011100011100011",
- b"1010010101111101",
- b"1001010110010010",
- b"1000100110111110",
- b"1000001001110110",
- b"1000000000000000"
- );
-
- constant wIm: wRowTyp :=
- (
- b"0111111111111111",
- b"0111110110001001",
- b"0111011001000001",
- b"0110101001101101",
- b"0101101010000010",
- b"0100011100011100",
- b"0011000011111011",
- b"0001100011111001",
- b"0000000000000000",
- b"1110011100000110",
- b"1100111100000100",
- b"1011100011100011",
- b"1010010101111101",
- b"1001010110010010",
- b"1000100110111110",
- b"1000001001110110",
- b"1000001001110110"
- );
-
- constant wMapRe: wMapTyp :=
- (
- (1,1,1,1),
- (1,2,3,4),
- (1,3,5,7),
- (1,4,7,10),
- (1,5,9,13),
- (1,6,11,16),
- (1,7,13,15),
- (1,8,15,12),
- (1,9,17,9),
- (1,10,15,6),
- (1,11,13,3),
- (1,12,11,2),
- (1,13,9,5),
- (1,14,7,8),
- (1,15,5,11),
- (1,16,3,14),
- (1,17,1,17),
- (1,16,3,14),
- (1,15,5,11),
- (1,14,7,8),
- (1,13,9,5),
- (1,12,11,2),
- (1,11,13,3),
- (1,10,15,6),
- (1,9,17,9),
- (1,8,15,12),
- (1,7,13,15),
- (1,6,11,16),
- (1,5,9,13),
- (1,4,7,10),
- (1,3,5,7),
- (1,2,3,4)
- );
-
- constant wMapIm: wMapTyp :=
- (
- (9,9,9,9),
- (9,8,7,6),
- (9,7,5,3),
- (9,6,3,2),
- (9,5,1,5),
- (9,4,3,8),
- (9,3,5,11),
- (9,2,7,14),
- (9,1,9,17),
- (9,2,11,14),
- (9,3,13,11),
- (9,4,15,8),
- (9,5,17,5),
- (9,6,15,2),
- (9,7,13,3),
- (9,8,11,6),
- (9,9,9,9),
- (9,10,7,12),
- (9,11,5,15),
- (9,12,3,16),
- (9,13,1,13),
- (9,14,3,10),
- (9,15,5,7),
- (9,16,7,4),
- (9,17,9,1),
- (9,16,11,4),
- (9,15,13,7),
- (9,14,15,10),
- (9,13,17,13),
- (9,12,15,16),
- (9,11,13,15),
- (9,10,11,12)
- );
-
- end package twiddlesPkg_wb;
diff --git a/libraries/dsp/rTwoSDF/tb/data/test/out/uniNoise_p1024_in8_out14_out_tw20.txt b/libraries/dsp/rTwoSDF/tb/data/test/out/uniNoise_p1024_in8_out14_out_tw20.txt
new file mode 100644
index 0000000000000000000000000000000000000000..27f3e2e98d8a4ea391cd1505d305bb2e001f5789
--- /dev/null
+++ b/libraries/dsp/rTwoSDF/tb/data/test/out/uniNoise_p1024_in8_out14_out_tw20.txt
@@ -0,0 +1,6145 @@
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diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
index a03663c51fb0056f341b11fb19774159d0bd5d62..f12448032c9abd2c9d51901f3dc5b228ae6c9689 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
@@ -42,7 +42,18 @@
-- compare it with the rTwoSDF implementation output file result.
-- 2) The rTwoSDF implementation output file is also kept in SVN as golden
-- reference result to allow verification using a file diff command like
--- e.g. WinMerge. This then avoids the need to run MATLAB to verify.
+-- e.g. meld or WinMerge. This then avoids the need to run MATLAB to
+-- verify. E.g.:
+--
+-- diff build/unb2c/modelsim/rTwoSDF/data/test/out/uniNoise_out.txt
+-- build/unb2c/modelsim/rTwoSDF/data/test/out/uniNoise_p1024_in8_out14_out.txt
+--
+-- The uniNoise_p1024_in8_out14_out.txt uses c_twiddle_w = 18 bit.
+-- The uniNoise_p1024_in8_out14_out_tw20.txt golden results was created by
+-- running the tb with g_use_reorder = true and copying the created
+-- uniNoise_out.txt. Using meld shows that the golden result files for
+-- c_twiddle_w = 18 b and 20 b only differ by +-1 for some values, as
+-- expected.
--
-- The tb asserts an error when the output does not match the expected output
-- that is read from the golden reference file. The output is also written
@@ -77,12 +88,12 @@ use work.twiddlesPkg.all;
entity tb_rTwoSDF is
generic(
-- generics for tb
- g_use_uniNoise_file : boolean := true;
+ g_use_uniNoise_file : boolean := true; -- golden results currently only available for false (noise data)
g_in_en : natural := 1; -- 1 = always active, others = random control
-- generics for rTwoSDF
- g_use_reorder : boolean := false; -- tb supports both true and false
+ g_use_reorder : boolean := true; -- tb supports both true and false, use true to create golden output file
g_nof_points : natural := 1024;
- g_in_dat_w : natural := 8;
+ g_in_dat_w : natural := 8; -- use g_in_dat_w = 8 when g_use_uniNoise_file = true
g_out_dat_w : natural := 14;
g_guard_w : natural := 2 -- guard bits are used to avoid overflow in single FFT stage.
);
@@ -96,6 +107,7 @@ architecture tb of tb_rTwoSDF is
constant c_nof_points_w : natural := ceil_log2(g_nof_points);
-- input/output data width
+ constant c_twiddle_w : natural := wTyp'length;
constant c_stage_dat_w : natural := sel_a_b(g_out_dat_w > c_dsp_mult_w, g_out_dat_w, c_dsp_mult_w); -- number of bits used between the stages
-- input/output files
@@ -103,13 +115,15 @@ architecture tb of tb_rTwoSDF is
constant c_repeat : natural := 2; -- >= 2 to have sufficent frames for c_outputFile evaluation by testFFT_output.m
-- input from uniform noise file created automatically by MATLAB testFFT_input.m
- constant c_noiseInputFile : string := "data/test/in/uniNoise_p" & natural'image(g_nof_points)& "_b"& natural'image(g_in_dat_w) &"_in.txt";
- constant c_noiseGoldenFile : string := "data/test/out/uniNoise_p" & natural'image(g_nof_points)& "_in"& natural'image(g_in_dat_w) &"_out"&natural'image(g_out_dat_w) &"_out.txt";
- constant c_noiseOutputFile : string := "data/test/out/uniNoise_out.txt";
+ constant c_noiseInputFile : string := "data/test/in/uniNoise_p" & natural'image(g_nof_points) & "_b" & natural'image(g_in_dat_w) & "_in.txt";
+ constant c_noiseGoldenFile_tw18 : string := "data/test/out/uniNoise_p" & natural'image(g_nof_points) & "_in" & natural'image(g_in_dat_w) & "_out" & natural'image(g_out_dat_w) & "_out.txt";
+ constant c_noiseGoldenFile_tw20 : string := "data/test/out/uniNoise_p" & natural'image(g_nof_points) & "_in" & natural'image(g_in_dat_w) & "_out" & natural'image(g_out_dat_w) & "_out_tw" & natural'image(c_twiddle_w) & ".txt";
+ constant c_noiseGoldenFile : string := sel_a_b(c_twiddle_w = 18, c_noiseGoldenFile_tw18, c_noiseGoldenFile_tw20);
+ constant c_noiseOutputFile : string := "data/test/out/uniNoise_out.txt";
-- input from manually created file
- constant c_impulseInputFile : string := "data/test/in/impulse_p" & natural'image(g_nof_points)& "_b"& natural'image(g_in_dat_w)& "_in.txt";
- constant c_impulseGoldenFile : string := "data/test/out/impulse_p" & natural'image(g_nof_points)& "_b"& natural'image(g_in_dat_w)& "_out.txt";
+ constant c_impulseInputFile : string := "data/test/in/impulse_p" & natural'image(g_nof_points)& "_b" & natural'image(g_in_dat_w)& "_in.txt";
+ constant c_impulseGoldenFile : string := "data/test/out/impulse_p" & natural'image(g_nof_points)& "_b" & natural'image(g_in_dat_w)& "_out.txt";
constant c_impulseOutputFile : string := "data/test/out/impulse_out.txt";
-- determine active stimuli and result files
@@ -254,7 +268,8 @@ begin
g_out_dat_w => g_out_dat_w,
g_stage_dat_w => c_stage_dat_w,
g_guard_w => g_guard_w,
- g_nof_points => g_nof_points
+ g_nof_points => g_nof_points,
+ g_round_even => false -- golden results use round half away instead of round half even
)
port map(
clk => clk,
diff --git a/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
index 3324698c2c237c5a69335797bcb40e5a9dfe4853..46e895987c2972ccb90183207a443e1c811775db 100644
--- a/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
@@ -37,6 +37,7 @@
-- the tb, because one tb needs to open the file for 'write' and the other
-- tb then need to open it for 'append'. Using manual copy of text from
-- transcript window is acceptable.
+-- . Can try different FIR filter coefficients from LOFAR1, pfs_coeff_final.m
--
-- Usage:
-- > as 4
@@ -56,10 +57,41 @@ END ENTITY tb_tb_verify_pfb_wg;
ARCHITECTURE tb OF tb_tb_verify_pfb_wg IS
- CONSTANT c_fil_coefs : STRING := "data/Coeffs16384Kaiser-quant_1wb"; -- PFIR coefficients file access
- CONSTANT c_fil_nodc : STRING := "data/Coeffs16384Kaiser-quant-nodc_1wb"; -- PFIR coefficients file access
- CONSTANT c_fil_bypass : STRING := "data/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb"; -- bypass PFIR
-
+ -- LOFAR1
+ CONSTANT c_fil_coefs : STRING := "data/Coeffs16384Kaiser-quant_1wb";
+
+ -- Modified LOFAR1
+ CONSTANT c_fil_nodc : STRING := "data/Coeffs16384Kaiser-quant-nodc_1wb";
+
+ -- Bypass PFIR to have PFB = FFT
+ CONSTANT c_fil_bypass : STRING := "data/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb";
+
+ -- PFIR coefficients from pfs_coeff_final.m
+ -- . Created FIR filter with Hanning window for almost equal DC per polyphase
+ -- . Created FIR filter with 18b or 20b coefficients to compare difference with 16b
+ -- MATLAB > cd applications/lofar2/model/
+ -- MATLAB > pfs_coeff_final
+ -- > cp applications/lofar2/model/data/Coefficient_16KHanning_16b.dat libraries/dsp/filter/src/hex/
+ -- > cp applications/lofar2/model/data/Coefficient_16KHanning_18b.dat libraries/dsp/filter/src/hex/
+ -- > cp applications/lofar2/model/data/Coefficient_16KKaiser_16b.dat libraries/dsp/filter/src/hex/
+ -- > cp applications/lofar2/model/data/Coefficient_16KKaiser_18b.dat libraries/dsp/filter/src/hex/
+ -- > cd ../upe_gear/
+ -- > . ./init_upe.sh
+ -- > cd libraries/dsp/filter/src/python/
+ -- > python fil_ppf_create_mifs.py -f ../hex/Coefficient_16KHanning_16b.dat -t 16 -p 1024 -w 1 -c 16
+ -- > python fil_ppf_create_mifs.py -f ../hex/Coefficient_16KHanning_18b.dat -t 16 -p 1024 -w 1 -c 18
+ -- > python fil_ppf_create_mifs.py -f ../hex/Coefficient_16KKaiser_16b.dat -t 16 -p 1024 -w 1 -c 16
+ -- > python fil_ppf_create_mifs.py -f ../hex/Coefficient_16KKaiser_16b.dat -t 16 -p 1024 -w 1 -c 18
+ -- > modelsim_config unb2c # to update verify_pfb build dir
+ -- > ll build/unb2c/modelsim/verify_pfb/data/Coefficient_*
+ -- Select FIR coefficients from pfs_coeff_final.m via c_fil_hanning and c_fil_kaiser
+ CONSTANT c_fil_hanning_16b : STRING := "data/Coefficient_16KHanning_16b_1wb";
+ CONSTANT c_fil_hanning_18b : STRING := "data/Coefficient_16KHanning_18b_1wb";
+ CONSTANT c_fil_hanning_20b : STRING := "data/Coefficient_16KHanning_20b_1wb";
+ CONSTANT c_fil_kaiser_16b : STRING := "data/Coefficient_16KKaiser_16b_1wb";
+ CONSTANT c_fil_kaiser_18b : STRING := "data/Coefficient_16KKaiser_18b_1wb";
+ CONSTANT c_fil_kaiser_20b : STRING := "data/Coefficient_16KKaiser_20b_1wb";
+
SIGNAL tb_end : STD_LOGIC := '0'; -- tb_end is used to end a tb if it cannot end itself, but is not needed for tb_verify_pfb_wg
-- however, do declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
@@ -76,7 +108,8 @@ ARCHITECTURE tb OF tb_tb_verify_pfb_wg IS
CONSTANT c_gen_vary_c_twiddle_w : BOOLEAN := FALSE;
CONSTANT c_gen_vary_extra_w : BOOLEAN := FALSE;
CONSTANT c_gen_2020_dec : BOOLEAN := FALSE;
-
+ CONSTANT c_gen_2022_mar : BOOLEAN := FALSE;
+
BEGIN
-- generics of tb_verify_pfb_wg
@@ -129,8 +162,6 @@ BEGIN
-- g_fft_stage_dat_w : NATURAL := 18; -- = c_dsp_mult_w = 18, number of bits that are used inter-stage
-- g_fft_guard_w : NATURAL := 1 -- = 2
-- g_switch_en : STD_LOGIC := '0'; -- two real input decorrelation option in PFB2
--- g_r2_mul_extra_w : NATURAL := 0 -- = 0, extra bits at rTwoWMul output in rTwoSDFStage to improve rTwoSDFStage output requantization in fft_r2_pipe in wpfb_unit_dev
--- g_sepa_extra_w : NATURAL := 2 -- = 2, extra LSbits in output of last rTwoSDFStage to improve two real separate requantization in fft_r2_pipe in wpfb_unit_dev
-- g_tb_index
@@ -151,24 +182,28 @@ BEGIN
-- . . . . . . . . . . . . . . . g_fft_stage_dat_w
-- . . . . . . . . . . . . . . . . g_fft_guard_w
-- . . . . . . . . . . . . . . . . . g_switch_en
- -- . . . . . . . . . . . . . . . . . . g_r2_mul_extra_w
- -- . . . . . . . . . . . . . . . . . . . g_sepa_extra_w
- -- . . . . . . . . . . . . . . . . . . . .
-gen_ref : IF c_gen_ref GENERATE -- . . . . . . . . . . . . . . . . . . . .
- -- WPFB . . . . . . . . . . . . . . . . . . . .
- u_apertif : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1001, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 8, 16, 18, 1, 18, 2, '0', 0, 0);
- u_lts_2020_11_23 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1002, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 1, 18, 2, '0', 0, 0);
- -- PFB2
- u_lofar1_12b : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1003, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 12, 18, 18, 0, 20, 0, '0', 0, 0);
- u_lofar1_14b : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1004, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0', 0, 0);
- u_lofar1_14b_22 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1005, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 22, 0, '0', 0, 0);
- u_lofar1_14b_24 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1006, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 24, 0, '0', 0, 0);
- -- WPFB
- u_wpfb_stage18 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1007, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0);
- u_wpfb_stage20 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1008, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 0);
- u_wpfb_stage22 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1009, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0', 0, 0);
- u_wpfb_stage23 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1010, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 23, 1, '0', 0, 0);
- u_wpfb_stage24 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1011, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0', 0, 0);
+ -- . . . . . . . . . . . . . . . . . .
+gen_ref : IF c_gen_ref GENERATE -- . . . . . . . . . . . . . . . . . .
+ -- WPFB . . . . . . . . . . . . . . . . . .
+ --u_apertif : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1001, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 8, 16, 18, 1, 18, 2, '0');
+ --u_lts_2020_11_23 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1002, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 1, 18, 2, '0');
+ ---- PFB2
+ u_lofar1_12b : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1003, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 12, 18, 18, 0, 20, 0, '0');
+ --u_lofar1_14b : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1004, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0');
+ --u_lofar1_14b_22 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1005, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 22, 0, '0');
+ --u_lofar1_14b_24 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1006, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 24, 0, '0');
+ ---- WPFB
+ --u_wpfb_stage18 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1007, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ --u_wpfb_stage20 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1008, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0');
+ --u_wpfb_stage22 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1009, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0');
+ --u_wpfb_stage23 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1010, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 23, 1, '0');
+ --u_wpfb_stage24 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1011, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0');
+ -- c_twiddle_w = 18
+ u_wpfb_lofar2_subbands_lts_2021 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1012, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
+ -- c_twiddle_w = 20
+ u_wpfb_lofar2_subbands_dts_18b : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1013, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 24, 1, '0'); -- = u_2000
+ u_wpfb_lofar2_subbands_dts_19b : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1014, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 24, 1, '0'); -- = u_2001
+
-- Results:
-- Coeffs16384Kaiser-quant
-- . Coeffs16384Kaiser-quant-nodc
@@ -186,6 +221,11 @@ gen_ref : IF c_gen_ref GENERATE -- . .
--tb-1009 . wpfb_measured_proc_gain_a_dB = 18.79 [dB] 24.29 [dB], = u_wpfb_stage22 : ~3.2 dB per extra g_fft_stage_dat_w bit
--tb-1010 . wpfb_measured_proc_gain_a_dB = 19.86 [dB] 26.58 [dB], = u_wpfb_stage23 : ~1.1 dB per extra g_fft_stage_dat_w bit
--tb-1011 . wpfb_measured_proc_gain_a_dB = 20.08 [dB] 28.17 [dB], = u_wpfb_stage24 : ~0.2 dB per extra g_fft_stage_dat_w bit
+
+--tb-1012 . wpfb_measured_proc_gain_a_dB = 19.26 [dB] > 18.79 [dB] from u_wpfb_stage22 in 2021, due to now c_twiddle_w = 20 (?)
+--tb-1013 . wpfb_measured_proc_gain_a_dB = 20.12 [dB] = u_2000
+--tb-1014 . wpfb_measured_proc_gain_a_dB = 18.50 [dB] = u_2001
+
--Conclusion:
--* For g_fft_stage_dat_w <= 22 the processing gain increases ~3 dB per extra g_fft_stage_dat_w bit, therefore choose 22, 23 or 24, more than 24 bit has not benefit.
END GENERATE;
@@ -193,22 +233,22 @@ END GENERATE;
gen_g_fil_backoff_w_1 : IF c_gen_g_fil_backoff_w_1 GENERATE
-- g_subband_index_a = 60.4, to check that with g_fil_backoff_w = 1 there is no FIR filter overflow
- u_149 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (149, "WPFB", 60.4, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 18, 1, '0', 0, 0);
+ u_149 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (149, "WPFB", 60.4, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 18, 1, '0');
-- g_subband_index_a = 60, WG at center subband frequency to determine PFB processing gain
-- g_fft_guard_w = 1, check that no extra FFT backoff guard at first stage is needed when g_fil_backoff_w = 1
- u_150 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (150, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 18, 1, '0', 0, 0);
- u_151 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (151, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 20, 1, '0', 0, 0);
- u_152 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (152, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 22, 1, '0', 0, 0);
- u_153 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (153, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 23, 1, '0', 0, 0);
- u_154 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (154, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 24, 1, '0', 0, 0);
- u_155 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (155, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 25, 1, '0', 0, 0);
+ u_150 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (150, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 18, 1, '0');
+ u_151 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (151, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 20, 1, '0');
+ u_152 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (152, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 22, 1, '0');
+ u_153 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (153, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 23, 1, '0');
+ u_154 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (154, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 24, 1, '0');
+ u_155 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (155, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 25, 1, '0');
-- g_fft_guard_w = 2, use extra FFT backoff guard at first FFT stage, which is compensated by no guard at last FFT stage, intermediate stages have backoff guard 1 to compensate for stage gain of factor 2
- u_156 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (156, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 18, 2, '0', 0, 0);
- u_157 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (157, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 20, 2, '0', 0, 0);
- u_158 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (158, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 22, 2, '0', 0, 0);
- u_159 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (159, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 23, 2, '0', 0, 0);
- u_160 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (160, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 24, 2, '0', 0, 0);
- u_161 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (161, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 25, 2, '0', 0, 0);
+ u_156 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (156, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 18, 2, '0');
+ u_157 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (157, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 20, 2, '0');
+ u_158 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (158, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 22, 2, '0');
+ u_159 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (159, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 23, 2, '0');
+ u_160 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (160, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 24, 2, '0');
+ u_161 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (161, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 0, 25, 2, '0');
--Results:
--g_fil_backoff_w = 1
-- g_fft_stage_dat_w
@@ -234,10 +274,10 @@ END GENERATE;
gen_vary_g_fil_backoff_w : IF c_gen_vary_g_fil_backoff_w GENERATE
- u_1000 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1000, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0', 0, 0); -- = u_wpfb_stage22
- u_1001 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1001, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 22, 0, '0', 0, 0);
- u_1002 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1002, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 18, 19, 0, 22, 0, '0', 0, 0);
- u_1003 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1003, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 18, 19, 1, 22, 0, '0', 0, 0);
+ u_1000 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1000, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
+ u_1001 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1001, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 22, 0, '0');
+ u_1002 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1002, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 18, 19, 0, 22, 0, '0');
+ u_1003 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1003, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 18, 19, 1, 22, 0, '0');
--Results:
-- . wpfb_measured_proc_gain_a_dB = 18.79 [dB]
-- . wpfb_measured_proc_gain_a_dB = 16.64 [dB]
@@ -248,13 +288,13 @@ END GENERATE;
gen_vary_g_fft_out_dat_w : IF c_gen_vary_g_fft_out_dat_w GENERATE
-- WPFB
- u_100 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (100, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0', 0, 0); -- = u_wpfb_stage22
- u_101 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (101, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 19, 0, 22, 1, '0', 0, 0);
- u_102 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (102, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 20, 0, 22, 1, '0', 0, 0);
+ u_100 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (100, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
+ u_101 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (101, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 19, 0, 22, 1, '0');
+ u_102 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (102, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 20, 0, 22, 1, '0');
-- PFB2
- u_103 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (103, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 22, 0, '0', 0, 0);
- u_104 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (104, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 19, 0, 22, 0, '0', 0, 0);
- u_105 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (105, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 20, 0, 22, 0, '0', 0, 0);
+ u_103 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (103, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 22, 0, '0');
+ u_104 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (104, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 19, 0, 22, 0, '0');
+ u_105 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (105, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 20, 0, 22, 0, '0');
-- Results:
-- g_fft_out_dat_w
-- WPFB .
@@ -267,15 +307,10 @@ gen_vary_g_fft_out_dat_w : IF c_gen_vary_g_fft_out_dat_w GENERATE
--tb-105 20 . wpfb_measured_proc_gain_a_dB = 16.36 [dB]
END GENERATE;
-
gen_2020_jan_18 : IF c_gen_2020_jan_18 GENERATE
- u_200 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (200, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 1, 18, 2, '0', 0, 0); -- = u_lts_2020_11_23
- u_201 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (201, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_202 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (202, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 2, 0);
- u_203 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (203, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 2, 2);
- u_204 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (204, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 0); -- = u_wpfb_stage20
- u_205 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (205, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 2, 0);
- u_206 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (206, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 2, 2);
+ u_200 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (200, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 16, 18, 1, 18, 2, '0'); -- = u_lts_2020_11_23
+ u_201 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (201, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_204 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (204, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0'); -- = u_wpfb_stage20
-- Results:
-- Table C: PFB processing gain for APERTIF WPFB quick improvements
@@ -293,22 +328,22 @@ END GENERATE;
gen_vary_wg_integer_freq : IF c_gen_vary_wg_integer_freq GENERATE
- u_2001 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2001, "WPFB", 1.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2002 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2002, "WPFB", 2.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2003 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2003, "WPFB", 3.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2004 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2004, "WPFB", 4.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2008 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2008, "WPFB", 8.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2016 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2016, "WPFB", 16.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2032 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2032, "WPFB", 32.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2037 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2037, "WPFB", 37.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2061 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2061, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2064 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2064, "WPFB", 64.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2117 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2117, "WPFB",117.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2128 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2128, "WPFB",128.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2256 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2256, "WPFB",256.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2257 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2257, "WPFB",257.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2373 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2373, "WPFB",373.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_2503 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2503, "WPFB",503.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
+ u_2001 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2001, "WPFB", 1.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2002 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2002, "WPFB", 2.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2003 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2003, "WPFB", 3.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2004 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2004, "WPFB", 4.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2008 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2008, "WPFB", 8.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2016 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2016, "WPFB", 16.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2032 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2032, "WPFB", 32.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2037 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2037, "WPFB", 37.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2061 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2061, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2064 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2064, "WPFB", 64.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2117 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2117, "WPFB",117.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2128 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2128, "WPFB",128.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2256 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2256, "WPFB",256.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2257 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2257, "WPFB",257.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2373 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2373, "WPFB",373.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2503 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2503, "WPFB",503.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
-- Results:
-- g_subband_index_a
@@ -335,29 +370,29 @@ gen_vary_wg_fractional_freq : IF c_gen_vary_wg_fractional_freq GENERATE
-- Use fractions that fit integer number of periods in sync interval c_N_blk = c_wpfb.nof_blk_per_sync = 10, so c_N_blk*fraction must be integer, to have stable SST value
-- Need to use g_amplitude_a = 0.9 ~< 0.95 to avoid overflow in PFS output, that occurs for some fractional g_subband_index_a
-- WG freq 60.0
- u_600 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (600, "WPFB", 60.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_601 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (601, "WPFB", 60.1, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_602 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (602, "WPFB", 60.2, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_603 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (603, "WPFB", 60.3, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_604 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (604, "WPFB", 60.4, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_605 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (605, "WPFB", 60.5, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_606 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (606, "WPFB", 60.6, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_607 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (607, "WPFB", 60.7, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_608 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (608, "WPFB", 60.8, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_609 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (609, "WPFB", 60.9, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
+ u_600 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (600, "WPFB", 60.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_601 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (601, "WPFB", 60.1, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_602 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (602, "WPFB", 60.2, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_603 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (603, "WPFB", 60.3, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_604 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (604, "WPFB", 60.4, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_605 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (605, "WPFB", 60.5, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_606 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (606, "WPFB", 60.6, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_607 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (607, "WPFB", 60.7, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_608 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (608, "WPFB", 60.8, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_609 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (609, "WPFB", 60.9, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
-- WG freq 61.0
- u_610 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (610, "WPFB", 61.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18 freq 61
- u_611 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (611, "WPFB", 61.1, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_612 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (612, "WPFB", 61.2, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_613 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (613, "WPFB", 61.3, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_614 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (614, "WPFB", 61.4, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_615 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (615, "WPFB", 61.5, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_616 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (616, "WPFB", 61.6, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_617 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (617, "WPFB", 61.7, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_618 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (618, "WPFB", 61.8, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_619 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (619, "WPFB", 61.9, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
+ u_610 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (610, "WPFB", 61.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18 freq 61
+ u_611 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (611, "WPFB", 61.1, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_612 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (612, "WPFB", 61.2, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_613 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (613, "WPFB", 61.3, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_614 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (614, "WPFB", 61.4, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_615 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (615, "WPFB", 61.5, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_616 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (616, "WPFB", 61.6, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_617 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (617, "WPFB", 61.7, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_618 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (618, "WPFB", 61.8, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_619 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (619, "WPFB", 61.9, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
-- WG freq 62.0
- u_620 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (620, "WPFB", 62.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
+ u_620 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (620, "WPFB", 62.0, 61.0, 0.9, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
-- Note>:
-- . For fractional subband frequencies the WG can only generate the average frequency, due to limited period accuracy of WG. This causes
@@ -392,65 +427,65 @@ END GENERATE;
gen_vary_g_fft_stage_dat_w : IF c_gen_vary_g_fft_stage_dat_w GENERATE
-- g_internal_dat_w = constant
-- WPFB
- u_300 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (300, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_301 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (301, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 19, 1, '0', 0, 0);
- u_302 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (302, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 0); -- = u_wpfb_stage20
- u_303 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (303, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 21, 1, '0', 0, 0);
- u_304 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (304, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0', 0, 0); -- = u_wpfb_stage22
- u_305 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (305, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 23, 1, '0', 0, 0); -- = u_wpfb_stage23
- u_306 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (306, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0', 0, 0); -- = u_wpfb_stage24
- u_307 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (307, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 25, 1, '0', 0, 0);
+ u_300 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (300, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_301 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (301, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 19, 1, '0');
+ u_302 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (302, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0'); -- = u_wpfb_stage20
+ u_303 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (303, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 21, 1, '0');
+ u_304 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (304, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
+ u_305 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (305, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 23, 1, '0'); -- = u_wpfb_stage23
+ u_306 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (306, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0'); -- = u_wpfb_stage24
+ u_307 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (307, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 25, 1, '0');
-- PFB2
- u_310 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (310, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 18, 0, '0', 0, 0);
- u_311 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (311, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 19, 0, '0', 0, 0);
- u_312 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (312, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0', 0, 0); -- = u_lofar1_14b
- u_313 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (313, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 21, 0, '0', 0, 0);
- u_314 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (314, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 22, 0, '0', 0, 0);
- u_315 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (315, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 23, 0, '0', 0, 0);
- u_316 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (316, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 24, 0, '0', 0, 0);
- u_317 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (317, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 25, 0, '0', 0, 0);
+ u_310 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (310, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 18, 0, '0');
+ u_311 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (311, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 19, 0, '0');
+ u_312 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (312, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0'); -- = u_lofar1_14b
+ u_313 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (313, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 21, 0, '0');
+ u_314 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (314, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 22, 0, '0');
+ u_315 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (315, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 23, 0, '0');
+ u_316 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (316, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 24, 0, '0');
+ u_317 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (317, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 25, 0, '0');
-- WPFB only FFT
- u_320 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (320, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_321 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (321, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 19, 1, '0', 0, 0);
- u_322 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (322, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 0);
- u_323 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (323, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 21, 1, '0', 0, 0);
- u_324 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (324, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 22, 1, '0', 0, 0);
- u_325 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (325, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 23, 1, '0', 0, 0);
- u_326 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (326, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 24, 1, '0', 0, 0);
- u_327 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (327, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 25, 1, '0', 0, 0);
+ u_320 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (320, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_321 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (321, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 19, 1, '0');
+ u_322 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (322, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 20, 1, '0');
+ u_323 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (323, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 21, 1, '0');
+ u_324 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (324, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 22, 1, '0');
+ u_325 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (325, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 23, 1, '0');
+ u_326 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (326, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 24, 1, '0');
+ u_327 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (327, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 25, 1, '0');
-- PFB2 only FFT
- u_330 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (330, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 18, 0, '0', 0, 0);
- u_331 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (331, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 19, 0, '0', 0, 0);
- u_332 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (332, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 20, 0, '0', 0, 0);
- u_333 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (333, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 21, 0, '0', 0, 0);
- u_334 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (334, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 22, 0, '0', 0, 0);
- u_335 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (335, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 23, 0, '0', 0, 0);
- u_336 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (336, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 24, 0, '0', 0, 0);
- u_337 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (337, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 25, 0, '0', 0, 0);
+ u_330 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (330, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 18, 0, '0');
+ u_331 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (331, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 19, 0, '0');
+ u_332 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (332, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 20, 0, '0');
+ u_333 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (333, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 21, 0, '0');
+ u_334 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (334, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 22, 0, '0');
+ u_335 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (335, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 23, 0, '0');
+ u_336 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (336, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 24, 0, '0');
+ u_337 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (337, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 25, 0, '0');
-- g_internal_dat_w = incrementing with g_fft_stage_dat_w
-- WPFB
- u_340 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (340, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_341 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (341, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 19, 1, '0', 0, 0);
- u_342 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (342, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 18, 0, 20, 1, '0', 0, 0);
- u_343 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (343, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 18, 0, 21, 1, '0', 0, 0);
- u_344 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (344, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 18, 0, 22, 1, '0', 0, 0);
- u_345 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (345, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 18, 0, 23, 1, '0', 0, 0);
- u_346 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (346, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 18, 0, 24, 1, '0', 0, 0);
- u_347 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (347, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 18, 0, 25, 1, '0', 0, 0);
+ u_340 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (340, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_341 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (341, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 19, 1, '0');
+ u_342 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (342, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 18, 0, 20, 1, '0');
+ u_343 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (343, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 18, 0, 21, 1, '0');
+ u_344 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (344, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 18, 0, 22, 1, '0');
+ u_345 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (345, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 18, 0, 23, 1, '0');
+ u_346 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (346, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 18, 0, 24, 1, '0');
+ u_347 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (347, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 18, 0, 25, 1, '0');
-- PFB2
- u_350 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (350, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 18, 0, '0', 0, 0);
- u_351 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (351, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 18, 0, 19, 0, '0', 0, 0);
- u_352 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (352, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 18, 0, 20, 0, '0', 0, 0);
- u_353 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (353, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 18, 0, 21, 0, '0', 0, 0);
- u_354 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (354, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 18, 0, 22, 0, '0', 0, 0);
- u_355 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (355, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 18, 0, 23, 0, '0', 0, 0);
- u_356 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (356, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 18, 0, 24, 0, '0', 0, 0);
- u_357 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (357, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 25, 18, 0, 25, 0, '0', 0, 0);
+ u_350 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (350, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 18, 0, '0');
+ u_351 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (351, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 18, 0, 19, 0, '0');
+ u_352 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (352, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 18, 0, 20, 0, '0');
+ u_353 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (353, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 18, 0, 21, 0, '0');
+ u_354 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (354, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 18, 0, 22, 0, '0');
+ u_355 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (355, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 18, 0, 23, 0, '0');
+ u_356 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (356, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 18, 0, 24, 0, '0');
+ u_357 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (357, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 25, 18, 0, 25, 0, '0');
-- Results:
-- Table A: PFB processing gain for increasing internal data width
@@ -475,37 +510,37 @@ END GENERATE;
gen_vary_g_fil_in_dat_w : IF c_gen_vary_g_fil_in_dat_w GENERATE
- u_400 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (400, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 8, 17, 18, 0, 20, 1, '0', 0, 0);
- u_401 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (401, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 9, 17, 18, 0, 20, 1, '0', 0, 0);
- u_402 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (402, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 10, 17, 18, 0, 20, 1, '0', 0, 0);
- u_403 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (403, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 11, 17, 18, 0, 20, 1, '0', 0, 0);
- u_404 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (404, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 12, 17, 18, 0, 20, 1, '0', 0, 0);
- u_405 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (405, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 13, 17, 18, 0, 20, 1, '0', 0, 0);
- u_406 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (406, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 0); -- u_wpfb_stage20
-
- u_410 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (410, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 8, 18, 18, 0, 20, 0, '0', 0, 0);
- u_411 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (411, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 9, 18, 18, 0, 20, 0, '0', 0, 0);
- u_412 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (412, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 10, 18, 18, 0, 20, 0, '0', 0, 0);
- u_413 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (413, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 11, 18, 18, 0, 20, 0, '0', 0, 0);
- u_414 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (414, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 12, 18, 18, 0, 20, 0, '0', 0, 0);
- u_415 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (415, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 13, 18, 18, 0, 20, 0, '0', 0, 0);
- u_416 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (416, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0', 0, 0); -- u_lofar1_14b
-
- u_420 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (420, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 8, 17, 18, 0, 20, 1, '0', 0, 0);
- u_421 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (421, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 9, 17, 18, 0, 20, 1, '0', 0, 0);
- u_422 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (422, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 10, 17, 18, 0, 20, 1, '0', 0, 0);
- u_423 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (423, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 11, 17, 18, 0, 20, 1, '0', 0, 0);
- u_424 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (424, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 12, 17, 18, 0, 20, 1, '0', 0, 0);
- u_425 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (425, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 13, 17, 18, 0, 20, 1, '0', 0, 0);
- u_426 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (426, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 0);
-
- u_430 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (430, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 8, 18, 18, 0, 20, 0, '0', 0, 0);
- u_431 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (431, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 9, 18, 18, 0, 20, 0, '0', 0, 0);
- u_432 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (432, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 10, 18, 18, 0, 20, 0, '0', 0, 0);
- u_433 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (433, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 11, 18, 18, 0, 20, 0, '0', 0, 0);
- u_434 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (434, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 12, 18, 18, 0, 20, 0, '0', 0, 0);
- u_435 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (435, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 13, 18, 18, 0, 20, 0, '0', 0, 0);
- u_436 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (436, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 20, 0, '0', 0, 0);
+ u_400 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (400, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 8, 17, 18, 0, 20, 1, '0');
+ u_401 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (401, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 9, 17, 18, 0, 20, 1, '0');
+ u_402 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (402, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 10, 17, 18, 0, 20, 1, '0');
+ u_403 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (403, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 11, 17, 18, 0, 20, 1, '0');
+ u_404 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (404, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 12, 17, 18, 0, 20, 1, '0');
+ u_405 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (405, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 13, 17, 18, 0, 20, 1, '0');
+ u_406 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (406, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0'); -- u_wpfb_stage20
+
+ u_410 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (410, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 8, 18, 18, 0, 20, 0, '0');
+ u_411 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (411, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 9, 18, 18, 0, 20, 0, '0');
+ u_412 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (412, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 10, 18, 18, 0, 20, 0, '0');
+ u_413 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (413, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 11, 18, 18, 0, 20, 0, '0');
+ u_414 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (414, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 12, 18, 18, 0, 20, 0, '0');
+ u_415 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (415, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 13, 18, 18, 0, 20, 0, '0');
+ u_416 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (416, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 20, 0, '0'); -- u_lofar1_14b
+
+ u_420 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (420, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 8, 17, 18, 0, 20, 1, '0');
+ u_421 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (421, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 9, 17, 18, 0, 20, 1, '0');
+ u_422 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (422, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 10, 17, 18, 0, 20, 1, '0');
+ u_423 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (423, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 11, 17, 18, 0, 20, 1, '0');
+ u_424 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (424, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 12, 17, 18, 0, 20, 1, '0');
+ u_425 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (425, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 13, 17, 18, 0, 20, 1, '0');
+ u_426 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (426, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 20, 1, '0');
+
+ u_430 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (430, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 8, 18, 18, 0, 20, 0, '0');
+ u_431 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (431, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 9, 18, 18, 0, 20, 0, '0');
+ u_432 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (432, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 10, 18, 18, 0, 20, 0, '0');
+ u_433 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (433, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 11, 18, 18, 0, 20, 0, '0');
+ u_434 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (434, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 12, 18, 18, 0, 20, 0, '0');
+ u_435 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (435, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 13, 18, 18, 0, 20, 0, '0');
+ u_436 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (436, "PFB2", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 18, 18, 0, 20, 0, '0');
-- Results:
-- The table B) shows the processing gain for different internal ADC input width between 8b and 14b. Conclusions:
@@ -527,13 +562,13 @@ END GENERATE;
-- 2021_jan_11
gen_vary_g_amplitude_a : IF c_gen_vary_g_amplitude_a GENERATE
- u_760 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (760, "WPFB", 61.0, 61.0, 1.0 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18, 1.0
- u_761 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (761, "WPFB", 61.0, 61.0, 0.5 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_762 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (762, "WPFB", 61.0, 61.0, 0.25 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_763 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (763, "WPFB", 61.0, 61.0, 0.125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_764 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (764, "WPFB", 61.0, 61.0, 0.0625 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_765 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (765, "WPFB", 61.0, 61.0, 0.03125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
- u_766 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (766, "WPFB", 61.0, 61.0, 0.015625, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- = u_wpfb_stage18
+ u_760 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (760, "WPFB", 61.0, 61.0, 1.0 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18, 1.0
+ u_761 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (761, "WPFB", 61.0, 61.0, 0.5 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_762 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (762, "WPFB", 61.0, 61.0, 0.25 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_763 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (763, "WPFB", 61.0, 61.0, 0.125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_764 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (764, "WPFB", 61.0, 61.0, 0.0625 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_765 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (765, "WPFB", 61.0, 61.0, 0.03125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_766 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (766, "WPFB", 61.0, 61.0, 0.015625, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
--Results:
--tb-761 . wpfb_measured_proc_gain_a_dB = 6.11 [dB]
--tb-762 . wpfb_measured_proc_gain_a_dB = 6.15 [dB]
@@ -547,8 +582,8 @@ END GENERATE;
gen_vary_c_twiddle_w : IF c_gen_vary_c_twiddle_w GENERATE
-- WPFB only FFT
- u_0 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (0, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 22, 1, '0', 0, 0); -- = u_324
- u_1 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 24, 1, '0', 0, 0); -- = u_326
+ u_0 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (0, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_324
+ u_1 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (1, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 24, 1, '0'); -- = u_326
-- Rerun the simulation per c_twiddle_w setting ## by first manually doing:
-- > cp libraries/dsp/rTwoSDF/src/vhdl/pkg/twiddlesPkg_w##.vhd libraries/dsp/rTwoSDF/src/vhdl/twiddlesPkg.vhd
@@ -571,82 +606,6 @@ END GENERATE;
gen_vary_extra_w : IF c_gen_vary_extra_w GENERATE
- u_900 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (900, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 0); -- u_wpfb_stage18
- u_901 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (901, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 1, 0);
- u_902 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (902, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 0, 1);
- u_903 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (903, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 1, 1);
-
- u_910 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (910, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 0); -- u_wpfb_stage20
- u_911 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (911, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 1, 0);
- u_912 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (912, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 1);
- u_913 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (913, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 1, 1);
-
- u_920 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (920, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0', 0, 0); -- u_wpfb_stage22
- u_921 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (921, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0', 1, 0);
- u_922 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (922, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0', 0, 1);
- u_923 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (923, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0', 1, 1);
-
- u_930 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (930, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0', 0, 0); -- u_wpfb_stage24
- u_931 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (931, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0', 1, 0);
- u_932 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (932, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0', 0, 1);
- u_933 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (933, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 24, 1, '0', 1, 1);
---Results:
--- g_fft_stage_dat_w
--- . g_r2_mul_extra_w
--- . . g_sepa_extra_w
--- . . .
---tb-900 18, 0, 0 . wpfb_measured_proc_gain_a_dB = 6.11 [dB] -- u_wpfb_stage18
--- 1, 0 . 6.09 [dB]
---tb-901 18, 2, 0 . 6.53 [dB]
---
--- 0, 0 . wpfb_measured_proc_gain_a_dB = 6.11 [dB] -- u_wpfb_stage18
--- 0, 1 . 5.09 [dB]
---tb-902 18, 0, 2 . 5.26 [dB]
---
--- 0, 0 . wpfb_measured_proc_gain_a_dB = 6.11 [dB] -- u_wpfb_stage18
--- 1, 1 . 6.09 [dB]
---tb-903 18, 2, 2 . 6.53 [dB]
--- 3, 3 . 6.70 [dB]
---
---tb-910 20, 0, 0 . wpfb_measured_proc_gain_a_dB = 12.38 [dB] -- u_wpfb_stage20
--- 1, 0 . 12.31 [dB]
---tb-911 20, 2, 0 . 12.35 [dB]
---
--- 0, 0 . wpfb_measured_proc_gain_a_dB = 12.38 [dB] -- u_wpfb_stage20
--- 0, 1 . 13.42 [dB]
---tb-912 20, 0, 2 . 13.42 [dB]
---
--- 0, 0 . wpfb_measured_proc_gain_a_dB = 12.38 [dB] -- u_wpfb_stage20
--- 1, 1 . 14.49 [dB]
---tb-913 20, 2, 2 . 14.62 [dB]
--- 3, 3 . 14.97 [dB]
---
---tb-920 22, 0, 0 . wpfb_measured_proc_gain_a_dB = 18.79 [dB] -- u_wpfb_stage22
--- 1, 0 . 18.97 [dB]
---tb-921 22, 2, 0 . 19.20 [dB]
---
--- 0, 0 . wpfb_measured_proc_gain_a_dB = 18.79 [dB] -- u_wpfb_stage22
--- 0, 1 . 18.97 [dB]
---tb-922 22, 0, 2 . 18.97 [dB]
---
--- 0, 0 . wpfb_measured_proc_gain_a_dB = 18.79 [dB] -- u_wpfb_stage22
--- 1, 1 . 19.59 [dB]
---tb-923 22, 2, 2 . 19.52 [dB]
--- 3, 3 . 19.59 [dB]
---
---tb-930 24, 0, 0 . wpfb_measured_proc_gain_a_dB = 20.08 [dB] -- u_wpfb_stage24
--- 1, 0 . 20.08 [dB]
---tb-931 24, 2, 0 . 20.08 [dB]
---
--- 0, 0 . wpfb_measured_proc_gain_a_dB = 20.08 [dB] -- u_wpfb_stage24
--- 0, 1 . 20.16 [dB]
---tb-932 24, 0, 2 . 20.16 [dB]
---
--- 0, 0 . wpfb_measured_proc_gain_a_dB = 20.08 [dB] -- u_wpfb_stage24
--- 1, 1 . 20.31 [dB]
---tb-933 24, 2, 2 . 20.23 [dB]
--- 3, 3 . 20.23 [dB]
---
--Conclusion:
--* If g_fft_stage_dat_w is large enough (~=> 24), then using extra_w has no benefit (as expected)
--* Combination of using both g_r2_mul_extra_w and g_sepa_extra_w has most benefit, for
@@ -660,40 +619,293 @@ END GENERATE;
gen_2020_dec : IF c_gen_2020_dec GENERATE
-- g_internal_dat_w = g_fft_stage_dat_w - g_fft_guard_w
-- g_fft_out_dat_w = 18
- u_800 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (800, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0', 2, 2);
- u_801 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (801, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 19, 1, '0', 2, 2);
- u_802 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (802, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 18, 0, 20, 1, '0', 2, 2);
- u_803 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (803, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 18, 0, 21, 1, '0', 2, 2);
- u_804 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (804, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 18, 0, 22, 1, '0', 2, 2);
- u_805 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (805, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 18, 0, 23, 1, '0', 2, 2);
- u_806 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (806, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 18, 0, 24, 1, '0', 2, 2);
- u_807 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (807, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 18, 0, 25, 1, '0', 2, 2);
- u_808 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (808, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 25, 18, 0, 26, 1, '0', 2, 2);
- u_809 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (809, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 26, 18, 0, 27, 1, '0', 2, 2);
+ u_800 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (800, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0');
+ u_801 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (801, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 18, 0, 19, 1, '0');
+ u_802 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (802, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 18, 0, 20, 1, '0');
+ u_803 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (803, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 18, 0, 21, 1, '0');
+ u_804 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (804, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 18, 0, 22, 1, '0');
+ u_805 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (805, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 18, 0, 23, 1, '0');
+ u_806 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (806, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 18, 0, 24, 1, '0');
+ u_807 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (807, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 18, 0, 25, 1, '0');
+ u_808 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (808, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 25, 18, 0, 26, 1, '0');
+ u_809 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (809, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 26, 18, 0, 27, 1, '0');
-- g_fft_out_dat_w = 19
- u_810 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (810, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 19, 0, 18, 1, '0', 2, 2);
- u_811 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (811, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 19, 0, 19, 1, '0', 2, 2);
- u_812 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (812, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 19, 0, 20, 1, '0', 2, 2);
- u_813 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (813, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 19, 0, 21, 1, '0', 2, 2);
- u_814 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (814, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 19, 0, 22, 1, '0', 2, 2);
- u_815 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (815, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 19, 0, 23, 1, '0', 2, 2);
- u_816 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (816, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 19, 0, 24, 1, '0', 2, 2);
- u_817 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (817, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 19, 0, 25, 1, '0', 2, 2);
- u_818 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (818, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 25, 19, 0, 26, 1, '0', 2, 2);
- u_819 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (819, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 26, 19, 0, 27, 1, '0', 2, 2);
+ u_810 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (810, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 19, 0, 18, 1, '0');
+ u_811 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (811, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 19, 0, 19, 1, '0');
+ u_812 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (812, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 19, 0, 20, 1, '0');
+ u_813 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (813, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 19, 0, 21, 1, '0');
+ u_814 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (814, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 19, 0, 22, 1, '0');
+ u_815 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (815, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 19, 0, 23, 1, '0');
+ u_816 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (816, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 19, 0, 24, 1, '0');
+ u_817 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (817, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 19, 0, 25, 1, '0');
+ u_818 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (818, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 25, 19, 0, 26, 1, '0');
+ u_819 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (819, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 26, 19, 0, 27, 1, '0');
-- g_fft_out_dat_w = 20
- u_820 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (820, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 20, 0, 18, 1, '0', 2, 2);
- u_821 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (821, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 20, 0, 19, 1, '0', 2, 2);
- u_822 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (822, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 20, 0, 20, 1, '0', 2, 2);
- u_823 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (823, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 20, 0, 21, 1, '0', 2, 2);
- u_824 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (824, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 20, 0, 22, 1, '0', 2, 2);
- u_825 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (825, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 20, 0, 23, 1, '0', 2, 2);
- u_826 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (826, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 20, 0, 24, 1, '0', 2, 2);
- u_827 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (827, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 20, 0, 25, 1, '0', 2, 2);
- u_828 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (828, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 25, 20, 0, 26, 1, '0', 2, 2);
- u_829 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (829, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 26, 20, 0, 27, 1, '0', 2, 2);
+ u_820 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (820, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 20, 0, 18, 1, '0');
+ u_821 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (821, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 18, 20, 0, 19, 1, '0');
+ u_822 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (822, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 19, 20, 0, 20, 1, '0');
+ u_823 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (823, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 20, 20, 0, 21, 1, '0');
+ u_824 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (824, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 21, 20, 0, 22, 1, '0');
+ u_825 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (825, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 22, 20, 0, 23, 1, '0');
+ u_826 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (826, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 23, 20, 0, 24, 1, '0');
+ u_827 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (827, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 24, 20, 0, 25, 1, '0');
+ u_828 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (828, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 25, 20, 0, 26, 1, '0');
+ u_829 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (829, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 26, 20, 0, 27, 1, '0');
END GENERATE;
-
+
+gen_2022_mar_21 : IF c_gen_2022_mar GENERATE
+ -- WPFB
+ -- g_fil_coefs_file_prefix
+ -- . g_fil_coef_dat_w
+ -- . . g_fil_backoff_w
+ -- . . . g_fil_in_dat_w
+ -- . . . . g_internal_dat_w
+ -- . . . . . g_fft_out_dat_w
+ -- . . . . . . g_fft_out_gain_w
+ -- . . . . . . . g_fft_stage_dat_w
+ -- . . . . . . . . g_fft_guard_w
+ -- . . . . . . . . . g_switch_en
+ -- . . . . . . . . . .
+ -- vary g_fft_out_dat_w
+ --u_2000 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2000, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 24, 1, '0');
+ --u_2001 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2001, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 24, 1, '0');
+ --u_2002 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2002, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 20, 1, 24, 1, '0');
+ --u_2003 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2003, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 0, 24, 1, '0');
+ --u_2004 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2004, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 0, 24, 1, '0');
+ --u_2005 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2005, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 20, 0, 24, 1, '0');
+ --u_2006 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2006, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 0, 18, 0, 24, 1, '0');
+ --u_2007 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2007, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 0, 19, 0, 24, 1, '0');
+ --u_2008 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2008, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 0, 20, 0, 24, 1, '0');
+
+ -- vary g_fft_stage_dat_w using c_fil_coefs or c_fil_nodc, c_fil_hanning_16b
+ --u_2010 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2010, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_16b, 16, 1, 14, 0, 19, 1, 22, 1, '0');
+ --u_2011 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2011, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_16b, 16, 1, 14, 0, 19, 1, 23, 1, '0');
+ --u_2012 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2012, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_16b, 16, 1, 14, 0, 19, 1, 24, 1, '0'); -- ~= 2001
+ --u_2013 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2013, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_16b, 16, 1, 14, 0, 19, 1, 25, 1, '0');
+ --u_2014 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2014, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_16b, 16, 1, 14, 0, 19, 1, 26, 1, '0');
+ --u_2015 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2015, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_16b, 16, 1, 14, 0, 19, 1, 27, 1, '0');
+ --u_2016 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2016, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_16b, 16, 0, 14, 0, 19, 0, 25, 1, '0');
+ --u_2017 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2017, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_16b, 16, 0, 14, 0, 19, 0, 26, 1, '0');
+ --
+ --c_wpfb_lofar2_subbands_dts_18b and c_twiddle_w = 20:
+ --u_2070 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2070, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 22, 1, '0');
+ --u_2071 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2071, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 23, 1, '0');
+ --u_2072 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2072, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 24, 1, '0'); -- = 2000
+ --u_2073 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2073, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 25, 1, '0');
+ --u_2074 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2074, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 26, 1, '0');
+ --u_2075 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2075, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 18, 1, 27, 1, '0');
+ --
+ --c_wpfb_lofar2_subbands_dts_19b and c_twiddle_w = 20:
+ --u_2080 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2080, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 22, 1, '0');
+ --u_2081 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2081, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 23, 1, '0');
+ --u_2082 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2082, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 24, 1, '0'); -- = 2001
+ --u_2083 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2083, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 25, 1, '0');
+ --u_2084 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2084, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 26, 1, '0');
+ --u_2085 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2085, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 27, 1, '0');
+ --
+ --g_fft_out_dat_w = 20 and c_twiddle_w = 20:
+ --u_2090 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2090, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 20, 1, 22, 1, '0');
+ --u_2091 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2091, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 20, 1, 23, 1, '0');
+ --u_2092 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2092, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 20, 1, 24, 1, '0'); -- ~= 2001
+ --u_2093 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2093, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 20, 1, 25, 1, '0');
+ --u_2094 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2094, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 20, 1, 26, 1, '0');
+ --u_2095 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2095, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 20, 1, 27, 1, '0');
+ --
+ --g_fft_out_dat_w = 19 and c_twiddle_w = 20:
+ --u_2100 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2100, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 12, 0, 19, 1, 22, 1, '0');
+ --u_2101 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2101, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 13, 0, 19, 1, 23, 1, '0');
+ --u_2102 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2102, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 24, 1, '0'); -- = 2001
+ --u_2103 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2103, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 15, 0, 19, 1, 25, 1, '0');
+ --u_2104 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2104, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 16, 0, 19, 1, 26, 1, '0');
+ --u_2105 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2105, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 17, 0, 19, 1, 27, 1, '0');
+ --
+ --u_2030 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2030, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_18b, 18, 1, 14, 0, 19, 1, 22, 1, '0');
+ --u_2031 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2031, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_18b, 18, 1, 14, 0, 19, 1, 23, 1, '0');
+ --u_2032 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2032, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_18b, 18, 1, 14, 0, 19, 1, 24, 1, '0'); -- ~= 2001
+ --u_2033 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2033, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_18b, 18, 1, 14, 0, 19, 1, 25, 1, '0');
+ --u_2034 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2034, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_18b, 18, 1, 14, 0, 19, 1, 26, 1, '0');
+ --u_2035 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2035, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_18b, 18, 1, 14, 0, 19, 1, 27, 1, '0');
+
+ --u_2040 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2040, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_16b, 16, 1, 14, 0, 19, 1, 22, 1, '0');
+ --u_2041 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2041, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_16b, 16, 1, 14, 0, 19, 1, 23, 1, '0');
+ --u_2042 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2042, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_16b, 16, 1, 14, 0, 19, 1, 24, 1, '0'); -- ~= 2001
+ --u_2043 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2043, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_16b, 16, 1, 14, 0, 19, 1, 25, 1, '0');
+ --u_2044 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2044, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_16b, 16, 1, 14, 0, 19, 1, 26, 1, '0');
+ --u_2045 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2045, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_16b, 16, 1, 14, 0, 19, 1, 27, 1, '0');
+
+ --u_2050 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2050, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_18b, 18, 1, 14, 0, 19, 1, 22, 1, '0');
+ --u_2051 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2051, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_18b, 18, 1, 14, 0, 19, 1, 23, 1, '0');
+ --u_2052 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2052, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_18b, 18, 1, 14, 0, 19, 1, 24, 1, '0'); -- ~= 2001
+ --u_2053 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2053, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_18b, 18, 1, 14, 0, 19, 1, 25, 1, '0');
+ --u_2054 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2054, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_18b, 18, 1, 14, 0, 19, 1, 26, 1, '0');
+ --u_2055 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2055, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_kaiser_18b, 18, 1, 14, 0, 19, 1, 27, 1, '0');
+
+ --u_2060 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2060, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_20b, 20, 1, 14, 0, 19, 1, 22, 1, '0');
+ --u_2061 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2061, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_20b, 20, 1, 14, 0, 19, 1, 23, 1, '0');
+ --u_2062 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2062, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_20b, 20, 1, 14, 0, 19, 1, 24, 1, '0'); -- ~= 2001
+ --u_2063 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2063, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_20b, 20, 1, 14, 0, 19, 1, 25, 1, '0');
+ --u_2064 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2064, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_20b, 20, 1, 14, 0, 19, 1, 26, 1, '0');
+ --u_2065 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2065, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_hanning_20b, 20, 1, 14, 0, 19, 1, 27, 1, '0');
+
+ -- vary g_fil_in_dat_w
+ --u_2020 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2020, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 8, 0, 19, 1, 24, 1, '0');
+ --u_2021 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2021, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 9, 0, 19, 1, 24, 1, '0');
+ --u_2022 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2022, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 10, 0, 19, 1, 24, 1, '0');
+ --u_2023 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2023, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 11, 0, 19, 1, 24, 1, '0');
+ --u_2024 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2024, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 12, 0, 19, 1, 24, 1, '0');
+ --u_2025 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2025, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 13, 0, 19, 1, 24, 1, '0');
+ --u_2026 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2026, "WPFB", 59.0, 59.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 24, 1, '0'); -- = 2001
+ --u_2027 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2027, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 15, 0, 19, 1, 24, 1, '0');
+
+
+-- Results:
+-- c_twiddle_w = 18
+-- g_fil_backoff_w = 1
+-- g_fft_out_dat_w g_fft_out_gain_w
+-- . g_stage_dat_w 1 0
+-- . . . .
+-- 18 24 : wpfb_measured_proc_gain_a_dB = 20.04 [dB] 17.38 [dB]
+-- 19 24 : wpfb_measured_proc_gain_a_dB = 18.53 [dB] 20.04 [dB]
+-- 20 24 : wpfb_measured_proc_gain_a_dB = 18.79 [dB] 18.53 [dB]
+--
+-- c_twiddle_w = 18
+-- g_fil_backoff_w = g_fft_out_gain_w = 0
+-- g_fft_out_dat_w
+-- . g_stage_dat_w
+-- . .
+-- 18 24 : wpfb_measured_proc_gain_a_dB = 20.16 [dB]
+-- 19 24 : wpfb_measured_proc_gain_a_dB = 19.02 [dB]
+-- 19 25 : wpfb_measured_proc_gain_a_dB = 19.14 [dB]
+-- 19 26 : wpfb_measured_proc_gain_a_dB = 19.23 [dB]
+-- 20 24 : wpfb_measured_proc_gain_a_dB = 19.26 [dB]
+--
+-- c_fil_coefs
+-- c_twiddle_w = 18
+-- g_fil_backoff_w = g_fft_out_gain_w = 1
+-- g_fft_out_dat_w = 19
+-- c_fil_coefs c_fil_nodc c_fil_coefs
+-- g_stage_dat_w c_twiddle_w: 18 18 20
+-- . . . .
+-- 22 : wpfb_measured_proc_gain_a_dB = 16.62 [dB] 22.20 [dB] 16.66 [dB]
+-- 23 : wpfb_measured_proc_gain_a_dB = 17.85 [dB] 23.87 [dB] 18.01 [dB]
+-- 24 : wpfb_measured_proc_gain_a_dB = 18.53 [dB] 24.76 [dB] 18.50 [dB]
+-- 25 : wpfb_measured_proc_gain_a_dB = 19.02 [dB] 25.22 [dB] 19.02 [dB]
+-- 26 : wpfb_measured_proc_gain_a_dB = 19.14 [dB] 25.64 [dB] 19.12 [dB]
+-- 27 : wpfb_measured_proc_gain_a_dB = 19.23 [dB] 25.78 [dB] 19.28 [dB]
+--
+-- c_fil_coefs
+-- c_twiddle_w = 20
+-- g_fil_backoff_w = g_fft_out_gain_w = 1
+-- g_stage_dat_w g_fft_out_dat_w = 18 19 20
+-- .
+-- 22 : wpfb_measured_proc_gain_a_dB = 17.09 [dB] 16.66 [dB] 16.73 [dB]
+-- 23 : wpfb_measured_proc_gain_a_dB = 19.39 [dB] 18.01 [dB] 18.06 [dB]
+-- 24 : wpfb_measured_proc_gain_a_dB = 20.12 [dB] 18.50 [dB] 18.77 [dB]
+-- 25 : wpfb_measured_proc_gain_a_dB = 20.23 [dB] 19.02 [dB] 19.25 [dB]
+-- 26 : wpfb_measured_proc_gain_a_dB = 20.23 [dB] 19.12 [dB] 19.38 [dB]
+-- 27 : wpfb_measured_proc_gain_a_dB = 20.31 [dB] 19.28 [dB] 19.43 [dB]
+--
+-- c_fil_coefs
+-- c_twiddle_w = 20
+-- g_fil_backoff_w = g_fft_out_gain_w = 1
+-- g_stage_dat_w = 24
+-- g_fft_out_dat_w = 19
+-- g_fil_in_dat_w
+-- .
+-- 12 . wpfb_measured_proc_gain_a_dB = 24.74 [dB]
+-- 13 . wpfb_measured_proc_gain_a_dB = 22.09 [dB]
+-- 14 . wpfb_measured_proc_gain_a_dB = 18.50 [dB]
+-- 15 . wpfb_measured_proc_gain_a_dB = 13.36 [dB] +6.02 = 19.38
+-- 16 . wpfb_measured_proc_gain_a_dB = 7.55 [dB] +12.04 = 19.59
+-- 17 . wpfb_measured_proc_gain_a_dB = 3.00 [dB] +18.06 = 21.06
+--
+-- c_twiddle_w =18 c_fil_ c_fil_ c_fil_ c_fil_ c_fil_
+-- g_stage_dat_w c_fil_coefs hanning_16b hanning_18b hanning_20b kaiser_16b kaiser_18b
+-- . . . . . . .
+-- 22 : wpfb_measured_proc_gain_a_dB = 16.62 [dB] 19.72 [dB] 21.57 [dB] 21.99 [dB] 16.40 [dB] 17.17 [dB]
+-- 23 : wpfb_measured_proc_gain_a_dB = 17.85 [dB] 22.23 [dB] 23.72 [dB] 23.85 [dB] 17.47 [dB] 17.91 [dB]
+-- 24 : wpfb_measured_proc_gain_a_dB = 18.53 [dB] 23.61 [dB] 24.56 [dB] 24.77 [dB] 18.01 [dB] 18.30 [dB]
+-- 25 : wpfb_measured_proc_gain_a_dB = 19.02 [dB] 24.58 [dB] 25.18 [dB] 25.34 [dB] 18.51 [dB] 18.56 [dB]
+-- 26 : wpfb_measured_proc_gain_a_dB = 19.14 [dB] 24.75 [dB] 25.37 [dB] 25.70 [dB] 18.91 [dB] 18.66 [dB]
+-- 27 : wpfb_measured_proc_gain_a_dB = 19.23 [dB] 24.86 [dB] 25.37 [dB] 25.77 [dB] 18.89 [dB] 18.81 [dB]
+--
+-- c_twiddle_w = 18
+-- g_stage_dat_w
+-- . g_fft_out_dat_w = 19 18
+-- 23 : wpfb_measured_proc_gain_a_dB = 16.62 [dB] 17.17 [dB]
+-- 24 : wpfb_measured_proc_gain_a_dB = 17.85 [dB] 19.33 [dB]
+-- 25 : wpfb_measured_proc_gain_a_dB = 18.53 [dB] 20.04 [dB]
+-- 26 : wpfb_measured_proc_gain_a_dB = 19.02 [dB] 20.16 [dB]
+-- 27 : wpfb_measured_proc_gain_a_dB = 19.14 [dB] 20.27 [dB]
+-- 22 : wpfb_measured_proc_gain_a_dB = 19.23 [dB] 20.39 [dB]
+--
+-- c_twiddle_w = 18
+-- g_fil_backoff_w = 1
+-- g_fft_out_gain_w = 1
+-- g_fft_out_dat_w = 19
+-- g_stage_dat_w = 24
+-- g_fil_in_dat_w
+-- .
+-- 8 : wpfb_measured_proc_gain_a_dB = 27.08 [dB] -- theoretical 20log10(sqrt(512)) = 27.1 dB
+-- 9 : wpfb_measured_proc_gain_a_dB = 27.00 [dB]
+-- 10 : wpfb_measured_proc_gain_a_dB = 26.93 [dB]
+-- 11 : wpfb_measured_proc_gain_a_dB = 26.65 [dB]
+-- 12 : wpfb_measured_proc_gain_a_dB = 25.77 [dB]
+-- 13 : wpfb_measured_proc_gain_a_dB = 22.73 [dB]
+-- 14 : wpfb_measured_proc_gain_a_dB = 18.53 [dB] -- 61.0
+-- 14 : wpfb_measured_proc_gain_a_dB = 18.70 [dB] -- 59.0
+-- 15 : wpfb_measured_proc_gain_a_dB = 12.70 [dB]
+--
+-- Conclusion:
+-- . Choose c_twiddle_w = 20 b >= g_fft_out_dat_w = 18 or 19 b (see
+-- c_gen_vary_c_twiddle_w): The M20K is 20b and multipliers have 27b.
+-- Synthesis shows that using c_twiddle_w = 20b costs no extra M20K or
+-- multipliers.
+-- . g_fil_coef_dat_w = 16b: The LOFAR1 FIR coefficients are fixed 16b, which
+-- is sufficient for the required stop band attenuation of 89 dB, because 16
+-- 6.02 dB/bit = 96 dB.
+-- . Use g_fil_backoff_w = 1 to fit temporary overshoot of FIR filter of about
+-- 10 %.
+-- . Use g_fft_out_gain_w = 1 to compensate for g_fil_backoff_w = 1.
+-- . Use g_fft_guard_w to compensate for FFT first stage gain > 2 (I think 1 +
+-- sqrt(2) ~= 2.41). Default g_fft_guard_w = 2 would be needed and the FFT
+-- then does not scale in its last 2 stages to ensure that the total reponse
+-- of the FFT remains unit. With g_fil_backoff_w = 1 and an FIR filter
+-- overshoot of about 10 % (is factor 1.1) using g_fft_guard_w = 1 is
+-- sufficient, because 1.1 * 2.41 < 2**2 = 4.
+-- . wpfb_measured_proc_gain_a_dB is limited by:
+-- . stop band attenuation
+-- . FIR quantisation noise floor level
+-- . DC response not exactly the same for each of the N_fft polyphases, this
+-- shows as a ripple in fil_noise_a, which is the difference between the
+-- FIR filter output and a matching sine wave. This variation in FIR filter
+-- output during a FFT block then cause leakage into other bins and thus a
+-- reduction in PFB processing gain compared to FFT processing gain.
+-- However the PFB does provide the required stop band attenuation, so the
+-- limited processing gain is probably due to the allowed stop band ripple
+-- of the FIR filter. Therefore I think the limited processing gain is not
+-- an issue or bug.
+-- . g_fft_out_dat_w = 19b is needed to accomodate g_fil_in_dat_w = 14 b +
+-- log2(sqrt(N_sub)) = 4.5 bit processing gain.
+-- . It is strange that wpfb_measured_proc_gain_a_dB is 20.12 [dB] for 18b
+-- and only 18.50 [dB] for 19b, but this may be due to the WG stimuli and
+-- related quantisation noise. Instead it would have been better to use a
+-- REAL SIN generator and REAL gaussian noise as signal input, to avoid
+-- WG artefacts.
+-- . g_stage_dat_w:
+-- . 27b is maximum for DSP multipliers, but does require extra logic and
+-- some BRAM
+-- . in LOFAR1 g_stage_dat_w = 20b with W_adc = 12b, so for LOFAR2.0 with
+-- W_adc = 14b the g_stage_dat_w >= 22b
+-- . 24b or 25b seems a good compromise for wpfb_measured_proc_gain_a_dB.
+-- . Given a WG amplitude of A_wg the expected subband phasor amplitude will be:
+-- A_sub = A_wg * func_wpfb_subband_gain(c_wpfb, fir_filter_dc_gain)
+-- The expected SST level for an integration interval of N_int subband blocks
+-- is then:
+-- SST = func_wpfb_sst_level(A_sub, N_blk)
+
+END GENERATE;
+
END tb;
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
index 28d0ddade877cb6a4a938ba8d00a2267e335d4c5..1d46215a1a3ab228128cffe664a713fd3a7a2727 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
@@ -10644,3 +10644,6089 @@ Table C: PFB processing gain for APERTIF WPFB quick improvements
-- u_4 : ENTITY work.tb_verify_pfb_wg GENERIC MAP ( 4, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 0, 0);
-- u_5 : ENTITY work.tb_verify_pfb_wg GENERIC MAP ( 5, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 2, 0);
-- u_6 : ENTITY work.tb_verify_pfb_wg GENERIC MAP ( 6, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 20, 1, '0', 2, 2);
+
+
+
+c_gen_2022_mar_21
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2000:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -65196
+# . sub_a_ampl = 65196.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250518416.000 = 96.28 [dB]
+# . sst_noise_a = 0.113 = -9.49 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.77 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.12 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2001:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.654 = -1.85 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.15 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.50 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2002:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -260783
+# . sub_a_ampl = 260783.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 6
+# . sub_a_ampl_frac = 6.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68007773089.000 = 108.33 [dB]
+# . sst_noise_a = 2.455 = 3.90 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.43 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.77 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2010:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -521520.000
+# . fir_max_a = 521520.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 521566.787
+# . fil_ampl_a = 521566.783
+# . sub_a_re = 0
+# . sub_a_im = -130393
+# . sub_a_ampl = 130393.000
+# . sub_a_re_frac = -1
+# . sub_a_im_frac = 4
+# . sub_a_ampl_frac = 4.123
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002334449.000 = 102.31 [dB]
+# . sst_noise_a = 0.998 = -0.01 [dB]
+# . sst_noise_b = 0.003 = -25.32 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 102.31 [dB]
+# . wpfb_measured_proc_gain_a_dB = 16.66 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2011:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1043041.000
+# . fir_max_a = 1043041.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1043133.576
+# . fil_ampl_a = 1043133.568
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.731 = -1.36 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 103.67 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.01 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2012:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.654 = -1.85 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.15 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.50 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2013:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.579 = -2.37 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.68 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.02 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2014:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344325.000
+# . fir_max_a = 8344325.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345068.660
+# . fil_ampl_a = 8345068.596
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.567 = -2.47 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.77 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.12 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2015:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688651.000
+# . fir_max_a = 16688651.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690137.335
+# . fil_ampl_a = 16690137.208
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.546 = -2.63 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 104.93 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.28 [dB]
+#
+
+
+xxxx
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2000:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -65195
+# . sub_a_ampl = 65195.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250388025.000 = 96.28 [dB]
+# . sst_noise_a = 0.114 = -9.41 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.70 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.04 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2001:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.650 = -1.87 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.18 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.53 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2002:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -260781
+# . sub_a_ampl = 260781.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 6
+# . sub_a_ampl_frac = 6.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68006729961.000 = 108.33 [dB]
+# . sst_noise_a = 2.445 = 3.88 [dB]
+# . sst_noise_b = 0.038 = -14.18 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.44 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.79 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2003:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -32598
+# . sub_a_ampl = 32598.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 1062629604.000 = 90.26 [dB]
+# . sst_noise_a = 0.053 = -12.77 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 103.03 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.38 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2004:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -65195
+# . sub_a_ampl = 65195.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250388025.000 = 96.28 [dB]
+# . sst_noise_a = 0.114 = -9.41 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.70 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.04 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2005:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.650 = -1.87 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.18 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.53 [dB]
+#
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2010:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -521520.000
+# . fir_max_a = 521520.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 521566.787
+# . fil_ampl_a = 521566.783
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_re_frac = -1
+# . sub_a_im_frac = 4
+# . sub_a_ampl_frac = 4.123
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 1.008 = 0.03 [dB]
+# . sst_noise_b = 0.023 = -16.29 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 102.27 [dB]
+# . wpfb_measured_proc_gain_a_dB = 16.62 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2011:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1043041.000
+# . fir_max_a = 1043041.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1043133.576
+# . fil_ampl_a = 1043133.568
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.759 = -1.20 [dB]
+# . sst_noise_b = 0.011 = -19.68 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 103.50 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.85 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2012:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.650 = -1.87 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.18 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.53 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2013:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.580 = -2.36 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.67 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.02 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2014:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344325.000
+# . fir_max_a = 8344325.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345068.660
+# . fil_ampl_a = 8345068.596
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.564 = -2.49 [dB]
+# . sst_noise_b = 0.001 = -30.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.80 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.14 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2015:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688651.000
+# . fir_max_a = 16688651.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690137.335
+# . fil_ampl_a = 16690137.208
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.553 = -2.57 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 104.88 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.23 [dB]
+#
+
+
+# . wpfb_measured_proc_gain_a_dB = 16.62 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.85 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.53 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.02 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.14 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.23 [dB]
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2006:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 0
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -65195
+# . sub_a_ampl = 65195.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250388025.000 = 96.28 [dB]
+# . sst_noise_a = 0.112 = -9.53 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.81 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.16 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2007:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 0
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.580 = -2.36 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.67 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.02 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2008:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 0
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -260780
+# . sub_a_ampl = 260780.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 6
+# . sub_a_ampl_frac = 6.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68006208400.000 = 108.33 [dB]
+# . sst_noise_a = 2.193 = 3.41 [dB]
+# . sst_noise_b = 0.037 = -14.30 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.92 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.26 [dB]
+#
+
+
+# . wpfb_measured_proc_gain_a_dB = 20.16 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.02 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.26 [dB]
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2016:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 0
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344325.000
+# . fir_max_a = 8344325.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345068.660
+# . fil_ampl_a = 8345068.596
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.564 = -2.49 [dB]
+# . sst_noise_b = 0.001 = -30.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.80 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.14 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2017:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 0
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688651.000
+# . fir_max_a = 16688651.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690137.335
+# . fil_ampl_a = 16690137.208
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.553 = -2.57 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 104.88 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.23 [dB]
+#
+
+# . wpfb_measured_proc_gain_a_dB = 19.14 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.23 [dB]
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2020:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 8
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -127.000
+# . input_max_a = 127.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2071243.000
+# . fir_max_a = 2071243.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 127
+# . input_ampl_a = 127.893
+# . cw_ampl_a = 127.893
+# . fir_ampl_a = 2084545.754
+# . fil_ampl_a = 2084531.396
+# . sub_a_re = 0
+# . sub_a_im = -130282
+# . sub_a_ampl = 130282.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16973399524.000 = 102.30 [dB]
+# . sst_noise_a = 459.008 = 26.62 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 49.86 [dB]
+# . wg_measured_snr_a_dB = 48.60 [dB]
+# . fil_measured_snr_a_dB = 48.61 [dB]
+# . sst_measured_snr_a_dB = 75.68 [dB]
+# . wpfb_measured_proc_gain_a_dB = 27.08 [dB]
+#
+# ** Error: Wrong estimated amplitude for FIR filter output a, 2.084546e+06 /~= 2.084531e+06
+# Time: 639255 ns Iteration: 0 Instance: /tb_tb_verify_pfb_wg/gen_2022_mar_21/u_2020
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2021:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 9
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -255.000
+# . input_max_a = 255.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2079398.000
+# . fir_max_a = 2079398.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 255
+# . input_ampl_a = 255.950
+# . cw_ampl_a = 255.950
+# . fir_ampl_a = 2085874.083
+# . fil_ampl_a = 2085870.647
+# . sub_a_re = 0
+# . sub_a_im = -130366
+# . sub_a_ampl = 130366.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16995293956.000 = 102.30 [dB]
+# . sst_noise_a = 110.087 = 20.42 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 55.91 [dB]
+# . wg_measured_snr_a_dB = 54.89 [dB]
+# . fil_measured_snr_a_dB = 54.82 [dB]
+# . sst_measured_snr_a_dB = 81.89 [dB]
+# . wpfb_measured_proc_gain_a_dB = 27.00 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2022:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 10
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -511.000
+# . input_max_a = 511.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2083475.000
+# . fir_max_a = 2083475.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 511
+# . input_ampl_a = 511.954
+# . cw_ampl_a = 511.954
+# . fir_ampl_a = 2086096.053
+# . fil_ampl_a = 2086095.189
+# . sub_a_re = 0
+# . sub_a_im = -130380
+# . sub_a_ampl = 130380.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16998944400.000 = 102.30 [dB]
+# . sst_noise_a = 28.064 = 14.48 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 61.95 [dB]
+# . wg_measured_snr_a_dB = 60.90 [dB]
+# . fil_measured_snr_a_dB = 60.82 [dB]
+# . sst_measured_snr_a_dB = 87.82 [dB]
+# . wpfb_measured_proc_gain_a_dB = 26.93 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2023:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 11
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -1023.000
+# . input_max_a = 1023.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2084363.000
+# . fir_max_a = 2084363.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 1023
+# . input_ampl_a = 1023.954
+# . cw_ampl_a = 1023.954
+# . fir_ampl_a = 2086187.176
+# . fil_ampl_a = 2086186.990
+# . sub_a_re = 0
+# . sub_a_im = -130385
+# . sub_a_ampl = 130385.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17000248225.000 = 102.30 [dB]
+# . sst_noise_a = 6.192 = 7.92 [dB]
+# . sst_noise_b = 0.006 = -22.31 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 67.98 [dB]
+# . wg_measured_snr_a_dB = 67.73 [dB]
+# . fil_measured_snr_a_dB = 67.48 [dB]
+# . sst_measured_snr_a_dB = 94.39 [dB]
+# . wpfb_measured_proc_gain_a_dB = 26.65 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2024:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 12
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -2047.000
+# . input_max_a = 2047.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2085381.000
+# . fir_max_a = 2085381.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 2047
+# . input_ampl_a = 2047.960
+# . cw_ampl_a = 2047.960
+# . fir_ampl_a = 2086241.156
+# . fil_ampl_a = 2086241.098
+# . sub_a_re = 0
+# . sub_a_im = -130389
+# . sub_a_ampl = 130389.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001291321.000 = 102.30 [dB]
+# . sst_noise_a = 2.019 = 3.05 [dB]
+# . sst_noise_b = 0.003 = -25.32 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 74.00 [dB]
+# . wg_measured_snr_a_dB = 73.48 [dB]
+# . fil_measured_snr_a_dB = 72.53 [dB]
+# . sst_measured_snr_a_dB = 99.25 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.77 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2025:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 13
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -4095.000
+# . input_max_a = 4095.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2085827.000
+# . fir_max_a = 2085827.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 4095
+# . input_ampl_a = 4095.976
+# . cw_ampl_a = 4095.976
+# . fir_ampl_a = 2086269.606
+# . fil_ampl_a = 2086269.581
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.930 = -0.32 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 80.03 [dB]
+# . wg_measured_snr_a_dB = 79.90 [dB]
+# . fil_measured_snr_a_dB = 76.25 [dB]
+# . sst_measured_snr_a_dB = 102.62 [dB]
+# . wpfb_measured_proc_gain_a_dB = 22.73 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2026:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 59.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086465.000
+# . fir_max_a = 2086593.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086263.204
+# . fil_ampl_a = 2086263.188
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.624 = -2.05 [dB]
+# . sst_noise_b = 0.003 = -25.32 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.22 [dB]
+# . sst_measured_snr_a_dB = 104.35 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.70 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2027:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 15
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -16383.000
+# . input_max_a = 16383.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086209.000
+# . fir_max_a = 2086209.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 16383
+# . input_ampl_a = 16383.977
+# . cw_ampl_a = 16383.977
+# . fir_ampl_a = 2086278.643
+# . fil_ampl_a = 2086278.628
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.564 = -2.49 [dB]
+# . sst_noise_b = 0.005 = -23.10 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 92.07 [dB]
+# . wg_measured_snr_a_dB = 92.09 [dB]
+# . fil_measured_snr_a_dB = 78.58 [dB]
+# . sst_measured_snr_a_dB = 104.80 [dB]
+# . wpfb_measured_proc_gain_a_dB = 12.70 [dB]
+#
+
+# . wpfb_measured_proc_gain_a_dB = 27.08 [dB]
+# . wpfb_measured_proc_gain_a_dB = 27.00 [dB]
+# . wpfb_measured_proc_gain_a_dB = 26.93 [dB]
+# . wpfb_measured_proc_gain_a_dB = 26.65 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.77 [dB]
+# . wpfb_measured_proc_gain_a_dB = 22.73 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.70 [dB]
+# . wpfb_measured_proc_gain_a_dB = 12.70 [dB]
+
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2010:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant-nodc_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -521504.000
+# . fir_max_a = 521504.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 521564.349
+# . fil_ampl_a = 521564.348
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.279 = -5.55 [dB]
+# . sst_noise_b = 0.031 = -15.04 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.66 [dB]
+# . sst_measured_snr_a_dB = 107.85 [dB]
+# . wpfb_measured_proc_gain_a_dB = 22.20 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2011:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant-nodc_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1043009.000
+# . fir_max_a = 1043009.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1043128.804
+# . fil_ampl_a = 1043128.803
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.190 = -7.22 [dB]
+# . sst_noise_b = 0.009 = -20.55 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 109.52 [dB]
+# . wpfb_measured_proc_gain_a_dB = 23.87 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2012:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant-nodc_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086017.000
+# . fir_max_a = 2086017.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086257.589
+# . fil_ampl_a = 2086257.586
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.155 = -8.11 [dB]
+# . sst_noise_b = 0.005 = -23.10 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 110.41 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.76 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2013:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant-nodc_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172035.000
+# . fir_max_a = 4172035.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172515.180
+# . fil_ampl_a = 4172515.174
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.139 = -8.57 [dB]
+# . sst_noise_b = 0.003 = -25.32 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 110.88 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.22 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2014:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant-nodc_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344069.000
+# . fir_max_a = 8344069.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345030.287
+# . fil_ampl_a = 8345030.275
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.126 = -8.99 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 111.29 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.64 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2015:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant-nodc_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688139.000
+# . fir_max_a = 16688139.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690060.643
+# . fil_ampl_a = 16690060.620
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.122 = -9.13 [dB]
+# . sst_noise_b = 0.001 = -30.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 111.43 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.78 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2016:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant-nodc_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 0
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344069.000
+# . fir_max_a = 8344069.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345030.287
+# . fil_ampl_a = 8345030.275
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.126 = -8.99 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 111.29 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.64 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2017:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant-nodc_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 0
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 0
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688139.000
+# . fir_max_a = 16688139.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690060.643
+# . fil_ampl_a = 16690060.620
+# . sub_a_re = 0
+# . sub_a_im = -130390
+# . sub_a_ampl = 130390.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001552100.000 = 102.30 [dB]
+# . sst_noise_a = 0.122 = -9.13 [dB]
+# . sst_noise_b = 0.001 = -30.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 111.43 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.78 [dB]
+#
+
+# . wpfb_measured_proc_gain_a_dB = 22.20 [dB]
+# . wpfb_measured_proc_gain_a_dB = 23.87 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.76 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.22 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.64 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.78 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.64 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.78 [dB]
+
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2010:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -519009.000
+# . fir_max_a = 519009.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 519051.897
+# . fil_ampl_a = 519051.896
+# . sub_a_re = 0
+# . sub_a_im = -129763
+# . sub_a_ampl = 129763.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838436169.000 = 102.26 [dB]
+# . sst_noise_a = 0.489 = -3.10 [dB]
+# . sst_noise_b = 0.026 = -15.78 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 84.09 [dB]
+# . sst_measured_snr_a_dB = 105.37 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.72 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2011:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1038017.000
+# . fir_max_a = 1038017.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1038103.792
+# . fil_ampl_a = 1038103.789
+# . sub_a_re = 0
+# . sub_a_im = -129762
+# . sub_a_ampl = 129762.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838176644.000 = 102.26 [dB]
+# . sst_noise_a = 0.274 = -5.62 [dB]
+# . sst_noise_b = 0.010 = -20.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 84.09 [dB]
+# . sst_measured_snr_a_dB = 107.89 [dB]
+# . wpfb_measured_proc_gain_a_dB = 22.23 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2012:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2076035.000
+# . fir_max_a = 2076035.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2076207.633
+# . fil_ampl_a = 2076207.629
+# . sub_a_re = 0
+# . sub_a_im = -129762
+# . sub_a_ampl = 129762.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838176644.000 = 102.26 [dB]
+# . sst_noise_a = 0.200 = -7.00 [dB]
+# . sst_noise_b = 0.006 = -22.31 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 84.09 [dB]
+# . sst_measured_snr_a_dB = 109.26 [dB]
+# . wpfb_measured_proc_gain_a_dB = 23.61 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2013:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4152069.000
+# . fir_max_a = 4152069.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4152415.206
+# . fil_ampl_a = 4152415.198
+# . sub_a_re = 0
+# . sub_a_im = -129762
+# . sub_a_ampl = 129762.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838176644.000 = 102.26 [dB]
+# . sst_noise_a = 0.159 = -7.97 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 84.09 [dB]
+# . sst_measured_snr_a_dB = 110.24 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.58 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2014:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8304138.000
+# . fir_max_a = 8304138.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8304830.399
+# . fil_ampl_a = 8304830.383
+# . sub_a_re = 0
+# . sub_a_im = -129761
+# . sub_a_ampl = 129761.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16837917121.000 = 102.26 [dB]
+# . sst_noise_a = 0.154 = -8.14 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 84.09 [dB]
+# . sst_measured_snr_a_dB = 110.40 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.75 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2015:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16608276.000
+# . fir_max_a = 16608276.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16609660.784
+# . fil_ampl_a = 16609660.752
+# . sub_a_re = 0
+# . sub_a_im = -129761
+# . sub_a_ampl = 129761.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16837917121.000 = 102.26 [dB]
+# . sst_noise_a = 0.150 = -8.25 [dB]
+# . sst_noise_b = 0.001 = -30.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 84.09 [dB]
+# . sst_measured_snr_a_dB = 110.51 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.86 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2030:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -519013.000
+# . fir_max_a = 519009.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 519064.653
+# . fil_ampl_a = 519064.652
+# . sub_a_re = 0
+# . sub_a_im = -129766
+# . sub_a_ampl = 129766.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16839214756.000 = 102.26 [dB]
+# . sst_noise_a = 0.319 = -4.96 [dB]
+# . sst_noise_b = 0.038 = -14.18 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.55 [dB]
+# . sst_measured_snr_a_dB = 107.23 [dB]
+# . wpfb_measured_proc_gain_a_dB = 21.57 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2031:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1038025.000
+# . fir_max_a = 1038017.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1038129.308
+# . fil_ampl_a = 1038129.307
+# . sub_a_re = 0
+# . sub_a_im = -129765
+# . sub_a_ampl = 129765.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838955225.000 = 102.26 [dB]
+# . sst_noise_a = 0.195 = -7.11 [dB]
+# . sst_noise_b = 0.011 = -19.68 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.54 [dB]
+# . sst_measured_snr_a_dB = 109.37 [dB]
+# . wpfb_measured_proc_gain_a_dB = 23.72 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2032:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2076051.000
+# . fir_max_a = 2076035.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2076258.573
+# . fil_ampl_a = 2076258.570
+# . sub_a_re = 0
+# . sub_a_im = -129765
+# . sub_a_ampl = 129765.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838955225.000 = 102.26 [dB]
+# . sst_noise_a = 0.160 = -7.95 [dB]
+# . sst_noise_b = 0.005 = -23.10 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.54 [dB]
+# . sst_measured_snr_a_dB = 110.21 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.56 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2033:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4152101.000
+# . fir_max_a = 4152069.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4152517.145
+# . fil_ampl_a = 4152517.139
+# . sub_a_re = 0
+# . sub_a_im = -129765
+# . sub_a_ampl = 129765.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838955225.000 = 102.26 [dB]
+# . sst_noise_a = 0.139 = -8.57 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.54 [dB]
+# . sst_measured_snr_a_dB = 110.83 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.18 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2034:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8304202.000
+# . fir_max_a = 8304138.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8305034.343
+# . fil_ampl_a = 8305034.331
+# . sub_a_re = 0
+# . sub_a_im = -129765
+# . sub_a_ampl = 129765.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838955225.000 = 102.26 [dB]
+# . sst_noise_a = 0.133 = -8.76 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.54 [dB]
+# . sst_measured_snr_a_dB = 111.02 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.37 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2035:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16608404.000
+# . fir_max_a = 16608276.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16610068.644
+# . fil_ampl_a = 16610068.620
+# . sub_a_re = 0
+# . sub_a_im = -129765
+# . sub_a_ampl = 129765.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838955225.000 = 102.26 [dB]
+# . sst_noise_a = 0.133 = -8.76 [dB]
+# . sst_noise_b = 0.001 = -30.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.54 [dB]
+# . sst_measured_snr_a_dB = 111.02 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.37 [dB]
+#
+
+ Hanning_16b
+# . wpfb_measured_proc_gain_a_dB = 19.72 [dB]
+# . wpfb_measured_proc_gain_a_dB = 22.23 [dB]
+# . wpfb_measured_proc_gain_a_dB = 23.61 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.58 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.75 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.86 [dB]
+
+ Hanning_18b
+# . wpfb_measured_proc_gain_a_dB = 21.57 [dB]
+# . wpfb_measured_proc_gain_a_dB = 23.72 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.56 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.18 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.37 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.37 [dB]
+
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2040:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -526352.000
+# . fir_max_a = 526336.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 526386.425
+# . fil_ampl_a = 526386.421
+# . sub_a_re = -1
+# . sub_a_im = -131596
+# . sub_a_ampl = 131596.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 4
+# . sub_a_ampl_frac = 4.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17317507216.500 = 102.38 [dB]
+# . sst_noise_a = 1.079 = 0.33 [dB]
+# . sst_noise_b = 0.027 = -15.62 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 77.73 [dB]
+# . sst_measured_snr_a_dB = 102.05 [dB]
+# . wpfb_measured_proc_gain_a_dB = 16.40 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2041:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1052703.000
+# . fir_max_a = 1052671.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1052772.857
+# . fil_ampl_a = 1052772.848
+# . sub_a_re = 0
+# . sub_a_im = -131596
+# . sub_a_ampl = 131596.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17317507216.000 = 102.38 [dB]
+# . sst_noise_a = 0.844 = -0.73 [dB]
+# . sst_noise_b = 0.010 = -20.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 77.73 [dB]
+# . sst_measured_snr_a_dB = 103.12 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.47 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2042:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2105407.000
+# . fir_max_a = 2105343.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2105545.730
+# . fil_ampl_a = 2105545.712
+# . sub_a_re = 0
+# . sub_a_im = -131595
+# . sub_a_ampl = 131595.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17317244025.000 = 102.38 [dB]
+# . sst_noise_a = 0.746 = -1.27 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 77.73 [dB]
+# . sst_measured_snr_a_dB = 103.66 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.01 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2043:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4210814.000
+# . fir_max_a = 4210686.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4211091.449
+# . fil_ampl_a = 4211091.413
+# . sub_a_re = 0
+# . sub_a_im = -131595
+# . sub_a_ampl = 131595.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17317244025.000 = 102.38 [dB]
+# . sst_noise_a = 0.663 = -1.78 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 77.72 [dB]
+# . sst_measured_snr_a_dB = 104.17 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.51 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2044:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8421628.000
+# . fir_max_a = 8421372.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8422182.840
+# . fil_ampl_a = 8422182.769
+# . sub_a_re = 0
+# . sub_a_im = -131595
+# . sub_a_ampl = 131595.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17317244025.000 = 102.38 [dB]
+# . sst_noise_a = 0.606 = -2.18 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 77.73 [dB]
+# . sst_measured_snr_a_dB = 104.56 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.91 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2045:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_16b_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16843256.000
+# . fir_max_a = 16842744.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16844365.658
+# . fil_ampl_a = 16844365.516
+# . sub_a_re = 0
+# . sub_a_im = -131595
+# . sub_a_ampl = 131595.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17317244025.000 = 102.38 [dB]
+# . sst_noise_a = 0.609 = -2.16 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 77.73 [dB]
+# . sst_measured_snr_a_dB = 104.54 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.89 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2050:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -526360.000
+# . fir_max_a = 526360.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 526400.729
+# . fil_ampl_a = 526400.725
+# . sub_a_re = 0
+# . sub_a_im = -131600
+# . sub_a_ampl = 131600.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 4
+# . sub_a_ampl_frac = 4.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17318428400.500 = 102.39 [dB]
+# . sst_noise_a = 0.903 = -0.44 [dB]
+# . sst_noise_b = 0.030 = -15.18 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.01 [dB]
+# . sst_measured_snr_a_dB = 102.83 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.17 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2051:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1052719.000
+# . fir_max_a = 1052719.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1052801.474
+# . fil_ampl_a = 1052801.465
+# . sub_a_re = 0
+# . sub_a_im = -131599
+# . sub_a_ampl = 131599.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17318296801.000 = 102.39 [dB]
+# . sst_noise_a = 0.762 = -1.18 [dB]
+# . sst_noise_b = 0.009 = -20.55 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.01 [dB]
+# . sst_measured_snr_a_dB = 103.56 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.91 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2052:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2105439.000
+# . fir_max_a = 2105439.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2105602.947
+# . fil_ampl_a = 2105602.930
+# . sub_a_re = 0
+# . sub_a_im = -131599
+# . sub_a_ampl = 131599.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17318296801.000 = 102.39 [dB]
+# . sst_noise_a = 0.697 = -1.57 [dB]
+# . sst_noise_b = 0.005 = -23.10 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.01 [dB]
+# . sst_measured_snr_a_dB = 103.95 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.30 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2053:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4210878.000
+# . fir_max_a = 4210878.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4211205.928
+# . fil_ampl_a = 4211205.895
+# . sub_a_re = 0
+# . sub_a_im = -131599
+# . sub_a_ampl = 131599.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17318296801.000 = 102.39 [dB]
+# . sst_noise_a = 0.657 = -1.83 [dB]
+# . sst_noise_b = 0.003 = -25.32 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.01 [dB]
+# . sst_measured_snr_a_dB = 104.21 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.56 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2054:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8421756.000
+# . fir_max_a = 8421756.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8422411.834
+# . fil_ampl_a = 8422411.768
+# . sub_a_re = 0
+# . sub_a_im = -131599
+# . sub_a_ampl = 131599.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17318296801.000 = 102.39 [dB]
+# . sst_noise_a = 0.642 = -1.93 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.01 [dB]
+# . sst_measured_snr_a_dB = 104.31 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.66 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2055:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KKaiser_18b_1wb
+# . c_pfir_coef_w = 18
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16843512.000
+# . fir_max_a = 16843512.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16844823.672
+# . fil_ampl_a = 16844823.538
+# . sub_a_re = 0
+# . sub_a_im = -131599
+# . sub_a_ampl = 131599.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17318296801.000 = 102.39 [dB]
+# . sst_noise_a = 0.620 = -2.07 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.01 [dB]
+# . sst_measured_snr_a_dB = 104.46 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.81 [dB]
+#
+
+ Kaiser_16b
+# . wpfb_measured_proc_gain_a_dB = 16.40 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.47 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.01 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.51 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.91 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.89 [dB]
+
+ Kaiser_18b
+# . wpfb_measured_proc_gain_a_dB = 17.17 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.91 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.30 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.56 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.66 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.81 [dB]
+
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2060:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_20b_1wb
+# . c_pfir_coef_w = 20
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -519011.000
+# . fir_max_a = 519012.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 519068.099
+# . fil_ampl_a = 519068.098
+# . sub_a_re = 0
+# . sub_a_im = -129767
+# . sub_a_ampl = 129767.000
+# . sub_a_re_frac = -1
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.414
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16839474289.000 = 102.26 [dB]
+# . sst_noise_a = 0.290 = -5.38 [dB]
+# . sst_noise_b = 0.037 = -14.30 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.66 [dB]
+# . sst_measured_snr_a_dB = 107.64 [dB]
+# . wpfb_measured_proc_gain_a_dB = 21.99 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2061:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_20b_1wb
+# . c_pfir_coef_w = 20
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1038021.000
+# . fir_max_a = 1038023.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1038136.245
+# . fil_ampl_a = 1038136.243
+# . sub_a_re = 0
+# . sub_a_im = -129766
+# . sub_a_ampl = 129766.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16839214756.000 = 102.26 [dB]
+# . sst_noise_a = 0.189 = -7.24 [dB]
+# . sst_noise_b = 0.010 = -20.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 109.50 [dB]
+# . wpfb_measured_proc_gain_a_dB = 23.85 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2062:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_20b_1wb
+# . c_pfir_coef_w = 20
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2076043.000
+# . fir_max_a = 2076047.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2076272.473
+# . fil_ampl_a = 2076272.470
+# . sub_a_re = 0
+# . sub_a_im = -129766
+# . sub_a_ampl = 129766.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16839214756.000 = 102.26 [dB]
+# . sst_noise_a = 0.153 = -8.16 [dB]
+# . sst_noise_b = 0.005 = -23.10 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.66 [dB]
+# . sst_measured_snr_a_dB = 110.43 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.77 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2063:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_20b_1wb
+# . c_pfir_coef_w = 20
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4152085.000
+# . fir_max_a = 4152093.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4152544.946
+# . fil_ampl_a = 4152544.940
+# . sub_a_re = 0
+# . sub_a_im = -129766
+# . sub_a_ampl = 129766.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16839214756.000 = 102.26 [dB]
+# . sst_noise_a = 0.134 = -8.73 [dB]
+# . sst_noise_b = 0.004 = -24.07 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 110.99 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.34 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2064:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_20b_1wb
+# . c_pfir_coef_w = 20
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8304170.000
+# . fir_max_a = 8304186.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8305089.917
+# . fil_ampl_a = 8305089.906
+# . sub_a_re = 0
+# . sub_a_im = -129765
+# . sub_a_ampl = 129765.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838955225.000 = 102.26 [dB]
+# . sst_noise_a = 0.123 = -9.09 [dB]
+# . sst_noise_b = 0.002 = -27.08 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 111.35 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.70 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2065:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coefficient_16KHanning_20b_1wb
+# . c_pfir_coef_w = 20
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16608340.000
+# . fir_max_a = 16608372.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16610179.784
+# . fil_ampl_a = 16610179.761
+# . sub_a_re = 0
+# . sub_a_im = -129765
+# . sub_a_ampl = 129765.000
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 0
+# . sub_a_ampl_frac = 0.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 16838955225.000 = 102.26 [dB]
+# . sst_noise_a = 0.121 = -9.16 [dB]
+# . sst_noise_b = 0.001 = -30.09 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 85.65 [dB]
+# . sst_measured_snr_a_dB = 111.42 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.77 [dB]
+#
+
+# . wpfb_measured_proc_gain_a_dB = 21.99 [dB]
+# . wpfb_measured_proc_gain_a_dB = 23.85 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.77 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.34 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.70 [dB]
+# . wpfb_measured_proc_gain_a_dB = 25.77 [dB]
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2070:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -521520.000
+# . fir_max_a = 521520.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 521566.787
+# . fil_ampl_a = 521566.783
+# . sub_a_re = 0
+# . sub_a_im = -65196
+# . sub_a_ampl = 65196.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 2
+# . sub_a_ampl_frac = 2.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250518416.000 = 96.28 [dB]
+# . sst_noise_a = 0.222 = -6.53 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 102.82 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.17 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2071:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1043041.000
+# . fir_max_a = 1043041.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1043133.576
+# . fil_ampl_a = 1043133.568
+# . sub_a_re = 0
+# . sub_a_im = -65195
+# . sub_a_ampl = 65195.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994918
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 2
+# . sub_a_ampl_frac = 2.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250388025.000 = 96.28 [dB]
+# . sst_noise_a = 0.135 = -8.70 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 104.98 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.33 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2072:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -65195
+# . sub_a_ampl = 65195.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994918
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250388025.000 = 96.28 [dB]
+# . sst_noise_a = 0.114 = -9.41 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.70 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.04 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2073:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -65195
+# . sub_a_ampl = 65195.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994918
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250388025.000 = 96.28 [dB]
+# . sst_noise_a = 0.112 = -9.53 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.81 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.16 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2074:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344325.000
+# . fir_max_a = 8344325.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345068.660
+# . fil_ampl_a = 8345068.596
+# . sub_a_re = 0
+# . sub_a_im = -65195
+# . sub_a_ampl = 65195.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994918
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250388025.000 = 96.28 [dB]
+# . sst_noise_a = 0.109 = -9.64 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.93 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.27 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2075:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 18
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688651.000
+# . fir_max_a = 16688651.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690137.335
+# . fil_ampl_a = 16690137.208
+# . sub_a_re = 0
+# . sub_a_im = -65195
+# . sub_a_ampl = 65195.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994918
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250388025.000 = 96.28 [dB]
+# . sst_noise_a = 0.106 = -9.76 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 106.04 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.39 [dB]
+#
+
+
+# . wpfb_measured_proc_gain_a_dB = 17.17 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.33 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.04 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.16 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.27 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.39 [dB]
+
+
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2070:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -521520.000
+# . fir_max_a = 521520.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 521566.787
+# . fil_ampl_a = 521566.783
+# . sub_a_re = 0
+# . sub_a_im = -65196
+# . sub_a_ampl = 65196.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 2
+# . sub_a_ampl_frac = 2.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250518416.000 = 96.28 [dB]
+# . sst_noise_a = 0.226 = -6.46 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 102.74 [dB]
+# . wpfb_measured_proc_gain_a_dB = 17.09 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2071:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1043041.000
+# . fir_max_a = 1043041.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1043133.576
+# . fil_ampl_a = 1043133.568
+# . sub_a_re = 0
+# . sub_a_im = -65196
+# . sub_a_ampl = 65196.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 2
+# . sub_a_ampl_frac = 2.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250518416.000 = 96.28 [dB]
+# . sst_noise_a = 0.133 = -8.76 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 105.04 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.39 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2072:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -65196
+# . sub_a_ampl = 65196.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250518416.000 = 96.28 [dB]
+# . sst_noise_a = 0.113 = -9.49 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.77 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.12 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2073:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -65196
+# . sub_a_ampl = 65196.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250518416.000 = 96.28 [dB]
+# . sst_noise_a = 0.110 = -9.60 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.89 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.23 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2074:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344325.000
+# . fir_max_a = 8344325.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345068.660
+# . fil_ampl_a = 8345068.596
+# . sub_a_re = 0
+# . sub_a_im = -65196
+# . sub_a_ampl = 65196.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250518416.000 = 96.28 [dB]
+# . sst_noise_a = 0.110 = -9.60 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.89 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.23 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2075:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 18
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688651.000
+# . fir_max_a = 16688651.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690137.335
+# . fil_ampl_a = 16690137.208
+# . sub_a_re = 0
+# . sub_a_im = -65196
+# . sub_a_ampl = 65196.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 1
+# . sub_a_ampl_frac = 1.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 4250518416.000 = 96.28 [dB]
+# . sst_noise_a = 0.108 = -9.68 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 105.97 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.31 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2080:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -521520.000
+# . fir_max_a = 521520.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 521566.787
+# . fil_ampl_a = 521566.783
+# . sub_a_re = 0
+# . sub_a_im = -130393
+# . sub_a_ampl = 130393.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994941
+# . sub_a_re_frac = -1
+# . sub_a_im_frac = 4
+# . sub_a_ampl_frac = 4.123
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002334449.000 = 102.31 [dB]
+# . sst_noise_a = 0.998 = -0.01 [dB]
+# . sst_noise_b = 0.003 = -25.32 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 102.31 [dB]
+# . wpfb_measured_proc_gain_a_dB = 16.66 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2081:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1043041.000
+# . fir_max_a = 1043041.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1043133.576
+# . fil_ampl_a = 1043133.568
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.731 = -1.36 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 103.67 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.01 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2082:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.654 = -1.85 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.15 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.50 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2083:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994926
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.579 = -2.37 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.68 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.02 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2084:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344325.000
+# . fir_max_a = 8344325.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345068.660
+# . fil_ampl_a = 8345068.596
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994926
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.567 = -2.47 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.77 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.12 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2085:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688651.000
+# . fir_max_a = 16688651.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690137.335
+# . fil_ampl_a = 16690137.208
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994926
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 0.546 = -2.63 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 104.93 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.28 [dB]
+#
+
+
+# . wpfb_measured_proc_gain_a_dB = 17.09 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.39 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.12 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.23 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.23 [dB]
+# . wpfb_measured_proc_gain_a_dB = 20.31 [dB]
+
+# . wpfb_measured_proc_gain_a_dB = 16.66 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.01 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.50 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.02 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.12 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.28 [dB]
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2090:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -521520.000
+# . fir_max_a = 521520.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 521566.787
+# . fil_ampl_a = 521566.783
+# . sub_a_re = -1
+# . sub_a_im = -260785
+# . sub_a_ampl = 260785.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994937
+# . sub_a_re_frac = -1
+# . sub_a_im_frac = 7
+# . sub_a_ampl_frac = 7.071
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68008816225.500 = 108.33 [dB]
+# . sst_noise_a = 3.927 = 5.94 [dB]
+# . sst_noise_b = 0.432 = -3.64 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 102.39 [dB]
+# . wpfb_measured_proc_gain_a_dB = 16.73 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2091:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1043041.000
+# . fir_max_a = 1043041.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 1043133.576
+# . fil_ampl_a = 1043133.568
+# . sub_a_re = 0
+# . sub_a_im = -260784
+# . sub_a_ampl = 260784.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 6
+# . sub_a_ampl_frac = 6.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68008294656.000 = 108.33 [dB]
+# . sst_noise_a = 2.891 = 4.61 [dB]
+# . sst_noise_b = 0.012 = -19.30 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 103.71 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.06 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2092:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -260783
+# . sub_a_ampl = 260783.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994930
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 6
+# . sub_a_ampl_frac = 6.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68007773089.000 = 108.33 [dB]
+# . sst_noise_a = 2.455 = 3.90 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.43 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.77 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2093:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172163.000
+# . fir_max_a = 4172163.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 4172534.342
+# . fil_ampl_a = 4172534.311
+# . sub_a_re = 0
+# . sub_a_im = -260783
+# . sub_a_ampl = 260783.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994930
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 6
+# . sub_a_ampl_frac = 6.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68007773089.000 = 108.33 [dB]
+# . sst_noise_a = 2.200 = 3.42 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.90 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.25 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2094:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8344325.000
+# . fir_max_a = 8344325.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 8345068.660
+# . fil_ampl_a = 8345068.596
+# . sub_a_re = 0
+# . sub_a_im = -260783
+# . sub_a_ampl = 260783.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994930
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 6
+# . sub_a_ampl_frac = 6.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68007773089.000 = 108.33 [dB]
+# . sst_noise_a = 2.132 = 3.29 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 105.04 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.38 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2095:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 20
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16688651.000
+# . fir_max_a = 16688651.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 16690137.335
+# . fil_ampl_a = 16690137.208
+# . sub_a_re = 0
+# . sub_a_im = -260783
+# . sub_a_ampl = 260783.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994930
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 6
+# . sub_a_ampl_frac = 6.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 68007512306.500 = 108.33 [dB]
+# . sst_noise_a = 2.109 = 3.24 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.19 [dB]
+# . sst_measured_snr_a_dB = 105.09 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.43 [dB]
+#
+
+# . wpfb_measured_proc_gain_a_dB = 16.73 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.06 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.77 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.25 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.38 [dB]
+# . wpfb_measured_proc_gain_a_dB = 19.43 [dB]
+
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2100:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 12
+# . c_internal_dat_w = 21
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 22
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -2047.000
+# . input_max_a = 2047.000
+# . input_mean_a = 0.000
+# . fir_min_a = -521345.000
+# . fir_max_a = 521345.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 2047
+# . input_ampl_a = 2047.960
+# . cw_ampl_a = 2047.960
+# . fir_ampl_a = 521560.286
+# . fil_ampl_a = 521560.271
+# . sub_a_re = 0
+# . sub_a_im = -130391
+# . sub_a_ampl = 130391.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.995290
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 4
+# . sub_a_ampl_frac = 4.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17001812881.000 = 102.30 [dB]
+# . sst_noise_a = 2.557 = 4.08 [dB]
+# . sst_noise_b = 0.006 = -22.31 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 74.00 [dB]
+# . wg_measured_snr_a_dB = 73.48 [dB]
+# . fil_measured_snr_a_dB = 72.53 [dB]
+# . sst_measured_snr_a_dB = 98.23 [dB]
+# . wpfb_measured_proc_gain_a_dB = 24.74 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2101:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 13
+# . c_internal_dat_w = 22
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 23
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -4095.000
+# . input_max_a = 4095.000
+# . input_mean_a = 0.000
+# . fir_min_a = -1042913.000
+# . fir_max_a = 1042913.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 4095
+# . input_ampl_a = 4095.976
+# . cw_ampl_a = 4095.976
+# . fir_ampl_a = 1043134.758
+# . fil_ampl_a = 1043134.746
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.995055
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 1.077 = 0.32 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 80.03 [dB]
+# . wg_measured_snr_a_dB = 79.90 [dB]
+# . fil_measured_snr_a_dB = 76.25 [dB]
+# . sst_measured_snr_a_dB = 101.98 [dB]
+# . wpfb_measured_proc_gain_a_dB = 22.09 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2102:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 14
+# . c_internal_dat_w = 23
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 24
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -8191.000
+# . input_max_a = 8191.000
+# . input_mean_a = 0.000
+# . fir_min_a = -2086081.000
+# . fir_max_a = 2086081.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 8191
+# . input_ampl_a = 8191.943
+# . cw_ampl_a = 8191.943
+# . fir_ampl_a = 2086267.127
+# . fil_ampl_a = 2086267.112
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994933
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.654 = -1.85 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 86.05 [dB]
+# . wg_measured_snr_a_dB = 85.65 [dB]
+# . fil_measured_snr_a_dB = 78.18 [dB]
+# . sst_measured_snr_a_dB = 104.15 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.50 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2103:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 15
+# . c_internal_dat_w = 24
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 25
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -16383.000
+# . input_max_a = 16383.000
+# . input_mean_a = 0.000
+# . fir_min_a = -4172417.000
+# . fir_max_a = 4172417.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 16383
+# . input_ampl_a = 16383.977
+# . cw_ampl_a = 16383.977
+# . fir_ampl_a = 4172557.299
+# . fil_ampl_a = 4172557.270
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994873
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.484 = -3.15 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 92.07 [dB]
+# . wg_measured_snr_a_dB = 92.09 [dB]
+# . fil_measured_snr_a_dB = 78.58 [dB]
+# . sst_measured_snr_a_dB = 105.45 [dB]
+# . wpfb_measured_proc_gain_a_dB = 13.36 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2104:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 16
+# . c_internal_dat_w = 25
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 26
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -32767.000
+# . input_max_a = 32767.000
+# . input_mean_a = 0.000
+# . fir_min_a = -8345089.000
+# . fir_max_a = 8344580.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 32767
+# . input_ampl_a = 32767.872
+# . cw_ampl_a = 32767.872
+# . fir_ampl_a = 8345093.842
+# . fil_ampl_a = 8345093.789
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994842
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.410 = -3.87 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 98.09 [dB]
+# . wg_measured_snr_a_dB = 98.63 [dB]
+# . fil_measured_snr_a_dB = 78.96 [dB]
+# . sst_measured_snr_a_dB = 106.18 [dB]
+# . wpfb_measured_proc_gain_a_dB = 7.55 [dB]
+#
+# -------------------------------------------------------------
+# -- WPFB settings of tb-2105:
+# -------------------------------------------------------------
+# . c_pfs_bypass = FALSE
+# . g_fil_coefs_file_prefix = data/Coeffs16384Kaiser-quant_1wb
+# . c_pfir_coef_w = 16
+# . g_fil_backoff_w = 1
+# . g_fil_in_dat_w = 17
+# . c_internal_dat_w = 26
+# . c_twiddle_w = 20
+# . g_fft_out_dat_w = 19
+# . g_fft_out_gain_w = 1
+# . g_fft_stage_dat_w = 27
+# . g_fft_guard_w = 1
+# . c_switch_en = 0
+#
+# WG settings:
+# . g_subband_index_a = 61.000
+# . g_amplitude_a = 1.000
+# . g_phase_a = 0.0 degrees
+#
+# DC, min, max levels
+# . input_min_a = -65535.000
+# . input_max_a = 65535.000
+# . input_mean_a = 0.000
+# . fir_min_a = -16690433.000
+# . fir_max_a = 16689415.000
+# . fir_mean_a = 0.000
+#
+# Amplitudes:
+# . c_wg_ampl_a = 65535
+# . input_ampl_a = 65535.833
+# . cw_ampl_a = 65535.833
+# . fir_ampl_a = 16690210.227
+# . fil_ampl_a = 16690210.121
+# . sub_a_re = 0
+# . sub_a_im = -130392
+# . sub_a_ampl = 130392.000
+# . sub_a_ampl/c_exp_sub_a_ampl = 0.994827
+# . sub_a_re_frac = 0
+# . sub_a_im_frac = 3
+# . sub_a_ampl_frac = 3.000
+#
+# Phases [Ts]:
+# . cw_phase_Ts_a = -1.000
+# . fil_phase_Ts_a = -1.000
+#
+# Powers:
+# . sst_wg_power_a = 17002073664.000 = 102.31 [dB]
+# . sst_noise_a = 0.380 = -4.21 [dB]
+# . sst_noise_b = 0.000 = -200.00 [dB]
+#
+# SNR and WPFB processing gain:
+# . c_wg_snr_a_dB = 104.11 [dB]
+# . wg_measured_snr_a_dB = 103.51 [dB]
+# . fil_measured_snr_a_dB = 78.98 [dB]
+# . sst_measured_snr_a_dB = 106.51 [dB]
+# . wpfb_measured_proc_gain_a_dB = 3.00 [dB]
+#
+
+# . wpfb_measured_proc_gain_a_dB = 24.74 [dB]
+# . wpfb_measured_proc_gain_a_dB = 22.09 [dB]
+# . wpfb_measured_proc_gain_a_dB = 18.50 [dB]
+# . wpfb_measured_proc_gain_a_dB = 13.36 [dB]
+# . wpfb_measured_proc_gain_a_dB = 7.55 [dB]
+# . wpfb_measured_proc_gain_a_dB = 3.00 [dB]
+
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
index fe84e21ca58d62cad52a94d62f450297d6ed2050..85e9724b6bf862de675c64c66c245a9d04bb8b9c 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
@@ -80,9 +80,6 @@
-- > observe the *_scope signals as radix decimal, format analogue format signals in the Wave window.
-- default use analogue(automatic), if necessary zoom in using right click analogue(custom).
--
--- Note:
--- . Must use ABS() with **2.0 of negative REAL, because (negative)**2.0 yields error and value 0.0,
--- . Must use brackets (ABS()) to avoid compile error
LIBRARY ieee, common_lib, dp_lib, diag_lib, filter_lib, rTwoSDF_lib, fft_lib, wpfb_lib;
LIBRARY pfs_lib, pft2_lib, pfb2_lib;
@@ -149,7 +146,7 @@ ENTITY tb_verify_pfb_wg IS
--g_fil_coefs_file_prefix : STRING := "data/run_pfir_coeff_m_fircls1_16taps_1024points_18b_1wb"; -- g_fil_coef_dat_w = 18 bit
g_fil_coef_dat_w : NATURAL := 16; -- = 16, data width of the FIR coefficients
--g_fil_coef_dat_w : NATURAL := 18; -- = 16, data width of the FIR coefficients
- g_fil_backoff_w : NATURAL := 0; -- = 0, number of bits for input backoff to avoid output overflow
+ g_fil_backoff_w : NATURAL := 1; -- = 0, number of bits for input backoff to avoid output overflow
g_fil_in_dat_w : NATURAL := 14; -- = W_adc, number of input bits
g_internal_dat_w : NATURAL := 0; -- = number of bits between fil and fft, use 0 to use maximum default:
@@ -161,9 +158,7 @@ ENTITY tb_verify_pfb_wg IS
g_fft_out_gain_w : NATURAL := 1; -- = 1, output gain factor applied after the last stage output, before requantization to out_dat_w
g_fft_stage_dat_w : NATURAL := 27; -- = c_dsp_mult_w = 18, number of bits that are used inter-stage
g_fft_guard_w : NATURAL := 1; -- = 2
- g_switch_en : STD_LOGIC := '0'; -- two real input decorrelation option in PFB2
- g_r2_mul_extra_w : NATURAL := 0; -- = 2, WPFB extra bits at rTwoWMul output in rTwoSDFStage to improve rTwoSDFStage output requantization in fft_r2_pipe in wpfb_unit_dev
- g_sepa_extra_w : NATURAL := 0 -- = 2, WPFB extra LSbits in output of last rTwoSDFStage to improve two real separate requantization in fft_r2_pipe in wpfb_unit_dev
+ g_switch_en : STD_LOGIC := '0' -- two real input decorrelation option in PFB2
);
END ENTITY tb_verify_pfb_wg;
@@ -177,7 +172,8 @@ ARCHITECTURE tb OF tb_verify_pfb_wg IS
--CONSTANT c_view_pfir_impulse_reponse : BOOLEAN := TRUE;
-- Determine bypass PFIR for PFB2, using g_fil_coefs_file_prefix setting for WPFB
- CONSTANT c_pfs_bypass : BOOLEAN := g_fil_coefs_file_prefix="data/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb";
+ CONSTANT c_pfs_bypass : BOOLEAN := g_fil_coefs_file_prefix = "data/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb";
+ CONSTANT c_pfs_lofar1 : BOOLEAN := g_fil_coefs_file_prefix = "data/Coeffs16384Kaiser-quant_1wb";
-- Determine PFIR coefficient width for WPFB and PFB2
CONSTANT c_pfir_coef_w : NATURAL := sel_a_b(g_sel_pfb="WPFB", g_fil_coef_dat_w, 16);
@@ -237,8 +233,6 @@ ARCHITECTURE tb OF tb_verify_pfb_wg IS
true, false, true, c_internal_dat_w, g_fft_out_dat_w, g_fft_out_gain_w, g_fft_stage_dat_w, g_fft_guard_w, true, 54, 2, 10,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
- CONSTANT c_wpfb_extra : t_wpfb_extra := (g_r2_mul_extra_w, g_sepa_extra_w);
-
CONSTANT c_N_fft : NATURAL := c_wpfb.nof_points;
CONSTANT c_N_sub : NATURAL := c_N_fft / c_nof_complex;
CONSTANT c_N_blk : NATURAL := c_wpfb.nof_blk_per_sync; -- nof FFT blocks per sync interval
@@ -246,8 +240,6 @@ ARCHITECTURE tb OF tb_verify_pfb_wg IS
CONSTANT c_nof_channels : NATURAL := 2**c_wpfb.nof_chan; -- = 2**0 = 1, so no time multiplexing of inputs
CONSTANT c_nof_sync : NATURAL := 5; -- nof sync intervals to simulate
- CONSTANT c_pfb_sub_scaling : REAL := 2.0**REAL(g_fft_out_dat_w + g_fft_out_gain_w - g_fil_in_dat_w - 1); -- expected subband amplitude gain relative to input WG amplitude
- -- -1 for divide by 2 in two real input separate (Ampl --> Ampl/2)
-- Subband at WG frequency
CONSTANT c_bin_a : NATURAL := NATURAL(FLOOR(g_subband_index_a));
CONSTANT c_bin_a_frac_en : BOOLEAN := g_subband_index_a > REAL(c_bin_a);
@@ -283,7 +275,18 @@ ARCHITECTURE tb OF tb_verify_pfb_wg IS
-- subband index / c_N_fft = 64 / 1024 = 1/16
-- SST
-
+ -- Expected subband amplitude gain relative to input WG amplitude -1 for divide by 2 in two real input separate (Ampl --> Ampl/2)
+ -- . default assume c_fir_filter_dc_gain ~= 1.0, like with c_fil_lofar1_fir_filter_dc_gain = 0.994817
+ CONSTANT c_fir_filter_dc_gain : REAL := sel_a_b(c_pfs_lofar1, c_fil_lofar1_fir_filter_dc_gain, 1.0);
+ CONSTANT c_pfb_sub_scaling : REAL := func_wpfb_subband_gain(c_wpfb, c_fir_filter_dc_gain);
+
+ CONSTANT c_exp_sub_a_ampl : REAL := c_wg_ampl_a * c_pfb_sub_scaling;
+ CONSTANT c_exp_sub_b_ampl : REAL := c_wg_ampl_b * c_pfb_sub_scaling;
+
+ -- Use 1 as integration interval, because measured sst_wg_power_a,b is normalized for c_N_blk
+ CONSTANT c_exp_sst_a : REAL := func_wpfb_sst_level(c_exp_sub_a_ampl, 1);
+ CONSTANT c_exp_sst_b : REAL := func_wpfb_sst_level(c_exp_sub_b_ampl, 1);
+
-- TB
SIGNAL bs_end : STD_LOGIC := '0';
SIGNAL tb_end : STD_LOGIC := '0';
@@ -798,12 +801,11 @@ BEGIN
sub_b_re_frac <= out_re WHEN rising_edge(dp_clk) AND out_bin = c_bin_b + 1 AND out_val_b = '1';
sub_b_im_frac <= out_im WHEN rising_edge(dp_clk) AND out_bin = c_bin_b + 1 AND out_val_b = '1';
- -- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0, also must use brackets (ABS()) to avoid compile error
- sub_a_ampl <= SQRT((ABS(REAL(sub_a_re)))**2.0 + (ABS(REAL(sub_a_im)))**2.0);
- sub_a_ampl_frac <= SQRT((ABS(REAL(sub_a_re_frac)))**2.0 + (ABS(REAL(sub_a_im_frac)))**2.0);
+ sub_a_ampl <= COMPLEX_RADIUS(sub_a_re, sub_a_im);
+ sub_a_ampl_frac <= COMPLEX_RADIUS(sub_a_re_frac, sub_a_im_frac);
- sub_b_ampl <= SQRT((ABS(REAL(sub_b_re)))**2.0 + (ABS(REAL(sub_b_im)))**2.0);
- sub_b_ampl_frac <= SQRT((ABS(REAL(sub_b_re_frac)))**2.0 + (ABS(REAL(sub_b_im_frac)))**2.0);
+ sub_b_ampl <= COMPLEX_RADIUS(sub_b_re, sub_b_im);
+ sub_b_ampl_frac <= COMPLEX_RADIUS(sub_b_re_frac, sub_b_im_frac);
---------------------------------------------------------------------------
-- Measure ADC/WG input mean (DC) and power, and determine sine amplitude
@@ -983,8 +985,6 @@ BEGIN
print_str(". g_fft_stage_dat_w = " & int_to_str(g_fft_stage_dat_w));
print_str(". g_fft_guard_w = " & int_to_str(g_fft_guard_w));
print_str(". c_switch_en = " & slv_to_str(slv(c_switch_en)));
- print_str(". g_r2_mul_extra_w = " & int_to_str(g_r2_mul_extra_w));
- print_str(". g_sepa_extra_w = " & int_to_str(g_sepa_extra_w));
END IF;
IF g_sel_pfb="PFB2" THEN
print_str("-------------------------------------------------------------");
@@ -1026,6 +1026,7 @@ BEGIN
print_str(". sub_a_re = " & int_to_str(sub_a_re));
print_str(". sub_a_im = " & int_to_str(sub_a_im));
print_str(". sub_a_ampl = " & real_to_str(sub_a_ampl, 10, 3));
+ print_str(". sub_a_ampl/c_exp_sub_a_ampl = " & real_to_str(sub_a_ampl/c_exp_sub_a_ampl, 10, 6));
print_str(". sub_a_re_frac = " & int_to_str(sub_a_re_frac));
print_str(". sub_a_im_frac = " & int_to_str(sub_a_im_frac));
print_str(". sub_a_ampl_frac = " & real_to_str(sub_a_ampl_frac, 10, 3));
@@ -1036,6 +1037,7 @@ BEGIN
print_str("");
print_str("Powers:");
print_str(". sst_wg_power_a = " & real_to_str(sst_wg_power_a, 15, 3) & " = " & real_to_str(sst_wg_power_a_dB, 7, 2) & " [dB]");
+ print_str(". sst_wg_power_a/c_exp_sst_a = " & real_to_str(sst_wg_power_a/c_exp_sst_a, 10, 6));
print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3) & " = " & real_to_str(sst_noise_a_dB, 7, 2) & " [dB]");
print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3) & " = " & real_to_str(sst_noise_b_dB, 7, 2) & " [dB]"); -- FFT cross talk power from a to b (if g_amplitude_b = 0)
print_str("");
@@ -1069,6 +1071,7 @@ BEGIN
print_str(". sub_b_re = " & int_to_str(sub_b_re));
print_str(". sub_b_im = " & int_to_str(sub_b_im));
print_str(". sub_b_ampl = " & real_to_str(sub_b_ampl, 10, 3));
+ print_str(". sub_b_ampl/c_exp_sub_b_ampl = " & real_to_str(sub_b_ampl/c_exp_sub_b_ampl, 10, 6));
print_str(". sub_b_re_frac = " & int_to_str(sub_b_re_frac));
print_str(". sub_b_im_frac = " & int_to_str(sub_b_im_frac));
print_str(". sub_b_ampl_frac = " & real_to_str(sub_b_ampl_frac, 10, 3));
@@ -1078,6 +1081,7 @@ BEGIN
print_str(". fil_phase_Ts_b = " & real_to_str(fil_phase_Ts_b, 10, 3));
print_str("Powers:");
print_str(". sst_wg_power_b = " & real_to_str(sst_wg_power_b, 15, 3) & " = " & real_to_str(sst_wg_power_b_dB, 7, 2) & " [dB]");
+ print_str(". sst_wg_power_b/c_exp_sst_b = " & real_to_str(sst_wg_power_b/c_exp_sst_b, 10, 6));
print_str(". sst_noise_b = " & real_to_str(sst_noise_b, 15, 3) & " = " & real_to_str(sst_noise_b_dB, 7, 2) & " [dB]");
print_str(". sst_noise_a = " & real_to_str(sst_noise_a, 15, 3) & " = " & real_to_str(sst_noise_a_dB, 7, 2) & " [dB]"); -- FFT cross talk power from b to a (if g_amplitude_a = 0)
print_str("");
@@ -1101,6 +1105,8 @@ BEGIN
ASSERT almost_equal(fir_ampl_a, fil_ampl_a, 10.0) REPORT "Wrong estimated amplitude for FIR filter output a, " & real_to_str(fir_ampl_a, 7, 0) & " /~= " & real_to_str(fil_ampl_a, 7, 0) SEVERITY ERROR;
ASSERT almost_equal(sub_a_ampl/cw_ampl_a/c_pfb_sub_scaling, 1.0, 0.01)
REPORT "Wrong measured scaling for PFB subband output a, " & real_to_str(sub_a_ampl/cw_ampl_a, 7, 0) & " /~= " & real_to_str(c_pfb_sub_scaling, 7, 0) SEVERITY ERROR;
+ ASSERT almost_equal(sst_wg_power_a/c_exp_sst_a, 1.0, 0.01)
+ REPORT "Wrong measured scaling for PFB SST output a, " & real_to_str(sst_wg_power_a/c_exp_sst_a, 7, 0) & " /~= 1.0" SEVERITY ERROR;
END IF;
tb_end <= '1';
WAIT;
@@ -1117,7 +1123,6 @@ BEGIN
u_wpfb_unit_dev : ENTITY wpfb_lib.wpfb_unit_dev
GENERIC MAP (
g_wpfb => c_wpfb,
- g_wpfb_extra => c_wpfb_extra,
g_coefs_file_prefix => g_fil_coefs_file_prefix
)
PORT MAP (
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
index 5b2aefd0e897ab4d2cf5042836c58a3d990634bc..71d31450368ce939a3edb09a389f35b33b9b1acc 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
@@ -21,6 +21,7 @@
library ieee, common_lib, rTwoSDF_lib, fft_lib, filter_lib;
use IEEE.std_logic_1164.all;
+use IEEE.math_real.all;
use common_lib.common_pkg.all;
use rTwoSDF_lib.rTwoSDFPkg.all;
use fft_lib.fft_pkg.all;
@@ -68,16 +69,62 @@ package wpfb_pkg is
fft_pipeline : t_fft_pipeline; -- Pipeline settings for the parallel FFT
fil_pipeline : t_fil_ppf_pipeline; -- Pipeline settings for the filter units
end record;
-
- -- Extra parameters for the (wideband) poly phase filter, put in new record to show that they are new
- type t_wpfb_extra is record
- r2_mul_extra_w : natural; -- 0 --> 2, extra LSbits at rTwoMult output in rTwoSDFStage to improve FFT stage output requantization
- sepa_extra_w : natural; -- 0 --> 2, extra LSbits in output of last rTwoSDFStage to improve two real separate requantization
- end record;
-
- CONSTANT c_wpfb_extra_none : t_wpfb_extra := (0, 0);
- CONSTANT c_wpfb_extra_lofar20 : t_wpfb_extra := (2, 2);
-
+
+ -----------------------------------------------------------------------------
+ -- LOFAR2 subband filter
+ -----------------------------------------------------------------------------
+
+ -- Fsub settings:
+ -- . Settings used on LTS and DTS until at least March 2022
+ constant c_wpfb_lofar2_subbands_lts_2021 : t_wpfb := (1, 1024, 0, 6,
+ 16, 0, 14, 17, 16,
+ true, false, true, 17, 18, 0, 22, 1, true, 54, 2, 195313,
+ c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
+
+ -- . Settings used on DTS in 2022 with fft_out_dat_w = 18b, to have same levels as with c_wpfb_lofar2_subbands_lts
+ -- - use fil_backoff_w to avoid overshoot and fft_out_gain_w = 1 to compensate to keep output level
+ -- - use stage_dat_w = 24 --> fil_out_dat_w = fft_in_dat_w = 23
+ constant c_wpfb_lofar2_subbands_dts_18b : t_wpfb := (1, 1024, 0, 6,
+ 16, 1, 14, 23, 16,
+ true, false, true, 23, 18, 1, 24, 1, true, 54, 2, 195313,
+ c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
+
+ -- . Settings used on DTS with fft_out_dat_w = 19b, to preserve FFT processing gain of 4.5 bits
+ -- - use stage_dat_w = 25 --> fil_out_dat_w = fft_in_dat_w = 24
+ -- - with fft_out_dat_w = 19 --> stat_data_w = 2*19 + 18 = 56 b
+ constant c_wpfb_lofar2_subbands_dts_19b : t_wpfb := (1, 1024, 0, 6,
+ 16, 1, 14, 24, 16,
+ true, false, true, 24, 19, 1, 25, 1, true, 56, 2, 195313,
+ c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
+
+ constant c_wpfb_lofar2_subbands : t_wpfb := c_wpfb_lofar2_subbands_dts_18b;
+
+ -- The FFT output has more bits to be able to preserve the sensitivity of
+ -- the processing gain of the FFT. The FFT has a processing gain of
+ -- sqrt(N_sub = N_fft / 2 = 512), so 4.5 bits. Therefore choose
+ -- fft_out_dat_w = fil_in_dat_w + 5 = 14 + 5 = 19b. Using fft_out_gain_w =
+ -- 1 compensates for the fil_backoff_w = 1 of the FIR filter. The
+ -- func_wpfb_subband_scale_w then thus returns 19 + 1 - (14 + 1) = 5 bits.
+ function func_wpfb_subband_scale_w(wpfb : t_wpfb) return natural;
+
+ -- The WPFB subband gain is the expected factor between subband amplitude
+ -- A_sub and real signal input amplitude A_sp, so:
+ -- A_sub = A_sp * func_wpfb_subband_gain()
+ -- The WPFB subband gain consists of:
+ -- . DC gain of the FIR filter (= fir_filter_dc_gain ~= 1.0),
+ -- . the FFT gain for a real input (= c_fft_real_input_gain_sine = 0.5) and
+ -- . the extra bits to preserve the sensitivity of the FFT processing gain
+ -- (derived from wpfb).
+ -- For example:
+ -- . func_wpfb_subband_gain() ~= 8 for c_wpfb_lofar2_subbands_lts_2021 and
+ -- for c_wpfb_lofar2_subbands_dts_18b
+ -- . func_wpfb_subband_gain() ~= 16 for c_wpfb_lofar2_subbands_dts_19b
+ function func_wpfb_subband_gain(wpfb : t_wpfb; fir_filter_dc_gain : real) return real;
+
+ -- The expected WPFB SST level for subband amplitude A_sub and an integration
+ -- interval of N_int subband blocks (periods).
+ function func_wpfb_sst_level(A_sub : real; N_int : natural) return real;
+
-----------------------------------------------------------------------------
-- Apertif application specfic settings
-----------------------------------------------------------------------------
@@ -152,7 +199,7 @@ package wpfb_pkg is
-- apertif_unb1_correlator_vis_offload
-- . fft_out_dat_w = 18, because in there is a separate dp_requantize to get from 18b --> 9b in
-- node_apertif_unb1_correlator_processing, this dp_requantize uses symmertical clipping.
- CONSTANT c_wpfb_apertif_channels : t_wpfb := (1, 64, 1, 12,
+ constant c_wpfb_apertif_channels : t_wpfb := (1, 64, 1, 12,
8, 0, 8, 16, 9,
false, false, false, 16, 18, 0, c_dsp_mult_w, 2, true, 56, 2, 12500,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
@@ -177,7 +224,7 @@ package wpfb_pkg is
-- . Using fft_out_dat_w = 12 instead of 9 and fft_out_gain_w = 2 instead of 0 created 12 - 9 - 2 = 1 bit more
-- dynamic range. Therefore it may not be necessary to use fine channel symmetrical clipping using an external
-- dp_requantize, like in Apertif X.
- CONSTANT c_wpfb_arts_channels_sc4 : t_wpfb := (1, 64, 1, 12,
+ constant c_wpfb_arts_channels_sc4 : t_wpfb := (1, 64, 1, 12,
8, 0, 8, 16, 9,
true, true, false, 16, 12, 2, c_dsp_mult_w, 2, true, 56, 2, 12500,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
@@ -193,12 +240,27 @@ package wpfb_pkg is
-- Estimate maximum number of blocks of latency between WPFB input and output
function func_wpfb_maximum_sop_latency(wpfb : t_wpfb) return natural;
- function func_wpfb_set_nof_block_per_sync(wpfb : t_wpfb; nof_block_per_sync : NATURAL) return t_wpfb;
+ function func_wpfb_set_nof_block_per_sync(wpfb : t_wpfb; nof_block_per_sync : natural) return t_wpfb;
end package wpfb_pkg;
package body wpfb_pkg is
+ function func_wpfb_subband_scale_w(wpfb : t_wpfb) return natural is
+ begin
+ return wpfb.fft_out_dat_w + wpfb.fft_out_gain_w - (wpfb.fil_in_dat_w + wpfb.fil_backoff_w);
+ end;
+
+ function func_wpfb_subband_gain(wpfb : t_wpfb; fir_filter_dc_gain : real) return real is
+ begin
+ return fir_filter_dc_gain * c_fft_real_input_gain_sine * 2.0**real(func_wpfb_subband_scale_w(wpfb));
+ end;
+
+ function func_wpfb_sst_level(A_sub : real; N_int : natural) return real is
+ begin
+ return A_sub ** 2.0 * REAL(N_int);
+ end;
+
function func_wpfb_maximum_sop_latency(wpfb : t_wpfb) return natural is
constant c_nof_channels : natural := 2**wpfb.nof_chan;
constant c_block_size : natural := c_nof_channels * wpfb.nof_points / wpfb.wb_factor;
@@ -217,7 +279,7 @@ package body wpfb_pkg is
end func_wpfb_maximum_sop_latency;
-- Overwrite nof_block_per_sync field in wpfb (typically for faster simulation)
- function func_wpfb_set_nof_block_per_sync(wpfb : t_wpfb; nof_block_per_sync : NATURAL) return t_wpfb is
+ function func_wpfb_set_nof_block_per_sync(wpfb : t_wpfb; nof_block_per_sync : natural) return t_wpfb is
variable v_wpfb : t_wpfb;
begin
v_wpfb := wpfb;
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 158f3cb747fb60b86fb13e8ba917f330920df0d1..ae905b69951111ea497fa1c49801a2886790ed0f 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -360,7 +360,6 @@ entity wpfb_unit_dev is
generic (
g_big_endian_wb_in : boolean := true;
g_wpfb : t_wpfb;
- g_wpfb_extra : t_wpfb_extra := c_wpfb_extra_none;
g_dont_flip_channels: boolean := false; -- True preserves channel interleaving for pipelined FFT
g_use_prefilter : boolean := TRUE;
g_stats_ena : boolean := TRUE; -- Enables the statistics unit
@@ -574,8 +573,7 @@ begin
generic map(
g_fft => c_fft, -- generics for the WFFT
g_pft_pipeline => g_wpfb.pft_pipeline,
- g_fft_pipeline => g_wpfb.fft_pipeline,
- g_r2_mul_extra_w => g_wpfb_extra.r2_mul_extra_w
+ g_fft_pipeline => g_wpfb.fft_pipeline
)
port map(
clk => dp_clk,
@@ -597,11 +595,10 @@ begin
gen_fft_r2_pipe_streams: for S in 0 to g_wpfb.nof_wb_streams-1 generate
u_fft_r2_pipe : entity fft_lib.fft_r2_pipe
generic map(
+ g_instance_index => S,
g_fft => c_fft,
g_pipeline => g_wpfb.fft_pipeline,
- g_dont_flip_channels => g_dont_flip_channels,
- g_r2_mul_extra_w => g_wpfb_extra.r2_mul_extra_w,
- g_sepa_extra_w => g_wpfb_extra.sepa_extra_w
+ g_dont_flip_channels => g_dont_flip_channels
)
port map(
clk => dp_clk,
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index 228c1ee4a79b2c0c20664a98a2794ddf4464f208..81cf3f0459c271f926837c3f13515666e53072f4 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -99,7 +99,7 @@ END tech_complex_mult;
ARCHITECTURE str of tech_complex_mult is
- CONSTANT c_dsp_dat_w : NATURAL := sel_a_b(g_in_a_w <= c_dsp_mult_18_w, c_dsp_mult_18_w, c_dsp_mult_27_w); -- g_in_a_w = g_in_b_w
+ CONSTANT c_dsp_dat_w : NATURAL := sel_a_b(g_in_a_w <= c_dsp_mult_18_w AND g_in_b_w <= c_dsp_mult_18_w, c_dsp_mult_18_w, c_dsp_mult_27_w); -- g_in_a_w = g_in_b_w
CONSTANT c_dsp_prod_w : NATURAL := 2*c_dsp_dat_w;
SIGNAL ar : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);