diff --git a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
index 201065eb7e30d3bbbb00ef293d79088d5dbe2bb5..102a636744d821e25dbda308ec28773efaf811dd 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+++ b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
@@ -65,6 +65,22 @@
type = "String";
}
}
+ element reg_tr_10GbE.mem
+ {
+ datum baseAddress
+ {
+ value = "524288";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "12416";
+ type = "long";
+ }
+ }
element reg_diag_data_buffer.mem
{
datum baseAddress
@@ -73,59 +89,59 @@
type = "long";
}
}
- element reg_mmdp_ctrl.mem
+ element reg_diag_bg.mem
{
datum baseAddress
{
- value = "12592";
+ value = "12544";
type = "long";
}
}
- element reg_dp_offload_tx.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "12512";
+ value = "12624";
type = "long";
}
}
- element reg_dp_offload_tx_hdr_ovr.mem
+ element reg_dp_offload_tx_hdr_dat.mem
{
datum baseAddress
{
- value = "512";
+ value = "13312";
type = "long";
}
}
- element reg_dpmm_data.mem
+ element reg_epcs.mem
{
datum baseAddress
{
- value = "12584";
+ value = "12480";
type = "long";
}
}
- element reg_diag_bg.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "12544";
+ value = "16384";
type = "long";
}
}
- element reg_dp_offload_rx_hdr_dat.mem
+ element reg_dpmm_data.mem
{
datum baseAddress
{
- value = "1024";
+ value = "12600";
type = "long";
}
}
- element reg_mmdp_data.mem
+ element reg_io_ddr.mem
{
datum baseAddress
{
- value = "12600";
+ value = "12576";
type = "long";
}
}
@@ -142,56 +158,51 @@
type = "long";
}
}
- element reg_epcs.mem
+ element reg_dp_offload_rx_hdr_dat.mem
{
datum baseAddress
{
- value = "12480";
+ value = "1024";
type = "long";
}
}
- element reg_unb_sens.mem
+ element reg_dpmm_ctrl.mem
{
datum baseAddress
{
- value = "12416";
+ value = "12592";
type = "long";
}
}
- element reg_remu.mem
+ element reg_mmdp_data.mem
{
datum baseAddress
{
- value = "12448";
+ value = "12616";
type = "long";
}
}
- element reg_wdi.mem
+ element reg_dp_offload_tx_hdr_ovr.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "12288";
+ value = "512";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element ram_diag_bg.mem
{
datum baseAddress
{
- value = "524288";
+ value = "262144";
type = "long";
}
}
- element reg_bsn_monitor.mem
+ element ram_diag_data_buffer.mem
{
datum baseAddress
{
- value = "256";
+ value = "65536";
type = "long";
}
}
@@ -203,27 +214,24 @@
type = "long";
}
}
- element reg_dp_offload_tx_hdr_dat.mem
+ element reg_wdi.mem
{
- datum baseAddress
+ datum _lockedAddress
{
- value = "13312";
- type = "long";
+ value = "1";
+ type = "boolean";
}
- }
- element ram_diag_data_buffer.mem
- {
datum baseAddress
{
- value = "65536";
+ value = "12288";
type = "long";
}
}
- element reg_dpmm_ctrl.mem
+ element reg_bsn_monitor.mem
{
datum baseAddress
{
- value = "12576";
+ value = "256";
type = "long";
}
}
@@ -240,27 +248,27 @@
type = "long";
}
}
- element ram_diag_bg.mem
+ element reg_mmdp_ctrl.mem
{
datum baseAddress
{
- value = "262144";
+ value = "12608";
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_dp_offload_tx.mem
{
datum baseAddress
{
- value = "16384";
+ value = "12512";
type = "long";
}
}
- element pio_pps.mem
+ element reg_remu.mem
{
datum baseAddress
{
- value = "12608";
+ value = "12448";
type = "long";
}
}
@@ -434,6 +442,14 @@
type = "int";
}
}
+ element reg_io_ddr
+ {
+ datum _sortIndex
+ {
+ value = "30";
+ type = "int";
+ }
+ }
element reg_mmdp_ctrl
{
datum _sortIndex
@@ -498,11 +514,16 @@
type = "int";
}
}
- element timer_0.s1
+ element onchip_memory2_0.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12320";
+ value = "131072";
type = "long";
}
}
@@ -514,16 +535,11 @@
type = "long";
}
}
- element onchip_memory2_0.s1
+ element timer_0.s1
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "131072";
+ value = "12320";
type = "long";
}
}
@@ -547,10 +563,10 @@
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VHDL" />
<parameter name="maxAdditionalLatency" value="0" />
- <parameter name="projectName" value="unb1_test_10GbE.qpf" />
+ <parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1426850848673" />
+ <parameter name="timeStamp" value="1427787271744" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
@@ -1858,6 +1874,41 @@
internal="ram_ss_ss_wide.reset"
type="conduit"
dir="end" />
+ <interface
+ name="reg_io_ddr_readdata"
+ internal="reg_io_ddr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_read"
+ internal="reg_io_ddr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_writedata"
+ internal="reg_io_ddr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_write"
+ internal="reg_io_ddr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_address"
+ internal="reg_io_ddr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_clk"
+ internal="reg_io_ddr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_io_ddr_reset"
+ internal="reg_io_ddr.reset"
+ type="conduit"
+ dir="end" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="125000000" />
<parameter name="clockFrequencyKnown" value="true" />
@@ -2098,7 +2149,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_unb_sens.mem' start='0x3080' end='0x30A0' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' /><slave name='reg_epcs.mem' start='0x30C0' end='0x30E0' /><slave name='reg_dp_offload_tx.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg.mem' start='0x3100' end='0x3120' /><slave name='reg_dpmm_ctrl.mem' start='0x3120' end='0x3128' /><slave name='reg_dpmm_data.mem' start='0x3128' end='0x3130' /><slave name='reg_mmdp_ctrl.mem' start='0x3130' end='0x3138' /><slave name='reg_mmdp_data.mem' start='0x3138' end='0x3140' /><slave name='pio_pps.mem' start='0x3140' end='0x3148' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_bg.mem' start='0x40000' end='0x80000' /><slave name='reg_tr_10GbE.mem' start='0x80000' end='0xA0000' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer.mem' start='0x80' end='0x100' /><slave name='reg_bsn_monitor.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_unb_sens.mem' start='0x3080' end='0x30A0' /><slave name='reg_remu.mem' start='0x30A0' end='0x30C0' /><slave name='reg_epcs.mem' start='0x30C0' end='0x30E0' /><slave name='reg_dp_offload_tx.mem' start='0x30E0' end='0x3100' /><slave name='reg_diag_bg.mem' start='0x3100' end='0x3120' /><slave name='reg_io_ddr.mem' start='0x3120' end='0x3130' /><slave name='reg_dpmm_ctrl.mem' start='0x3130' end='0x3138' /><slave name='reg_dpmm_data.mem' start='0x3138' end='0x3140' /><slave name='reg_mmdp_ctrl.mem' start='0x3140' end='0x3148' /><slave name='reg_mmdp_data.mem' start='0x3148' end='0x3150' /><slave name='pio_pps.mem' start='0x3150' end='0x3158' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_data_buffer.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='ram_diag_bg.mem' start='0x40000' end='0x80000' /><slave name='reg_tr_10GbE.mem' start='0x80000' end='0xA0000' /><slave name='ram_ss_ss_wide.mem' start='0xA0000' end='0xB0000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="125000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -2187,6 +2238,11 @@ q]]></parameter>
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_io_ddr">
+ <parameter name="g_adr_w" value="2" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
<connection
kind="avalon"
version="11.1"
@@ -2299,7 +2355,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3120" />
+ <parameter name="baseAddress" value="0x3130" />
</connection>
<connection
kind="avalon"
@@ -2307,7 +2363,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3128" />
+ <parameter name="baseAddress" value="0x3138" />
</connection>
<connection
kind="avalon"
@@ -2315,7 +2371,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3130" />
+ <parameter name="baseAddress" value="0x3140" />
</connection>
<connection
kind="avalon"
@@ -2323,7 +2379,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3138" />
+ <parameter name="baseAddress" value="0x3148" />
</connection>
<connection
kind="avalon"
@@ -2339,7 +2395,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3140" />
+ <parameter name="baseAddress" value="0x3150" />
</connection>
<connection
kind="avalon"
@@ -2867,4 +2923,23 @@ q]]></parameter>
version="11.1"
start="clk_0.clk"
end="ram_ss_ss_wide.system" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_0.clk_reset"
+ end="reg_io_ddr.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_io_ddr.system_reset" />
+ <connection kind="clock" version="11.1" start="clk_0.clk" end="reg_io_ddr.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_io_ddr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3120" />
+ </connection>
</system>
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 0a04a641c735b8251af0620662cedcbfd2d53215..02bed12f68e34436940ff1d88bde9a26f0559a68 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -136,7 +136,10 @@ ENTITY mmm_unb1_test IS
reg_tr_xaui_miso : IN t_mem_miso;
ram_ss_ss_transp_mosi : OUT t_mem_mosi;
- ram_ss_ss_transp_miso : IN t_mem_miso
+ ram_ss_ss_transp_miso : IN t_mem_miso;
+
+ reg_io_ddr_mosi : OUT t_mem_mosi;
+ reg_io_ddr_miso : IN t_mem_miso
);
END mmm_unb1_test;
@@ -202,6 +205,8 @@ ARCHITECTURE str OF mmm_unb1_test IS
SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL i_reset_n : STD_LOGIC;
+
----------------------------------------------------------------------------
@@ -274,6 +279,9 @@ BEGIN
u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+ u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
+ PORT MAP(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
+
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
@@ -327,11 +335,14 @@ BEGIN
----------------------------------------------------------------------------
-- QSYS
----------------------------------------------------------------------------
+ i_reset_n <= NOT mm_rst;
+
gen_qsys : IF g_sim = FALSE GENERATE
+
u_qsys : qsys_unb1_test
PORT MAP (
clk_0 => mm_clk,
- reset_n => NOT mm_rst,
+ reset_n => i_reset_n,
-- the_avs_eth_0
coe_clk_export_from_the_avs_eth_0 => OPEN,
@@ -564,7 +575,16 @@ BEGIN
ram_ss_ss_wide_readdata_export => ram_ss_ss_transp_miso.rddata(c_word_w-1 DOWNTO 0),
ram_ss_ss_wide_reset_export => OPEN,
ram_ss_ss_wide_write_export => ram_ss_ss_transp_mosi.wr,
- ram_ss_ss_wide_writedata_export => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ ram_ss_ss_wide_writedata_export => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- reg_io_ddr
+ reg_io_ddr_address_export => reg_io_ddr_mosi.address(1 DOWNTO 0),
+ reg_io_ddr_clk_export => OPEN,
+ reg_io_ddr_read_export => reg_io_ddr_mosi.rd,
+ reg_io_ddr_readdata_export => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_io_ddr_reset_export => OPEN,
+ reg_io_ddr_write_export => reg_io_ddr_mosi.wr,
+ reg_io_ddr_writedata_export => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 00ee53dcf7b7faf58d48a593b63b886551a24161..bc766fbea91214b65068579100339730f4782347 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -215,7 +215,14 @@ PACKAGE qsys_unb1_test_pkg IS
ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_ss_ss_wide_reset_export : out std_logic; -- export
ram_ss_ss_wide_write_export : out std_logic; -- export
- ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0) -- export
+ ram_ss_ss_wide_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_io_ddr_address_export : out std_logic_vector(1 downto 0);
+ reg_io_ddr_clk_export : out std_logic;
+ reg_io_ddr_read_export : out std_logic;
+ reg_io_ddr_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X');
+ reg_io_ddr_reset_export : out std_logic;
+ reg_io_ddr_write_export : out std_logic;
+ reg_io_ddr_writedata_export : out std_logic_vector(31 downto 0)
);
end component qsys_unb1_test;
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index fa70177f5bec9ea478a02d1c583a694381653551..b118e0b49176c70a276d42ac725a4079080a83ec 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -382,6 +382,8 @@ ARCHITECTURE str OF unb1_test IS
SIGNAL from_mem_siso2 : t_dp_siso := c_dp_siso_rdy;
SIGNAL from_mem_sosi2 : t_dp_sosi;
+ SIGNAL reg_io_ddr_mosi : t_mem_mosi;
+ SIGNAL reg_io_ddr_miso : t_mem_miso;
-- SIGNAL seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0);
-- SIGNAL parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0);
BEGIN
@@ -502,6 +504,9 @@ BEGIN
ETH_SGOUT => ETH_SGOUT
);
+ --dp_clk <= CLK;
+ --dp_rst <= mm_rst;
+
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
@@ -599,7 +604,10 @@ BEGIN
reg_tr_xaui_miso => reg_tr_xaui_miso,
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
- ram_ss_ss_transp_miso => ram_ss_ss_transp_miso
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso
);
@@ -987,6 +995,12 @@ BEGIN
g_rd_data_w => c_st_dat_w
)
PORT MAP (
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ reg_io_ddr_mosi => reg_io_ddr_mosi,
+ reg_io_ddr_miso => reg_io_ddr_miso,
+
ctlr_ref_clk => dp_clk,
ctlr_ref_rst => dp_rst,