diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd
index 5cacff24528788878d3c3bcdb7381e29931adc58..f88e7b63966dd85fe14088400947308d1d128fd2 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/pack.vhd
@@ -4,13 +4,17 @@ USE dp_lib.dp_stream_pkg.ALL;
ENTITY pack IS
GENERIC (
+
g_nof_streams : POSITIVE := 12;
- g_data_w : NATURAL := 14
+ g_data_w : NATURAL := 14
+
);
PORT (
- clk : IN STD_LOGIC;
- in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0)
+
+ clk : IN STD_LOGIC;
+ in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+ out_data : OUT STD_LOGIC_VECTOR((g_nof_streams*g_data_w)-1 DOWNTO 0)
+
);
END pack;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_pack.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_pack.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..11817d27a93627b171e749097f0478a6bfebb569
--- /dev/null
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_pack.vhd
@@ -0,0 +1,114 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, technology_lib, tech_ddr_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_ddr_lib.tech_ddr_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY tb_pack IS
+ GENERIC (
+
+ g_nof_streams : POSITIVE := 12;
+ g_data_w : NATURAL := 14;
+ g_sim_model : BOOLEAN := TRUE
+
+ );
+END tb_pack;
+
+ARCHITECTURE tb OF tb_pack IS
+
+ CONSTANT c_clk_freq : NATURAL := 200; -- MHz
+ CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps;
+
+ CONSTANT c_data_w : NATURAL := g_nof_streams * g_data_w; -- 168
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+
+ SIGNAL clk : STD_LOGIC := '1';
+
+ SIGNAL in_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_init);
+
+ SIGNAL out_data : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+
+BEGIN
+
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2;
+
+ p_mm : PROCESS
+ BEGIN
+
+ tb_end <= '0';
+
+ WAIT UNTIL rising_edge(clk); -- align to rising edge
+ WAIT FOR c_clk_period*2;
+
+ in_sosi_arr(0).data(g_data_w - 1 DOWNTO 0) <= "11111111111111";
+ in_sosi_arr(1).data(g_data_w - 1 DOWNTO 0) <= "11111111111100";
+ in_sosi_arr(2).data(g_data_w - 1 DOWNTO 0) <= "11111111110000";
+ in_sosi_arr(3).data(g_data_w - 1 DOWNTO 0) <= "11111111000000";
+ in_sosi_arr(4).data(g_data_w - 1 DOWNTO 0) <= "11111100000000";
+ in_sosi_arr(5).data(g_data_w - 1 DOWNTO 0) <= "11110000000000";
+ in_sosi_arr(6).data(g_data_w - 1 DOWNTO 0) <= "11000000000000";
+ in_sosi_arr(7).data(g_data_w - 1 DOWNTO 0) <= "00000000000000";
+ in_sosi_arr(8).data(g_data_w - 1 DOWNTO 0) <= "00000000000011";
+ in_sosi_arr(9).data(g_data_w - 1 DOWNTO 0) <= "00000000001111";
+ in_sosi_arr(10).data(g_data_w - 1 DOWNTO 0) <= "00000000111111";
+ in_sosi_arr(11).data(g_data_w - 1 DOWNTO 0) <= "00000011111111";
+
+ for_loop : FOR J IN 0 TO 4 LOOP
+ WAIT FOR c_clk_period*1;
+ gen_switch_data : FOR I IN 0 TO g_nof_streams-1 LOOP
+ in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0) <= NOT in_sosi_arr(I).data(g_data_w - 1 DOWNTO 0);
+ END LOOP;
+ END LOOP;
+
+ WAIT FOR c_clk_period*4;
+
+ tb_end <= '1';
+
+ WAIT;
+ END PROCESS;
+
+ u_pack : ENTITY work.pack
+ GENERIC MAP (
+ g_nof_streams => g_nof_streams,
+ g_data_w => g_data_w
+ )
+ PORT MAP (
+ clk => clk,
+ in_sosi_arr => in_sosi_arr,
+
+ out_data => out_data
+ );
+
+END tb;
+
+
+
+
+