From 9419afdb74773cf966e5f14eac89b130ada723cb Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Tue, 3 Nov 2020 10:16:36 +0100
Subject: [PATCH] L2SDP-180, now with checks
---
.../common/src/vhdl/common_variable_delay.vhd | 57 +++++-----
.../tb/vhdl/tb_common_variable_delay.vhd | 101 ++++++++++--------
2 files changed, 81 insertions(+), 77 deletions(-)
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index c5be42f723..33876f3e20 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -33,13 +33,11 @@ USE work.common_pkg.ALL;
ENTITY common_variable_delay IS
- --GENERIC (
- --);
PORT (
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
- delay : IN NATURAL := 0;
+ delay : IN NATURAL := 0;
enable : IN STD_LOGIC := '0';
in_val : IN STD_LOGIC;
out_val : OUT STD_LOGIC
@@ -53,44 +51,39 @@ ARCHITECTURE rtl OF common_variable_delay IS
SIGNAL nxt_i_out_val : STD_LOGIC;
SIGNAL delay_cnt : NATURAL;
SIGNAL nxt_delay_cnt : NATURAL;
- SIGNAL in_val_hold : STD_LOGIC;
- SIGNAL nxt_in_val_hold : STD_LOGIC;
+ SIGNAL in_val_lock : STD_LOGIC;
+ SIGNAL nxt_in_val_lock : STD_LOGIC;
BEGIN
- out_val <= i_out_val AND enable;
+ out_val <= i_out_val; -- AND enable;
- p_delay: PROCESS(delay, in_val, i_out_val, delay_cnt, in_val_hold)
+ p_delay: PROCESS(enable, delay, in_val, i_out_val, delay_cnt, in_val_lock)
BEGIN
- nxt_i_out_val <= i_out_val;
- nxt_delay_cnt <= delay_cnt;
- nxt_in_val_hold <= in_val_hold;
-
- IF delay = 0 THEN
- nxt_i_out_val <= in_val;
- ELSE
- IF RISING_EDGE(in_val) AND in_val_hold = '0' THEN
- nxt_in_val_hold <= '1';
- nxt_delay_cnt <= 1;
- END IF;
-
- IF in_val_hold = '1' AND i_out_val = '1' THEN
- nxt_in_val_hold <= '0';
+ nxt_i_out_val <= '0';
+ nxt_delay_cnt <= delay_cnt + 1;
+ nxt_in_val_lock <= in_val_lock;
+
+ IF enable = '1' THEN
+ IF rising_edge(in_val) THEN
+ nxt_in_val_lock <= '1';
+ IF delay = 0 THEN
+ nxt_delay_cnt <= 0;
+ END IF;
END IF;
- IF in_val_hold = '1' THEN
- nxt_delay_cnt <= delay_cnt + 1;
+ IF nxt_in_val_lock = '0' THEN
+ nxt_delay_cnt <= 0;
END IF;
- IF i_out_val = '1' THEN
- nxt_i_out_val <= '0';
- END IF;
-
- IF delay_cnt = delay THEN
+ IF nxt_delay_cnt = (delay+1) THEN
nxt_i_out_val <= '1';
- nxt_in_val_hold <= '0';
- --nxt_delay_cnt <= 0;
+ nxt_in_val_lock <= '0';
END IF;
+ ELSE
+ nxt_delay_cnt <= 0;
+ nxt_in_val_lock <= '0';
END IF;
+
END PROCESS;
p_clk : PROCESS(rst, clk)
@@ -98,11 +91,11 @@ BEGIN
IF rst = '1' THEN
i_out_val <= '0';
delay_cnt <= 0;
- in_val_hold <= '0';
+ in_val_lock <= '0';
ELSIF rising_edge(clk) THEN
i_out_val <= nxt_i_out_val;
delay_cnt <= nxt_delay_cnt;
- in_val_hold <= nxt_in_val_hold;
+ in_val_lock <= nxt_in_val_lock;
END IF;
END PROCESS;
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index d25232b835..41db5ceadb 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -23,6 +23,7 @@ LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.common_pkg.ALL;
+USE work.common_str_pkg.ALL;
USE work.tb_common_pkg.ALL;
ENTITY tb_common_variable_delay IS
@@ -30,66 +31,79 @@ END tb_common_variable_delay;
ARCHITECTURE tb OF tb_common_variable_delay IS
- CONSTANT clk_period : TIME := 10 ns;
- CONSTANT max_delay : NATURAL := 5;
+ CONSTANT c_clk_period : TIME := 10 ns;
+ CONSTANT c_trigger_interval : NATURAL := 40; -- in clk's
+ CONSTANT c_trigger_latency : NATURAL := 3; -- in clk's
+ CONSTANT c_delay_arr : t_natural_arr(0 TO 3) := (0, 1, 3, 12);
- SIGNAL tb_end : STD_LOGIC := '0';
-
- SIGNAL rst : STD_LOGIC;
- SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL rst : STD_LOGIC;
+ SIGNAL clk : STD_LOGIC := '0';
- SIGNAL delay : NATURAL := 0;
- SIGNAL enable : STD_LOGIC := '0';
- SIGNAL trigger : STD_LOGIC;
- SIGNAL trigger_dly : STD_LOGIC;
+ SIGNAL delay : NATURAL := 0;
+ SIGNAL enable : STD_LOGIC := '0';
+ SIGNAL trigger : STD_LOGIC := '0';
+ SIGNAL trigger_dly : STD_LOGIC := '0';
+ SIGNAL clk_cnt : NATURAL := 0;
BEGIN
- clk <= (NOT clk) OR tb_end AFTER clk_period/2;
- rst <= '1', '0' AFTER clk_period*3;
+ clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
+ rst <= '1', '0' AFTER c_clk_period*4;
+
+ -- generate trigger signal
+ p_trigger : PROCESS
+ BEGIN
+ WAIT UNTIL rst = '0';
+ proc_common_wait_some_cycles(clk, 10);
+ WAIT UNTIL rising_edge(clk);
+ WHILE tb_end = '0' LOOP
+ trigger <= NOT trigger;
+ proc_common_wait_some_cycles(clk, c_trigger_interval/2);
+ END LOOP;
+ WAIT;
+ END PROCESS;
+
- -- run 1 us
p_in_stimuli : PROCESS
BEGIN
- delay <= 0;
- enable <= '0';
- trigger <= '0';
+ delay <= 0;
+ enable <= '0';
WAIT UNTIL rst = '0';
WAIT UNTIL rising_edge(clk);
- -- Start counting
- enable <= '0';
+ -- If enable = 0, no trigger_dly is expected, see wave-window
proc_common_wait_some_cycles(clk, 50);
- FOR i IN 0 TO 10 LOOP
- trigger <= '1';
- proc_common_wait_some_cycles(clk, 4);
- trigger <= '0';
- proc_common_wait_some_cycles(clk, 4);
- END LOOP;
+
enable <= '1';
- FOR i IN 0 TO 10 LOOP
- trigger <= '1';
- proc_common_wait_some_cycles(clk, 4);
- trigger <= '0';
- proc_common_wait_some_cycles(clk, 4);
+ -- enable trigger output and count clk's between trigger lo-hi and trigger_dly lo-hi
+ -- check if counted clk's = c_trigger_latency + delay
+ FOR i IN 0 TO c_delay_arr'LENGTH-1 LOOP
+ delay <= c_delay_arr(i);
+ clk_cnt <= 0;
+ proc_common_wait_until_lo_hi(clk, trigger);
+ WHILE trigger_dly = '0' LOOP
+ clk_cnt <= clk_cnt + 1;
+ proc_common_wait_some_cycles(clk, 1);
+ END LOOP;
+ ASSERT clk_cnt = (c_trigger_latency + delay) REPORT "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency+delay) SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 10);
END LOOP;
- delay <= 1;
- FOR i IN 0 TO 10 LOOP
- trigger <= '1';
- proc_common_wait_some_cycles(clk, 4);
- trigger <= '0';
- proc_common_wait_some_cycles(clk, 4);
+ -- If delay > trigger interval, trigger lo-hi shold not start new delay, see also wave window
+ delay <= c_trigger_interval+2;
+ clk_cnt <= 0;
+ proc_common_wait_until_lo_hi(clk, trigger);
+ WHILE trigger_dly = '0' LOOP
+ clk_cnt <= clk_cnt + 1;
+ proc_common_wait_some_cycles(clk, 1);
END LOOP;
+ ASSERT clk_cnt = (c_trigger_latency + delay) REPORT "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency+delay) SEVERITY ERROR;
+ proc_common_wait_some_cycles(clk, 10);
- delay <= 12;
- FOR i IN 0 TO 10 LOOP
- trigger <= '1';
- proc_common_wait_some_cycles(clk, 4);
- trigger <= '0';
- proc_common_wait_some_cycles(clk, 4);
- END LOOP;
+ enable <= '0';
+ proc_common_wait_some_cycles(clk, 10);
tb_end <= '1';
@@ -98,9 +112,6 @@ BEGIN
-- device under test
u_dut : ENTITY work.common_variable_delay
- GENERIC MAP (
- g_max_delay => max_delay
- )
PORT MAP (
rst => rst,
clk => clk,
--
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