diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 3661f25e565078f9cf693c7d68946687b9285f4a..890a3ff711e7f426b05b94b64b9f8adc9326bae6 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -47,9 +47,12 @@ package tech_jesd204b_component_pkg is
);
port (
-- JESD204B external signals
- jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
- jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock
+ -- reference pin
+ jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase with
+ -- respect to jesd204b_device_clk
+ jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization /
+ -- syncronization phase
-- Data to fabric
rx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data out to fabric
@@ -72,6 +75,42 @@ package tech_jesd204b_component_pkg is
);
end component;
+ component ip_arria10_e1sg_jesd204b_v2 is
+ generic (
+ g_sim : boolean := false;
+ g_nof_streams : natural := 1;
+ g_nof_sync_n : natural := 1;
+ g_direction : string := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_jesd_freq : string := "200MHz"
+ );
+ port (
+ -- JESD204B external signals
+ jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock
+ -- reference pin
+ jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase with
+ -- respect to jesd204b_device_clk
+ jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization /
+ -- syncronization phase
+
+ -- Data to fabric
+ dp_clk : in std_logic;
+ dp_rst : in std_logic;
+ dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
+
+ -- MM Control
+ mm_clk : in std_logic;
+ mm_rst : in std_logic;
+ jesd204b_disable_arr : in std_logic_vector(g_nof_streams - 1 downto 0);
+
+ jesd204b_mosi : in t_mem_mosi; -- mm control
+ jesd204b_miso : out t_mem_miso;
+
+ -- Serial connections to transceiver pins
+ serial_tx_arr : out std_logic_vector(g_nof_streams - 1 downto 0); -- Not used for ADC
+ serial_rx_arr : in std_logic_vector(g_nof_streams - 1 downto 0)
+ );
+ end component;
+
------------------------------------------------------------------------------
-- TX ONLY, 1 channel
------------------------------------------------------------------------------
@@ -142,9 +181,12 @@ package tech_jesd204b_component_pkg is
);
port (
-- JESD204B external signals
- jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
- jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
- jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock
+ -- reference pin
+ jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase with
+ -- respet to jesd204b_device_clk
+ jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization /
+ -- syncronization phase
-- Data to fabric
rx_src_out_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data out to fabric
@@ -167,6 +209,42 @@ package tech_jesd204b_component_pkg is
);
end component;
+ component ip_arria10_e2sg_jesd204b_v2 is
+ generic (
+ g_sim : boolean := false;
+ g_nof_streams : natural := 1;
+ g_nof_sync_n : natural := 1;
+ g_direction : string := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_jesd_freq : string := "200MHz"
+ );
+ port (
+ -- JESD204B external signals
+ jesd204b_refclk : in std_logic := '0'; -- Reference clock. For AD9683 use 200MHz direct from clock
+ -- reference pin
+ jesd204b_sysref : in std_logic := '0'; -- SYSREF should drive ADC and FPGA with correct phase with
+ -- respect to jesd204b_device_clk
+ jesd204b_sync_n_arr : out std_logic_vector(g_nof_sync_n - 1 downto 0); -- output to control ADC initialization /
+ -- syncronization phase
+
+ -- Data to fabric
+ dp_clk : in std_logic;
+ dp_rst : in std_logic;
+ dp_sosi_arr : out t_dp_sosi_arr(g_nof_streams - 1 downto 0); -- Parallel data and sync to fabric
+
+ -- MM Control
+ mm_clk : in std_logic;
+ mm_rst : in std_logic;
+ jesd204b_disable_arr : in std_logic_vector(g_nof_streams - 1 downto 0);
+
+ jesd204b_mosi : in t_mem_mosi; -- mm control
+ jesd204b_miso : out t_mem_miso;
+
+ -- Serial connections to transceiver pins
+ serial_tx_arr : out std_logic_vector(g_nof_streams - 1 downto 0); -- Not used for ADC
+ serial_rx_arr : in std_logic_vector(g_nof_streams - 1 downto 0)
+ );
+ end component;
+
-- TX ONLY, 1 channel
component ip_arria10_e2sg_jesd204b_tx is
port (