diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd index f2037baea1eba75d1b831865ccf0a6688dc2a91b..6ffed7b0a82c3bb9da46471a609a84529025b028 100644 --- a/libraries/technology/eth_10g/tech_eth_10g.vhd +++ b/libraries/technology/eth_10g/tech_eth_10g.vhd @@ -50,6 +50,7 @@ ENTITY tech_eth_10g IS GENERIC ( g_technology : NATURAL := c_tech_select_default; g_sim : BOOLEAN := FALSE; + g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model g_nof_channels : NATURAL := 1; g_link_status_check : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11"; g_pre_header_padding : BOOLEAN := FALSE @@ -58,6 +59,7 @@ ENTITY tech_eth_10g IS -- Transceiver PLL reference clock tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R tr_ref_clk_156 : IN STD_LOGIC := '0'; -- 156.25 MHz for XAUI + tr_ref_rst_156 : IN STD_LOGIC := '0'; -- for XAUI -- Calibration & reconfig clock cal_rec_clk : IN STD_LOGIC := '0'; -- for XAUI; @@ -111,6 +113,7 @@ BEGIN u0 : ENTITY work.tech_eth_10g_stratixiv GENERIC MAP ( g_sim => g_sim, + g_sim_level => g_sim_level, g_nof_channels => g_nof_channels, g_link_status_check => g_link_status_check, g_pre_header_padding => g_pre_header_padding @@ -118,6 +121,7 @@ BEGIN PORT MAP ( -- Transceiver PLL reference clock tr_ref_clk_156 => tr_ref_clk_156, + tr_ref_rst_156 => tr_ref_rst_156, -- Calibration & reconfig clock cal_rec_clk => cal_rec_clk, @@ -156,6 +160,7 @@ BEGIN u0 : ENTITY work.tech_eth_10g_arria10 GENERIC MAP ( g_sim => g_sim, + g_sim_level => g_sim_level, g_nof_channels => g_nof_channels, g_link_status_check => g_link_status_check, g_pre_header_padding => g_pre_header_padding