diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd index 715fea29d700940de060ebd96fe6117c94ae84f1..4dc0c47b99f95ed7b3aafb7a8f894382a97dc879 100644 --- a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd +++ b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd @@ -89,7 +89,7 @@ BEGIN g_in_new_latency => 1, g_readback => TRUE, g_reg => c_mm_reg, - g_init_reg => TO_UVEC(1, c_word_w) + g_init_reg => RESIZE_UVEC(TO_UVEC(1, c_word_w), c_mem_reg_init_w) ) PORT MAP ( -- Clocks and reset