diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
rename to applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
index 813749edd207c1b261ecdaa78c6e3e9a1e8d593c..99094d9434cb93ed9894873ebe4acabd6632283b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
@@ -1,8 +1,8 @@
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</spirit:library>
- <spirit:name>qsys_lofar2_unb2b_filterbank_reg_bsn_source</spirit:name>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</spirit:library>
+ <spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -774,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
- <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</spirit:library>
+ <spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
@@ -824,6 +824,9 @@
<spirit:displayName>bonusData</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="bonusData">bonusData
{
+ element qsys_lofar2_unb2b_filterbank_reg_bsn_source
+ {
+ }
}
</spirit:value>
</spirit:parameter>
@@ -1406,38 +1409,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.mem" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.system" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.system_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_filterbank_reg_bsn_source.writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
index b545c1e43c6ea6a60258c9545576cf6c9bf790ad..0f0dec9fd0811fd92124d7f67af11d81fabf0f7f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/qsys_lofar2_unb2b_sdp_station.qsys
@@ -414,7 +414,7 @@
type = "String";
}
}
- element reg_bsn_source
+ element reg_bsn_source_v2
{
datum _sortIndex
{
@@ -422,7 +422,7 @@
type = "int";
}
}
- element reg_bsn_source.mem
+ element reg_bsn_source_v2.mem
{
datum baseAddress
{
@@ -1571,38 +1571,33 @@
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_address"
- internal="reg_bsn_source.address"
+ name="reg_bsn_source_v2_address"
+ internal="reg_bsn_source_v2.address"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_clk"
- internal="reg_bsn_source.clk"
+ name="reg_bsn_source_v2_read"
+ internal="reg_bsn_source_v2.read"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_read"
- internal="reg_bsn_source.read"
+ name="reg_bsn_source_v2_readdata"
+ internal="reg_bsn_source_v2.readdata"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_readdata"
- internal="reg_bsn_source.readdata"
+ name="reg_bsn_source_v2_reset"
+ internal="reg_bsn_source_v2.reset"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_reset"
- internal="reg_bsn_source.reset"
+ name="reg_bsn_source_v2_write"
+ internal="reg_bsn_source_v2.write"
type="conduit"
dir="end" />
<interface
- name="reg_bsn_source_write"
- internal="reg_bsn_source.write"
- type="conduit"
- dir="end" />
- <interface
- name="reg_bsn_source_writedata"
- internal="reg_bsn_source.writedata"
+ name="reg_bsn_source_v2_writedata"
+ internal="reg_bsn_source_v2.writedata"
type="conduit"
dir="end" />
<interface
@@ -5295,7 +5290,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_bsn_source.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /><slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_wg.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3200' end='0x3300' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3300' end='0x3400' datawidth='32' /><slave name='reg_sdp_info.mem' start='0x3400' end='0x3440' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x3440' end='0x3480' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0x3480' end='0x34A0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x34A0' end='0x34C0' datawidth='32' /><slave name='reg_epcs.mem' start='0x34C0' end='0x34E0' datawidth='32' /><slave name='reg_remu.mem' start='0x34E0' end='0x3500' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0x3500' end='0x3510' datawidth='32' /><slave name='reg_bf_scale.mem' start='0x3510' end='0x3520' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0x3520' end='0x3528' datawidth='32' /><slave name='reg_dp_selector.mem' start='0x3528' end='0x3530' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0x3530' end='0x3538' datawidth='32' /><slave name='reg_si.mem' start='0x3538' end='0x3540' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x3540' end='0x3548' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x3548' end='0x3550' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3550' end='0x3558' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3558' end='0x3560' datawidth='32' /><slave name='pio_pps.mem' start='0x3560' end='0x3568' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3568' end='0x3570' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x10000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_wg.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_st_sst.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x90000' end='0x98000' datawidth='32' /><slave name='jesd204b.mem' start='0x98000' end='0x9C000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x9C000' end='0x9D000' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -5362,19 +5357,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_cpu_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_cpu_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -6179,19 +6174,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_jesd204b</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_jesd204b</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jesd204b</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -6735,19 +6730,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_jtag_uart_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_jtag_uart_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_jtag_uart_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_jtag_uart_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -7182,19 +7177,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_onchip_memory2_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_onchip_memory2_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_onchip_memory2_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_onchip_memory2_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -8511,19 +8506,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_pio_pps</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_pps</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -9127,19 +9122,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_pio_system_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_system_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_system_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -9678,19 +9673,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_pio_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_pio_wdi</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_pio_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -10371,19 +10366,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_bf_weights</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_bf_weights</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -11603,19 +11598,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_equalizer_gains</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -12219,19 +12214,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_fil_coefs</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_fil_coefs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -12835,19 +12830,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_scrap</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_scrap</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -13451,19 +13446,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -14067,19 +14062,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_bst</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_bst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -14683,19 +14678,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_st_sst</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_st_sst</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -15299,19 +15294,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_ram_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_ram_wg</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_ram_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -15915,19 +15910,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_aduh_monitor</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -16531,19 +16526,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bf_scale</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bf_scale</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -17147,19 +17142,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -17763,19 +17758,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -17790,7 +17785,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_bsn_source"
+ name="reg_bsn_source_v2"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -18376,30 +18371,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</hdlLibraryName>
+ <hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_bsn_source</fileSetName>
- <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source</fileSetFixedName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetName>
+ <fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">../lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip</parameter>
+ <parameter name="logicalView">/home/walle/git-lofar/hdl/build/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -19611,19 +19606,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_selector</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_selector</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -20227,19 +20222,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_shiftram</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -20843,19 +20838,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_dp_xonoff</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -21459,19 +21454,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -22075,19 +22070,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_dpmm_data</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -22691,19 +22686,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_epcs</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -23307,19 +23302,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -23923,19 +23918,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -24539,19 +24534,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_hdr_dat</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_hdr_dat</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -25155,19 +25150,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -25771,19 +25766,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_mmdp_data</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -26387,19 +26382,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -27003,19 +26998,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -27619,19 +27614,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_remu</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -28235,19 +28230,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_sdp_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_sdp_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -28851,19 +28846,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_si</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_si</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_si</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -29467,19 +29462,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_pmbus</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_pmbus</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_pmbus</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -30083,19 +30078,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_unb_sens</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -30699,19 +30694,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_wdi</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_wdi</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_reg_wdi</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -31315,19 +31310,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_reg_wg</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_beamformer_reg_wg</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_reg_wg</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -31931,19 +31926,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_rom_system_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_rom_system_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_rom_system_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_rom_system_info</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -32602,19 +32597,19 @@
<hdlLibraryName>qsys_lofar2_unb2b_sdp_station_timer_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_timer_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_timer_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_lofar2_unb2b_filterbank_timer_0</fileSetName>
+ <fileSetName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetName>
<fileSetFixedName>qsys_lofar2_unb2b_sdp_station_timer_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
@@ -32853,7 +32848,7 @@
kind="avalon"
version="18.0"
start="cpu_0.data_master"
- end="reg_bsn_source.mem">
+ end="reg_bsn_source_v2.mem">
<parameter name="baseAddress" value="0x3480" />
</connection>
<connection
@@ -33123,7 +33118,7 @@
kind="clock"
version="18.0"
start="clk_0.clk"
- end="reg_bsn_source.system" />
+ end="reg_bsn_source_v2.system" />
<connection kind="clock" version="18.0" start="clk_0.clk" end="reg_wg.system" />
<connection
kind="clock"
@@ -33352,7 +33347,7 @@
kind="reset"
version="18.0"
start="clk_0.clk_reset"
- end="reg_bsn_source.system_reset" />
+ end="reg_bsn_source_v2.system_reset" />
<connection
kind="reset"
version="18.0"
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 0fec6f1d887e446beef850d2248d959fff1f41e6..70df4b5df7277eb49c1f646442805263adc76b0b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -65,7 +65,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
index 7f0682d13b962d04ad7545db73bd0739577dfd83..15ce2fe9fa68e7cc5bcfc61a4c97c58615b9b9d2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
@@ -73,11 +73,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
- CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
@@ -86,19 +87,19 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
-- WG
CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
- CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
+ CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
- CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
- CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
-- ADUH
CONSTANT c_mon_buffer_nof_samples : NATURAL := 512; --samples per stream
-- MM
CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
- CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
CONSTANT c_mm_file_reg_aduh_mon : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_ADUH_MONITOR";
@@ -177,6 +178,7 @@ BEGIN
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
g_scope_selected_subband => NATURAL(c_subband_sp_0)
)
PORT MAP (
@@ -236,10 +238,10 @@ BEGIN
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
----------------------------------------------------------------------------
-- Enable WG
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index 8b78dac6c7c19db0abfaf4634afe133ccb08c132..9d999569781b9844f2a354f238a0930e40ea98b1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -71,7 +71,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index 212ea5a0cedd4c771ad18d08931279fdf42ee5d1..f5ac005c34271b70b011c5e43f507457d25f1963 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -80,11 +80,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
CONSTANT c_sa_clk_period : TIME := tech_pll_clk_644_period; -- 644MHz
- CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
- CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
@@ -97,9 +98,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1) / 2; -- in number of lsb
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
- CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
- CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
-- WPFB
CONSTANT c_wb_leakage_bin : NATURAL := c_wpfb_sim.nof_points / c_wpfb_sim.wb_factor; -- = 256, leakage will occur in this bin if FIR wb_factor is reversed
@@ -112,7 +113,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_bf IS
-- MM
CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
- CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
CONSTANT c_mm_file_ram_st_bst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_BST";
@@ -219,6 +220,7 @@ BEGIN
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr,
g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
g_scope_selected_subband => NATURAL(c_subband_sp_0)
)
PORT MAP (
@@ -330,10 +332,10 @@ BEGIN
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
----------------------------------------------------------------------------
-- Enable WG
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index 8cd4f41a0db61adb7803418495e3ed0378d4f65a..bbdd8b6c5416dc4d088a12432b3ef9486c385931 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -70,7 +70,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index f760f1cff64a87ee80a4e0040ebeb37a73761bcc..1a467b6b499c9fa611d9feab9baf1cfdf113c68d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -74,11 +74,12 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
- CONSTANT c_pps_period : NATURAL := 1000;
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
- CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
CONSTANT c_wpfb_sim : t_wpfb := func_wpfb_set_nof_block_per_sync(c_sdp_wpfb_subbands, c_nof_block_per_sync);
CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
@@ -93,7 +94,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
CONSTANT c_wg_ampl_lsb : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl; -- amplitude in number of LSbit resolution steps
- CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_sdp_N_fft*c_nof_block_per_sync);
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
-- WPFB
CONSTANT c_nof_pfb : NATURAL := 1; -- Verifying 1 of c_sdp_P_pfb = 6 pfb to speed up simulation.
@@ -107,7 +108,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
-- MM
CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
- CONSTANT c_mm_file_reg_bsn_source : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
CONSTANT c_mm_file_ram_st_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
@@ -192,6 +193,7 @@ BEGIN
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr,
g_wpfb => c_wpfb_sim,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
g_scope_selected_subband => NATURAL(c_subband_sp_0)
)
PORT MAP (
@@ -250,10 +252,10 @@ BEGIN
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 1, c_nof_block_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
----------------------------------------------------------------------------
-- Enable WG
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index 75afb61dfab930e52372c596fed9cb4a0b11e504..0e2c058d57ea520fe9bf7991b49e1bb95df5e83a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -56,6 +56,7 @@ ENTITY lofar2_unb2b_sdp_station IS
g_factory_image : BOOLEAN := FALSE;
g_protect_addr_range : BOOLEAN := FALSE;
g_wpfb : t_wpfb := c_sdp_wpfb_subbands;
+ g_bsn_nof_clk_per_sync : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M, overide for short simulation
g_scope_selected_subband : NATURAL := 0
);
PORT (
@@ -232,8 +233,8 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
SIGNAL reg_dp_shiftram_miso : t_mem_miso := c_mem_miso_rst;
-- bsn source
- SIGNAL reg_bsn_source_mosi : t_mem_mosi := c_mem_mosi_rst;
- SIGNAL reg_bsn_source_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_bsn_source_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_bsn_source_v2_miso : t_mem_miso := c_mem_miso_rst;
-- bsn scheduler
SIGNAL reg_bsn_scheduler_wg_mosi : t_mem_mosi := c_mem_mosi_rst;
@@ -579,8 +580,8 @@ BEGIN
jesd_ctrl_miso => jesd_ctrl_miso,
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
reg_bsn_scheduler_mosi => reg_bsn_scheduler_wg_mosi,
reg_bsn_scheduler_miso => reg_bsn_scheduler_wg_miso,
reg_wg_mosi => reg_wg_mosi,
@@ -670,7 +671,8 @@ BEGIN
u_ait: ENTITY lofar2_sdp_lib.node_sdp_adc_input_and_timing
GENERIC MAP(
g_technology => g_technology,
- g_sim => g_sim
+ g_sim => g_sim,
+ g_bsn_nof_clk_per_sync => g_bsn_nof_clk_per_sync
)
PORT MAP(
-- clocks and resets
@@ -686,8 +688,8 @@ BEGIN
jesd204b_miso => jesd204b_miso,
reg_dp_shiftram_mosi => reg_dp_shiftram_mosi,
reg_dp_shiftram_miso => reg_dp_shiftram_miso,
- reg_bsn_source_mosi => reg_bsn_source_mosi,
- reg_bsn_source_miso => reg_bsn_source_miso,
+ reg_bsn_source_v2_mosi => reg_bsn_source_v2_mosi,
+ reg_bsn_source_v2_miso => reg_bsn_source_v2_miso,
reg_bsn_scheduler_wg_mosi => reg_bsn_scheduler_wg_mosi,
reg_bsn_scheduler_wg_miso => reg_bsn_scheduler_wg_miso,
reg_wg_mosi => reg_wg_mosi,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index e194d9412f3286d42a7f4b70ab9ab2695b3cc639..41c51dd2529fdc9432f5d82e6a22de87d5acf6a7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -107,8 +107,8 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_dp_shiftram_miso : IN t_mem_miso;
-- Bsn source
- reg_bsn_source_mosi : OUT t_mem_mosi;
- reg_bsn_source_miso : IN t_mem_miso;
+ reg_bsn_source_v2_mosi : OUT t_mem_mosi;
+ reg_bsn_source_v2_miso : IN t_mem_miso;
-- bsn schduler for wg trigger
reg_bsn_scheduler_mosi : OUT t_mem_mosi;
@@ -249,8 +249,8 @@ BEGIN
u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_mosi, reg_dp_shiftram_miso );
- u_mm_file_reg_bsn_source : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE")
- PORT MAP(mm_rst, mm_clk, reg_bsn_source_mosi, reg_bsn_source_miso );
+ u_mm_file_reg_bsn_source_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SOURCE_V2")
+ PORT MAP(mm_rst, mm_clk, reg_bsn_source_v2_mosi, reg_bsn_source_v2_miso );
u_mm_file_reg_bsn_scheduler : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER")
PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_mosi, reg_bsn_scheduler_miso );
@@ -482,13 +482,13 @@ BEGIN
reg_dp_shiftram_write_export => reg_dp_shiftram_mosi.wr,
reg_dp_shiftram_writedata_export => reg_dp_shiftram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- reg_bsn_source_clk_export => OPEN,
- reg_bsn_source_reset_export => OPEN,
- reg_bsn_source_address_export => reg_bsn_source_mosi.address(c_sdp_reg_bsn_source_addr_w-1 DOWNTO 0),
- reg_bsn_source_read_export => reg_bsn_source_mosi.rd,
- reg_bsn_source_readdata_export => reg_bsn_source_miso.rddata(c_word_w-1 DOWNTO 0),
- reg_bsn_source_write_export => reg_bsn_source_mosi.wr,
- reg_bsn_source_writedata_export => reg_bsn_source_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_clk_export => OPEN,
+ reg_bsn_source_v2_reset_export => OPEN,
+ reg_bsn_source_v2_address_export => reg_bsn_source_v2_mosi.address(c_sdp_reg_bsn_source_v2_addr_w-1 DOWNTO 0),
+ reg_bsn_source_v2_read_export => reg_bsn_source_v2_mosi.rd,
+ reg_bsn_source_v2_readdata_export => reg_bsn_source_v2_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_bsn_source_v2_write_export => reg_bsn_source_v2_mosi.wr,
+ reg_bsn_source_v2_writedata_export => reg_bsn_source_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_scheduler_clk_export => OPEN,
reg_bsn_scheduler_reset_export => OPEN,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index 7a30524578af614f7bebb2eae797c37b1c50e4d0..1f8d495b0b7dea61db86c6642e138995248ca9c7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -168,13 +168,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_bsn_scheduler_reset_export : out std_logic; -- export
reg_bsn_scheduler_write_export : out std_logic; -- export
reg_bsn_scheduler_writedata_export : out std_logic_vector(31 downto 0); -- export
- reg_bsn_source_address_export : out std_logic_vector(2 downto 0); -- export
- reg_bsn_source_clk_export : out std_logic; -- export
- reg_bsn_source_read_export : out std_logic; -- export
- reg_bsn_source_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- reg_bsn_source_reset_export : out std_logic; -- export
- reg_bsn_source_write_export : out std_logic; -- export
- reg_bsn_source_writedata_export : out std_logic_vector(31 downto 0); -- export
+ reg_bsn_source_v2_address_export : out std_logic_vector(2 downto 0); -- export
+ reg_bsn_source_v2_clk_export : out std_logic; -- export
+ reg_bsn_source_v2_read_export : out std_logic; -- export
+ reg_bsn_source_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ reg_bsn_source_v2_reset_export : out std_logic; -- export
+ reg_bsn_source_v2_write_export : out std_logic; -- export
+ reg_bsn_source_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_data_buffer_bsn_address_export : out std_logic_vector(4 downto 0); -- export
reg_diag_data_buffer_bsn_clk_export : out std_logic; -- export
reg_diag_data_buffer_bsn_read_export : out std_logic; -- export
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index 3a9ba31cadaa1d8ebbd431ac05edcbba3e9328fe..c2b6942f2a7a57349ae260b8f17091191d80ac55 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -40,7 +40,7 @@ ENTITY node_sdp_adc_input_and_timing IS
GENERIC (
g_technology : NATURAL := c_tech_arria10_e1sg;
g_buf_nof_data : NATURAL := c_sdp_V_si_db;
- g_bsn_sync_timeout : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M, overide for short simulation
+ g_bsn_nof_clk_per_sync : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M, overide for short simulation
g_sim : BOOLEAN := FALSE
);
PORT (
@@ -61,8 +61,8 @@ ENTITY node_sdp_adc_input_and_timing IS
reg_dp_shiftram_miso : OUT t_mem_miso := c_mem_miso_rst;
-- bsn source
- reg_bsn_source_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_bsn_source_miso : OUT t_mem_miso := c_mem_miso_rst;
+ reg_bsn_source_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_bsn_source_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
-- bsn scheduler
reg_bsn_scheduler_wg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
@@ -116,8 +116,6 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
-- Frame parameters TBC
CONSTANT c_bs_bsn_w : NATURAL := 64; --51;
CONSTANT c_bs_block_size : NATURAL := c_sdp_N_fft; -- =1024;
- CONSTANT c_bs_nof_clk_per_sync : NATURAL := 2 * c_sdp_f_adc_MHz * 10**6; -- = 400M, use a sync interval of 2s for testing
- CONSTANT c_bs_nof_block_per_sync : NATURAL := c_bs_nof_clk_per_sync / c_sdp_N_fft; -- = 390625, to have integer number of blocks per sync interval for testing
CONSTANT c_dp_fifo_dc_size : NATURAL := 64;
-- JESD signals
@@ -234,11 +232,11 @@ BEGIN
-----------------------------------------------------------------------------
-- Timestamp
-----------------------------------------------------------------------------
- u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source
+ u_bsn_source_v2 : ENTITY dp_lib.mms_dp_bsn_source_v2
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_block_size => c_bs_block_size,
- g_nof_block_per_sync => c_bs_nof_block_per_sync,
+ g_nof_clk_per_sync => g_bsn_nof_clk_per_sync,
g_bsn_w => c_bs_bsn_w
)
PORT MAP (
@@ -250,8 +248,8 @@ BEGIN
dp_pps => rx_sysref,
-- Memory-mapped clock domain
- reg_mosi => reg_bsn_source_mosi,
- reg_miso => reg_bsn_source_miso,
+ reg_mosi => reg_bsn_source_v2_mosi,
+ reg_miso => reg_bsn_source_v2_miso,
-- Streaming clock domain
bs_sosi => bs_sosi
@@ -364,7 +362,7 @@ BEGIN
u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
GENERIC MAP (
g_nof_streams => 1, -- They're all the same
- g_sync_timeout => g_bsn_sync_timeout,
+ g_sync_timeout => g_bsn_nof_clk_per_sync,
g_bsn_w => c_bs_bsn_w,
g_log_first_bsn => FALSE
)
@@ -391,7 +389,7 @@ BEGIN
g_nof_streams => c_sdp_S_pn,
g_symbol_w => c_sdp_W_adc_jesd,
g_nof_symbols_per_data => 1, -- Wideband factor is 1
- g_nof_accumulations => c_bs_nof_clk_per_sync
+ g_nof_accumulations => g_bsn_nof_clk_per_sync
)
PORT MAP (
-- Memory-mapped clock domain
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index 1122d1727166167e43af0594f72d89dcc0c742a9..c2914456898e87400450a1f40aca3b31c17f431b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -146,7 +146,7 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_wg_addr_w : NATURAL := 2 + ceil_log2(c_sdp_S_pn);
CONSTANT c_sdp_ram_wg_addr_w : NATURAL := 10 + ceil_log2(c_sdp_S_pn);
CONSTANT c_sdp_reg_dp_shiftram_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);
- CONSTANT c_sdp_reg_bsn_source_addr_w : NATURAL := 3;
+ CONSTANT c_sdp_reg_bsn_source_v2_addr_w : NATURAL := 3;
CONSTANT c_sdp_reg_bsn_scheduler_addr_w : NATURAL := 1;
CONSTANT c_sdp_ram_diag_data_buf_bsn_addr_w : NATURAL := ceil_log2(c_sdp_S_pn*c_sdp_V_si_db_large); -- Dimension DB address range for largest DB, so that both the large and the default small DB fit.
CONSTANT c_sdp_reg_diag_data_buf_bsn_addr_w : NATURAL := 1 + ceil_log2(c_sdp_S_pn);