diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index 33b251f5cdb9e291ce4e54697ccd98eb920f33f2..853f266f3017bc3c108d0e40d018fb4b2c396cb6 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -37,15 +37,18 @@ PACKAGE tech_ddr_pkg IS
dm_w : NATURAL; -- = 8;
cs_w : NATURAL; -- = 2;
clk_w : NATURAL; -- = 2;
+ terminationcontrol_w : NATURAL; -- = 14;
END RECORD;
- CONSTANT c_tech_ddr_phy : t_c_tech_ddr_phy := (16, 16, 10, 3, 64, 8, 8, 2, 2);
- CONSTANT c_tech_ddr_phy_4g : t_c_tech_ddr_phy := (15, 15, 10, 3, 64, 8, 8, 2, 2);
+ CONSTANT c_tech_ddr_phy : t_c_tech_ddr_phy := (16, 16, 10, 3, 64, 8, 8, 2, 2, 14);
+ CONSTANT c_tech_ddr_phy_4g : t_c_tech_ddr_phy := (15, 15, 10, 3, 64, 8, 8, 2, 2, 14);
TYPE t_tech_ddr_phy_in IS RECORD
- evt : STD_LOGIC;
- oct_rup : STD_LOGIC;
- oct_rdn : STD_LOGIC;
+ evt : STD_LOGIC; -- event signal is Not Connected to DDR3 PHY
+ oct_rup : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs
+ oct_rdn : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs
+ seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY
+ parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY
END RECORD;
TYPE t_tech_ddr_phy_io IS RECORD
@@ -59,21 +62,23 @@ PACKAGE tech_ddr_pkg IS
END RECORD;
TYPE t_tech_ddr_phy_ou IS RECORD
- a : STD_LOGIC_VECTOR(c_tech_ddr_phy.a_w-1 DOWNTO 0); -- row and column address
- ba : STD_LOGIC_VECTOR(c_tech_ddr_phy.ba_w-1 DOWNTO 0); -- bank address
- dm : STD_LOGIC_VECTOR(c_tech_ddr_phy.dm_w-1 DOWNTO 0); -- data mask bus
- cas_n : STD_LOGIC; -- column address strobe
- ras_n : STD_LOGIC; -- row address strobe
- we_n : STD_LOGIC; -- write enable signal
- reset_n : STD_LOGIC; -- reset signal
- odt : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- on-die termination control signal
- cke : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- clock enable
- cs_n : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- chip select
+ a : STD_LOGIC_VECTOR(c_tech_ddr_phy.a_w-1 DOWNTO 0); -- row and column address
+ ba : STD_LOGIC_VECTOR(c_tech_ddr_phy.ba_w-1 DOWNTO 0); -- bank address
+ dm : STD_LOGIC_VECTOR(c_tech_ddr_phy.dm_w-1 DOWNTO 0); -- data mask bus
+ cas_n : STD_LOGIC; -- column address strobe
+ ras_n : STD_LOGIC; -- row address strobe
+ we_n : STD_LOGIC; -- write enable signal
+ reset_n : STD_LOGIC; -- reset signal
+ odt : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- on-die termination control signal
+ cke : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- clock enable
+ cs_n : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- chip select
+ seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY
+ parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY
END RECORD;
- CONSTANT c_tech_ddr_phy_in_rst : t_tech_ddr_phy_in := ('0', 'X', 'X', 'X');
+ CONSTANT c_tech_ddr_phy_in_rst : t_tech_ddr_phy_in := ('0', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'));
CONSTANT c_tech_ddr_phy_io_rst : t_tech_ddr_phy_io := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0');
- CONSTANT c_tech_ddr_phy_ou_rst : t_tech_ddr_phy_ou := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
+ CONSTANT c_tech_ddr_phy_ou_rst : t_tech_ddr_phy_ou := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), '0', '0', '0', '0', (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
TYPE t_tech_ddr_phy_in_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_in;
TYPE t_tech_ddr_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_io;
@@ -94,10 +99,10 @@ PACKAGE tech_ddr_pkg IS
address_w : NATURAL; -- = 32 = (2**32)*c_tech_ddr_phy.dq_w/c_byte_w bytes
data_w : NATURAL; -- = 256 = rsl * c_tech_ddr_phy.dq_w
maxburstsize : NATURAL; -- = 64
- maxburstsize_w : NATURAL; -- = 8 = ceil_log2(maxburstsize+1)
+ maxburstsize_w : NATURAL; -- = 7 = ceil_log2(maxburstsize+1)
END RECORD;
- CONSTANT c_tech_ddr_ctlr : t_c_tech_ddr_ctlr := (4, 2, 256, 64, 9);
+ CONSTANT c_tech_ddr_ctlr : t_c_tech_ddr_ctlr := (4, 2, 32, 256, 64, 7);
CONSTANT c_tech_ddr_ctrl_nof_latent_reads : NATURAL := 100; -- Due to having a command cue, even after de-asserting read requests, the PHY keeps processing the cued read requests.
-- This makes sure 100 words are still available in the read FIFO after it de-asserted its siso.ready signal towards the ddr3 read side.
@@ -108,17 +113,17 @@ PACKAGE tech_ddr_pkg IS
TYPE t_tech_ddr_miso IS RECORD
rddata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.data_w-1 DOWNTO 0);
- rd : STD_LOGIC;
+ rdval : STD_LOGIC;
waitrequest_n : STD_LOGIC;
END RECORD;
TYPE t_tech_ddr_mosi IS RECORD
- address : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.address_w-1 DOWNTO 0);
- wrdata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.data_w-1 DOWNTO 0);
- wr : STD_LOGIC;
- rd : STD_LOGIC;
- burstbegin : STD_LOGIC;
- burstsize : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.maxburstsize_w-1 DOWNTO 0);
+ address : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.address_w-1 DOWNTO 0);
+ wrdata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.data_w-1 DOWNTO 0);
+ wr : STD_LOGIC;
+ rd : STD_LOGIC;
+ burstbegin : STD_LOGIC;
+ burstsize : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.maxburstsize_w-1 DOWNTO 0);
END RECORD;
END tech_ddr_pkg;