diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
index 138a0b4cba5d0d93d7c91c1c77f0a4cbff200c9c..846e784f55181cb84a27903a7e897ac3d01fa383 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
@@ -1,10 +1,8 @@
README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
-
-1) Description
The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
-The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT.
+The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
+
+For more information see: $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
-2) Issues
-The tb_ip_arria10_tse_sgmii_gx.vhd verifies does not simulate OK (yet).
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index fdef6c52eda5145c7fb7b4e607e3942dac929474..8d029f93eb0a14eb85f9756383d312dfcd205021 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -1,22 +1,17 @@
hdl_lib_name = ip_arria10_tse_sgmii_gx
hdl_library_clause_name = ip_arria10_tse_sgmii_gx_lib
-hdl_lib_uses = common
+hdl_lib_uses = ip_arria10_tse_sgmii_gx_altera_eth_tse_140 common
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
-
synth_files =
+ ip_arria10_tse_sgmii_gx_top.vhd
test_bench_files =
- tb_ip_arria10_tse_sgmii_gx.vhd
+ tb_ip_arria10_tse_sgmii_gx_top.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
-
-quartus_qip_files =
- generated/ip_arria10_tse_sgmii_gx.qip
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/ip/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/ip/compile_ip.tcl
index 0b9d4edb1acd90df5fd68f1b397d84e909f890d1..ac5ebd77a95d7dafd50428084ccb6a7fc3c50b56 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/ip/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/ip/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_gx/generated/sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_gx/ip/generated/sim"
vlib ./work/
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/ip/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/ip/hdllib.cfg
index fdef6c52eda5145c7fb7b4e607e3942dac929474..2a78efb7ebb56c071560663cab46ca3c8262bd5d 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/ip/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/ip/hdllib.cfg
@@ -1,22 +1,17 @@
-hdl_lib_name = ip_arria10_tse_sgmii_gx
-hdl_library_clause_name = ip_arria10_tse_sgmii_gx_lib
-hdl_lib_uses = common
+hdl_lib_name = ip_arria10_tse_sgmii_gx_altera_eth_tse_140
+hdl_library_clause_name = ip_arria10_tse_sgmii_gx_altera_eth_tse_140
+hdl_lib_uses =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+ $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx/ip/compile_ip.tcl
synth_files =
test_bench_files =
- tb_ip_arria10_tse_sgmii_gx.vhd
-
-modelsim_search_libraries =
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
- altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
quartus_qip_files =
generated/ip_arria10_tse_sgmii_gx.qip
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx_top.vhd b/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx_top.vhd
index 31da23915a78862512d28776cf6142bf91f4fd90..404ea376b8ad034dad85dc027b24a28cce11ae8b 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx_top.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx_top.vhd
@@ -589,6 +589,9 @@ BEGIN
WHILE mm_init/='0' LOOP
WAIT UNTIL rising_edge(dp_clk);
END LOOP;
+ WHILE tse_led_link/='1' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, "0000000000010000", 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
@@ -607,7 +610,7 @@ BEGIN
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
- FOR I IN 0 TO 1500 * 2 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ FOR I IN 0 TO 1500 * 4 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
tb_end <= '1';
WAIT;
END PROCESS;
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
index 70a8776c06827a8e20d74f6dcb7b692ccc188013..4fd44f3096f0bc459367d730cb705664b9d309fe 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
@@ -1,11 +1,13 @@
README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+Contents:
1) Porting
2) IP component
3) Compilation, simulation and verification
4) Synthesis
+
1) Porting
The tse_sgmii_lvds IP was ported manually from Quartus v9.1 for Stratix IV to Quartus 14.0a10 for Arria10 by creating it in Qsys using
@@ -45,3 +47,33 @@ No synthesis trials were done, because this will implicitely be done when the IP
generated/ip_arria10_tse_sgmii_lvds.qip
is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+5) Issues
+
+a) Generated ip_arria10_tse_sgmii_lvds.vhd uses IP specific library ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
+
+ The generated ip_arria10_tse_sgmii_lvds.vhd uses library ip_arria10_tse_sgmii_lvds_altera_eth_tse_140. This library needs to be vmap-ed
+ in every design that uses this IP. Therefore to make this library known created it in the ./ip directory with its own hdllib.cfg. The
+ hdllib.cfg defines the IP library:
+
+ hdl_lib_name = ip_arria10_tse_sgmii_lvds
+ hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_lib
+
+ The ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library name is IP specific. The tech_tse/ library should not need to know about it, so
+ therefore use a wrapper in ip_arria10_tse_sgmii_lvds_lib that merely instantiates the IP.
+
+ An alternative would be to directly instantiate the generated IP ip_arria10_tse_sgmii_lvds.vhd in tech_tse_arria10.vhd, but then the
+ ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 also needs to be vmap-ped for the tech_tse library. This vmap could be done with a map_ip.tcl
+ script at the modelsim_compile_ip_files key containing:
+
+ vmap ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 $HDL_BUILD_DIR/modelsim/ip_arria10_tse_sgmii_lvds/work
+
+ However it is preferred not to bother the tech_tse library with such IP level details, so therefore using a seperate ./ip/hdllib.cfg and
+ the ip_arria10_tse_sgmii_lvds_top.vhd wrapper is deemed a better solution.
+
+b) Generated IP uses several more libraries
+
+ The generated IP uses several more libraries. Just as the ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library these other libraries are
+ all mapped to ./work in compile_ip.tcl.
+
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index 036458884bc29ede3e230b788c9382f785a333ae..230634b03a3e38b3c9839df85d9620f7c9bf2f7e 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -1,22 +1,17 @@
hdl_lib_name = ip_arria10_tse_sgmii_lvds
hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_lib
-hdl_lib_uses = common
+hdl_lib_uses = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 common
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
-modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
-
synth_files =
+ ip_arria10_tse_sgmii_lvds_top.vhd
test_bench_files =
- tb_ip_arria10_tse_sgmii_lvds.vhd
+ tb_ip_arria10_tse_sgmii_lvds_top.vhd
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
-
-quartus_qip_files =
- generated/ip_arria10_tse_sgmii_lvds.qip
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/compile_ip.tcl
index 4442185310e7ef3f87eacb16c112b90633acebb8..6973840c9fe59f8078a0be5685d3b53902eda94a 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_lvds/generated/sim"
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/generated/sim"
vlib ./work/
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/hdllib.cfg
index 036458884bc29ede3e230b788c9382f785a333ae..d5e1204466d8cc329f26371ae811e10c555592cb 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/hdllib.cfg
@@ -1,22 +1,17 @@
-hdl_lib_name = ip_arria10_tse_sgmii_lvds
-hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_lib
-hdl_lib_uses = common
+hdl_lib_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
+hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_altera_eth_tse_140
+hdl_lib_uses =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
- $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+ $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/ip/compile_ip.tcl
synth_files =
test_bench_files =
- tb_ip_arria10_tse_sgmii_lvds.vhd
-
-modelsim_search_libraries =
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
- altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
quartus_qip_files =
generated/ip_arria10_tse_sgmii_lvds.qip
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds_top.vhd b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds_top.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d6a52191dae4bdbfa4f611a6026cea67d280839e
--- /dev/null
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/ip_arria10_tse_sgmii_lvds_top.vhd
@@ -0,0 +1,134 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Wrapper for generated ip_arria10_tse_sgmii_lvds.vhd
+-- Description:
+-- This wrapper avoids the need to vmap the ip_arria10_tse_sgmii_lvds_altera_eth_tse_140 library
+-- in the tech_tse library that instantiate this IP.
+-- Remarks:
+-- . Manually created from generated ip_arria10_tse_sgmii_lvds.vhd.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library ip_arria10_tse_sgmii_lvds_altera_eth_tse_140;
+
+entity ip_arria10_tse_sgmii_lvds_top is
+ port (
+ clk : in std_logic := '0'; -- control_port_clock_connection.clk
+ reset : in std_logic := '0'; -- reset_connection.reset
+ reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd : in std_logic := '0'; -- .read
+ reg_data_in : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr : in std_logic := '0'; -- .write
+ reg_busy : out std_logic; -- .waitrequest
+ reg_addr : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ ff_rx_clk : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_tx_clk : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_rx_data : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_eop : out std_logic; -- .endofpacket
+ rx_err : out std_logic_vector(5 downto 0); -- .error
+ ff_rx_mod : out std_logic_vector(1 downto 0); -- .empty
+ ff_rx_rdy : in std_logic := '0'; -- .ready
+ ff_rx_sop : out std_logic; -- .startofpacket
+ ff_rx_dval : out std_logic; -- .valid
+ ff_tx_data : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_eop : in std_logic := '0'; -- .endofpacket
+ ff_tx_err : in std_logic := '0'; -- .error
+ ff_tx_mod : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_rdy : out std_logic; -- .ready
+ ff_tx_sop : in std_logic := '0'; -- .startofpacket
+ ff_tx_wren : in std_logic := '0'; -- .valid
+ ff_tx_crc_fwd : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy : out std_logic; -- .ff_tx_septy
+ tx_ff_uflow : out std_logic; -- .tx_ff_uflow
+ ff_tx_a_full : out std_logic; -- .ff_tx_a_full
+ ff_tx_a_empty : out std_logic; -- .ff_tx_a_empty
+ rx_err_stat : out std_logic_vector(17 downto 0); -- .rx_err_stat
+ rx_frm_type : out std_logic_vector(3 downto 0); -- .rx_frm_type
+ ff_rx_dsav : out std_logic; -- .ff_rx_dsav
+ ff_rx_a_full : out std_logic; -- .ff_rx_a_full
+ ff_rx_a_empty : out std_logic; -- .ff_rx_a_empty
+ led_crs : out std_logic; -- status_led_connection.crs
+ led_link : out std_logic; -- .link
+ led_col : out std_logic; -- .col
+ led_an : out std_logic; -- .an
+ led_char_err : out std_logic; -- .char_err
+ led_disp_err : out std_logic; -- .disp_err
+ rx_recovclkout : out std_logic; -- serdes_control_connection.export
+ ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ rxp : in std_logic := '0'; -- serial_connection.rxp_0
+ txp : out std_logic -- .txp_0
+ );
+end ip_arria10_tse_sgmii_lvds_top;
+
+architecture str of ip_arria10_tse_sgmii_lvds_top is
+begin
+
+ u_ip_arria10_tse_sgmii_lvds : entity ip_arria10_tse_sgmii_lvds_altera_eth_tse_140.ip_arria10_tse_sgmii_lvds
+ port map (
+ clk => clk, -- control_port_clock_connection.clk
+ reset => reset, -- reset_connection.reset
+ reg_data_out => reg_data_out, -- control_port.readdata
+ reg_rd => reg_rd, -- .read
+ reg_data_in => reg_data_in, -- .writedata
+ reg_wr => reg_wr, -- .write
+ reg_busy => reg_busy, -- .waitrequest
+ reg_addr => reg_addr, -- .address
+ ff_rx_clk => ff_rx_clk, -- receive_clock_connection.clk
+ ff_tx_clk => ff_tx_clk, -- transmit_clock_connection.clk
+ ff_rx_data => ff_rx_data, -- receive.data
+ ff_rx_eop => ff_rx_eop, -- .endofpacket
+ rx_err => rx_err, -- .error
+ ff_rx_mod => ff_rx_mod, -- .empty
+ ff_rx_rdy => ff_rx_rdy, -- .ready
+ ff_rx_sop => ff_rx_sop, -- .startofpacket
+ ff_rx_dval => ff_rx_dval, -- .valid
+ ff_tx_data => ff_tx_data, -- transmit.data
+ ff_tx_eop => ff_tx_eop, -- .endofpacket
+ ff_tx_err => ff_tx_err, -- .error
+ ff_tx_mod => ff_tx_mod, -- .empty
+ ff_tx_rdy => ff_tx_rdy, -- .ready
+ ff_tx_sop => ff_tx_sop, -- .startofpacket
+ ff_tx_wren => ff_tx_wren, -- .valid
+ ff_tx_crc_fwd => ff_tx_crc_fwd, -- mac_misc_connection.ff_tx_crc_fwd
+ ff_tx_septy => ff_tx_septy, -- .ff_tx_septy
+ tx_ff_uflow => tx_ff_uflow, -- .tx_ff_uflow
+ ff_tx_a_full => ff_tx_a_full, -- .ff_tx_a_full
+ ff_tx_a_empty => ff_tx_a_empty, -- .ff_tx_a_empty
+ rx_err_stat => rx_err_stat, -- .rx_err_stat
+ rx_frm_type => rx_frm_type, -- .rx_frm_type
+ ff_rx_dsav => ff_rx_dsav, -- .ff_rx_dsav
+ ff_rx_a_full => ff_rx_a_full, -- .ff_rx_a_full
+ ff_rx_a_empty => ff_rx_a_empty, -- .ff_rx_a_empty
+ ref_clk => ref_clk, -- pcs_ref_clk_clock_connection.clk
+ rxp => rxp, -- serial_connection.rxp_0
+ txp => txp, -- .txp_0
+ led_crs => led_crs, -- status_led_connection.crs
+ led_link => led_link, -- .link
+ led_col => led_col, -- .col
+ led_an => led_an, -- .an
+ led_char_err => led_char_err, -- .char_err
+ led_disp_err => led_disp_err, -- .disp_err
+ rx_recovclkout => rx_recovclkout -- serdes_control_connection.export
+ );
+
+end str;
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds_top.vhd b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds_top.vhd
index 596f0127adc9ee9f816f078fe3cbcde1101ec505..d286367caece3e3ef6f9d2fc405e7f298536ac52 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds_top.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds_top.vhd
@@ -19,7 +19,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Testbench for ip_arria10_tse_sgmii_lvds.
+-- Purpose: Testbench for ip_arria10_tse_sgmii_lvds_top.
-- Description:
-- The testbench in /testbench/tse_sgmii_lvds/tse_sgmii_lvds_tb.vhd that is
-- generated by the MegaWizard provides an elaborate testbench. For
@@ -38,11 +38,11 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
-ENTITY tb_ip_arria10_tse_sgmii_lvds IS
-END tb_ip_arria10_tse_sgmii_lvds;
+ENTITY tb_ip_arria10_tse_sgmii_lvds_top IS
+END tb_ip_arria10_tse_sgmii_lvds_top;
-ARCHITECTURE tb OF tb_ip_arria10_tse_sgmii_lvds IS
+ARCHITECTURE tb OF tb_ip_arria10_tse_sgmii_lvds_top IS
CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
@@ -588,6 +588,9 @@ BEGIN
WHILE mm_init/='0' LOOP
WAIT UNTIL rising_edge(dp_clk);
END LOOP;
+ WHILE tse_led_link/='1' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, "0000000000010000", 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
@@ -628,7 +631,7 @@ BEGIN
WAIT;
END PROCESS;
- dut : ENTITY work.ip_arria10_tse_sgmii_lvds
+ dut : ENTITY work.ip_arria10_tse_sgmii_lvds_top
-- The ip_arria10_tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
-- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests