diff --git a/applications/arts/designs/arts_unb2b_sc4_fwd/src/vhdl/arts_unb2b_sc4_fwd.vhd b/applications/arts/designs/arts_unb2b_sc4_fwd/src/vhdl/arts_unb2b_sc4_fwd.vhd
index 70b865e84d5032be0ce03a5504650a3563579f34..8f18962649eca10cbb35ffbc1abe2327b5f6d5c5 100644
--- a/applications/arts/designs/arts_unb2b_sc4_fwd/src/vhdl/arts_unb2b_sc4_fwd.vhd
+++ b/applications/arts/designs/arts_unb2b_sc4_fwd/src/vhdl/arts_unb2b_sc4_fwd.vhd
@@ -33,7 +33,7 @@
 --   . QSFP 4, RX 2 -> QSFP 1, TX 2
 --   . QSFP 5, RX 1 -> QSFP 1, TX 3 
 
-LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, diag_lib, technology_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, eth_lib, tr_10GbE_lib, tech_pll_lib, diag_lib, technology_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
@@ -133,6 +133,7 @@ ARCHITECTURE str OF arts_unb2b_sc4_fwd IS
   -- 10GbE
   CONSTANT c_nof_streams_qsfp       : NATURAL := 24;
   CONSTANT c_nof_qsfp_bus           : NATURAL := 6;
+  CONSTANT c_def_10GbE_block_size   : NATURAL := 700; -- (700/1000) * 200MHz * 64b = 8.96Gbps user rate (excl. header overhead (16 words/packet) )
 
   -- System
   SIGNAL cs_sim                     : STD_LOGIC;
@@ -225,25 +226,29 @@ ARCHITECTURE str OF arts_unb2b_sc4_fwd IS
   SIGNAL reg_remu_miso              : t_mem_miso;
 
   -- 10GbE
-  SIGNAL i_QSFP_TX                                   : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0); 
-  SIGNAL i_QSFP_RX                                   : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
+  SIGNAL tr_ref_clk_312                    : STD_LOGIC;
+  SIGNAL tr_ref_clk_156                    : STD_LOGIC;
+  SIGNAL tr_ref_rst_156                    : STD_LOGIC;
+  
+  SIGNAL i_QSFP_TX                         : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0); 
+  SIGNAL i_QSFP_RX                         : t_unb2_board_qsfp_bus_2arr(c_nof_qsfp_bus-1 DOWNTO 0);
  
-  SIGNAL unb2_board_front_io_serial_tx_arr           : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
-  SIGNAL unb2_board_front_io_serial_rx_arr           : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
+  SIGNAL unb2_board_front_io_serial_tx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS=>'0');
+  SIGNAL unb2_board_front_io_serial_rx_arr : STD_LOGIC_VECTOR(c_nof_streams_qsfp-1 DOWNTO 0);
 
-  SIGNAL unb2_board_10gbe_snk_in_arr                 : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-  SIGNAL unb2_board_10gbe_snk_out_arr                : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
-  SIGNAL unb2_board_10gbe_src_out_arr                : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-  SIGNAL unb2_board_10gbe_src_in_arr                 : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst); 
+  SIGNAL unb2_board_10gbe_snk_in_arr       : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL unb2_board_10gbe_snk_out_arr      : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst);
+  SIGNAL unb2_board_10gbe_src_out_arr      : t_dp_sosi_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+  SIGNAL unb2_board_10gbe_src_in_arr       : t_dp_siso_arr(c_nof_streams_qsfp-1 DOWNTO 0) := (OTHERS => c_dp_siso_rst); 
  
-  SIGNAL reg_tr_10GbE_mac_mosi                 : t_mem_mosi;
-  SIGNAL reg_tr_10GbE_mac_miso                 : t_mem_miso;
+  SIGNAL reg_tr_10GbE_mac_mosi             : t_mem_mosi;
+  SIGNAL reg_tr_10GbE_mac_miso             : t_mem_miso;
 
-  SIGNAL reg_tr_10GbE_eth10g_mosi                   : t_mem_mosi;
-  SIGNAL reg_tr_10GbE_eth10g_miso                   : t_mem_miso;
+  SIGNAL reg_tr_10GbE_eth10g_mosi          : t_mem_mosi;
+  SIGNAL reg_tr_10GbE_eth10g_miso          : t_mem_miso;
 
-  SIGNAL reg_10gbase_r_24_mosi : t_mem_mosi; 
-  SIGNAL reg_10gbase_r_24_miso : t_mem_miso;
+  SIGNAL reg_10gbase_r_24_mosi             : t_mem_mosi; 
+  SIGNAL reg_10gbase_r_24_miso             : t_mem_miso;
   
   -- Interface: 1GbE UDP streaming ports
   SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_1GbE-1 DOWNTO 0);
@@ -319,9 +324,9 @@ BEGIN
       g_technology    => g_technology,
       g_sim           => g_sim,
       g_sim_level     => 1,
-      g_nof_macs      => g_nof_macs,
-      g_tx_fifo_fill  => g_tx_fifo_fill,
-      g_tx_fifo_size  => g_tx_fifo_size
+      g_nof_macs      => c_nof_streams_qsfp,
+      g_tx_fifo_fill  => c_def_10GbE_block_size,
+      g_tx_fifo_size  => c_def_10GbE_block_size*2
     )
     PORT MAP (
       -- Transceiver PLL reference clock