From 919fa3117b305b4e2a0a53f27f22d683ecfa3f00 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 11 Mar 2021 16:31:02 +0100
Subject: [PATCH] Added fpga.yaml for lofar2_unb2b_filterbank and
 peripheral.yaml for peripherals that are new in node_sdp_filterbank.vhd.

---
 .../lofar2_unb2b_filterbank.fpga.yaml         | 168 ++++++++++++++++++
 .../lofar2/libraries/sdp/sdp.peripheral.yaml  |  35 ++++
 libraries/dsp/filter/filter.peripheral.yaml   |  44 +++++
 libraries/dsp/si/si.peripheral.yaml           |  20 +++
 libraries/dsp/st/st.peripheral.yaml           |  69 +++++++
 5 files changed, 336 insertions(+)
 create mode 100644 applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
 create mode 100644 applications/lofar2/libraries/sdp/sdp.peripheral.yaml
 create mode 100644 libraries/dsp/filter/filter.peripheral.yaml
 create mode 100644 libraries/dsp/si/si.peripheral.yaml
 create mode 100644 libraries/dsp/st/st.peripheral.yaml

diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
new file mode 100644
index 0000000000..2270b22c66
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/lofar2_unb2b_filterbank.fpga.yaml
@@ -0,0 +1,168 @@
+schema_name   : args
+schema_version: 1.0
+schema_type   : fpga
+
+hdl_library_name: lofar2_unb2b_filterbank
+fpga_name       : lofar2_unb2b_filterbank
+fpga_description: "FPGA design lofar2_unb2b_filterbank"
+
+peripherals:
+  #############################################################################
+  # Factory / minimal (see ctrl_unb2b_board.vhd)
+  #############################################################################
+  - peripheral_name: unb2b_board/system_info
+    slave_port_names:
+      - ROM_SYSTEM_INFO
+      - PIO_SYSTEM_INFO
+    lock_base_address: 0x10000
+
+  - peripheral_name: unb2b_board/wdi
+    slave_port_names:
+      - PIO_WDI
+
+  - peripheral_name: unb2b_board/unb2_fpga_sens
+    slave_port_names:
+      - REG_FPGA_TEMP_SENS
+      - REG_FPGA_VOLTAGE_SENS
+    
+  - peripheral_name: unb2b_board/ram_scrap
+    slave_port_names:
+      - RAM_SCRAP
+      
+  - peripheral_name: eth/eth
+    slave_port_names:
+      - AVS_ETH_0_TSE
+      - AVS_ETH_0_REG
+      - AVS_ETH_0_RAM
+      
+  - peripheral_name: ppsh/ppsh
+    slave_port_names:
+      - PIO_PPS
+      
+  - peripheral_name: epcs/epcs
+    slave_port_names:
+      - REG_EPCS
+      
+  - peripheral_name: dp/dpmm
+    slave_port_names:
+      - REG_DPMM_CTRL
+      - REG_DPMM_DATA
+      
+  - peripheral_name: dp/mmdp
+    slave_port_names:
+      - REG_MMDP_CTRL
+      - REG_MMDP_DATA
+      
+  - peripheral_name: remu/remu
+    slave_port_names:
+      - REG_REMU
+ 
+  #############################################################################
+  # AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
+  #############################################################################
+  
+  - peripheral_name: tech_jesd204b/jesd_ctrl
+    slave_port_names:
+      - PIO_JESD_CTRL
+      
+  - peripheral_name: tech_jesd204b/jesd204b_arria10
+    slave_port_names:
+      - JESD204B
+  
+  - peripheral_name: dp/dp_shiftram
+    parameter_overrides:
+      - { name: g_nof_streams, value: 12 }  # = S_pn
+      - { name: g_nof_words, value: 4096 }
+      - { name: g_data_w, value: 16 }
+    slave_port_names:
+      - REG_DP_SHIFTRAM
+
+  - peripheral_name: dp/dp_bsn_source
+    parameter_overrides:
+      - { name: g_nof_block_per_sync, value: 195313 }  # 390625 = 2 * 195312, to have integer number of blocks in 2 s sync interval
+    slave_port_names:
+      - REG_BSN_SOURCE
+      
+  # TODO: Use REG_BSN_SOURCE_V2 instead of REG_BSN_SOURCE
+  #peripheral_name: dp/dp_bsn_source_v2
+  #parameter_overrides:
+  #  - { name: g_nof_clk_per_sync, value: 200000000 }  # = f_adc
+  #  - { name: g_block_size, value: 1024 }       # = N_fft
+  #  - { name: g_bsn_time_offset_w, value: 10 }  # note: g_bsn_time_offset_w = ceil_log2(g_block_size)
+  #slave_port_names:
+  #  - REG_BSN_SOURCE_V2
+      
+  - peripheral_name: dp/dp_bsn_scheduler
+    slave_port_names:
+      - REG_BSN_SCHEDULER
+  
+  - peripheral_name: dp/dp_bsn_monitor
+    peripheral_group: input
+    slave_port_names:
+      - REG_BSN_MONITOR_INPUT
+  
+  - peripheral_name: diag/diag_wg_wideband
+    parameter_overrides:
+      - { name: g_nof_streams, value: 12 }  # = S_pn
+    slave_port_names:
+      - REG_DIAG_WG
+      - RAM_DIAG_WG
+      
+  - peripheral_name: aduh/aduh_mon_dc_power
+    parameter_overrides:
+      - { name: g_nof_streams, value: 12 }  # = S_pn
+    slave_port_names:
+      - REG_ADUH_MON
+
+  # Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
+  #- peripheral_name: aduh/aduh_mon_data_buffer
+  #  parameter_overrides:
+  #    - { name: g_nof_streams, value: 12 }  # = S_pn
+  #    - { name: g_symbol_w, value: 16 }
+  #    - { name: g_nof_symbols_per_data, value: 1 }
+  #    - { name: g_buffer_nof_symbols, value: 512 }
+  #    - { name: g_buffer_use_sync, value: true }
+  #  slave_port_names:
+  #    - RAM_ADUH_MON
+
+  - peripheral_name: diag/diag_data_buffer
+    peripheral_group: bsn
+    parameter_overrides:
+      - { name: g_nof_streams, value: 12 }  # = S_pn
+      - { name: g_data_w, value: 16 }
+      - { name: g_nof_data, value: 1024 }
+    slave_port_names:
+      - REG_DIAG_DATA_BUF_BSN
+      - RAM_DIAG_DATA_BUF_BSN
+  
+  #############################################################################
+  # Fsub = Subband Filterbank (from node_sdp_filterbank.vhd)
+  #############################################################################
+  
+  - peripheral_name: si/si
+    slave_port_names:
+      - REG_SI
+      
+  - peripheral_name: filter/fil_ppf_w
+    parameter_overrides:
+      - { name: g_wb_factor, value: 1 }
+      - { name: g_nof_taps, value: 16 }  # = N_taps
+      - { name: g_nof_bands, value: 1024 }  # = N_fft
+      - { name: g_coef_dat_w, value: 16 }  # = W_fir_coef
+    slave_port_names:
+      - RAM_FIL_COEFS
+      
+  - peripheral_name: sdp/sdp_subband_equalizer
+    slave_port_names:
+      - RAM_EQUALIZER_GAINS
+      
+  - peripheral_name: dp/dp_selector
+    slave_port_names:
+      - REG_DP_SELECTOR   # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
+      
+  - peripheral_name: st/st_sst_for_sdp
+    slave_port_names:
+      - RAM_ST_SST
+      
+      
+      
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
new file mode 100644
index 0000000000..ee6fb7b31d
--- /dev/null
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -0,0 +1,35 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: sdp
+hdl_library_description: "Station Digital Processor (SDP) for LOFAR2.0"
+
+peripherals:
+  - peripheral_name: sdp_subband_equalizer    # pi_sdp_subband_equalizer.py
+    peripheral_description: "Subband equalizer coefficients."
+    parameters:
+      # Parameters of pi_sdp_subband_equalizer.py, fixed in sdp_subband_equalizer.vhd / sdp_pkg.vhd
+      - { name: g_nof_instances, value: 6 }  # P_pfb = S_pn / Q_fft = 12 / 2 = 6
+    slave_ports:                            
+      # MM port for sdp_subband_equalizer.vhd
+      - slave_name: RAM_EQUALIZER_GAINS
+        slave_description: |
+          "The subband weigths per PN are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of 
+           Q_fft * N_sub = 2 * 512 = 1024 complex coefficients as:
+          
+           (cint16)subband_weights[S_pn/Q_fft]_[Q_fft][N_sub]
+          
+           where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
+        slave_type: RAM
+        number_of_slaves: g_nof_instances
+        fields:
+          - - field_name: coef
+              field_description: |
+                "Complex coefficient to calibrate the gain and phase per subband. Packed as imaginary in high part,
+                 real in low part of width = N_complex * W_sub_weight = 2 * 16 = 32 bit."
+              width: 32  # = N_complex * W_sub_weight
+              address_offset: 0x0
+              number_of_fields: 1024  # = Q_fft * N_sub = 2 signal inputs * 512 subbands
+              radix: complx
+
diff --git a/libraries/dsp/filter/filter.peripheral.yaml b/libraries/dsp/filter/filter.peripheral.yaml
new file mode 100644
index 0000000000..a9d6107582
--- /dev/null
+++ b/libraries/dsp/filter/filter.peripheral.yaml
@@ -0,0 +1,44 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: filter
+hdl_library_description: "Poly-phase filter (PPF) for a Wideband Poly-phase filterbank (WPFB)"
+
+peripherals:
+  - peripheral_name: fil_ppf_w    # pi_fil_ppf_w.py
+    peripheral_description: |
+      "PPF FIR filter for wideband data streams, all data streams use the same FIR coefficients.
+       The PPF has g_nof_bands phases, where g_nof_bands is equal to the size of the FFT in the
+       PFB. The PPF has g_nof_taps FIR taps per phase. Hence the total number of FIR coefficients
+       is g_nof_taps * g_nof_bands. 
+       The PPF can process a data stream that is clocked at a wideband factor g_wb_factor higher
+       data rate, by running g_wb_factor parts in parallel.
+       The FIR coefficients are real values."
+    parameters:
+      # Parameters of fil_ppf_wide.vhd
+      - { name: g_wb_factor, value: 1 }
+      - { name: g_nof_taps, value: 8 }
+      - { name: g_nof_bands, value: 256 }
+      - { name: g_coef_dat_w, value: 16 }
+    slave_ports:                            
+      # MM port for fil_ppf_wide.vhd / fil_ppf_single.vhd
+      - slave_name: RAM_FIL_COEFS
+        slave_description: | 
+           "The FIR filter coefficients are stored in blocks of g_nof_bands/g_wb_factor real
+            coefficients:
+           
+            (int16)coefs[g_wb_factor][g_nof_taps][g_nof_bands/g_wb_factor]
+           
+            For g_wb_factor = 1 this reduces to g_nof_taps blocks of g_nof_bands/g_wb_factor
+            coefficients:
+           
+            (int16)coefs[g_nof_taps][g_nof_bands]"
+        slave_type: RAM
+        number_of_slaves: g_wb_factor * g_nof_taps
+        fields:
+          - - field_name: coef
+              field_description: "Real FIR filter coefficient"
+              width: g_coef_dat_w
+              address_offset: 0x0
+              number_of_fields: g_nof_bands / g_wb_factor
diff --git a/libraries/dsp/si/si.peripheral.yaml b/libraries/dsp/si/si.peripheral.yaml
new file mode 100644
index 0000000000..c8310c476a
--- /dev/null
+++ b/libraries/dsp/si/si.peripheral.yaml
@@ -0,0 +1,20 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: si
+hdl_library_description: "Spectral Inversion (SI)"
+
+peripherals:
+  - peripheral_name: si    # pi_si.py
+    peripheral_description: "Spectral Inversion control."
+    slave_ports:                            
+      # MM port for si_arr.vhd
+      - slave_name: REG_SI
+        slave_description: "In the even Nyquist zones the sampled spectrum gets flipped in frequency. This flip can be compensated for by enabling spectral inversion (SI)."
+        slave_type: REG
+        fields:
+          - - field_name: enable
+              field_description: "When 0 then pass on the array of input signals, when 1 then enable spectral inversion for all the input signals."
+              width: 1
+              address_offset: 0x0
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
new file mode 100644
index 0000000000..de1db29e29
--- /dev/null
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -0,0 +1,69 @@
+schema_name: args
+schema_version: 1.0
+schema_type: peripheral
+
+hdl_library_name: st
+hdl_library_description: "Statistics (ST)"
+
+peripherals:
+  - peripheral_name: st_sst  # pi_st_sst.py
+    peripheral_description: |
+       "Accumulate the signal power values during a sync interval:
+        . g_xst_enable = false : Auto power statistics for subbands (SST), beamlets (BST)
+        . g_xst_enable = true : Cross power statistics for subbands = crosslets (XST)."
+    parameters:
+      # Parameters of pi_st_sst.py
+      - { name: g_nof_instances, value: 1 }
+      # Parameters of st_sst.vhd
+      - { name: g_nof_stat, value: 512 }  # nof accumulators
+      - { name: g_xst_enable, value: false }  # false for auto powers, true for cross powers
+      - { name: g_stat_data_w, value: 64 }  # statistics accumulator width in bits
+      - { name: g_stat_data_sz, value: 2 }  # statistics accumulator width in 32b MM words
+    slave_ports:                            
+      # MM port for st_sst.vhd
+      - slave_name: RAM_ST_SST
+        slave_description: |
+           "The statistics are calculated for blocks of g_nof_stat time multiplexed data streams.
+            There are g_nof_instances parallel time multiplexed data streams.
+            The statistic power values have g_stat_data_w bits. The memory format is:
+            . g_xst_enable = false, for real powers : (uint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]
+            . g_xst_enable = true, for complex powers : (cuint32 * g_stat_data_sz)st[g_nof_instances]_[g_nof_stat]"
+        slave_type: RAM
+        number_of_slaves: g_nof_instances
+        fields:
+          - - field_name: power
+              field_description: ""
+              width: g_stat_data_w
+              address_offset: 0x0
+              number_of_fields: g_nof_stat * g_stat_data_sz
+
+              
+  - peripheral_name: st_sst_for_sdp  # pi_st_sst.py
+    peripheral_description: |
+       "Accumulate the subband auto power values during a sync interval for the subband statistics (SST) in LOFAR2.0 SDP"
+    parameters:
+      # Parameters of pi_st_sst.py, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
+      - { name: g_nof_instances, value: 6 }
+      # Parameters of st_sst.vhd, fixed in node_sdp_filterbank.vhd / sdp_pkg.vhd
+      - { name: g_nof_stat, value: 1024 }  # nof accumulators:  N_sub * Q_fft = 512 * 2 = 1024
+      - { name: g_stat_data_w, value: 54 }  # statistics accumulator width in bits: W_statistic = 64
+      - { name: g_stat_data_sz, value: 2 }  # statistics accumulator width in 32b MM words: W_statistic_sz = 2
+    slave_ports:                            
+      # MM port for st_sst.vhd
+      - slave_name: RAM_ST_SST
+        slave_description: |
+          "The subband statistics per PN are stored in g_nof_instances = P_pfb = S_pn / Q_fft = 6 blocks of 
+           N_sub * Q_fft = 512 * 2 = 1024 real values as:
+          
+           (uint64)SST[g_nof_instances]_[g_nof_stat] = (uint64)SST[S_pn/Q_fft]_[N_sub][Q_fft]
+          
+           where S_pn = 12, Q_fft = 2 and N_sub = 512 are defined in sdp_pkg.vhd."
+        slave_type: RAM
+        number_of_slaves: g_nof_instances
+        fields:
+          - - field_name: power
+              field_description: ""
+              width: 32
+              address_offset: 0x0
+              number_of_fields: g_nof_stat * g_stat_data_sz
+              radix_width: g_stat_data_w
-- 
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