From 91328eda31fe2b2f79d7e85a95d5f9401312ce78 Mon Sep 17 00:00:00 2001 From: Pepping <pepping> Date: Thu, 25 Jun 2015 11:43:50 +0000 Subject: [PATCH] UPdated names --- .../reorder/tb/vhdl/tb_reorder_col_wide.vhd | 184 ++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd new file mode 100644 index 0000000000..4614efb3b7 --- /dev/null +++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd @@ -0,0 +1,184 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2010 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, dp_lib; +USE IEEE.std_logic_1164.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE common_lib.tb_common_pkg.ALL; +USE common_lib.tb_common_mem_pkg.ALL; +USE common_lib.common_lfsr_sequences_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE dp_lib.tb_dp_pkg.ALL; + + +-- Usage: +-- > as 10 +-- > run -all +-- . Observe in_sosi_arr and out_sosi_arr in the Wave window +-- +-- Description: + +ENTITY tb_reorder_col_wide IS +END tb_reorder_col_wide; + + +ARCHITECTURE tb OF tb_reorder_col_wide IS + + CONSTANT c_clk_period : TIME := 10 ns; + + CONSTANT c_rl : NATURAL := 1; + CONSTANT c_dsp_data_w : NATURAL := 16; + + CONSTANT c_nof_sync : NATURAL := 5; + + CONSTANT c_wb_factor : NATURAL := 4; + CONSTANT c_nof_ch_in : NATURAL := 256; + CONSTANT c_nof_ch_sel : NATURAL := 192; + CONSTANT c_nof_block_per_sync : NATURAL := 4; + + CONSTANT c_adr_incr : NATURAL := 2**ceil_log2(c_nof_ch_sel/c_wb_factor); + CONSTANT c_select_file_prefix : STRING := "../../../src/data/select_buf"; + + SIGNAL rst : STD_LOGIC; + SIGNAL clk : STD_LOGIC := '1'; + SIGNAL tb_end : STD_LOGIC; + + SIGNAL mm_mosi : t_mem_mosi; + SIGNAL mm_miso : t_mem_miso; + SIGNAL mm_done : STD_LOGIC; + + SIGNAL st_en : STD_LOGIC := '1'; + SIGNAL st_siso_arr : t_dp_siso_arr(c_wb_factor-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL st_sosi_arr : t_dp_sosi_arr(c_wb_factor-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + + SIGNAL bsn : NATURAL := 10; + + SIGNAL in_sosi_arr : t_dp_sosi_arr(c_wb_factor-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); + + SIGNAL out_siso_arr : t_dp_siso_arr(c_wb_factor-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); + SIGNAL out_sosi_arr : t_dp_sosi_arr(c_wb_factor-1 DOWNTO 0); + +BEGIN + + clk <= (NOT clk) OR tb_end AFTER c_clk_period/2; + rst <= '1', '0' AFTER c_clk_period*7; + + -- MM domain + p_mm_stimuli : PROCESS + BEGIN + mm_mosi <= c_mem_mosi_rst; + mm_done <= '0'; + proc_common_wait_until_low(clk, rst); + proc_common_wait_some_cycles(clk, 10); + + FOR J IN 0 TO c_wb_factor-1 LOOP + FOR I IN 0 TO c_nof_ch_sel/c_wb_factor-1 LOOP + proc_mem_mm_bus_wr(J*c_adr_incr+I, I, clk, mm_mosi); -- Write the default SS map: (0, 1, 2, ... c_nof_ch_sel-1) ==> (0, 1, 2, ... c_nof_ch_sel-1) + END LOOP; + END LOOP; + mm_done <= '1'; + + WAIT; + END PROCESS; + + ------------------------------------------------------------------------------ + -- Data blocks + ------------------------------------------------------------------------------ + gen_stimuli : FOR K IN 0 TO c_wb_factor-1 GENERATE + p_st_stimuli : PROCESS + VARIABLE v_re : NATURAL := 0; + VARIABLE v_im : NATURAL := 1; + BEGIN + tb_end <= '0'; + st_sosi_arr(K) <= c_dp_sosi_rst; + proc_common_wait_until_high(clk, mm_done); + + -- Run some sync intervals with DSP counter data for the real and imag fields + WAIT UNTIL rising_edge(clk); + FOR I IN 0 TO c_nof_sync-1 LOOP + proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in/c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync + v_re := v_re + c_nof_ch_in; + v_im := v_im + c_nof_ch_in; + FOR J IN 0 TO c_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference + proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in/c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync + v_re := v_re + c_nof_ch_in; + v_im := v_im + c_nof_ch_in; + END LOOP; + END LOOP; + st_sosi_arr(K) <= c_dp_sosi_rst; + proc_common_wait_some_cycles(clk, 100); + -- Run some sync intervals more + WAIT UNTIL rising_edge(clk); + FOR I IN 0 TO c_nof_sync-1 LOOP + proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in/c_wb_factor, 0, 0, '1', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- next sync + v_re := v_re + c_nof_ch_in; + v_im := v_im + c_nof_ch_in; + FOR J IN 0 TO c_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference + proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, c_nof_ch_in/c_wb_factor, 0, 0, '0', "0", clk, st_en, st_siso_arr(K), st_sosi_arr(K)); -- no sync + v_re := v_re + c_nof_ch_in; + v_im := v_im + c_nof_ch_in; + END LOOP; + END LOOP; + proc_common_wait_some_cycles(clk, 10); + tb_end <= '1'; + WAIT; + END PROCESS; + END GENERATE; + + -- Time stimuli + bsn <= bsn + 1 WHEN rising_edge(clk) AND (st_sosi_arr(0).eop='1'); -- OR st_sosi.sync='1'); + + -- Add BSN to the ST data + p_in_sosi : PROCESS(st_sosi_arr, bsn) + BEGIN + FOR I IN 0 TO c_wb_factor-1 LOOP + in_sosi_arr(I) <= st_sosi_arr(I); + in_sosi_arr(I).bsn <= TO_DP_BSN(bsn); + END LOOP; + END PROCESS; + + u_dut : ENTITY work.reorder_col_wide + GENERIC MAP ( + g_wb_factor => c_wb_factor, + g_dsp_data_w => c_dsp_data_w, + g_nof_ch_in => c_nof_ch_in, + g_nof_ch_sel => c_nof_ch_sel, + g_select_file_prefix => c_select_file_prefix + ) + PORT MAP ( + mm_rst => rst, + mm_clk => clk, + dp_rst => rst, + dp_clk => clk, + + -- Memory Mapped + ram_ss_ss_wide_mosi => mm_mosi, + ram_ss_ss_wide_miso => mm_miso, + + -- Streaming + input_sosi_arr => in_sosi_arr, + + output_sosi_arr => out_sosi_arr, + output_siso_arr => out_siso_arr + ); + +END tb; -- GitLab