diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 61d5b04dccc37eb36ad1042e6815e65e05331b33..ae1566cea9497125fe55eb71660ac76c597b33e0 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -26,7 +26,7 @@
 --
 -- Testbench is selftesting: 
 --
--- > as 8
+-- > as 10
 -- > run -all 
 --
 
@@ -54,12 +54,12 @@ ENTITY tb_io_ddr IS
     g_dvr_clk_period        : TIME := 5000 ps;   -- 50 MHz
     g_dp_clk_period         : TIME := 5000 ps;   -- 200 MHz
     g_dp_factor             : NATURAL := 4;      -- 1 or power of 2, c_dp_data_w = c_ctlr_data_w / g_dp_factor
-    g_block_len             : NATURAL := 5;   -- block length for a DDR write access and read back access in number of c_ctlr_data_w words
-    g_nof_block             : NATURAL := 1;      -- number of blocks that will be written to DDR and readback from DDR
-    g_nof_wr_per_block      : NATURAL := 6;      -- number of write accesses per block
-    g_nof_rd_per_block      : NATURAL := 5;      -- number of read accesses per block
+    g_block_len             : NATURAL := 2500;   -- block length for a DDR write access and read back access in number of c_ctlr_data_w words
+    g_nof_block             : NATURAL := 3;      -- number of blocks that will be written to DDR and readback from DDR
+    g_nof_wr_per_block      : NATURAL := 1;      -- number of write accesses per block
+    g_nof_rd_per_block      : NATURAL := 1;      -- number of read accesses per block
     g_nof_repeat            : NATURAL := 1;      -- number of stimuli repeats with write flush after each repeat
-    g_wr_flush_mode         : STRING := "SYN"    -- "VAL", "SOP", "SYN"
+    g_wr_flush_mode         : STRING := "VAL"    -- "VAL", "SOP", "SYN"
   );
   PORT (
     tb_end : OUT STD_LOGIC
@@ -145,7 +145,7 @@ ARCHITECTURE str of tb_io_ddr IS
   CONSTANT c_ctlr_wr_not_rd_arr       : STD_LOGIC_VECTOR(0 TO c_nof_access-1)  := func_ctlr_wr_not_rd_arr;
                                                       
   CONSTANT c_wr_fifo_depth            : NATURAL := 256;
-  CONSTANT c_rd_fifo_depth            : NATURAL := 256;
+  CONSTANT c_rd_fifo_depth            : NATURAL := 16384;--256;
   
   -- Frame size for sop/eop
   CONSTANT c_wr_frame_size            : NATURAL := 32;
@@ -221,7 +221,6 @@ BEGIN
   tb_end <= i_tb_end;
   
   p_stimuli : PROCESS
-    VARIABLE v_diag_first_rd : BOOLEAN;
   BEGIN
     i_tb_end          <= '0';
     dvr_en            <= '0';
@@ -242,7 +241,6 @@ BEGIN
     proc_common_wait_some_cycles(dp_clk, 1);
     src_diag_en <= '1';
     snk_diag_en <= '1';
-    v_diag_first_rd := TRUE;
     
     -- After reset the write FIFO is flushed until the first write access is started, even when dvr_wr_flush_en='0'
     proc_common_wait_some_cycles(ctlr_clk, 1000);
@@ -262,24 +260,14 @@ BEGIN
         -- ACCESS DONE
         proc_common_wait_until_lo_hi(dvr_clk, dvr_done);
 
-        -- wait for first valid read data that starts the diagnostics
-        IF v_diag_first_rd=TRUE AND c_ctlr_wr_not_rd_arr(I)='0' THEN
-          v_diag_first_rd := FALSE;
-          proc_common_wait_some_cycles(dp_clk, 100);   -- wait for somewhat longer than the dvr_en read latency
-        END IF;
-        
         IF c_ctlr_wr_not_rd_arr(I)='0' THEN
           expected_cnt <= expected_cnt + c_ctlr_nof_address_arr(I)*g_dp_factor;
-        
-          ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!"  SEVERITY FAILURE;
-          ASSERT snk_diag_res = '0'     REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE;
         END IF;
       END LOOP;
       
-      -- Stop diagnostics source and sink
+      -- Stop diagnostics source
       proc_common_wait_some_cycles(dp_clk, 1);
       src_diag_en <= '0';
-      snk_diag_en <= '0';
       
       -- Flush the wr fifo
       proc_common_wait_some_cycles(dvr_clk, 1);
@@ -296,11 +284,18 @@ BEGIN
       ASSERT UNSIGNED(rd_fifo_usedw) = 0            REPORT "[ERROR] Read FIFO is not empty!" SEVERITY FAILURE;
       ASSERT UNSIGNED(snk_val_cnt)   = expected_cnt REPORT "[ERROR] Unexpected number of read data!" SEVERITY FAILURE;
       
+      -- Check diagnostics sink after the rd fifo has been read empty
+      proc_common_wait_some_cycles(dp_clk, 1);
+      ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!"  SEVERITY FAILURE;
+      ASSERT snk_diag_res = '0'     REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE;
+          
+      -- Stop diagnostics sink
+      snk_diag_en <= '0';
+      
       -- Restart diagnostics source and sink
       proc_common_wait_some_cycles(dp_clk, 1);
       src_diag_en <= '1';
       snk_diag_en <= '1';
-      v_diag_first_rd := TRUE;
     END LOOP;
     
     -- If the test failed then it would have stopped already, so it the test has passed