diff --git a/applications/lofar2/doc/prestudy/desp_hdl_design_article.txt b/applications/lofar2/doc/prestudy/desp_hdl_design_article.txt
index 76087b7e1c613420100e5522f8a4b95fdf6eb64a..3a6c99add1f57ebf8770978eacc876a7388c33b8 100644
--- a/applications/lofar2/doc/prestudy/desp_hdl_design_article.txt
+++ b/applications/lofar2/doc/prestudy/desp_hdl_design_article.txt
@@ -26,6 +26,10 @@ Idea / rule: Distinguish beteen state registers and pipeline registers.
   the pipelining is added as a seperate stage. Either pipeline sosi if no flow control is needed
   or pipeline siso if flow control is needed. For example: dp_block_resize.vhd, dp_block_select.vhd,
   dp_counter.vhd.
+. Components that do not need input flow control can support external flow control by simply wiring the 
+  output_siso to the input_siso.
+. Components that do need input flow control can OR their input flow control with the external flow control
+  and wire that to the input_siso.
 
 
 $RADIOHDL_WORK/applications/lofar2/doc/prestudy/