diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
index c17e494eb6f07d436f9ae722f90652f4642090fe..05492b51da30827d7df0c2f09aa673b4e96275e2 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
@@ -19,12 +19,12 @@ begin
begin
if rising_edge(clk) then
result <= add_c(add_c'high downto add_c'length - result'length);
- add_a <= std_logic_vector(resize(signed(res_0),add_a'length) + signed(res_1));
- add_b <= std_logic_vector(resize(signed(res_2),add_b'length) + signed(res_3));
+ add_a <= std_logic_vector(resize(signed(res_0), add_a'length) + signed(res_1));
+ add_b <= std_logic_vector(resize(signed(res_2), add_b'length) + signed(res_3));
end if;
end process;
- add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
+ add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a), add_c'length) + signed(add_b)), 4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
gen : for i in 0 to 7 generate
@@ -51,10 +51,10 @@ begin
pipe : process (clk)
begin
if rising_edge(clk) then
- res_0 <= std_logic_vector(resize(signed(res(0)),res_0'length) + resize(signed(res(1)),res_0'length));
- res_1 <= std_logic_vector(resize(signed(res(2)),res_0'length) + resize(signed(res(3)),res_0'length));
- res_2 <= std_logic_vector(resize(signed(res(4)),res_0'length) + resize(signed(res(5)),res_0'length));
- res_3 <= std_logic_vector(resize(signed(res(6)),res_0'length) + resize(signed(res(7)),res_0'length));
+ res_0 <= std_logic_vector(resize(signed(res(0)), res_0'length) + resize(signed(res(1)), res_0'length));
+ res_1 <= std_logic_vector(resize(signed(res(2)), res_0'length) + resize(signed(res(3)), res_0'length));
+ res_2 <= std_logic_vector(resize(signed(res(4)), res_0'length) + resize(signed(res(5)), res_0'length));
+ res_3 <= std_logic_vector(resize(signed(res(6)), res_0'length) + resize(signed(res(7)), res_0'length));
end if;
end process;
end rtl;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
index d551fa62270d140d88209eb96a728e47634e08c8..38eca59f89efad45e99ad632f61b97486f8e01e0 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
@@ -93,12 +93,12 @@ begin
add_b <= (others => '0');
elsif rising_edge(clk) then
result <= add_c(add_c'high downto add_c'length - result'length);
- add_a <= std_logic_vector(resize(signed(res_0),add_a'length) + signed(res_1));
- add_b <= std_logic_vector(resize(signed(res_2),add_b'length) + signed(res_3));
+ add_a <= std_logic_vector(resize(signed(res_0), add_a'length) + signed(res_1));
+ add_b <= std_logic_vector(resize(signed(res_2), add_b'length) + signed(res_3));
end if;
end process;
- add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
+ add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a), add_c'length) + signed(add_b)), 4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
ALTMULT_ADD_0 : altmult_add
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
index ba25c7ab38656b7edf7bf6ce78db76ffb66da00d..f9e6b52374cc7ff05090749e62f3f7c1da8dadcd 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
@@ -59,12 +59,12 @@ begin
begin
if rising_edge(clk) then
result <= add_c(add_c'high downto add_c'length - result'length);
- add_a <= std_logic_vector(resize(signed(res_0),add_a'length) + signed(res_1));
- add_b <= std_logic_vector(resize(signed(res_2),add_b'length) + signed(res_3));
+ add_a <= std_logic_vector(resize(signed(res_0), add_a'length) + signed(res_1));
+ add_b <= std_logic_vector(resize(signed(res_2), add_b'length) + signed(res_3));
end if;
end process;
- add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
+ add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a), add_c'length) + signed(add_b)), 4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
gen : for i in 0 to 7 generate
@@ -91,10 +91,10 @@ begin
pipe : process (clk)
begin
if rising_edge(clk) then
- res_0 <= std_logic_vector(resize(signed(res(0)),res_0'length) + resize(signed(res(1)),res_0'length));
- res_1 <= std_logic_vector(resize(signed(res(2)),res_0'length) + resize(signed(res(3)),res_0'length));
- res_2 <= std_logic_vector(resize(signed(res(4)),res_0'length) + resize(signed(res(5)),res_0'length));
- res_3 <= std_logic_vector(resize(signed(res(6)),res_0'length) + resize(signed(res(7)),res_0'length));
+ res_0 <= std_logic_vector(resize(signed(res(0)), res_0'length) + resize(signed(res(1)), res_0'length));
+ res_1 <= std_logic_vector(resize(signed(res(2)), res_0'length) + resize(signed(res(3)), res_0'length));
+ res_2 <= std_logic_vector(resize(signed(res(4)), res_0'length) + resize(signed(res(5)), res_0'length));
+ res_3 <= std_logic_vector(resize(signed(res(6)), res_0'length) + resize(signed(res(7)), res_0'length));
end if;
end process;
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
index 36e8e2a0075c428aee6e6f9a319fd30ec9a899c6..dbf3d35cf7964b4c13a3f5661d3b14825a992269 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -137,7 +137,7 @@ begin
end if;
end process;
- init_proc : process(cnt,init,in_val)
+ init_proc : process(cnt, init, in_val)
begin
nxt_init <= init;
if unsigned(cnt) = c_regbank_size-1 and in_val = '1' then
@@ -145,7 +145,7 @@ begin
end if;
end process;
- rd_proc : process(rd_dat,sig)
+ rd_proc : process(rd_dat, sig)
begin
rd_re <= rd_dat(rd_dat'high downto rd_im'length);
rd_im <= rd_dat(rd_im'range);
@@ -159,8 +159,8 @@ begin
rd_req <= in_val and init;
- nxt_reg_re <= std_logic_vector(resize(signed(in_re),c_dat_w));
- nxt_reg_im <= std_logic_vector(resize(signed(in_im),c_dat_w));
+ nxt_reg_re <= std_logic_vector(resize(signed(in_re), c_dat_w));
+ nxt_reg_im <= std_logic_vector(resize(signed(in_im), c_dat_w));
nxt_sig(sig'high).val <= rd_req;
nxt_sig(sig'high).s0 <= s0;
@@ -195,15 +195,15 @@ begin
end if;
end process;
- out_proc : process (sig, add_cr,add_ci,sub_cr,sub_ci)
+ out_proc : process (sig, add_cr, add_ci, sub_cr, sub_ci)
begin
- nxt_out_re <= std_logic_vector(resize(signed(add_cr),g_out_dat_w));
- nxt_out_im <= std_logic_vector(resize(signed(add_ci),g_out_dat_w));
+ nxt_out_re <= std_logic_vector(resize(signed(add_cr), g_out_dat_w));
+ nxt_out_im <= std_logic_vector(resize(signed(add_ci), g_out_dat_w));
nxt_wr_re <= sub_cr;
nxt_wr_im <= sub_ci;
if sig(1).s0 = '1' and sig(1).s1 = '1' then
- nxt_out_re <= std_logic_vector(resize(signed(add_cr),g_out_dat_w));
- nxt_out_im <= std_logic_vector(resize(signed(sub_ci),g_out_dat_w));
+ nxt_out_re <= std_logic_vector(resize(signed(add_cr), g_out_dat_w));
+ nxt_out_im <= std_logic_vector(resize(signed(sub_ci), g_out_dat_w));
nxt_wr_re <= sub_cr;
nxt_wr_im <= add_ci;
end if;
@@ -322,7 +322,7 @@ begin
end if;
end process;
- fifo2_proc : process(fifo_dat,wr_req,wr_dat)
+ fifo2_proc : process(fifo_dat, wr_req, wr_dat)
begin
nxt_fifo_dat <= fifo_dat;
if wr_req = '1' then
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index 52eebaf095bcdbb3292059b408909b75c15f7ed5..15716280cd64321ce948a30f255e20e76d535dee 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -184,7 +184,7 @@ begin
end if;
end process;
- init_proc : process(cnt,init,in_val)
+ init_proc : process(cnt, init, in_val)
begin
nxt_init <= init;
if unsigned(cnt) = c_regbank_size-1 and in_val = '1' then
@@ -192,7 +192,7 @@ begin
end if;
end process;
- rd_proc : process(rd_dat,sig)
+ rd_proc : process(rd_dat, sig)
begin
rd_re <= rd_dat(rd_dat'high downto rd_im'length);
rd_im <= rd_dat(rd_im'range);
@@ -206,8 +206,8 @@ begin
rd_req <= in_val and init;
- nxt_reg_re <= std_logic_vector(resize(signed(in_re),c_dat_w));
- nxt_reg_im <= std_logic_vector(resize(signed(in_im),c_dat_w));
+ nxt_reg_re <= std_logic_vector(resize(signed(in_re), c_dat_w));
+ nxt_reg_im <= std_logic_vector(resize(signed(in_im), c_dat_w));
nxt_sig(sig'high).val <= rd_req;
nxt_sig(sig'high).s0 <= s0;
@@ -242,15 +242,15 @@ begin
end if;
end process;
- out_proc : process (sig, add_cr,add_ci,sub_cr,sub_ci)
+ out_proc : process (sig, add_cr, add_ci, sub_cr, sub_ci)
begin
- nxt_out_re <= std_logic_vector(resize(signed(add_cr),g_out_dat_w));
- nxt_out_im <= std_logic_vector(resize(signed(add_ci),g_out_dat_w));
+ nxt_out_re <= std_logic_vector(resize(signed(add_cr), g_out_dat_w));
+ nxt_out_im <= std_logic_vector(resize(signed(add_ci), g_out_dat_w));
nxt_wr_re <= sub_cr;
nxt_wr_im <= sub_ci;
if sig(1).s0 = '1' and sig(1).s1 = '1' then
- nxt_out_re <= std_logic_vector(resize(signed(add_cr),g_out_dat_w));
- nxt_out_im <= std_logic_vector(resize(signed(sub_ci),g_out_dat_w));
+ nxt_out_re <= std_logic_vector(resize(signed(add_cr), g_out_dat_w));
+ nxt_out_im <= std_logic_vector(resize(signed(sub_ci), g_out_dat_w));
nxt_wr_re <= sub_cr;
nxt_wr_im <= add_ci;
end if;
@@ -369,7 +369,7 @@ begin
end if;
end process;
- fifo2_proc : process(fifo_dat,wr_req,wr_dat)
+ fifo2_proc : process(fifo_dat, wr_req, wr_dat)
begin
nxt_fifo_dat <= fifo_dat;
if wr_req = '1' then
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
index c8467e44759e8f153de12a1fc307f04e6963a553..227b1d39bc7d43b1ad288097ec479d75b51c7342 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
@@ -97,7 +97,7 @@ begin
end if;
end process;
- process(s0,s1,xr,xi)
+ process(s0, s1, xr, xi)
variable state : std_logic_vector(1 downto 0);
begin
state := s1 & s0;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
index f777f5e18d382a71341aaa2c01de40cff0f3f6e2..a4b6e8f54b5c6f9a4f8bf9ba2156de2a543f67e6 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
@@ -144,7 +144,7 @@ begin
end if;
end process;
- process(s0,s1,xr,xi)
+ process(s0, s1, xr, xi)
variable state : std_logic_vector(1 downto 0);
begin
state := s1 & s0;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
index 85ff4fdba8fa3418b4ad97b1822d11048cf95d67..72d7eda26943a050a59a951fe02e907258997ca1 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
@@ -60,7 +60,7 @@ begin
end if;
end process;
- pipe_proc: process(pipe_val,rd_en)
+ pipe_proc: process(pipe_val, rd_en)
begin
nxt_pipe_val <= rd_en & pipe_val (pipe_val 'high downto 1);
rd_val <= pipe_val(0);
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
index 33f764deb9248f081270a60e9b8f988ee8ba4d68..a5fcbf38943928cd318d11f3db632d792e6a6a90 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
@@ -106,7 +106,7 @@ begin
end if;
end process;
- pipe_proc: process(pipe_val,rd_en)
+ pipe_proc: process(pipe_val, rd_en)
begin
nxt_pipe_val <= rd_en & pipe_val (pipe_val 'high downto 1);
rd_val <= pipe_val(0);
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
index 73c752e25b1ca2a39e139d33bf2679c903f3049f..999140f7d8a51e517669a577939a5ea849871f8e 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
@@ -16,7 +16,7 @@ architecture rtl of pft_lfsr is
signal s2 : std_logic_vector(c_max - 1 downto 0);
signal nxt_s2 : std_logic_vector(c_max - 1 downto 0);
begin
- regs: process(rst,clk)
+ regs: process(rst, clk)
begin
if rst = '1' then
s1 <= "01000101011101110101001011111000101100001";
@@ -30,7 +30,7 @@ begin
out_bit1 <= s1(s1'high);
out_bit2 <= s2(s2'high);
- seed_proc: process(in_en,s1,s2)
+ seed_proc: process(in_en, s1, s2)
begin
nxt_s1 <= s1;
nxt_s2 <= s2;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
index c6250be5bcfe8928822af3b70a4ea08bd354f43f..b0a0d7a23391ce996a7a22bca253854adefb8823 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
@@ -51,7 +51,7 @@ architecture rtl of pft_lfsr is
signal s2 : std_logic_vector(c_max - 1 downto 0);
signal nxt_s2 : std_logic_vector(c_max - 1 downto 0);
begin
- regs: process(rst,clk)
+ regs: process(rst, clk)
begin
if rst = '1' then
s1 <= "01000101011101110101001011111000101100001";
@@ -65,7 +65,7 @@ begin
out_bit1 <= s1(s1'high);
out_bit2 <= s2(s2'high);
- seed_proc: process(in_en,s1,s2)
+ seed_proc: process(in_en, s1, s2)
begin
nxt_s1 <= s1;
nxt_s2 <= s2;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
index 885d8a147e4ce267f05bdcc4e7fbf506db9f85c8..f4f57969c8949a5e9e4e8552299854f39937e46e 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
@@ -56,7 +56,7 @@ begin
out_sync <= '0';
rden <= '0';
-- Internal signals.
- cnt <= std_logic_vector(to_signed(-2,g_fft_sz_w));
+ cnt <= std_logic_vector(to_signed(-2, g_fft_sz_w));
rd_cnt <= (others => '0');
page_rdy_dly <= (others => '0');
rddata_re_dly <= (others => (others => '0'));
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
index 538b57aac83328aa950606c8ec148b4e48c09ae2..810c62d0948635c88e03694b028c9d6c70580814 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
@@ -102,7 +102,7 @@ begin
out_sync <= '0';
rden <= '0';
-- Internal signals.
- cnt <= std_logic_vector(to_signed(-2,g_fft_sz_w));
+ cnt <= std_logic_vector(to_signed(-2, g_fft_sz_w));
rd_cnt <= (others => '0');
page_rdy_dly <= (others => '0');
rddata_re_dly <= (others => (others => '0'));
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
index 51ba8e9fbc7dbcb809306889733e6cdfdfa998fc..75203c3f44320d5e1be062d220e1864079ff13a1 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
@@ -165,7 +165,7 @@ begin
clk => clk
);
- p_regs: process(clk,rst)
+ p_regs: process(clk, rst)
begin
if rst = '1' then
reg_val <= '0';
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
index 494ab310049f9493d4fc92620461d35c8b37a2b5..de2b89067a22f042960bde0beb3df53404db7d3b 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
@@ -189,7 +189,7 @@ begin
clk => clk
);
- p_regs: process(clk,rst)
+ p_regs: process(clk, rst)
begin
if rst = '1' then
reg_val <= '0';
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
index f721e586262435efb9becf043fdc10c9dacd8185..f97c0603ecec5436b05582069cf590365cfa8d87 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
@@ -45,7 +45,7 @@ begin
end if;
end process;
- lfsr_ctrl: process(cnt,in_val)
+ lfsr_ctrl: process(cnt, in_val)
begin
if signed(cnt) = -1 and in_val = '1' then
lfsr_en <= '1';
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
index 0c6daed641bee4d02364616f52b3da4f03912ad7..e8b52dbef88e4a95ee4384d8fffcca1e98564a01 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
@@ -87,7 +87,7 @@ begin
end if;
end process;
- lfsr_ctrl: process(cnt,in_val)
+ lfsr_ctrl: process(cnt, in_val)
begin
if signed(cnt) = -1 and in_val = '1' then
lfsr_en <= '1';
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
index e12c3622fe32f9a7f9dd5390db7f249959ea1788..3baf9dac8cba91752af2d99b890deb9d3411539a 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
@@ -46,7 +46,7 @@ begin
end if;
end process;
- lfsr_ctrl: process(cnt,in_val)
+ lfsr_ctrl: process(cnt, in_val)
begin
if signed(cnt) = -1 and in_val = '1' then
lfsr_en <= '1';
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
index 726636e03b031b6933e1dfad0b6a0a8e589d7902..906802ba2d5af2ade370ab141677c59b26ae01bd 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
@@ -88,7 +88,7 @@ begin
end if;
end process;
- lfsr_ctrl: process(cnt,in_val)
+ lfsr_ctrl: process(cnt, in_val)
begin
if signed(cnt) = -1 and in_val = '1' then
lfsr_en <= '1';
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
index cdc09c717a053e14a256d95aaf0a35ef34f2159d..1ce349464f74626cfcd3f4fc424c354016ed21a9 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
@@ -2,7 +2,7 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-library pft2_lib,common_lib;
+library pft2_lib, common_lib;
use pft2_lib.pft_pkg.all;
use common_lib.common_pkg.all;
@@ -137,11 +137,11 @@ begin
-- X = sinus Fs/2 and Y = DC
--
-----------------------------------------------------------------------------
- in_gen: process (clk,rst)
+ in_gen: process (clk, rst)
begin
if rst = '1' then
- in_x <= std_logic_vector(to_signed(300,g_in_dat_w));
- in_y <= std_logic_vector(to_signed(250,g_in_dat_w));
+ in_x <= std_logic_vector(to_signed(300, g_in_dat_w));
+ in_y <= std_logic_vector(to_signed(250, g_in_dat_w));
elsif rising_edge(clk) then
if cnt(0) = '1' then
if in_val = '1' then
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 0d815568ee1674d47062268d8106f9c41ab9358d..9fe19c12b1f0358f5a1acd4461a42268bebe43d7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -890,8 +890,8 @@ begin
generic map (
g_nof_input => c_sdp_N_beamsets,
g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ g_fifo_size => array_init(0, c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0, c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
)
port map (
clk => dp_clk,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index aef82a89ff36116894d3267561d23df702a525e7..38c9c29ca545a7de4efa2e4863e7ad2b145557bb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -331,8 +331,8 @@ begin
----------------------------------------------------------------------------
-- Enable UDP offload (dp_xonoff) of beamset 0
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,0 , 1, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff,2 , 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff, 0, 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff, 2, 1, tb_clk);
----------------------------------------------------------------------------
-- Enable BS
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index 95899d4d5894634e6b1ab3fda7976c57cc8819e0..3902a64fd639f8bbd67cb1b1f3ecac6d6363e4fa 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -253,7 +253,7 @@ begin
-- Crosslets Info
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 0, integer(c_subband_sp_0), tb_clk); -- offset
- mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0 , tb_clk); -- stepsize
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0, tb_clk); -- stepsize
----------------------------------------------------------------------------
-- Enable WG
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index 9e7401c049e4ad2d0100efebeca9f6cac2999df2..40bdccebcd2bc83a47ce1174c706386050febd04 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -329,7 +329,7 @@ begin
-- Crosslets Info
----------------------------------------------------------------------------
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 0, integer(c_subband_sp_0), tb_clk); -- offset
- mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 15, 0 , tb_clk); -- stepsize
+ mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_CROSSLETS_INFO", 15, 0, tb_clk); -- stepsize
end loop;
----------------------------------------------------------------------------
-- Enable WG
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index 2e4ac9d8d868dd53538e960a49ef02807376189c..2b57c8af914d953f2d44e79ab7b65132ec962edc 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -271,9 +271,9 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
- mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K, sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
- mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2, sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 + 1, sosi_out_not_bsn(c_rd_data_w - 1 downto 0), tb_clk);
end loop;
end loop;
@@ -291,9 +291,9 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
- mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K, sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
- mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2, sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 + 1, sosi_out_not_bsn(c_rd_data_w - 1 downto 0), tb_clk);
end loop;
end loop;
@@ -311,9 +311,9 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
- mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K, sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
- mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2, sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 + 1, sosi_out_not_bsn(c_rd_data_w - 1 downto 0), tb_clk);
end loop;
end loop;
@@ -331,9 +331,9 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
- mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K, sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
- mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2, sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 + 1, sosi_out_not_bsn(c_rd_data_w - 1 downto 0), tb_clk);
end loop;
end loop;
@@ -351,9 +351,9 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
- mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K, sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
- mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2, sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 + 1, sosi_out_not_bsn(c_rd_data_w - 1 downto 0), tb_clk);
end loop;
end loop;
@@ -371,9 +371,9 @@ begin
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
- mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K , sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_ram_data_buf, (J * c_block_size) + K, sosi_out_data(c_rd_data_w - 1 downto 0), tb_clk);
sosi_out_data_sin(c_data_w - 1 downto 0) <= sosi_out_data(c_data_w - 1 downto 0);
- mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 , sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
+ mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2, sosi_out_bsn(c_rd_data_w - 1 downto 0), tb_clk);
mmf_mm_bus_rd( c_mm_file_ram_bsn_buf, ((J * c_block_size) + k) * 2 + 1, sosi_out_not_bsn(c_rd_data_w - 1 downto 0), tb_clk);
end loop;
end loop;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
index ae39ff5891c1972fcf7a040bd245d465d9095cbc..ca762db8b08e547014cb2d4afc68209e9ff12f47 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -234,7 +234,7 @@ begin
-- Crosslets Info
----------------------------------------------------------------------------
mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 0, integer(c_subband_sp), tb_clk); -- offset
- mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0 , tb_clk); -- stepsize
+ mmf_mm_bus_wr(c_mm_file_reg_crosslets_info, 15, 0, tb_clk); -- stepsize
----------------------------------------------------------------------------
-- Enable WG
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 69b4c10a71d9cde40702755a4709d38f7f538417..ac0a4bff369ab623b414b08ce732207064579920 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -292,7 +292,7 @@ begin
v.last_adr_to_write_to(c_adr_w - 1 downto c_bitshift_w) := v.stop_adr(c_adr_w - 1 downto c_bitshift_w);
end if;
v.last_adr_to_write_to(c_bitshift_w - 1 downto 0) := (others => '0');
- v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w - 1 downto 0), -1 * TO_UINT(v.last_adr_to_write_to)),1));
+ v.stop_burstsize := TO_UINT(INCR_UVEC(INCR_UVEC(v.stop_adr(c_adr_w - 1 downto 0), -1 * TO_UINT(v.last_adr_to_write_to)), 1));
-- still a write cyle
-- if adr mod g_burstsize = 0
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index dee188c0b1a2d0c1e24e21be34797d944da75c36..14fa653747a0f32a94a27d4a7e69a578a7119eb4 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -1172,8 +1172,8 @@ begin
generic map (
g_nof_input => c_sdp_N_beamsets,
g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
+ g_fifo_size => array_init(0, c_sdp_N_beamsets), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0, c_sdp_N_beamsets) -- no FIFO used but must match g_nof_input
)
port map (
clk => dp_clk,
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
index ef323ac858df135b1b286ed9e8a2a1728705fed4..5203e24044fdb3ce66819da95e4b446ff0a2fe21 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
@@ -95,15 +95,15 @@ begin
proc_common_wait_some_cycles(mm_clk, 100);
-- default all register hold value 0, try to write 1 in all registers
- proc_mem_mm_bus_wr(c_mm_addr_block_period ,11 ,mm_clk, reg_miso, reg_mosi); -- RO
- proc_mem_mm_bus_wr(c_mm_addr_beam_repositioning_flag,1 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_fsub_type ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
- proc_mem_mm_bus_wr(c_mm_addr_f_adc ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
- proc_mem_mm_bus_wr(c_mm_addr_nyquist_zone_index ,3 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_observation_id ,16 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_antenna_band_index ,1 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_station_id ,17 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_antenna_field_index ,15 ,mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_block_period, 11, mm_clk, reg_miso, reg_mosi); -- RO
+ proc_mem_mm_bus_wr(c_mm_addr_beam_repositioning_flag, 1, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_fsub_type, 1, mm_clk, reg_miso, reg_mosi); -- RO
+ proc_mem_mm_bus_wr(c_mm_addr_f_adc, 1, mm_clk, reg_miso, reg_mosi); -- RO
+ proc_mem_mm_bus_wr(c_mm_addr_nyquist_zone_index, 3, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_observation_id, 16, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_antenna_band_index, 1, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_station_id, 17, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_antenna_field_index, 15, mm_clk, reg_miso, reg_mosi);
proc_common_wait_cross_clock_domain_latency(dp_clk, mm_clk);
proc_mem_mm_bus_rd(c_mm_addr_block_period, mm_clk, reg_mosi);
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index a6f9b19d3f5f044bee8c7b314f833dac4efd3275..c55cec9834af2cddad72c06cf0e3d410b6236cf0 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -718,7 +718,7 @@ package body tb_sdp_pkg is
clk,
rx_beamlet_sosi,
rx_beamlet_cnt,
- rx_beamlet_valid ,
+ rx_beamlet_valid,
rx_beamlet_arr_re,
rx_beamlet_arr_im,
rx_packet_list_re,
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index 235b962b494b04abec47bb73ebe22f026af5bdfa..d7b7ac56025bfd48b2bdefe53859b7fff5beba35 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -73,7 +73,7 @@ end tb_sdp_statistics_offload;
architecture tb of tb_sdp_statistics_offload is
constant c_dp_clk_period : time := 5 ns; -- 200 MHz
- constant c_mm_clk_period : time := sel_a_b(g_fast_mm_clk, 1 , 10) * 1 ns;
+ constant c_mm_clk_period : time := sel_a_b(g_fast_mm_clk, 1, 10) * 1 ns;
constant c_mm_dp_clk_ratio : natural := sel_a_b(c_mm_clk_period > c_dp_clk_period, c_mm_clk_period / c_dp_clk_period, 1);
constant c_cross_clock_domain_latency : natural := 20;
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
index b93df20cd5b8b6253f38d5d3c0c7c67a0fdd06e4..670dae14581dcba6df9d1f76df7fbc4a8ef3cc3b 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
@@ -401,7 +401,7 @@ package body rdma_packetiser_pkg is
v.bth.psn := hdr_fields_raw(field_hi(c_hdr_field_arr, "bth_psn") downto field_lo(c_hdr_field_arr, "bth_psn"));
-- reth header (optional)
- v.reth := ((others => '0'), (others => '0'),(others => '0'));
+ v.reth := ((others => '0'), (others => '0'), (others => '0'));
if field_exists(c_hdr_field_arr, "reth_virtual_address") then -- reth header exists
v.reth.virtual_address := hdr_fields_raw(field_hi(c_hdr_field_arr, "reth_virtual_address") downto field_lo(c_hdr_field_arr, "reth_virtual_address"));
v.reth.r_key := hdr_fields_raw(field_hi(c_hdr_field_arr, "reth_r_key") downto field_lo(c_hdr_field_arr, "reth_r_key"));
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
index 76989ef8807129187a6a2f6fde13837526a4bae7..5ce71265b6d3805bcf948bf52d288dff61713b28 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
@@ -56,6 +56,6 @@ package body ring_pkg is
function nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector is
begin
- return TO_SVEC(nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(N_rn), TO_UINT(N_rn), lane_dir),hops'length);
+ return TO_SVEC(nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(N_rn), TO_UINT(N_rn), lane_dir), hops'length);
end;
end ring_pkg;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
index 34b1424f815182181ca35334120e421656f29c93..0ba7f3c35dd8f4ff29d86c325dc7c389b177ac25 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
@@ -261,8 +261,8 @@ begin
----------------------------------------------------------------------------
-- Enable UDP offload (dp_xonoff) of beamset 0
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_bg,0 , 1, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_from_lane,0 , 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_bg, 0, 1, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_dp_xonoff_from_lane, 0, 0, tb_clk);
----------------------------------------------------------------------------
-- Enable BG
@@ -276,16 +276,16 @@ begin
-- 6: BSN_init[31:0]
-- 7: BSN_init[63:32]
- mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 0 , tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 1, 750 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 1, 750, tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 2, c_nof_block_per_sync, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 3, 250 , tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 4, 0 , tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 5, 127 , tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 6, 0 , tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 7, 0 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 3, 250, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 4, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 5, 127, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 6, 0, tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 7, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 3 , tb_clk);
+ mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 3, tb_clk);
proc_common_wait_some_cycles(ext_clk, 2 * c_nof_block_per_sync * 1000);
---------------------------------------------------------------------------
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
index 1083a6bc1589f0b8464b7266b90955fc2250ec08..731d588c4bc8e360a714bdaba6aee47962369e0b 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
@@ -123,7 +123,7 @@ begin
kernel_clk => kernel_clk,
kernel_reset => kernel_reset,
- kernel_src_data => kernel_src_data ,
+ kernel_src_data => kernel_src_data,
kernel_src_valid => kernel_src_valid,
kernel_src_ready => kernel_src_ready,
kernel_snk_data => kernel_snk_data,
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index d0dbf2fd6e39c1f69358d620fdbd979b401fc58f..b1cf9ad847a3aa9a31be4e797b73e0feaabe6205 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -133,8 +133,8 @@ architecture str of mmm_unb1_minimal is
----------------------------------------------------------------------------
constant c_nof_slaves : natural := 11;
- constant c_slave_base_arr : t_natural_arr(c_nof_slaves - 1 downto 0) := ( 0, 32,4128,4256,4264,4272,4304,4336,4344,4352,4360);
- constant c_slave_high_arr : t_natural_arr(c_nof_slaves - 1 downto 0) := (31,4127,4255,4263,4271,4303,4335,4343,4351,4359,4367);
+ constant c_slave_base_arr : t_natural_arr(c_nof_slaves - 1 downto 0) := ( 0, 32, 4128, 4256, 4264, 4272, 4304, 4336, 4344, 4352, 4360);
+ constant c_slave_high_arr : t_natural_arr(c_nof_slaves - 1 downto 0) := (31, 4127, 4255, 4263, 4271, 4303, 4335, 4343, 4351, 4359, 4367);
signal master_mosi : t_mem_mosi;
signal master_miso : t_mem_miso;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
index a9747754f1745d8a09223b4dc012ea48eb23212c..a0fc53d37953d177be7a57eb2e1950f219999c1b 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
@@ -62,10 +62,10 @@ architecture rtl of unb1_board_sens_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , FPGA_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , HOTSWAP_LTC4260_ADR, LTC4260_CMD_SENSE,
- SMBUS_READ_BYTE , HOTSWAP_LTC4260_ADR, LTC4260_CMD_SOURCE,
+ SMBUS_READ_BYTE, FPGA_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, HOTSWAP_LTC4260_ADR, LTC4260_CMD_SENSE,
+ SMBUS_READ_BYTE, HOTSWAP_LTC4260_ADR, LTC4260_CMD_SOURCE,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
SMBUS_C_NOP
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
index 594354d35e7a30d3ea330b3020a46e422530eea1..7ba74b50efc0946f11cc4f28dbd4eabb5c197a56 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
@@ -88,7 +88,7 @@ architecture rtl of unb1_board_system_info_reg is
constant c_use_phy_w : natural := 8;
constant c_use_phy : std_logic_vector(c_use_phy_w - 1 downto 0) := TO_UVEC(g_use_phy.eth1g, 1) &
- TO_UVEC(g_use_phy.tr_front,1) &
+ TO_UVEC(g_use_phy.tr_front, 1) &
TO_UVEC(g_use_phy.tr_mesh, 1) &
TO_UVEC(g_use_phy.tr_back, 1) &
TO_UVEC(g_use_phy.ddr3_I, 1) &
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 0d1307487a4c2462548021e907a4f0140d09842d..c67b97f3b81156324ced4581d116adc5cba18b54 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -422,7 +422,7 @@ begin
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
- mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+ mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 623466cb77376317cf2608cce70b318a3b948b02..66f15cf9b17ff4b34eaf8ed68de9c7cba61e3204 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -159,19 +159,19 @@ architecture str of unb2_test is
constant c_nof_back1 : natural := 0; -- c_unb2_board_tr_back.bus_w;
-- 1GbE
- constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0); -- sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+ constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE, 1, 0); -- sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
-- 10GbE
- constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
- constant c_nof_streams_ring : natural := sel_a_b(c_use_10GbE_ring,c_nof_ring,0);
- constant c_nof_streams_back0 : natural := sel_a_b(c_use_10GbE_back0,c_nof_back0,0);
- constant c_nof_streams_back1 : natural := sel_a_b(c_use_10GbE_back1,c_nof_back1,0);
+ constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp, c_nof_qsfp, 0);
+ constant c_nof_streams_ring : natural := sel_a_b(c_use_10GbE_ring, c_nof_ring, 0);
+ constant c_nof_streams_back0 : natural := sel_a_b(c_use_10GbE_back0, c_nof_back0, 0);
+ constant c_nof_streams_back1 : natural := sel_a_b(c_use_10GbE_back1, c_nof_back1, 0);
constant c_nof_streams_10GbE : natural := c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1;
- constant c_nof_qsfp_bus : natural := ceil_div(c_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
- constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring,c_unb2_board_tr_ring.bus_w);
- constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2_board_tr_back.bus_w);
+ constant c_nof_qsfp_bus : natural := ceil_div(c_nof_streams_qsfp, c_unb2_board_tr_qsfp.bus_w);
+ constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring, c_unb2_board_tr_ring.bus_w);
+ constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0, c_unb2_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1, c_unb2_board_tr_back.bus_w);
constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
@@ -442,7 +442,7 @@ begin
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
+ g_mm_clk_freq => sel_a_b(g_sim, c_unb2_board_mm_clk_freq_25M, c_unb2_board_mm_clk_freq_125M),
g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
g_aux => c_unb2_board_aux,
g_udp_offload => c_use_1GbE,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index 45987424f355bbc7e5349362e411a7b0c149e1f6..8f2d4dd3f62e0dbb67093617734e06a6168b226a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -81,10 +81,10 @@ architecture rtl of unb2_board_pmbus_ctrl is
-- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_IOUT,
-- SMBUS_READ_WORD , LOC_POWER_ERAM, LP_TEMP,
--
- SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
- SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
- SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
- SMBUS_READ_BYTE , LOC_POWER_TR_R, LP_VOUT_MODE,
+ SMBUS_READ_BYTE, LOC_POWER_TR_R, LP_VOUT_MODE,
+ SMBUS_READ_BYTE, LOC_POWER_TR_R, LP_VOUT_MODE,
+ SMBUS_READ_BYTE, LOC_POWER_TR_R, LP_VOUT_MODE,
+ SMBUS_READ_BYTE, LOC_POWER_TR_R, LP_VOUT_MODE,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_VOUT,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_IOUT,
--SMBUS_READ_WORD , LOC_POWER_TR_R, LP_TEMP,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
index da90d846f87364a7d68931a44fd5d93028a51c8d..50f36be1a961b094038cef527fb304a97592e1b5 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -61,10 +61,10 @@ architecture rtl of unb2_board_sens_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ETH_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index c195237ee34ac2df932fd235d08ca3c1169a9bbd..c93df3635ced3da126d93044cd5543363ae1c313 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -431,7 +431,7 @@ begin
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
- mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+ mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index d982da0f3b9d70e1a262c3f8e47910c1ec3cc41a..8ff0a270b25b24eae9d611f1084ddcaec0ebf33d 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -159,19 +159,19 @@ architecture str of unb2a_test is
constant c_nof_back1 : natural := 0; -- c_unb2_board_tr_back.bus_w;
-- 1GbE
- constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0); -- sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
+ constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE, 1, 0); -- sel_a_b(c_use_1GbE,c_unb2_board_nof_eth,0);
-- 10GbE
- constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
- constant c_nof_streams_ring : natural := sel_a_b(c_use_10GbE_ring,c_nof_ring,0);
- constant c_nof_streams_back0 : natural := sel_a_b(c_use_10GbE_back0,c_nof_back0,0);
- constant c_nof_streams_back1 : natural := sel_a_b(c_use_10GbE_back1,c_nof_back1,0);
+ constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp, c_nof_qsfp, 0);
+ constant c_nof_streams_ring : natural := sel_a_b(c_use_10GbE_ring, c_nof_ring, 0);
+ constant c_nof_streams_back0 : natural := sel_a_b(c_use_10GbE_back0, c_nof_back0, 0);
+ constant c_nof_streams_back1 : natural := sel_a_b(c_use_10GbE_back1, c_nof_back1, 0);
constant c_nof_streams_10GbE : natural := c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1;
- constant c_nof_qsfp_bus : natural := ceil_div(c_nof_streams_qsfp,c_unb2_board_tr_qsfp.bus_w);
- constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring,c_unb2_board_tr_ring.bus_w);
- constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0,c_unb2_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2_board_tr_back.bus_w);
+ constant c_nof_qsfp_bus : natural := ceil_div(c_nof_streams_qsfp, c_unb2_board_tr_qsfp.bus_w);
+ constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring, c_unb2_board_tr_ring.bus_w);
+ constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0, c_unb2_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1, c_unb2_board_tr_back.bus_w);
constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
@@ -446,7 +446,7 @@ begin
g_stamp_time => g_stamp_time,
g_stamp_svn => g_stamp_svn,
g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2_board_mm_clk_freq_25M,c_unb2_board_mm_clk_freq_125M),
+ g_mm_clk_freq => sel_a_b(g_sim, c_unb2_board_mm_clk_freq_25M, c_unb2_board_mm_clk_freq_125M),
g_eth_clk_freq => c_unb2_board_eth_clk_freq_125M,
g_aux => c_unb2_board_aux,
g_udp_offload => c_use_1GbE,
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
index 69510a62c4d13b3d2f1c7d1a038c9ab6f4307484..c47e0fe74f2760c16cef27e6b3c82dfcc2d9f4f6 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
@@ -252,7 +252,7 @@ architecture str of ctrl_unb2_board is
constant c_rom_version : natural := 1; -- Only increment when something changes to the register map of rom_system_info.
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
- constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2_board_mm_clk_freq_10M);
+ constant c_mm_clk_freq : natural := sel_a_b(g_sim = false, g_mm_clk_freq, c_unb2_board_mm_clk_freq_10M);
-- Clock and reset
signal i_ext_clk200 : std_logic;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
index 226d6091e3a666822673eee57b30d41e244cb5cc..f72a5aeee46fea8e87d6081cf7dd4ebdebf789e7 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
@@ -56,35 +56,35 @@ architecture rtl of unb2_board_hmc_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index efe7114174765639425ad726eff2c665d6c350ed..2f201817deca8cf548f38983d9ab3bd687fd679b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -56,35 +56,35 @@ architecture rtl of unb2_board_pmbus_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 9da0c246c199f3d96b40c90dda720db9f370a1f9..59708628cdc4f0fef84c8ec68876ba1c64ff0a54 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -70,37 +70,37 @@ architecture rtl of unb2_board_sens_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_SENS_EEPROM_CAT24C02_ADR, CAT24C02_ADR_00,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_HI,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_LO,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_HI,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_LO,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_EEPROM_CAT24C02_ADR, CAT24C02_ADR_00,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_HI,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_LO,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_HI,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_LO,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index dacf249e9ae17f882d7d5452d0a0301e47349381..39b5813291efa0a74eaac9a18d3ebfc68cfda098 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -68,10 +68,10 @@ package common_pkg is
-- logic
constant c_sl0 : std_logic := '0';
constant c_sl1 : std_logic := '1';
- constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0,1);
- constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1,1);
- constant c_signed_0 : signed(1 downto 0) := to_signed(0,2);
- constant c_signed_1 : signed(1 downto 0) := to_signed(1,2);
+ constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0, 1);
+ constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1, 1);
+ constant c_signed_0 : signed(1 downto 0) := to_signed(0, 2);
+ constant c_signed_1 : signed(1 downto 0) := to_signed(1, 2);
constant c_slv0 : std_logic_vector(255 downto 0) := (others => '0');
constant c_slv1 : std_logic_vector(255 downto 0) := (others => '1');
constant c_word_01 : std_logic_vector(31 downto 0) := "01010101010101010101010101010101";
@@ -532,7 +532,7 @@ package body common_pkg is
function ratio2(n, m : natural) return natural is
begin
- return largest(ratio(n,m), ratio(m,n));
+ return largest(ratio(n, m), ratio(m, n));
end;
function ceil_div(n, d : natural) return natural is
@@ -1383,7 +1383,7 @@ package body common_pkg is
begin
for I in 0 to nof_a - 1 loop
for J in 0 to nof_b - 1 loop
- v_mat(I,J) := TO_SVEC(k, 64);
+ v_mat(I, J) := TO_SVEC(k, 64);
end loop;
end loop;
return v_mat;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index dacf249e9ae17f882d7d5452d0a0301e47349381..39b5813291efa0a74eaac9a18d3ebfc68cfda098 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -68,10 +68,10 @@ package common_pkg is
-- logic
constant c_sl0 : std_logic := '0';
constant c_sl1 : std_logic := '1';
- constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0,1);
- constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1,1);
- constant c_signed_0 : signed(1 downto 0) := to_signed(0,2);
- constant c_signed_1 : signed(1 downto 0) := to_signed(1,2);
+ constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0, 1);
+ constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1, 1);
+ constant c_signed_0 : signed(1 downto 0) := to_signed(0, 2);
+ constant c_signed_1 : signed(1 downto 0) := to_signed(1, 2);
constant c_slv0 : std_logic_vector(255 downto 0) := (others => '0');
constant c_slv1 : std_logic_vector(255 downto 0) := (others => '1');
constant c_word_01 : std_logic_vector(31 downto 0) := "01010101010101010101010101010101";
@@ -532,7 +532,7 @@ package body common_pkg is
function ratio2(n, m : natural) return natural is
begin
- return largest(ratio(n,m), ratio(m,n));
+ return largest(ratio(n, m), ratio(m, n));
end;
function ceil_div(n, d : natural) return natural is
@@ -1383,7 +1383,7 @@ package body common_pkg is
begin
for I in 0 to nof_a - 1 loop
for J in 0 to nof_b - 1 loop
- v_mat(I,J) := TO_SVEC(k, 64);
+ v_mat(I, J) := TO_SVEC(k, 64);
end loop;
end loop;
return v_mat;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index dacf249e9ae17f882d7d5452d0a0301e47349381..39b5813291efa0a74eaac9a18d3ebfc68cfda098 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -68,10 +68,10 @@ package common_pkg is
-- logic
constant c_sl0 : std_logic := '0';
constant c_sl1 : std_logic := '1';
- constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0,1);
- constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1,1);
- constant c_signed_0 : signed(1 downto 0) := to_signed(0,2);
- constant c_signed_1 : signed(1 downto 0) := to_signed(1,2);
+ constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0, 1);
+ constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1, 1);
+ constant c_signed_0 : signed(1 downto 0) := to_signed(0, 2);
+ constant c_signed_1 : signed(1 downto 0) := to_signed(1, 2);
constant c_slv0 : std_logic_vector(255 downto 0) := (others => '0');
constant c_slv1 : std_logic_vector(255 downto 0) := (others => '1');
constant c_word_01 : std_logic_vector(31 downto 0) := "01010101010101010101010101010101";
@@ -532,7 +532,7 @@ package body common_pkg is
function ratio2(n, m : natural) return natural is
begin
- return largest(ratio(n,m), ratio(m,n));
+ return largest(ratio(n, m), ratio(m, n));
end;
function ceil_div(n, d : natural) return natural is
@@ -1383,7 +1383,7 @@ package body common_pkg is
begin
for I in 0 to nof_a - 1 loop
for J in 0 to nof_b - 1 loop
- v_mat(I,J) := TO_SVEC(k, 64);
+ v_mat(I, J) := TO_SVEC(k, 64);
end loop;
end loop;
return v_mat;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index dacf249e9ae17f882d7d5452d0a0301e47349381..39b5813291efa0a74eaac9a18d3ebfc68cfda098 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -68,10 +68,10 @@ package common_pkg is
-- logic
constant c_sl0 : std_logic := '0';
constant c_sl1 : std_logic := '1';
- constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0,1);
- constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1,1);
- constant c_signed_0 : signed(1 downto 0) := to_signed(0,2);
- constant c_signed_1 : signed(1 downto 0) := to_signed(1,2);
+ constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0, 1);
+ constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1, 1);
+ constant c_signed_0 : signed(1 downto 0) := to_signed(0, 2);
+ constant c_signed_1 : signed(1 downto 0) := to_signed(1, 2);
constant c_slv0 : std_logic_vector(255 downto 0) := (others => '0');
constant c_slv1 : std_logic_vector(255 downto 0) := (others => '1');
constant c_word_01 : std_logic_vector(31 downto 0) := "01010101010101010101010101010101";
@@ -532,7 +532,7 @@ package body common_pkg is
function ratio2(n, m : natural) return natural is
begin
- return largest(ratio(n,m), ratio(m,n));
+ return largest(ratio(n, m), ratio(m, n));
end;
function ceil_div(n, d : natural) return natural is
@@ -1383,7 +1383,7 @@ package body common_pkg is
begin
for I in 0 to nof_a - 1 loop
for J in 0 to nof_b - 1 loop
- v_mat(I,J) := TO_SVEC(k, 64);
+ v_mat(I, J) := TO_SVEC(k, 64);
end loop;
end loop;
return v_mat;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 7b38390d6c017bdb270e744864d6a4b9d6defa03..7724451df9914a32444863b49bed4678f3c60897 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -426,7 +426,7 @@ begin
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
- mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+ mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index a179bf532dd19b1576a27913b1a9c45d30e7d257..c2449c717265db350df3ebac967dec6c8708687d 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -159,19 +159,19 @@ architecture str of unb2b_test is
constant c_nof_back1 : natural := 0; -- c_unb2b_board_tr_back.bus_w;
-- 1GbE
- constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE,1,0); -- sel_a_b(c_use_1GbE,c_unb2b_board_nof_eth,0);
+ constant c_nof_streams_1GbE : natural := sel_a_b(c_use_1GbE, 1, 0); -- sel_a_b(c_use_1GbE,c_unb2b_board_nof_eth,0);
-- 10GbE
- constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
- constant c_nof_streams_ring : natural := sel_a_b(c_use_10GbE_ring,c_nof_ring,0);
- constant c_nof_streams_back0 : natural := sel_a_b(c_use_10GbE_back0,c_nof_back0,0);
- constant c_nof_streams_back1 : natural := sel_a_b(c_use_10GbE_back1,c_nof_back1,0);
+ constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp, c_nof_qsfp, 0);
+ constant c_nof_streams_ring : natural := sel_a_b(c_use_10GbE_ring, c_nof_ring, 0);
+ constant c_nof_streams_back0 : natural := sel_a_b(c_use_10GbE_back0, c_nof_back0, 0);
+ constant c_nof_streams_back1 : natural := sel_a_b(c_use_10GbE_back1, c_nof_back1, 0);
constant c_nof_streams_10GbE : natural := c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1;
- constant c_nof_qsfp_bus : natural := ceil_div(c_nof_streams_qsfp,c_unb2b_board_tr_qsfp.bus_w);
- constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring,c_unb2b_board_tr_ring.bus_w);
- constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0,c_unb2b_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1,c_unb2b_board_tr_back.bus_w);
+ constant c_nof_qsfp_bus : natural := ceil_div(c_nof_streams_qsfp, c_unb2b_board_tr_qsfp.bus_w);
+ constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring, c_unb2b_board_tr_ring.bus_w);
+ constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0, c_unb2b_board_tr_back.bus_w) + ceil_div(c_nof_streams_back1, c_unb2b_board_tr_back.bus_w);
constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
@@ -443,7 +443,7 @@ begin
g_stamp_time => g_stamp_time,
g_revision_id => g_revision_id,
g_fw_version => c_fw_version,
- g_mm_clk_freq => sel_a_b(g_sim,c_unb2b_board_mm_clk_freq_25M,c_unb2b_board_mm_clk_freq_125M),
+ g_mm_clk_freq => sel_a_b(g_sim, c_unb2b_board_mm_clk_freq_25M, c_unb2b_board_mm_clk_freq_125M),
g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
g_aux => c_unb2b_board_aux,
g_udp_offload => c_use_1GbE,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index a23d26634c2fbf51d0e5ce4ec96d2069c24970cc..fcebd741b5e9f617bb0909bb0309a6188130354e 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -258,7 +258,7 @@ architecture str of ctrl_unb2b_board is
constant c_rom_version : natural := 3; -- Only increment when something changes to the register map of rom_system_info.
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
- constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2b_board_mm_clk_freq_10M);
+ constant c_mm_clk_freq : natural := sel_a_b(g_sim = false, g_mm_clk_freq, c_unb2b_board_mm_clk_freq_10M);
constant c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2**9, 'X');
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
index 06b87a197e1dbb9cfea0f70f306cb3308e86a314..24561d86ed9adff486780785ca0485b21783ed59 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
@@ -56,35 +56,35 @@ architecture rtl of unb2b_board_hmc_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
index c900196512ceae7f91f3fea9cbf0e2aba2b702cd..d1106726eca3bb1ace272ffc7335ce4e9d46ff5d 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
@@ -56,35 +56,35 @@ architecture rtl of unb2b_board_pmbus_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- RX supply
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE, -- TX supply
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
index 60b4028d32b6c4203b3485c3e4794d9ec058570d..f76ad37ca1d0b3e3ee6552291f12e0cddcf9abce 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
@@ -70,37 +70,37 @@ architecture rtl of unb2b_board_sens_ctrl is
constant c_timeout_sda : natural := sel_a_b(g_sim, 0, 16); -- wait 16 * 256 = 4096 clk periods
constant c_SEQ : t_SEQUENCE := (
- SMBUS_READ_BYTE , I2C_UNB2_SENS_EEPROM_CAT24C02_ADR, CAT24C02_ADR_00,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_HI,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_LO,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_HI,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_LO,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_TEMP,
-
- SMBUS_READ_BYTE , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_WORD , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_EEPROM_CAT24C02_ADR, CAT24C02_ADR_00,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_HI,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_LOC_LO,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_HI,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_TMP451_ADR, TMP451_REM_LO,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_TEMP,
+
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT_MODE,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_WORD, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_SAMPLE_SDA, 0, c_timeout_sda, 0, 0,
SMBUS_C_END,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index c42d46238a51097a2d45793968e5cbd2180c1448..d2f3bed7101503c0f3730e89c4d550d2ff70b86b 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -423,7 +423,7 @@ begin
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
- mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+ mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index 2127db9b7344e254dcedb98dc3779bec30f49696..a2b0e6140eb6ad0dcfe1db5cbf7c9ebbac0ccc5e 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -162,16 +162,16 @@ architecture str of unb2c_test is
constant c_base_udp : std_logic_vector(8 - 1 downto 0) := c_eth_tester_udp_src_port_15_8; -- = X"E0"
-- 10GbE
- constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp,c_nof_qsfp,0);
- constant c_nof_streams_ring : natural := sel_a_b(c_use_10GbE_ring,c_nof_ring,0);
- constant c_nof_streams_back0 : natural := sel_a_b(c_use_10GbE_back0,c_nof_back0,0);
- constant c_nof_streams_jesd204b : natural := sel_a_b(c_use_jesd204b,c_nof_jesd204b,0);
+ constant c_nof_streams_qsfp : natural := sel_a_b(c_use_10GbE_qsfp, c_nof_qsfp, 0);
+ constant c_nof_streams_ring : natural := sel_a_b(c_use_10GbE_ring, c_nof_ring, 0);
+ constant c_nof_streams_back0 : natural := sel_a_b(c_use_10GbE_back0, c_nof_back0, 0);
+ constant c_nof_streams_jesd204b : natural := sel_a_b(c_use_jesd204b, c_nof_jesd204b, 0);
constant c_nof_streams_10GbE : natural := c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0;
- constant c_nof_qsfp_bus : natural := ceil_div(c_nof_streams_qsfp,c_unb2c_board_tr_qsfp.bus_w);
- constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring,c_unb2c_board_tr_ring.bus_w);
- constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0,c_unb2c_board_tr_back.bus_w);
+ constant c_nof_qsfp_bus : natural := ceil_div(c_nof_streams_qsfp, c_unb2c_board_tr_qsfp.bus_w);
+ constant c_nof_ring_bus : natural := ceil_div(c_nof_streams_ring, c_unb2c_board_tr_ring.bus_w);
+ constant c_nof_back_bus : natural := ceil_div(c_nof_streams_back0, c_unb2c_board_tr_back.bus_w);
constant c_data_w_32 : natural := c_eth_data_w; -- 1GbE
constant c_data_w_64 : natural := c_xgmii_data_w; -- 10GbE
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index c7f237d4c5ffbb1aefd7369b4a9bf3b43e7c55e3..772f0a77abcde1ccd6d90cee47b7350b19510575 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -77,16 +77,16 @@ package unb2c_test_pkg is
end record;
-- loop 1GbE 1GbE qsfp ring bk0 jesd DDR4 DDR4 heatr
- constant c_test_minimal : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_1GbE_I_UDP : t_unb2c_test_config := (false, true,false,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_1GbE_II_UDP : t_unb2c_test_config := (false, true, true,false,false,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_10GbE : t_unb2c_test_config := (false,false,false, true, true,false,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_10GbE_qb : t_unb2c_test_config := (false,false,false, true,false, true,false,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_ddr : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_ddr_16G : t_unb2c_test_config := (false,false,false,false,false,false,false, true, true,false,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
- constant c_test_ddr_16G_I : t_unb2c_test_config := (false,false,false,false,false,false,false, true,false,false,c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
- constant c_test_heater : t_unb2c_test_config := (false,false,false,false,false,false,false,false,false, true,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
- constant c_test_jesd204b : t_unb2c_test_config := (false,false,false,false,false,false, true,false,false,false,c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_minimal : t_unb2c_test_config := (false, false, false, false, false, false, false, false, false, false, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_1GbE_I_UDP : t_unb2c_test_config := (false, true, false, false, false, false, false, false, false, false, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_1GbE_II_UDP : t_unb2c_test_config := (false, true, true, false, false, false, false, false, false, false, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_10GbE : t_unb2c_test_config := (false, false, false, true, true, false, false, false, false, false, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_10GbE_qb : t_unb2c_test_config := (false, false, false, true, false, true, false, false, false, false, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_ddr : t_unb2c_test_config := (false, false, false, false, false, false, false, true, true, false, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_ddr_16G : t_unb2c_test_config := (false, false, false, false, false, false, false, true, true, false, c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
+ constant c_test_ddr_16G_I : t_unb2c_test_config := (false, false, false, false, false, false, false, true, false, false, c_tech_ddr4_16g_1600m_64, c_tech_ddr4_16g_1600m_72_64);
+ constant c_test_heater : t_unb2c_test_config := (false, false, false, false, false, false, false, false, false, true, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
+ constant c_test_jesd204b : t_unb2c_test_config := (false, false, false, false, false, false, true, false, false, false, c_tech_ddr4_8g_1600m, c_tech_ddr4_8g_1600m);
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_unb2c_test_config;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
index a70a149bd08d3dee249b442ad835ac716ceec948..cfc81d0e611761b4098b1e03d414810cd5e2ad42 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
@@ -78,7 +78,7 @@ architecture str of jtag_top is
IDN => "0000"
);
- p_jtagselect: process(TDI,MSPTDI(jtag_chains - 1 downto 0),TCK,TMS,TRST)
+ p_jtagselect: process(TDI, MSPTDI(jtag_chains - 1 downto 0), TCK, TMS, TRST)
begin
ENABLE_SB <= '0';
MSPTDO(jtag_chains - 1 downto 0) <= "ZZZZZ";
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 74bc5570a961ed53b0fcd6feed3601bfff152d3f..bef86d6dce68fb6c55697810d6fc967acdaeb815 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -242,7 +242,7 @@ architecture str of ctrl_unb2c_board is
constant c_rom_version : natural := 3; -- Only increment when something changes to the register map of rom_system_info.
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
- constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2c_board_mm_clk_freq_10M);
+ constant c_mm_clk_freq : natural := sel_a_b(g_sim = false, g_mm_clk_freq, c_unb2c_board_mm_clk_freq_10M);
constant c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2**9, 'X');
diff --git a/libraries/base/common/src/vhdl/common_demultiplexer.vhd b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
index 52f37b9cd5be508a913914ed8705e79346678cc1..b0cb49c9845b10ab178997fbc09a285f02575c56 100644
--- a/libraries/base/common/src/vhdl/common_demultiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
@@ -87,5 +87,5 @@ begin
-- pipeline output
u_pipe_out_dat : common_pipeline generic map ("SIGNED", g_pipeline_out, 0, g_nof_out * g_dat_w, g_nof_out * g_dat_w) port map (rst, clk, '1', '0', '1', sel_dat, out_dat);
- u_pipe_out_val : common_pipeline generic map ("SIGNED", g_pipeline_out, 0, g_nof_out , g_nof_out ) port map (rst, clk, '1', '0', '1', sel_val, out_val);
+ u_pipe_out_val : common_pipeline generic map ("SIGNED", g_pipeline_out, 0, g_nof_out, g_nof_out ) port map (rst, clk, '1', '0', '1', sel_val, out_val);
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
index de8d0d4caca0b3b9d2dd5e3f1786b1eda623cd8f..52e390a3838d426683ea9f76cb1ab1af84c67023 100644
--- a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
@@ -51,78 +51,78 @@ package common_lfsr_sequences_pkg is
-- (0,0,0,0, 2, 1) yields repeat <0, 1, 2>
-- XNOR feedbacks from outputs for n = 3 .. 72 from Xilinx xapp052.pdf (that lists feedbacks for in total 168 sequences)
- constant c_common_lfsr_sequences : t_SEQUENCES := ((0,0,0,0,0, 1), -- 1 : <0, 1>
- (0,0,0,0, 0, 2), -- 2 : <0, 1, 3, 2>
- (0,0,0,0, 3, 2), -- 3
- (0,0,0,0, 4, 3), -- 4
- (0,0,0,0, 5, 3), -- 5
- (0,0,0,0, 6, 5), -- 6
- (0,0,0,0, 7, 6), -- 7
- (0,0, 8, 6, 5, 4), -- 8
- (0,0,0,0, 9, 5), -- 9
- (0,0,0,0, 10, 7), -- 10
- (0,0,0,0, 11, 9), -- 11
- (0,0, 12, 6, 4, 1), -- 12
- (0,0, 13, 4, 3, 1), -- 13
- (0,0, 14, 5, 3, 1), -- 14
- (0,0,0,0, 15,14 ), -- 15
- (0,0, 16,15,13, 4), -- 16
- (0,0,0,0, 17,14 ), -- 17
- (0,0,0,0, 18,11 ), -- 18
- (0,0, 19, 6, 2, 1), -- 19
- (0,0,0,0, 20,17 ), -- 20
- (0,0,0,0, 21,19 ), -- 21
- (0,0,0,0, 22,21 ), -- 22
- (0,0,0,0, 23,18 ), -- 23
- (0,0, 24,23,22,17), -- 24
- (0,0,0,0, 25,22 ), -- 25
- (0,0, 26, 6, 2, 1), -- 26
- (0,0, 27, 5, 2, 1), -- 27
- (0,0,0,0, 28,25 ), -- 28
- (0,0,0,0, 29,27 ), -- 29
- (0,0, 30, 6, 4, 1), -- 30
- (0,0,0,0, 31,28 ), -- 31
- (0,0, 32,22, 2, 1), -- 32
- (0,0,0,0, 33,20 ), -- 33
- (0,0, 34,27, 2, 1), -- 34
- (0,0,0,0, 35,33 ), -- 35
- (0,0,0,0, 36,25 ), -- 36
+ constant c_common_lfsr_sequences : t_SEQUENCES := ((0, 0, 0, 0, 0, 1), -- 1 : <0, 1>
+ (0, 0, 0, 0, 0, 2), -- 2 : <0, 1, 3, 2>
+ (0, 0, 0, 0, 3, 2), -- 3
+ (0, 0, 0, 0, 4, 3), -- 4
+ (0, 0, 0, 0, 5, 3), -- 5
+ (0, 0, 0, 0, 6, 5), -- 6
+ (0, 0, 0, 0, 7, 6), -- 7
+ (0, 0, 8, 6, 5, 4), -- 8
+ (0, 0, 0, 0, 9, 5), -- 9
+ (0, 0, 0, 0, 10, 7), -- 10
+ (0, 0, 0, 0, 11, 9), -- 11
+ (0, 0, 12, 6, 4, 1), -- 12
+ (0, 0, 13, 4, 3, 1), -- 13
+ (0, 0, 14, 5, 3, 1), -- 14
+ (0, 0, 0, 0, 15, 14 ), -- 15
+ (0, 0, 16, 15, 13, 4), -- 16
+ (0, 0, 0, 0, 17, 14 ), -- 17
+ (0, 0, 0, 0, 18, 11 ), -- 18
+ (0, 0, 19, 6, 2, 1), -- 19
+ (0, 0, 0, 0, 20, 17 ), -- 20
+ (0, 0, 0, 0, 21, 19 ), -- 21
+ (0, 0, 0, 0, 22, 21 ), -- 22
+ (0, 0, 0, 0, 23, 18 ), -- 23
+ (0, 0, 24, 23, 22, 17), -- 24
+ (0, 0, 0, 0, 25, 22 ), -- 25
+ (0, 0, 26, 6, 2, 1), -- 26
+ (0, 0, 27, 5, 2, 1), -- 27
+ (0, 0, 0, 0, 28, 25 ), -- 28
+ (0, 0, 0, 0, 29, 27 ), -- 29
+ (0, 0, 30, 6, 4, 1), -- 30
+ (0, 0, 0, 0, 31, 28 ), -- 31
+ (0, 0, 32, 22, 2, 1), -- 32
+ (0, 0, 0, 0, 33, 20 ), -- 33
+ (0, 0, 34, 27, 2, 1), -- 34
+ (0, 0, 0, 0, 35, 33 ), -- 35
+ (0, 0, 0, 0, 36, 25 ), -- 36
( 37, 5, 4, 3, 2, 1), -- 37
- (0,0, 38, 6, 5, 1), -- 38
- (0,0,0,0, 39,35 ), -- 39
- (0,0, 40,38,21,19), -- 40
- (0,0,0,0, 41,38 ), -- 41
- (0,0, 42,41,20,19), -- 42
- (0,0, 43,42,38,37), -- 43
- (0,0, 44,43,18,17), -- 44
- (0,0, 45,44,42,41), -- 45
- (0,0, 46,45,26,25), -- 46
- (0,0,0,0, 47,42 ), -- 47
- (0,0, 48,47,21,20), -- 48
- (0,0,0,0, 49,40 ), -- 49
- (0,0, 50,49,24,23), -- 50
- (0,0, 51,50,36,35), -- 51
- (0,0,0,0, 52,49 ), -- 52
- (0,0, 53,52,38,37), -- 53
- (0,0, 54,53,18,17), -- 54
- (0,0,0,0, 55,31 ), -- 55
- (0,0, 56,55,35,34), -- 56
- (0,0,0,0, 57,50 ), -- 57
- (0,0,0,0, 58,39 ), -- 58
- (0,0, 59,58,38,37), -- 59
- (0,0,0,0, 60,59 ), -- 60
- (0,0, 61,60,46,45), -- 61
- (0,0, 62,61, 6, 5), -- 62
- (0,0,0,0, 63,62 ), -- 63
- (0,0, 64,63,61,60), -- 64
- (0,0,0,0, 65,47 ), -- 65
- (0,0, 66,65,57,56), -- 66
- (0,0, 67,66,58,57), -- 67
- (0,0,0,0, 68,59 ), -- 68
- (0,0, 69,67,42,40), -- 69
- (0,0, 70,69,55,54), -- 70
- (0,0,0,0, 71,65 ), -- 71
- (0,0, 72,66,25,19)); -- 72
+ (0, 0, 38, 6, 5, 1), -- 38
+ (0, 0, 0, 0, 39, 35 ), -- 39
+ (0, 0, 40, 38, 21, 19), -- 40
+ (0, 0, 0, 0, 41, 38 ), -- 41
+ (0, 0, 42, 41, 20, 19), -- 42
+ (0, 0, 43, 42, 38, 37), -- 43
+ (0, 0, 44, 43, 18, 17), -- 44
+ (0, 0, 45, 44, 42, 41), -- 45
+ (0, 0, 46, 45, 26, 25), -- 46
+ (0, 0, 0, 0, 47, 42 ), -- 47
+ (0, 0, 48, 47, 21, 20), -- 48
+ (0, 0, 0, 0, 49, 40 ), -- 49
+ (0, 0, 50, 49, 24, 23), -- 50
+ (0, 0, 51, 50, 36, 35), -- 51
+ (0, 0, 0, 0, 52, 49 ), -- 52
+ (0, 0, 53, 52, 38, 37), -- 53
+ (0, 0, 54, 53, 18, 17), -- 54
+ (0, 0, 0, 0, 55, 31 ), -- 55
+ (0, 0, 56, 55, 35, 34), -- 56
+ (0, 0, 0, 0, 57, 50 ), -- 57
+ (0, 0, 0, 0, 58, 39 ), -- 58
+ (0, 0, 59, 58, 38, 37), -- 59
+ (0, 0, 0, 0, 60, 59 ), -- 60
+ (0, 0, 61, 60, 46, 45), -- 61
+ (0, 0, 62, 61, 6, 5), -- 62
+ (0, 0, 0, 0, 63, 62 ), -- 63
+ (0, 0, 64, 63, 61, 60), -- 64
+ (0, 0, 0, 0, 65, 47 ), -- 65
+ (0, 0, 66, 65, 57, 56), -- 66
+ (0, 0, 67, 66, 58, 57), -- 67
+ (0, 0, 0, 0, 68, 59 ), -- 68
+ (0, 0, 69, 67, 42, 40), -- 69
+ (0, 0, 70, 69, 55, 54), -- 70
+ (0, 0, 0, 0, 71, 65 ), -- 71
+ (0, 0, 72, 66, 25, 19)); -- 72
-- Procedure for calculating the next PSRG and COUNTER sequence value
procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 1906c4c1bf12a05a695f6214e30d9a05b8298f4a..647f70111985dc2c85195594f415c4ba6b02dd07 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -68,10 +68,10 @@ package common_pkg is
-- logic
constant c_sl0 : std_logic := '0';
constant c_sl1 : std_logic := '1';
- constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0,1);
- constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1,1);
- constant c_signed_0 : signed(1 downto 0) := to_signed(0,2);
- constant c_signed_1 : signed(1 downto 0) := to_signed(1,2);
+ constant c_unsigned_0 : unsigned(0 downto 0) := to_unsigned(0, 1);
+ constant c_unsigned_1 : unsigned(0 downto 0) := to_unsigned(1, 1);
+ constant c_signed_0 : signed(1 downto 0) := to_signed(0, 2);
+ constant c_signed_1 : signed(1 downto 0) := to_signed(1, 2);
constant c_slv0 : std_logic_vector(255 downto 0) := (others => '0');
constant c_slv1 : std_logic_vector(255 downto 0) := (others => '1');
constant c_word_01 : std_logic_vector(31 downto 0) := "01010101010101010101010101010101";
@@ -674,7 +674,7 @@ package body common_pkg is
function ratio2(n, m : natural) return natural is
begin
- return largest(ratio(n,m), ratio(m,n));
+ return largest(ratio(n, m), ratio(m, n));
end;
function almost_equal(a, b, delta : real) return boolean is
@@ -1710,7 +1710,7 @@ package body common_pkg is
begin
for I in 0 to nof_a - 1 loop
for J in 0 to nof_b - 1 loop
- v_mat(I,J) := TO_SVEC(k, 64);
+ v_mat(I, J) := TO_SVEC(k, 64);
end loop;
end loop;
return v_mat;
diff --git a/libraries/base/common/src/vhdl/common_pulse_extend.vhd b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
index 23b38e1ebf0c4f404cd18e126280c803865b4914..1f942bb86e2f5e97abfeee2f06d2586da67a3397 100644
--- a/libraries/base/common/src/vhdl/common_pulse_extend.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
@@ -82,7 +82,7 @@ begin
begin
nxt_cnt <= (others => '0');
if p_in = g_p_in_level then
- nxt_cnt <= std_logic_vector(to_unsigned(1,cnt'length));
+ nxt_cnt <= std_logic_vector(to_unsigned(1, cnt'length));
elsif cnt_is_0 = '0' then
nxt_cnt <= std_logic_vector(unsigned(cnt) + 1);
if g_nof_cycles > 1 and unsigned(cnt) = g_nof_cycles - 1 then
diff --git a/libraries/base/common/src/vhdl/common_shiftreg.vhd b/libraries/base/common/src/vhdl/common_shiftreg.vhd
index e18a57174abfb7bb2165f3de14ee4fab9b2e8780..2dd596346d327daafb02b72a5b73293b51b0889b 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg.vhd
@@ -61,7 +61,7 @@ entity common_shiftreg is
out_val_vec : out std_logic_vector(g_nof_dat - 1 downto 0);
out_sop_vec : out std_logic_vector(g_nof_dat - 1 downto 0);
out_eop_vec : out std_logic_vector(g_nof_dat - 1 downto 0);
- out_cnt : out std_logic_vector(sel_a_b(g_nof_dat = 1,1,ceil_log2(g_nof_dat)) - 1 downto 0); -- avoid ISE synthesis failure on NULL range for g_nof_dat=1
+ out_cnt : out std_logic_vector(sel_a_b(g_nof_dat = 1, 1, ceil_log2(g_nof_dat)) - 1 downto 0); -- avoid ISE synthesis failure on NULL range for g_nof_dat=1
out_dat : out std_logic_vector(g_dat_w - 1 downto 0); -- = out_data_vec(0)
out_val : out std_logic; -- = out_val_vec(0)
diff --git a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
index 6756091b74036d98dd9ca990cc91ef5f6fc23334..f2a1258b825549c68786d4cb1a9fb2baf29c7ca7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
@@ -126,7 +126,7 @@ begin
p_cnt_dat_gaps : process
begin
cnt_rdy <= '0';
- wait for c_clk_period * (ceil_div(g_nof_in,g_nof_out) - 1);
+ wait for c_clk_period * (ceil_div(g_nof_in, g_nof_out) - 1);
cnt_rdy <= '1';
wait for c_clk_period;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
index a2e3cb2e3b6db3b0c8b783dabb56c78052c1d16e..950612a7b6c673b59b2ac1db2da098d8c48ad2d0 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
@@ -53,8 +53,8 @@ entity tb_common_reorder_symbol is
g_nof_input : natural := 5;
g_nof_output : natural := 5;
g_symbol_w : natural := 8;
- g_select_arr : t_natural_arr := (3,3,3,3,3, 3,3,3,3,3); -- array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
- g_pipeline_arr : t_natural_arr := (0,0,0,0,0,0) -- array_init(0, 5) -- range must fit [0:c_N]
+ g_select_arr : t_natural_arr := (3, 3, 3, 3, 3, 3, 3, 3, 3, 3); -- array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
+ g_pipeline_arr : t_natural_arr := (0, 0, 0, 0, 0, 0) -- array_init(0, 5) -- range must fit [0:c_N]
);
end tb_common_reorder_symbol;
diff --git a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
index 5fc43a60f2effd7296ebfdefaa345d0a7e5ac0e3..09e49410315ee9ba2aeb8ce0deee19568c22bd44 100644
--- a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
@@ -43,7 +43,7 @@ entity tb_common_select_m_symbols is
g_pipeline_in : natural := 0; -- pipeline in_data
g_pipeline_in_m : natural := 0; -- pipeline in_data for M-fold fan out
g_pipeline_out : natural := 1; -- pipeline out_data
- g_select_arr : t_natural_arr := (2,3,0,1)
+ g_select_arr : t_natural_arr := (2, 3, 0, 1)
);
end tb_common_select_m_symbols;
diff --git a/libraries/base/common/tb/vhdl/tb_common_switch.vhd b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
index b886c140d3c3ab207d673fca077f4f840a99c9f8..884ced7b4c855832d539ec8be5f0900d35d51a9e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_switch.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
@@ -225,9 +225,9 @@ begin
generic map (
g_rst_level => '0', -- output level at reset.
--g_rst_level => '1',
- g_priority_lo => c_generics_matrix(I,0),
- g_or_high => c_generics_matrix(I,1),
- g_and_low => c_generics_matrix(I,2)
+ g_priority_lo => c_generics_matrix(I, 0),
+ g_or_high => c_generics_matrix(I, 1),
+ g_and_low => c_generics_matrix(I, 2)
)
port map (
clk => clk,
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
index d76e0e916dab65fdcc25e62784fa8e02406fb119..0eee79e8b1900caca45e86bc15c8ee77689fba20 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
@@ -47,5 +47,5 @@ begin
u_val_2_2_4_incr : entity work.tb_common_fanout_tree generic map (false, true, 2, 2, 4, (1, 2), (1, 0));
u_val_3_3_27_incr : entity work.tb_common_fanout_tree generic map (false, true, 3, 3, 27, (1, 3, 9), (2, 1, 0));
u_val_4_3_75_incr : entity work.tb_common_fanout_tree generic map (false, true, 4, 3, 75, (1, 3, 9, 27), (2, 1, 0));
- u_val_8_2_256_equal : entity work.tb_common_fanout_tree generic map (false, true, 8, 2, 256, array_init(1,8), array_init(1,2));
+ u_val_8_2_256_equal : entity work.tb_common_fanout_tree generic map (false, true, 8, 2, 256, array_init(1, 8), array_init(1, 2));
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
index 309b4f2b8c154f874014d7e79b7fc408992e882b..694c11c5d12d323d4ab7b06620740f8978e2a928 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
@@ -38,24 +38,24 @@ begin
-- g_select_arr : t_natural_arr := (3, 3, 3, 3, 3, 0); --array_init(3, 6) -- range must fit [c_N*(c_N-1)/2-1:0]
-- g_pipeline_arr : t_natural_arr := (0,0,0,0,0) --array_init(0, 5) -- range must fit [0:c_N]
- u_3_3_sel_333_p1111 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3,3,3), (1,1,1,1));
- u_3_3_sel_333_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3,3,3), (0,0,0,0));
- u_3_3_sel_330_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3,3,0), (0,0,0,0));
- u_3_3_sel_303_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3,0,3), (0,0,0,0));
- u_3_3_sel_033_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (0,3,3), (0,0,0,0));
- u_3_3_sel_003_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (0,0,3), (0,0,0,0));
- u_3_3_sel_030_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (0,3,0), (0,0,0,0));
- u_3_3_sel_300_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3,0,0), (0,0,0,0));
- u_3_3_sel_000_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (0,0,0), (0,0,0,0));
+ u_3_3_sel_333_p1111 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3, 3, 3), (1, 1, 1, 1));
+ u_3_3_sel_333_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3, 3, 3), (0, 0, 0, 0));
+ u_3_3_sel_330_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3, 3, 0), (0, 0, 0, 0));
+ u_3_3_sel_303_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3, 0, 3), (0, 0, 0, 0));
+ u_3_3_sel_033_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (0, 3, 3), (0, 0, 0, 0));
+ u_3_3_sel_003_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (0, 0, 3), (0, 0, 0, 0));
+ u_3_3_sel_030_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (0, 3, 0), (0, 0, 0, 0));
+ u_3_3_sel_300_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (3, 0, 0), (0, 0, 0, 0));
+ u_3_3_sel_000_p0000 : entity work.tb_common_reorder_symbol generic map (3, 3, 8, (0, 0, 0), (0, 0, 0, 0));
- u_4_4_sel_333333_p11111 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3,3,3,3,3,3), (1,1,1,1,1));
- u_4_4_sel_333333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3,3,3,3,3,3), (0,0,0,0,0));
- u_4_4_sel_333330_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3,3,3,3,3,0), (0,0,0,0,0));
- u_4_4_sel_333303_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3,3,3,3,0,3), (0,0,0,0,0));
- u_4_4_sel_333033_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3,3,3,0,3,3), (0,0,0,0,0));
- u_4_4_sel_330333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3,3,0,3,3,3), (0,0,0,0,0));
- u_4_4_sel_303333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3,0,3,3,3,3), (0,0,0,0,0));
- u_4_4_sel_033333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (0,3,3,3,3,3), (0,0,0,0,0));
+ u_4_4_sel_333333_p11111 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3, 3, 3, 3, 3, 3), (1, 1, 1, 1, 1));
+ u_4_4_sel_333333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3, 3, 3, 3, 3, 3), (0, 0, 0, 0, 0));
+ u_4_4_sel_333330_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3, 3, 3, 3, 3, 0), (0, 0, 0, 0, 0));
+ u_4_4_sel_333303_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3, 3, 3, 3, 0, 3), (0, 0, 0, 0, 0));
+ u_4_4_sel_333033_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3, 3, 3, 0, 3, 3), (0, 0, 0, 0, 0));
+ u_4_4_sel_330333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3, 3, 0, 3, 3, 3), (0, 0, 0, 0, 0));
+ u_4_4_sel_303333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (3, 0, 3, 3, 3, 3), (0, 0, 0, 0, 0));
+ u_4_4_sel_033333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (0, 3, 3, 3, 3, 3), (0, 0, 0, 0, 0));
- u_5_5_sel_3333333333_p000000 : entity work.tb_common_reorder_symbol generic map (5, 5, 8, (3,3,3,3,3,3,3,3,3,3), (0,0,0,0,0,0));
+ u_5_5_sel_3333333333_p000000 : entity work.tb_common_reorder_symbol generic map (5, 5, 8, (3, 3, 3, 3, 3, 3, 3, 3, 3, 3), (0, 0, 0, 0, 0, 0));
end tb;
diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd
index bd3278afea5b92ce79b73619ee18367090a2a300..0cc6464aae6e7919ca6589bc934758714131e68b 100644
--- a/libraries/base/diag/src/vhdl/diag_pkg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd
@@ -236,11 +236,11 @@ package body diag_pkg is
return ( bg_ctrl_int.enable,
bg_ctrl_int.enable_sync,
TO_UVEC(bg_ctrl_int.samples_per_packet, c_diag_bg_samples_per_packet_w),
- TO_UVEC(bg_ctrl_int.blocks_per_sync , c_diag_bg_blocks_per_sync_w),
- TO_UVEC(bg_ctrl_int.gapsize , c_diag_bg_gapsize_w),
- TO_UVEC(bg_ctrl_int.mem_low_adrs , c_diag_bg_mem_low_adrs_w),
- TO_UVEC(bg_ctrl_int.mem_high_adrs , c_diag_bg_mem_high_adrs_w),
- TO_UVEC(bg_ctrl_int.bsn_init , c_diag_bg_bsn_init_w));
+ TO_UVEC(bg_ctrl_int.blocks_per_sync, c_diag_bg_blocks_per_sync_w),
+ TO_UVEC(bg_ctrl_int.gapsize, c_diag_bg_gapsize_w),
+ TO_UVEC(bg_ctrl_int.mem_low_adrs, c_diag_bg_mem_low_adrs_w),
+ TO_UVEC(bg_ctrl_int.mem_high_adrs, c_diag_bg_mem_high_adrs_w),
+ TO_UVEC(bg_ctrl_int.bsn_init, c_diag_bg_bsn_init_w));
end;
function func_diag_bg_ctrl_slv_to_integer(bg_ctrl_slv : t_diag_block_gen) return t_diag_block_gen_integer is
diff --git a/libraries/base/dp/src/vhdl/dp_add_flow_control.vhd b/libraries/base/dp/src/vhdl/dp_add_flow_control.vhd
index 739917a35ef9a1b434fd9992a04d6b3eebe57d5d..f3b5a715f5bc97ffbd4dfa3ed2b8881d5f7c693b 100644
--- a/libraries/base/dp/src/vhdl/dp_add_flow_control.vhd
+++ b/libraries/base/dp/src/vhdl/dp_add_flow_control.vhd
@@ -83,7 +83,7 @@
-- flow control logic may even get entirely optimized away during synthesis
-- when snk_in.ready = '1' fixed.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
index 2c4615062225e116938992f2938b63e0af3a1bfd..19b833ce57c5d1720a1202128482269d3c9609d3 100644
--- a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
+++ b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- Description:
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 96e84bff329d7f69694decb02a38a5b9c9ec8825..9445957155c4435429ccff96ee8abafb4cb1cffc 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -63,7 +63,7 @@
-- is kept at bsn_at_sync.
-- --------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index a5dbf8136b58958fbfc2b228b8f53ed13d73e326..c40af62f011a2a783ffde8bbcfe00eb7bc5f4fff 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -39,7 +39,7 @@
--
-- --------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
index 5e1dce61c28cd8686f0af5b7fc9d5db06be4f3af..38836f046e1004101481532862ef2e42358092fb 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
@@ -71,7 +71,7 @@
-- . dp_block_gen can act as block source, dp_block_reshape can only alter
-- an input block stream.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
index d0d7039eca77f37147710560ded3f457982c4f40..236d5a83d4d9c29ba96310f06e0f1ce5ea76113c 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
@@ -32,7 +32,7 @@
-- of the other streams.
--
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
index 2934cf719e37345e6970b6e9ab2353f0db9fd976..45351f5f61b9f01cce872f3107c83173a6036eb4 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
@@ -64,7 +64,7 @@
-- . With g_reshape_bsn = TRUE this dp_block_reshape_sync is equivalent to
-- dp_sync_insert.vhd.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 0c1cb305606823ade252d499f0f6e54719c9547b..5ef26d90d0054062f0ddb6a8d015c50583f54810 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -25,7 +25,7 @@
-- . https://support.astron.nl/confluence/display/L2M/L5+SDPFW+Design+Document%3A+Subband+filterbank
-- --------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
index f8c6daeaf27d4dc1e0a86bd3b0f4d462fa7e7f8f..e44f57da70480c87925c1f7abc63ed0ca6576ab1 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index e61f67f6d1c107d08a5503175bc68c441091127a..484b5248bc53b3fb72692df2efd3cbe758048d30 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -119,7 +119,7 @@
-- power of two number of blocks, makes the circular buffer control and
-- access more complicated and is not investigated further.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_concat.vhd b/libraries/base/dp/src/vhdl/dp_concat.vhd
index e2d6a58f0de31b72bf1c5cebac263981e076a05b..27cdc9c28116150aaebd32f61fd5f58b2186a2e1 100644
--- a/libraries/base/dp/src/vhdl/dp_concat.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
index c115e41e883e85637f1ea7bc9eac1a4fbb1e4d4d..dfc63459ffd7fa4ee076f64c08c919d6f91ed039 100644
--- a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
@@ -74,7 +74,7 @@ entity dp_concat_field_blk is
end dp_concat_field_blk;
architecture str of dp_concat_field_blk is
- constant c_dp_field_blk_snk_data_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr , "RW"));
+ constant c_dp_field_blk_snk_data_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr, "RW"));
constant c_dp_field_blk_src_data_w : natural := g_data_w;
signal dbg_c_dp_field_blk_snk_data_w : natural := c_dp_field_blk_snk_data_w;
@@ -123,7 +123,7 @@ begin
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr, "RW"),
g_field_sel => g_hdr_field_sel,
g_snk_data_w => c_dp_field_blk_snk_data_w,
g_src_data_w => c_dp_field_blk_src_data_w,
diff --git a/libraries/base/dp/src/vhdl/dp_counter.vhd b/libraries/base/dp/src/vhdl/dp_counter.vhd
index fd007ff4d311a18b5acbea3091bc3851cd46f99d..cd164e348fd74e759d159547257093e3560b2443 100644
--- a/libraries/base/dp/src/vhdl/dp_counter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter.vhd
@@ -62,7 +62,7 @@
-- It only works when g_range_start(i) + count_offset_in_arr(i) < g_range_stop(i)
-- Any other useage will break counters >= stage i
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func.vhd b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
index 9e8f19ea7fb299de539224144807e109e256790a..711efb6254a53d7d2296a8704d2501ddf91eea6d 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
@@ -37,7 +37,7 @@
-- . The extra outputs (e.g. c0_min, c0_max) can be used to trigger other
-- logic when minimum/maximum values per dimension are reached.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
index 01c3d94c4a083a11f3794596d02ae05a34bf6f91..848477776a4dad121c480a4f7a27599af6e1d7de 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
@@ -28,7 +28,7 @@
-- Usage:
-- . Not for standalone use; part of dp_counter_func.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
index 9c54eddb6a363cf469a0edb78f312d3235749a9b..9e1cfb3addfa6909374800a342518044bb4691de 100644
--- a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
index aea3de86d75eeb404cded71d73fb6ba2e9b20b91..6ac5006541648d8703f3a6330aa5ca3760ba008a 100755
--- a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_demux.vhd b/libraries/base/dp/src/vhdl/dp_demux.vhd
index f70721856d148527ca0ca2e041dab4a0107c098d..0b4a7a99a140208e69e999fb8ca0f2123d56a0a9 100644
--- a/libraries/base/dp/src/vhdl/dp_demux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_demux.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_distribute.vhd b/libraries/base/dp/src/vhdl/dp_distribute.vhd
index 4165fd637055cd2ac3a3fb7b73ad9388147200f9..82d9419fd97afe0cf78d0cdcf7f2aab7dcc80b45 100644
--- a/libraries/base/dp/src/vhdl/dp_distribute.vhd
+++ b/libraries/base/dp/src/vhdl/dp_distribute.vhd
@@ -75,7 +75,7 @@
-- . Thanks to the non-blocking dp_mux the distribution continuous when a frame
-- gets lost or an input is not used.
-library IEEE,common_lib, technology_lib;
+library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index 3ec0c419a8368a0b4a1730d264765f4a3405d620..4a0c776339c694d58a4bd551773ebeac17866697 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -22,7 +22,7 @@
-- Purpose: DP FIFO for dual clock (= dc) domain wr and rd.
-- Description: See dp_fifo_core.vhd.
-library IEEE,common_lib, technology_lib;
+library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
index 5a6d2b1441b06c503b019b891732c203a0c3c30e..c4bcccba5462b7f5dafbdf33e12c1a42ebe4a2ed 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -24,7 +24,7 @@
-- Purpose: DP FIFO array for dual clock (= dc) domain wr and rd.
-- Description: See dp_fifo_core_arr.vhd.
-library IEEE,common_lib, technology_lib;
+library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index 1ff22a1a71f019ff5204f1c73543dc5581a91022..42a77dfb43366c88f6a1b40a6cd4ccc918e12421 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -22,7 +22,7 @@
-- Purpose: DP FIFO for single clock (= sc) domain wr and rd.
-- Description: See dp_fifo_core.vhd.
-library IEEE,common_lib, technology_lib;
+library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_frame.vhd b/libraries/base/dp/src/vhdl/dp_frame.vhd
index c60355be35a771512e0c64b922e20d5eecd30133..86322d027496d2e538f9aae8dab30ef5a1a7c139 100644
--- a/libraries/base/dp/src/vhdl/dp_frame.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame.vhd
@@ -85,8 +85,8 @@ architecture rtl of dp_frame is
-- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
constant c_input_reg : boolean := false;
- constant c_brc_ok : std_logic_vector(in_dat'range) := std_logic_vector(to_unsigned(c_dp_brc_ok ,in_dat'length));
- constant c_brc_err : std_logic_vector(in_dat'range) := std_logic_vector(to_unsigned(c_dp_brc_err,in_dat'length));
+ constant c_brc_ok : std_logic_vector(in_dat'range) := std_logic_vector(to_unsigned(c_dp_brc_ok, in_dat'length));
+ constant c_brc_err : std_logic_vector(in_dat'range) := std_logic_vector(to_unsigned(c_dp_brc_err, in_dat'length));
-- Registered inputs (see c_input_reg)
signal in_fsn_reg : std_logic_vector(in_fsn'range);
@@ -181,7 +181,7 @@ begin
-- overrule default nxt_out_dat
if in_sof_reg = '1' then -- insert fsn, no need to delay input fsn, because it holds
- nxt_out_dat <= RESIZE_SVEC(in_fsn_reg,out_dat'length); -- sign extend is fsync,
+ nxt_out_dat <= RESIZE_SVEC(in_fsn_reg, out_dat'length); -- sign extend is fsync,
nxt_out_val <= '1';
nxt_out_sof <= '1';
elsif in_eof_dly2 = '1' then
diff --git a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
index 4aab4563dadf030151ecdff3e1096011a24545f8..7e82d1515df8810d56617512ce7597d3648faac1 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
@@ -110,7 +110,7 @@ begin
out_eof => repack_eof
);
- repack_fsn <= RESIZE_SVEC(pack_fsn,repack_fsn'length); -- pack_fsn remains valid
+ repack_fsn <= RESIZE_SVEC(pack_fsn, repack_fsn'length); -- pack_fsn remains valid
frame : entity work.dp_frame
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
index 6a5304e97b99986ec0aa59e0d2326aacebfceae3..58b3a482af716093917da3cda10b404fb0d835bb 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
@@ -103,8 +103,8 @@ architecture rtl of dp_frame_rx is
constant c_idle : std_logic_vector := c_dp_idle(in_dat'range);
constant c_sfd : std_logic_vector := g_sfd(in_dat'range);
- constant c_brc_ok : std_logic_vector := std_logic_vector(to_unsigned(c_dp_brc_ok ,g_dat_w));
- constant c_brc_err : std_logic_vector := std_logic_vector(to_unsigned(c_dp_brc_err,g_dat_w));
+ constant c_brc_ok : std_logic_vector := std_logic_vector(to_unsigned(c_dp_brc_ok, g_dat_w));
+ constant c_brc_err : std_logic_vector := std_logic_vector(to_unsigned(c_dp_brc_err, g_dat_w));
constant c_timeout_cnt_w : natural := g_timeout_w + 1;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
index 6d587242c714b91955a5a045c0c90bd96e81b6fc..1066e3d820c2cc853479af1fe749c7e35f13f3d2 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
@@ -40,7 +40,7 @@
-- dp_xonoff ensures that in_dis is applied during entire frames and before
-- they are written into the input FIFO.
-library IEEE,common_lib, technology_lib;
+library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_status.vhd b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
index abff3ccbce1c083e43e0999622f2285906f6e407..7c8e7dd4b23987d3ae44c2c5c08732d777a0085d 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_status.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
@@ -29,7 +29,7 @@
-- The status output is aggregate input discarded & frame sync & aggregate brc & count nof rx frames. The
-- status applies to the interval before the previous sync interval, due to the data processing latency.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
index 01dbbf256a3037d038122e4ba592fdce060154ab..7ed95725e6ee6406595987378c4c22f05840fe2f 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
@@ -89,7 +89,7 @@ architecture rtl of dp_frame_tx is
constant c_idle : std_logic_vector := c_dp_idle(in_dat'range);
constant c_sfd : std_logic_vector := g_sfd(in_dat'range);
- constant c_brc_ok : std_logic_vector := std_logic_vector(to_unsigned(c_dp_brc_ok ,g_dat_w));
+ constant c_brc_ok : std_logic_vector := std_logic_vector(to_unsigned(c_dp_brc_ok, g_dat_w));
signal crc : std_logic_vector(c_dp_crc_w - 1 downto 0);
signal nxt_crc : std_logic_vector(crc'range);
diff --git a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
index 5335ee16ed78480f4a624009dcb6de60297a4bb6..2729a1067639057e60a7bc928f51c036e5034b85 100755
--- a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
+++ b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_loopback.vhd b/libraries/base/dp/src/vhdl/dp_loopback.vhd
index c28f0223b38c2075e710c0decdd323ac3b4d3bc6..1d1f273cc85fa5f5b6b0d83186f69844b21e1e92 100644
--- a/libraries/base/dp/src/vhdl/dp_loopback.vhd
+++ b/libraries/base/dp/src/vhdl/dp_loopback.vhd
@@ -18,7 +18,7 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index 6a40ad62d17cd46f0bdf21138f4e42683428a66d..702ee9294f1f00c4c9842358cf383ab00c90e865 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -78,7 +78,7 @@
-- . For multiplexing time series frames or sample it can be applicable to
-- use g_append_channel_lo=FALSE in combination with g_mode=2.
-library IEEE,common_lib, technology_lib;
+library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
index 374201d300f1a3efa12bd2673c87a690242d40b7..e5a52b09f9296463f3f85e5c5c82f03b3f23aa53 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
@@ -102,7 +102,7 @@ architecture str of dp_offload_rx is
signal dp_tail_remove_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
constant c_dp_field_blk_snk_data_w : natural := g_data_w;
- constant c_dp_field_blk_src_data_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"));
+ constant c_dp_field_blk_src_data_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr, "RO"));
begin
---------------------------------------------------------------------------------------
-- Remove header
@@ -139,7 +139,7 @@ begin
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
u_dp_field_blk : entity work.dp_field_blk
generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RO"),
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr, "RO"),
g_field_sel => c_field_sel,
g_snk_data_w => c_dp_field_blk_snk_data_w, -- g_data_w,
g_src_data_w => c_dp_field_blk_src_data_w, -- field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"))
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
index f21d8df41643b97d8deef8172178d16cedaabb13..bb626dbb9222c2faf0668c3b633e7a6a2132ce4c 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
@@ -54,7 +54,7 @@ entity dp_offload_rx_filter is
end dp_offload_rx_filter;
architecture str of dp_offload_rx_filter is
- constant c_header_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"));
+ constant c_header_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr, "RO"));
constant c_nof_words: natural := c_header_w / g_data_w;
constant c_head : natural := 1;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
index ae1a6d18cd781bb503be493c49162fe0af613bcc..0ab3b748ca59c1988f629df847196b7c01f3b581 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
@@ -57,13 +57,13 @@ entity dp_offload_rx_filter_mm is
end dp_offload_rx_filter_mm;
architecture str of dp_offload_rx_filter_mm is
- constant c_header_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"));
+ constant c_header_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr, "RO"));
constant c_nof_words: natural := c_header_w / g_data_w;
constant c_head : natural := 1;
constant c_tail : natural := 0;
- constant c_field_slv_out_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr , "RW"));
+ constant c_field_slv_out_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr, "RW"));
constant c_nof_ena : natural := 4;
constant c_reg_w : natural := c_nof_ena * c_word_w;
@@ -223,7 +223,7 @@ begin
u_mm_fields_slv: entity mm_lib.mm_fields
generic map(
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr, "RW")
)
port map (
mm_clk => mm_clk,
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
index e88d96a678f6c1bb1baa800c0e18d7eba17b0c01..71469529b4426e2a3f8495ea0ac50f38db79700c 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
@@ -87,7 +87,7 @@ architecture str of dp_offload_tx is
constant c_dp_packet_merge_val_latency : natural := 2;
constant c_nof_header_words : natural := field_nof_words(g_hdr_field_arr, g_data_w);
constant c_nof_merged_pkt_words : natural := g_nof_words_per_block * g_nof_blocks_per_packet;
- constant c_dp_field_blk_snk_data_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr , "RW"));
+ constant c_dp_field_blk_snk_data_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr, "RW"));
constant c_dp_field_blk_src_data_w : natural := g_data_w;
-- Internal FIFO fill level: one merged packet (to provide an uninterrupted output packet)
@@ -294,7 +294,7 @@ begin
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr, "RW"),
g_field_sel => g_hdr_field_sel,
g_snk_data_w => c_dp_field_blk_snk_data_w,
g_src_data_w => c_dp_field_blk_src_data_w
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
index 4242e252a3c9ef2f0df6c281231fb367de73f503..032a348855e1b3e587911b2d4d4c35df81af17ee 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
@@ -79,7 +79,7 @@ entity dp_offload_tx_v3 is
end dp_offload_tx_v3;
architecture str of dp_offload_tx_v3 is
- constant c_dp_field_blk_snk_data_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr , "RW"));
+ constant c_dp_field_blk_snk_data_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr, "RW"));
constant c_dp_field_blk_src_data_w : natural := g_data_w;
signal dbg_c_dp_field_blk_snk_data_w : natural := c_dp_field_blk_snk_data_w;
@@ -152,7 +152,7 @@ begin
---------------------------------------------------------------------------------------
u_mm_fields_slv: entity mm_lib.mm_fields
generic map(
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW")
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr, "RW")
)
port map (
mm_clk => mm_clk,
@@ -170,7 +170,7 @@ begin
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
generic map (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr, "RW"),
g_field_sel => g_hdr_field_sel,
g_snk_data_w => c_dp_field_blk_snk_data_w,
g_src_data_w => c_dp_field_blk_src_data_w,
diff --git a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
index 08011772520ca371f8a98548e918e3421cd0749a..c4fb4c1f25e229c3ebd8fd95d092f9f80e46f684 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index 9aece76e341e24dbe289499c3b71d48b5243fd6c..3d739b3edea80ea041f7925de31bebd8e652df5b 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -49,7 +49,7 @@
-- . The input packets do not have to have equal length, because they are
-- merged based on counting their eop.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
index 8f706fe08b9b1afe5fab7b674ae91aedd939696d..648e1b3db77b6d1fb6e595daefcd9e9457fcbcd1 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
@@ -63,7 +63,7 @@
-- dynamic pkt_len control. When the pkt_len control input is used, g_pkt_len
-- sets the maximum number length of the unmerged packets.
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
index 2c64e9af365815eb697055ff2584e28cab76db8b..a0c634d9bbba0e4ec6b75b1f7cb661640e75742a 100644
--- a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
@@ -103,8 +103,8 @@ package body dp_packetizing_pkg is
case dat'length is
when 1 to 4 => nxt_crc := nextCRC16_D4( RESIZE_UVEC(dat, 4), crc);
when 5 to 8 => nxt_crc := nextCRC16_D8( RESIZE_UVEC(dat, 8), crc);
- when 9 => nxt_crc := nextCRC16_D9( dat , crc);
- when 10 => nxt_crc := nextCRC16_D10( dat , crc);
+ when 9 => nxt_crc := nextCRC16_D9( dat, crc);
+ when 10 => nxt_crc := nextCRC16_D10( dat, crc);
when 11 to 16 => nxt_crc := nextCRC16_D16(RESIZE_UVEC(dat, 16), crc);
when 17 to 18 => nxt_crc := nextCRC16_D18(RESIZE_UVEC(dat, 18), crc);
when 19 to 20 => nxt_crc := nextCRC16_D20(RESIZE_UVEC(dat, 20), crc);
@@ -121,8 +121,8 @@ package body dp_packetizing_pkg is
case dat'length is
when 1 to 4 => nxt_crc := nextCRC32_D4( RESIZE_UVEC(dat, 4), crc);
when 5 to 8 => nxt_crc := nextCRC32_D8( RESIZE_UVEC(dat, 8), crc);
- when 9 => nxt_crc := nextCRC32_D9( dat , crc);
- when 10 => nxt_crc := nextCRC32_D10( dat , crc);
+ when 9 => nxt_crc := nextCRC32_D9( dat, crc);
+ when 10 => nxt_crc := nextCRC32_D10( dat, crc);
when 11 to 16 => nxt_crc := nextCRC32_D16(RESIZE_UVEC(dat, 16), crc);
when 17 to 18 => nxt_crc := nextCRC32_D18(RESIZE_UVEC(dat, 18), crc);
when 19 to 20 => nxt_crc := nextCRC32_D20(RESIZE_UVEC(dat, 20), crc);
diff --git a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
index 6d85066f23931ab92e7285e9c0340133e377705e..ae86184b71af1cacae5d71f4f139eb72c7d9189b 100644
--- a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_repack.vhd b/libraries/base/dp/src/vhdl/dp_repack.vhd
index ebc3dd4c1b829e0f05476741b0623d7f483619e9..c30907c8837d3459fddaf9954c64998e87db571d 100644
--- a/libraries/base/dp/src/vhdl/dp_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack.vhd
@@ -216,12 +216,12 @@ begin
else
if g_ls_to_ms = true then
-- Push SLV to the right so new word appears at LS position
- nxt_out_dat_vec <= std_logic_vector(to_unsigned(0,out_dat'length)) &
+ nxt_out_dat_vec <= std_logic_vector(to_unsigned(0, out_dat'length)) &
out_dat_vec(out_dat_vec'high downto out_dat'length);
else
-- Push SLV to the left so new word appears at MS position
nxt_out_dat_vec <= out_dat_vec(out_dat_vec'high - out_dat'length downto 0) &
- std_logic_vector(to_unsigned(0,out_dat'length));
+ std_logic_vector(to_unsigned(0, out_dat'length));
end if;
nxt_out_val_vec <= '0' & out_val_vec(out_val_vec'high downto 1);
diff --git a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
index 5149b5f2aa0e10f745d397dc9562715acf3a1058..9b38b600dc71df0c22c9d0b15d1cb9124c6b70bc 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
@@ -216,12 +216,12 @@ begin
else
if g_ls_to_ms = true then
-- Push SLV to the right so new word appears at LS position
- nxt_out_dat_vec <= std_logic_vector(to_unsigned(0,out_dat'length)) &
+ nxt_out_dat_vec <= std_logic_vector(to_unsigned(0, out_dat'length)) &
out_dat_vec(out_dat_vec'high downto out_dat'length);
else
-- Push SLV to the left so new word appears at MS position
nxt_out_dat_vec <= out_dat_vec(out_dat_vec'high - out_dat'length downto 0) &
- std_logic_vector(to_unsigned(0,out_dat'length));
+ std_logic_vector(to_unsigned(0, out_dat'length));
end if;
nxt_out_val_vec <= '0' & out_val_vec(out_val_vec'high downto 1);
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
index 7e76bc93ba2fda5f3dbb0ee1e46025cd77b1f1a0..3a391b076658e433888f54ca6a4707c96f93777e 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
@@ -18,7 +18,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
index 77741d7694fc2fd2e24368c07c94994743ee86ab..017458fd7d4de8bbac11efe38db3ea28f9936880 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
@@ -18,7 +18,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_split.vhd b/libraries/base/dp/src/vhdl/dp_split.vhd
index 19ac1fb2b5140c73dc0ba9b4000292b702788c65..14f0547efc5f9e867009400f246e7969b3e8b2b9 100644
--- a/libraries/base/dp/src/vhdl/dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
index e47aa13cbc082f269f16527fd5c4d6bcc6e09aa2..80926f2706bc064bf1382f5d77de65cab1079043 100644
--- a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
+++ b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
@@ -19,7 +19,7 @@
--
--------------------------------------------------------------------------------
-library IEEE,common_lib;
+library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/base/dp/src/vhdl/dp_unframe.vhd b/libraries/base/dp/src/vhdl/dp_unframe.vhd
index 2e9d0f5b21e5c852c17edee51b699a5beabc3431..0178a44fe4c990ab6cc41be6d378d6cf7984c13f 100644
--- a/libraries/base/dp/src/vhdl/dp_unframe.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unframe.vhd
@@ -85,8 +85,8 @@ architecture rtl of dp_unframe is
-- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
constant c_input_reg : boolean := false;
- constant c_brc_ok : std_logic_vector(in_dat'range) := std_logic_vector(to_unsigned(c_dp_brc_ok ,in_dat'length));
- constant c_brc_err : std_logic_vector(in_dat'range) := std_logic_vector(to_unsigned(c_dp_brc_err,in_dat'length));
+ constant c_brc_ok : std_logic_vector(in_dat'range) := std_logic_vector(to_unsigned(c_dp_brc_ok, in_dat'length));
+ constant c_brc_err : std_logic_vector(in_dat'range) := std_logic_vector(to_unsigned(c_dp_brc_err, in_dat'length));
-- Registered inputs (see c_input_reg)
signal in_dat_reg : std_logic_vector(in_dat'range);
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
index 63de286f7c454f9e294ebe2725b020774714f619..7ea9233a9fe332224da7955e8e846933cc9ea060 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
@@ -154,7 +154,7 @@ begin
force_en => force_en,
force_value => force_value,
force_zero_n => force_zero_n,
- force_data => force_data ,
+ force_data => force_data,
force_re => force_re,
force_im => force_im,
force_index => force_index,
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
index de5f5139e019b4afd37b3280ca0e1788e993a306..e201739f6caf3b8f34b3ceb183ec0dd29168ab67 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
@@ -214,7 +214,7 @@ begin
end loop;
-- End of stimuli
- expected_out_data(I,J) <= TO_UVEC(v_data_init - 1, c_data_w);
+ expected_out_data(I, J) <= TO_UVEC(v_data_init - 1, c_data_w);
wait;
end process;
end generate;
@@ -229,17 +229,17 @@ begin
gen_verify : for I in 0 to c_nof_type-1 generate
gen_output : for J in 0 to c_nof_input - 1 generate
-- Verification logistics
- verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
- count_eop(I,J) <= count_eop(I,J) + 1 when rising_edge(clk) and out_sosi_2arr(I)(J).eop = '1'; -- count number of output eop
- verify_done(I,J) <= '1' when rising_edge(clk) and count_eop(I,J) = c_out_repeat_arr(I * c_nof_input + J) and count_eop(I,J) /= prev_count_eop(I,J) else '0';
- tb_end_vec(I * c_nof_input + J) <= '1' when rising_edge(clk) and count_eop(I,J) = c_out_repeat_arr(I * c_nof_input + J);
+ verify_en(I, J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
+ count_eop(I, J) <= count_eop(I, J) + 1 when rising_edge(clk) and out_sosi_2arr(I)(J).eop = '1'; -- count number of output eop
+ verify_done(I, J) <= '1' when rising_edge(clk) and count_eop(I, J) = c_out_repeat_arr(I * c_nof_input + J) and count_eop(I, J) /= prev_count_eop(I, J) else '0';
+ tb_end_vec(I * c_nof_input + J) <= '1' when rising_edge(clk) and count_eop(I, J) = c_out_repeat_arr(I * c_nof_input + J);
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi_2arr.data", c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, out_sosi_2arr(I)(J).valid, out_data(I,J), prev_out_data(I,J)); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, prev_out_ready(I,J), out_sosi_2arr(I)(J).valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi_2arr(I)(J).valid, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).eop, hold_out_sop(I,J)); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done(I,J), expected_out_data(I,J), prev_out_data(I,J)); -- Verify that the stimuli have been applied at all
- proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en(I,J), out_sosi_2arr(I)(J).sync, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).bsn);
+ proc_dp_verify_data("out_sosi_2arr.data", c_rl, clk, verify_en(I, J), out_siso_2arr(I)(J).ready, out_sosi_2arr(I)(J).valid, out_data(I, J), prev_out_data(I, J)); -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_valid(c_rl, clk, verify_en(I, J), out_siso_2arr(I)(J).ready, prev_out_ready(I, J), out_sosi_2arr(I)(J).valid); -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_sop_and_eop(clk, out_sosi_2arr(I)(J).valid, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).eop, hold_out_sop(I, J)); -- Verify that sop and eop come in pairs
+ proc_dp_verify_value(e_equal, clk, verify_done(I, J), expected_out_data(I, J), prev_out_data(I, J)); -- Verify that the stimuli have been applied at all
+ proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en(I, J), out_sosi_2arr(I)(J).sync, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).bsn);
end generate;
end generate;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index b8030bfb668188ed5d08feab8ba81c3d93ccd442..b874761a171a63b4bc40c5a6714f467233381792 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -163,7 +163,7 @@ begin
p_read_ram : process
begin
ram_rd_en <= '0';
- ram_rd_adr <= TO_UVEC(0 , c_ram.adr_w);
+ ram_rd_adr <= TO_UVEC(0, c_ram.adr_w);
proc_common_wait_until_high(clk, transfer_done);
ram_rd_en <= '1';
for i in 0 to c_ram_data_size - 1 loop
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
index e4ceabe74ded544ff68ac1da6ed7d0e1ece038e7..55bfa14c93dc3bca40c85e200064745dce2491ca 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
@@ -113,7 +113,7 @@ begin
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 5, 5, v_bsn + 2, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0)); -- 5, 6, 7, 8, 9
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 16, 10, v_bsn + 3, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0)); -- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 37, 50, v_bsn + 4, '1', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 137,101, v_bsn + 5, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 137, 101, v_bsn + 5, '0', clk, in_en(0), in_siso_arr(0), in_sosi_arr(0));
wait;
end process;
@@ -132,7 +132,7 @@ begin
wait for 15 * c_period;
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 26, 11, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1)); -- 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36
proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 87, 50, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
- proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 238,100, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
+ proc_dp_gen_frame(c_rl, g_data_w, g_symbol_w, 238, 100, 0, '1', clk, in_en(1), in_siso_arr(1), in_sosi_arr(1));
-- the end
expected_data <= TO_UVEC(136, g_data_w);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
index 50c0401ffe35f78b823caac59d9754c36cfe1961..3d341e7d6003c60a5789e7d9be1b7dfa53bc8c35 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
@@ -51,9 +51,9 @@ entity tb_dp_counter is
g_pipeline_src_in : natural := 0; -- Pipeline source inputs (ready,xon). This will also pipeline src_out.
g_nof_counters : natural := 3;
-- min range = [0,2,1] => (0,1) 'the Python way'
- g_range_start : t_nat_natural_arr(9 downto 0) := (0,0,0,0,0,0,0, 1, 0, 0);
- g_range_stop : t_nat_natural_arr(9 downto 0) := (2,2,2,2,2,2,7,16,16, 1);
- g_range_step : t_nat_natural_arr(9 downto 0) := (1,1,1,1,1,1,2, 2, 2, 1)
+ g_range_start : t_nat_natural_arr(9 downto 0) := (0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
+ g_range_stop : t_nat_natural_arr(9 downto 0) := (2, 2, 2, 2, 2, 2, 7, 16, 16, 1);
+ g_range_step : t_nat_natural_arr(9 downto 0) := (1, 1, 1, 1, 1, 1, 2, 2, 2, 1)
);
end tb_dp_counter;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
index 2eef1c0aabe5bb7ea7e2ad9b9d67f3b47e3c2a36..0212988e86d2907d43ef84b2e9da618917f9246b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
@@ -50,9 +50,9 @@ entity tb_dp_counter_func is
generic (
g_nof_counters : natural := 2;
-- min range = [0,2,1] => (0,1) 'the python way'
- g_range_start : t_nat_natural_arr(9 downto 0) := (0,0,0,0,0,0,0, 1, 0, 0);
- g_range_stop : t_nat_natural_arr(9 downto 0) := (2,2,2,2,2,2,7,16,16,16);
- g_range_step : t_nat_natural_arr(9 downto 0) := (1,1,1,1,1,1,2, 2, 2, 1)
+ g_range_start : t_nat_natural_arr(9 downto 0) := (0, 0, 0, 0, 0, 0, 0, 1, 0, 0);
+ g_range_stop : t_nat_natural_arr(9 downto 0) := (2, 2, 2, 2, 2, 2, 7, 16, 16, 16);
+ g_range_step : t_nat_natural_arr(9 downto 0) := (1, 1, 1, 1, 1, 1, 2, 2, 2, 1)
);
end tb_dp_counter_func;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
index 0d79d8e8f69e8bfae23a695169653267af9d8078..4c0d3633c2b0759344ad0e8dabb04da77e241986 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
@@ -52,9 +52,9 @@ entity tb_dp_counter_offset is
g_nof_counters : natural := 3;
-- min range = [0,2,1] => (0,1) 'the Python way'
--g_range_start : t_nat_natural_arr(9 DOWNTO 0) := (0,0,0,0,0,0,0, 1, 0, 0);
- g_range_start : t_nat_natural_arr(9 downto 0) := (0,0,0,0,0,0,0, 0, 1, 0);
- g_range_stop : t_nat_natural_arr(9 downto 0) := (2,2,2,2,2,2,7,16,16,16);
- g_range_step : t_nat_natural_arr(9 downto 0) := (1,1,1,1,1,1,2, 2, 2, 1)
+ g_range_start : t_nat_natural_arr(9 downto 0) := (0, 0, 0, 0, 0, 0, 0, 0, 1, 0);
+ g_range_stop : t_nat_natural_arr(9 downto 0) := (2, 2, 2, 2, 2, 2, 7, 16, 16, 16);
+ g_range_step : t_nat_natural_arr(9 downto 0) := (1, 1, 1, 1, 1, 1, 2, 2, 2, 1)
);
end tb_dp_counter_offset;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
index f0d5e7bde9cc567b2d583ebaf038e3f8adf32b95..45b691744bca9c09bab4661c10a2134e1a95c839 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
@@ -226,7 +226,7 @@ begin
proc_dp_verify_data("rx_sosi.err", c_rl, clk, verify_en, rx_siso.ready, rx_eop, rx_err, prev_rx_err); -- Verify that the output is incrementing err, like the input stimuli
proc_dp_verify_value(e_equal, clk, verify_done, expected_rx_err, prev_rx_err); -- Verify that the stimuli have been applied at all
- proc_dp_verify_data("rx_sosi.channel", c_rl, to_unsigned(c_nof_ch - 1,32), clk, verify_en, rx_siso.ready, rx_sop, rx_channel, prev_rx_channel); -- Verify that the output is incrementing channel MOD c_nof_ch, like the input stimuli
+ proc_dp_verify_data("rx_sosi.channel", c_rl, to_unsigned(c_nof_ch - 1, 32), clk, verify_en, rx_siso.ready, rx_sop, rx_channel, prev_rx_channel); -- Verify that the output is incrementing channel MOD c_nof_ch, like the input stimuli
proc_dp_verify_valid(c_rl, clk, verify_en, pkt_siso.ready, prev_pkt_ready, pkt_val); -- Verify that the encoder output valid fits with the output ready latency
proc_dp_verify_valid(c_rl, clk, verify_en, rx_siso.ready, prev_rx_ready, rx_val); -- Verify that the output valid fits with the output ready latency
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
index 42624ba3ea0b2b1778240d19a80e9e19e62df7b4..2adb0cb2d7de12b4f8dbb258f7d3680402afac9a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
@@ -94,7 +94,7 @@ architecture tb of tb_dp_packet_merge is
constant c_nof_pkt_not_zero : natural := sel_a_b(g_nof_pkt = 0, 1, g_nof_pkt);
constant c_nof_merged_sop : natural := sel_a_b(g_nof_pkt = 0, 0, ceil_div(g_nof_repeat, c_nof_pkt_not_zero));
- constant c_verify_at_least : natural := largest(1,c_nof_merged_sop / 2); -- verify that at least some packets have been merged, not exact to allow variation by p_stimuli_mm
+ constant c_verify_at_least : natural := largest(1, c_nof_merged_sop / 2); -- verify that at least some packets have been merged, not exact to allow variation by p_stimuli_mm
constant c_verify_data_gap : natural := g_nof_pkt;
constant c_verify_bsn_gap : natural := g_nof_pkt * g_bsn_increment;
constant c_exp_err_at_pkt_index : natural := g_bsn_err_at_pkt_index / sel_a_b(g_nof_pkt = 0, 1, g_nof_pkt);
@@ -256,10 +256,10 @@ begin
gen_verify_err : if g_nof_pkt = 1 generate
-- Assume verifying g_nof_pkt = 1 is sufficient. Verifing g_nof_pkt > 1 is more difficult,
-- because the merged output error field is the bitwise OR of the input error fields
- proc_dp_verify_data("verify_snk_in.err", c_rl, c_unsigned_0, to_unsigned(c_verify_data_gap,32), clk, verify_en_eop, verify_snk_out.ready, verify_snk_in.eop, verify_snk_in.err, prev_verify_snk_in.err);
+ proc_dp_verify_data("verify_snk_in.err", c_rl, c_unsigned_0, to_unsigned(c_verify_data_gap, 32), clk, verify_en_eop, verify_snk_out.ready, verify_snk_in.eop, verify_snk_in.err, prev_verify_snk_in.err);
end generate;
end generate;
- proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, to_unsigned(c_verify_data_gap,32), clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.channel, prev_verify_snk_in.channel);
+ proc_dp_verify_data("verify_snk_in.channel", c_rl, c_unsigned_0, to_unsigned(c_verify_data_gap, 32), clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.channel, prev_verify_snk_in.channel);
-- Verify that the output bsn error bit is set if an input block was missed in a merge
merged_pkt_err <= verify_snk_in.err(c_bsn_err_bi);
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
index 275d85700bd6a50eeeca057f5a52634eff691b37..32ceaf429d2e3cae53e880dbfd16195f55b6efff 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge_unmerge.vhd
@@ -108,7 +108,7 @@ architecture tb of tb_dp_packet_merge_unmerge is
constant c_nof_pkt_not_zero : natural := sel_a_b(g_nof_pkt_merge = 0, 1, g_nof_pkt_merge);
constant c_nof_merged_sop : natural := sel_a_b(g_nof_pkt_merge = 0, 0, ceil_div(g_nof_repeat, c_nof_pkt_not_zero));
-- verify that at least some packets have been merged, not exact to allow variation by p_stimuli_mm
- constant c_verify_at_least : natural := largest(1,c_nof_merged_sop / 2);
+ constant c_verify_at_least : natural := largest(1, c_nof_merged_sop / 2);
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
index da2ad8b364e2d8096b719a92456d7eb26b19e944..64c7b7108956651dfd25b9c8a2d254a3eb68822c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
@@ -105,7 +105,7 @@ begin
begin
snk_out_arr(i).xon <= '1';
snk_out_arr(i).ready <= '0';
- wait for c_clk_period * (ceil_div(g_nof_in,g_nof_out) - 1);
+ wait for c_clk_period * (ceil_div(g_nof_in, g_nof_out) - 1);
snk_out_arr(i).ready <= '1';
wait for c_clk_period;
end process;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
index f37559d35294d2e80d2fbac675d336b5234596fa..ad50f545e62c48b1d6f655a55548964ae06038c3 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
@@ -38,8 +38,8 @@ architecture tb of tb_mms_dp_fields is
( field_name_pad("test_field_1"), "RO", 8, field_default(x"AA") ), -- 0xEE
( field_name_pad("test_field_0"), "RO", 4, field_default(x"B") )); -- 0xF
- constant c_field_arr2: t_common_field_arr(2 downto 0) := (( field_name_pad("test_field_2"), "RO", 4 , field_default(x"B")), -- 0xF
- ( field_name_pad("test_field_1"), "RO", 8 , field_default(x"AA")), -- 0xEE
+ constant c_field_arr2: t_common_field_arr(2 downto 0) := (( field_name_pad("test_field_2"), "RO", 4, field_default(x"B")), -- 0xF
+ ( field_name_pad("test_field_1"), "RO", 8, field_default(x"AA")), -- 0xEE
( field_name_pad("test_field_0"), "RW", 36, field_default(x"BADC0DE56"))); -- 0xCAFEDEADB
signal clk : std_logic := '0';
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
index c7195a0344274b49ae9067bc68c868505763a535..59fce1933c9ff7df0b4bc22fc8dc083bc1a05a3d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
@@ -47,11 +47,11 @@ begin
-- Maximum expected sync count is 9
-- Default usage
- u_mm32b_cnt16b_no_gap : entity work.tb_dp_strobe_total_count generic map(32, 16, 10,10, 10, 0);
- u_mm32b_cnt16b_gap : entity work.tb_dp_strobe_total_count generic map(32, 16, 10,10, 10, 3);
+ u_mm32b_cnt16b_no_gap : entity work.tb_dp_strobe_total_count generic map(32, 16, 10, 10, 10, 0);
+ u_mm32b_cnt16b_gap : entity work.tb_dp_strobe_total_count generic map(32, 16, 10, 10, 10, 3);
-- Check MM high word and counter overflow (clipping)
- u_mm8b_cnt16b_high : entity work.tb_dp_strobe_total_count generic map(8, 16, 10,10, 10, 3); -- use high part
- u_mm8b_cnt9b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 9, 10,10, 10, 3); -- cause overflow to clip count high part
- u_mm8b_cnt7b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 7, 10,10, 10, 3); -- cause overflow to clip count low part
+ u_mm8b_cnt16b_high : entity work.tb_dp_strobe_total_count generic map(8, 16, 10, 10, 10, 3); -- use high part
+ u_mm8b_cnt9b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 9, 10, 10, 10, 3); -- cause overflow to clip count high part
+ u_mm8b_cnt7b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 7, 10, 10, 10, 3); -- cause overflow to clip count low part
end tb;
diff --git a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
index ef7a16c082c50884216910e4584b13abed97440f..30664c795f555f8b653dbacf0621ddb3706fe15f 100644
--- a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
@@ -42,38 +42,38 @@ package reorder_pkg is
constant c_reorder_table: t_reorder_table :=
(
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
);
-----------------------------------------------------------------------------
diff --git a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
index e62740d57c941a0665ee8106efb5ff0090f1526c..87dcb12eb142c5d53e00317da795fa008325dae2 100644
--- a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
@@ -378,7 +378,7 @@ begin
clk => dp_clk,
wr_dat => pipe_merged_snk_in.bsn,
wr_req => pipe_merged_snk_in.sync,
- wr_ful => open ,
+ wr_ful => open,
rd_dat => rd_dat_i,
rd_req => rd_req_i,
rd_emp => open,
diff --git a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
index 5572720cd77f88818651c29408756de5700f538d..b62c71da2cbc6e033d1704e676cc11a63691bca9 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
@@ -91,38 +91,38 @@ architecture tb of tb_mms_reorder_rewire is
constant c_sel_table: t_reorder_table :=
(
--FN0 FN1 FN2 FN3 BN0 BN1 BN2 BN3
- ( 19, 10, 13, 16, 8 , 8 , 8 , 8 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 0
- ( 10, 13, 16, 19, 11, 11, 11, 11, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 1
- ( 13, 16, 19, 10, 14, 14, 14, 14, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 2
- ( 16, 19, 10, 13, 17, 17, 17, 17, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 3
- ( 8 , 8 , 8 , 8 , 10, 19, 16, 13, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 4
- ( 11, 11, 11, 11, 13, 10, 19, 16, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 5
- ( 14, 14, 14, 14, 16, 13, 10, 19, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 6
- ( 17, 17, 17, 17, 19, 16, 13, 10, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Local processing output 7
- ( 1 , 1 , 1 , 1 , 0 , 0 , 0 , 0 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 0
- ( 2 , 0 , 6 , 4 , 1 , 3 , 5 , 7 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 1
- ( 9 , 12, 15, 18, 12, 15, 18, 9 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 2
- ( 3 , 3 , 3 , 3 , 2 , 2 , 2 , 2 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 3
- ( 4 , 2 , 0 , 6 , 7 , 1 , 3 , 5 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 4
- ( 12, 15, 18, 9 , 9 , 12, 15, 18, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 5
- ( 5 , 5 , 5 , 5 , 4 , 4 , 4 , 4 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 6
- ( 6 , 4 , 2 , 0 , 5 , 7 , 1 , 3 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 7
- ( 15, 18, 9 , 12, 18, 9 , 12, 15, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 8
- ( 7 , 7 , 7 , 7 , 6 , 6 , 6 , 6 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 9
- ( 0 , 6 , 4 , 2 , 3 , 5 , 7 , 1 , 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 10
- ( 18, 9 , 12, 15, 15, 18, 9 , 12, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), -- Mesh Transmit output 11
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
+ ( 19, 10, 13, 16, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Local processing output 0
+ ( 10, 13, 16, 19, 11, 11, 11, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Local processing output 1
+ ( 13, 16, 19, 10, 14, 14, 14, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Local processing output 2
+ ( 16, 19, 10, 13, 17, 17, 17, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Local processing output 3
+ ( 8, 8, 8, 8, 10, 19, 16, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Local processing output 4
+ ( 11, 11, 11, 11, 13, 10, 19, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Local processing output 5
+ ( 14, 14, 14, 14, 16, 13, 10, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Local processing output 6
+ ( 17, 17, 17, 17, 19, 16, 13, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Local processing output 7
+ ( 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 0
+ ( 2, 0, 6, 4, 1, 3, 5, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 1
+ ( 9, 12, 15, 18, 12, 15, 18, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 2
+ ( 3, 3, 3, 3, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 3
+ ( 4, 2, 0, 6, 7, 1, 3, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 4
+ ( 12, 15, 18, 9, 9, 12, 15, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 5
+ ( 5, 5, 5, 5, 4, 4, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 6
+ ( 6, 4, 2, 0, 5, 7, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 7
+ ( 15, 18, 9, 12, 18, 9, 12, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 8
+ ( 7, 7, 7, 7, 6, 6, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 9
+ ( 0, 6, 4, 2, 3, 5, 7, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 10
+ ( 18, 9, 12, 15, 15, 18, 9, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), -- Mesh Transmit output 11
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0),
+ (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
);
-- Custom definitions of constants
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
index c0669ea2dfb18f5bffb521bb5de561c7898ccd49..06173b870707659db4221c00438e318f3c1d813c 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
@@ -302,12 +302,12 @@ begin
-- verify incrementing re and im
gen_verify_complex: if g_use_complex generate
- proc_dp_verify_data("out_sosi.re", c_unsigned_0, to_unsigned(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.re, prev_out_sosi.re);
- proc_dp_verify_data("out_sosi.im", c_unsigned_0, to_unsigned(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.im, prev_out_sosi.im);
+ proc_dp_verify_data("out_sosi.re", c_unsigned_0, to_unsigned(c_nof_ch_gap, 32), clk, verify_en, out_sosi.valid, out_sosi.re, prev_out_sosi.re);
+ proc_dp_verify_data("out_sosi.im", c_unsigned_0, to_unsigned(c_nof_ch_gap, 32), clk, verify_en, out_sosi.valid, out_sosi.im, prev_out_sosi.im);
end generate;
gen_verify_non_complex: if not(g_use_complex) generate
- proc_dp_verify_data("out_sosi.data", c_unsigned_0, to_unsigned(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.data, prev_out_sosi.data);
+ proc_dp_verify_data("out_sosi.data", c_unsigned_0, to_unsigned(c_nof_ch_gap, 32), clk, verify_en, out_sosi.valid, out_sosi.data, prev_out_sosi.data);
end generate;
-- verify output framing
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
index fe473421bb2a3e70b7736ae4d0275915f529a29f..bab2257bb476a011e899a16ed9edd26888ebb681 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
@@ -57,5 +57,5 @@ begin
u_data_3_5_valid_gap_1 : entity work.tb_reorder_col_select_all generic map(16, 3, 6, 3, 5, 1, 0, false, false, false);
u_dynamic_data_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3, 0, 0, false, false, true);
- u_dynamic_data_5_3_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3,10,100, false, false, true);
+ u_dynamic_data_5_3_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3, 10, 100, false, false, true);
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
index 1306c592df15126d11c403bd19903ed5e80fbde5..44613f38d67e65c13a8d35cfe49f58d25222fc69 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
@@ -54,6 +54,6 @@ begin
-- g_reorder_row_select_pipe_out : NATURAL := 1
u_sdp : entity work.tb_reorder_col_wide_row_select generic map (6, 1, c_dsp_data_w, c_nof_sync, 4, 1024, 2, 2, (0, 16), 3, 0, 1, 1);
- u_max_out : entity work.tb_reorder_col_wide_row_select generic map (8, 1, c_dsp_data_w, c_nof_sync, 1, 512, 8, 8, (0 ,64, 128, 192, 256, 320, 384, 448), 0, 0, 1, 1); -- rows * cols * offsets = 8*8*8 = 512
+ u_max_out : entity work.tb_reorder_col_wide_row_select generic map (8, 1, c_dsp_data_w, c_nof_sync, 1, 512, 8, 8, (0, 64, 128, 192, 256, 320, 384, 448), 0, 0, 1, 1); -- rows * cols * offsets = 8*8*8 = 512
u_multiple_out : entity work.tb_reorder_col_wide_row_select generic map (2, 5, c_dsp_data_w, c_nof_sync, 4, 1024, 2, 2, (0, 16), 3, 0, 1, 1);
end tb;
diff --git a/libraries/base/ring/src/vhdl/ring_pkg.vhd b/libraries/base/ring/src/vhdl/ring_pkg.vhd
index 50b55d733a54efb9ea36c3c4616e2cd958e70549..a5e76d9a55f13f186699a3097d14905477d22406 100644
--- a/libraries/base/ring/src/vhdl/ring_pkg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_pkg.vhd
@@ -122,6 +122,6 @@ package body ring_pkg is
function func_ring_nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector is
begin
- return TO_UVEC(func_ring_nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(this_rn), TO_UINT(N_rn), lane_dir),hops'length);
+ return TO_UVEC(func_ring_nof_hops_to_source_rn(TO_UINT(hops), TO_UINT(this_rn), TO_UINT(N_rn), lane_dir), hops'length);
end;
end ring_pkg;
diff --git a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
index 7ce96472307a11181609ce2427f412747b04b4fb..88d237b1b35b3d948971f68b6875aa15accca9fc 100644
--- a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
+++ b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
@@ -86,8 +86,8 @@ begin
proc_common_wait_some_cycles(mm_clk, 100);
-- default all register hold value 0, try to write 1 in all registers
- proc_mem_mm_bus_wr(c_mm_addr_transport_nof_hops ,11 ,mm_clk, reg_miso, reg_mosi);
- proc_mem_mm_bus_wr(c_mm_addr_lane_direction ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
+ proc_mem_mm_bus_wr(c_mm_addr_transport_nof_hops, 11, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_wr(c_mm_addr_lane_direction, 1, mm_clk, reg_miso, reg_mosi); -- RO
proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
proc_mem_mm_bus_rd(c_mm_addr_transport_nof_hops, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
diff --git a/libraries/base/sens/src/vhdl/sens_ctrl.vhd b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
index e3a0cc0b377ce888cf5469821964d2fe5732d5a7..92de049ce534905efe7225992fae240eb0b6917c 100644
--- a/libraries/base/sens/src/vhdl/sens_ctrl.vhd
+++ b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
@@ -58,27 +58,27 @@ architecture rtl of sens_ctrl is
constant SEQ : SEQUENCE := (
SMBUS_C_NOP,
- SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_VIN_2_5,
- SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_VIN_3_3,
- SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_VCC,
- SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_TEMP,
- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX6652, MAX6652_REG_READ_VIN_2_5,
+ SMBUS_READ_BYTE, ADR_MAX6652, MAX6652_REG_READ_VIN_3_3,
+ SMBUS_READ_BYTE, ADR_MAX6652, MAX6652_REG_READ_VCC,
+ SMBUS_READ_BYTE, ADR_MAX6652, MAX6652_REG_READ_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX1617_BP, MAX1617_CMD_READ_REMOTE_TEMP,
-- For debugging, use AP temp fields in RSR to read other info from the sensor, e.g.:
-- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_STATUS,
-- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_CONFIG,
-- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_HIGH,
-- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_LOW,
- SMBUS_READ_BYTE , ADR_MAX1617_AP0, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ADR_MAX1617_AP1, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ADR_MAX1617_AP2, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ADR_MAX1617_AP3, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_WRITE_BYTE, ADR_MAX6652 , MAX6652_REG_CONFIG, MAX6652_CONFIG_LINE_FREQ_SEL + MAX6652_CONFIG_START,
- SMBUS_WRITE_BYTE, ADR_MAX1617_BP , MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
+ SMBUS_READ_BYTE, ADR_MAX1617_AP0, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX1617_AP1, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX1617_AP2, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX1617_AP3, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_WRITE_BYTE, ADR_MAX6652, MAX6652_REG_CONFIG, MAX6652_CONFIG_LINE_FREQ_SEL + MAX6652_CONFIG_START,
+ SMBUS_WRITE_BYTE, ADR_MAX1617_BP, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP0, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP1, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP2, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP3, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
- SMBUS_WRITE_BYTE, ADR_MAX1617_BP , MAX1617_CMD_WRITE_REMOTE_HIGH, g_temp_high,
+ SMBUS_WRITE_BYTE, ADR_MAX1617_BP, MAX1617_CMD_WRITE_REMOTE_HIGH, g_temp_high,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP0, MAX1617_CMD_WRITE_REMOTE_HIGH, g_temp_high,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP1, MAX1617_CMD_WRITE_REMOTE_HIGH, g_temp_high,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP2, MAX1617_CMD_WRITE_REMOTE_HIGH, g_temp_high,
@@ -104,7 +104,7 @@ architecture rtl of sens_ctrl is
begin
evt_dat_reg <= i_evt_dat_reg;
- regs: process(rst,clk)
+ regs: process(rst, clk)
begin
if rst = '1' then
seq_start <= '0';
@@ -139,7 +139,7 @@ begin
end if;
end process;
- out_dat <= std_logic_vector(to_unsigned(SEQ(seq_cnt),8));
+ out_dat <= std_logic_vector(to_unsigned(SEQ(seq_cnt), 8));
out_val <= not rst when seq_cnt < SEQ'high else '0';
p_evt_dat : process(evt_dat, seq_start, in_dat, in_val)
diff --git a/libraries/base/ss/tb/vhdl/tb_ss.vhd b/libraries/base/ss/tb/vhdl/tb_ss.vhd
index 35585289e6e8b6bee6ccb558681014c2b88c800c..1f04d4fab47c5d378070a409ee7a3cf6cbcda5e0 100644
--- a/libraries/base/ss/tb/vhdl/tb_ss.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_ss.vhd
@@ -302,12 +302,12 @@ begin
-- verify incrementing re and im
gen_verify_complex: if g_use_complex generate
- proc_dp_verify_data("out_sosi.re", c_unsigned_0, to_unsigned(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.re, prev_out_sosi.re);
- proc_dp_verify_data("out_sosi.im", c_unsigned_0, to_unsigned(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.im, prev_out_sosi.im);
+ proc_dp_verify_data("out_sosi.re", c_unsigned_0, to_unsigned(c_nof_ch_gap, 32), clk, verify_en, out_sosi.valid, out_sosi.re, prev_out_sosi.re);
+ proc_dp_verify_data("out_sosi.im", c_unsigned_0, to_unsigned(c_nof_ch_gap, 32), clk, verify_en, out_sosi.valid, out_sosi.im, prev_out_sosi.im);
end generate;
gen_verify_non_complex: if not(g_use_complex) generate
- proc_dp_verify_data("out_sosi.data", c_unsigned_0, to_unsigned(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.data, prev_out_sosi.data);
+ proc_dp_verify_data("out_sosi.data", c_unsigned_0, to_unsigned(c_nof_ch_gap, 32), clk, verify_en, out_sosi.valid, out_sosi.data, prev_out_sosi.data);
end generate;
-- verify output framing
diff --git a/libraries/base/tst/src/vhdl/tst_output.vhd b/libraries/base/tst/src/vhdl/tst_output.vhd
index 2398cf1223bf1c63eacd6b5174957dc2a1b991aa..c7987b4f93d53f246a27f9cdea1362b90037276e 100644
--- a/libraries/base/tst/src/vhdl/tst_output.vhd
+++ b/libraries/base/tst/src/vhdl/tst_output.vhd
@@ -63,7 +63,7 @@ begin
write(out_line, ' ');
end if;
end loop;
- writeline(out_file,out_line);
+ writeline(out_file, out_line);
end if;
end if;
end process;
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
index 7ad85b075dfb7e19e94f8272e7c49280cd41bbe4..1e550b7099d228bf61633e1c1a8da473fc375b34 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
@@ -260,7 +260,7 @@ begin
end loop;
-- End of stimuli
- expected_out_data(I,J) <= TO_UVEC(v_data - 1, g_data_w);
+ expected_out_data(I, J) <= TO_UVEC(v_data - 1, g_data_w);
wait;
end process;
@@ -293,16 +293,16 @@ begin
gen_verify : for I in 0 to c_nof_tlen - 1 generate
gen_output : for J in 0 to c_nof_input - 1 generate
-- Verification logistics
- verify_en(I,J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
- count_eop(I,J) <= count_eop(I,J) + 1 when rising_edge(clk) and out_sosi_2arr(I)(J).eop = '1'; -- count number of output eop
- verify_done(I,J) <= '1' when rising_edge(clk) and count_eop(I,J) = c_repeat_arr(I * c_nof_input + J) and count_eop(I,J) /= prev_count_eop(I,J) else '0';
- tb_end_vec(I * c_nof_input + J) <= '1' when rising_edge(clk) and count_eop(I,J) = c_repeat_arr(I * c_nof_input + J);
+ verify_en(I, J) <= '1' when rising_edge(clk) and out_sosi_2arr(I)(J).sop = '1'; -- verify enable after first output sop
+ count_eop(I, J) <= count_eop(I, J) + 1 when rising_edge(clk) and out_sosi_2arr(I)(J).eop = '1'; -- count number of output eop
+ verify_done(I, J) <= '1' when rising_edge(clk) and count_eop(I, J) = c_repeat_arr(I * c_nof_input + J) and count_eop(I, J) /= prev_count_eop(I, J) else '0';
+ tb_end_vec(I * c_nof_input + J) <= '1' when rising_edge(clk) and count_eop(I, J) = c_repeat_arr(I * c_nof_input + J);
-- Actual verification of the output streams
- proc_dp_verify_data("out_sosi_2arr.data", c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, out_sosi_2arr(I)(J).valid, out_data(I,J), prev_out_data(I,J)); -- Verify that the output is incrementing data, like the input stimuli
- proc_dp_verify_valid(c_rl, clk, verify_en(I,J), out_siso_2arr(I)(J).ready, prev_out_ready(I,J), out_sosi_2arr(I)(J).valid); -- Verify that the output valid fits with the output ready latency
- proc_dp_verify_sop_and_eop(clk, out_sosi_2arr(I)(J).valid, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).eop, hold_out_sop(I,J)); -- Verify that sop and eop come in pairs
- proc_dp_verify_value(e_equal, clk, verify_done(I,J), expected_out_data(I,J), prev_out_data(I,J)); -- Verify that the stimuli have been applied at all
+ proc_dp_verify_data("out_sosi_2arr.data", c_rl, clk, verify_en(I, J), out_siso_2arr(I)(J).ready, out_sosi_2arr(I)(J).valid, out_data(I, J), prev_out_data(I, J)); -- Verify that the output is incrementing data, like the input stimuli
+ proc_dp_verify_valid(c_rl, clk, verify_en(I, J), out_siso_2arr(I)(J).ready, prev_out_ready(I, J), out_sosi_2arr(I)(J).valid); -- Verify that the output valid fits with the output ready latency
+ proc_dp_verify_sop_and_eop(clk, out_sosi_2arr(I)(J).valid, out_sosi_2arr(I)(J).sop, out_sosi_2arr(I)(J).eop, hold_out_sop(I, J)); -- Verify that sop and eop come in pairs
+ proc_dp_verify_value(e_equal, clk, verify_done(I, J), expected_out_data(I, J), prev_out_data(I, J)); -- Verify that the stimuli have been applied at all
end generate;
end generate;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
index 9289aa48472f038e9d7e6332b842d12316209c46..535b86b64ed6f2cf15c273bd38f14268585a29aa 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
@@ -120,7 +120,7 @@ begin
-- clock cycle, we always reset the counter at that moment and and spend the
-- following clock cycles putting the folded data on the outputs.
-----------------------------------------------------------------------------
- nxt_cycle_cnt <= (others => '0') when unsigned(cycle_cnt) = g_nof_cycles - 1 else INCR_UVEC(cycle_cnt,1) when common_pulse_extend_ep_out_valid = '1' or snk_in_arr(0).valid = '1' else cycle_cnt;
+ nxt_cycle_cnt <= (others => '0') when unsigned(cycle_cnt) = g_nof_cycles - 1 else INCR_UVEC(cycle_cnt, 1) when common_pulse_extend_ep_out_valid = '1' or snk_in_arr(0).valid = '1' else cycle_cnt;
-----------------------------------------------------------------------------
-- For each output, select the inputs with indices provided by
@@ -132,15 +132,15 @@ begin
for i in 0 to g_nof_outputs - 1 loop
if snk_in_arr(0).valid = '1' then -- cycle_cnt=0
-- First (or only) (folding) cycle; Take data present on snk_in_arr
- nxt_perm_2arr_2(i)(0) <= snk_in_arr(c_permutation_table(0,i)(0));
- nxt_perm_2arr_2(i)(1) <= snk_in_arr(c_permutation_table(0,i)(1));
+ nxt_perm_2arr_2(i)(0) <= snk_in_arr(c_permutation_table(0, i)(0));
+ nxt_perm_2arr_2(i)(1) <= snk_in_arr(c_permutation_table(0, i)(1));
elsif g_nof_cycles > 1 then
-- We're folding the permutation pairs; different outputs on next clock cycle(s).
-- . Now take the data from common_paged_reg as snk_in_arr is no longer valid
for j in 1 to g_nof_cycles - 1 loop
if TO_UINT(cycle_cnt) = j then
- nxt_perm_2arr_2(i)(0) <= common_paged_reg_src_out_arr(c_permutation_table(j,i)(0));
- nxt_perm_2arr_2(i)(1) <= common_paged_reg_src_out_arr(c_permutation_table(j,i)(1));
+ nxt_perm_2arr_2(i)(0) <= common_paged_reg_src_out_arr(c_permutation_table(j, i)(0));
+ nxt_perm_2arr_2(i)(1) <= common_paged_reg_src_out_arr(c_permutation_table(j, i)(1));
end if;
end loop;
end if;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
index 08e85e2dd6a891f00ef6169e7a1386f5ff798fc8..0fc5e952d8efc6533ea06a706b984702e7ae48a3 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
@@ -60,7 +60,7 @@ package body corr_permutor_pkg is
-----------------------------------------------------------------------------
for i in 0 to nof_inputs - 1 loop
for j in 0 to nof_inputs - 1 loop
- v_input_index_mat(i,j) := c_input_index_arr(i);
+ v_input_index_mat(i, j) := c_input_index_arr(i);
end loop;
end loop;
@@ -120,8 +120,8 @@ package body corr_permutor_pkg is
v_duplicates := i;
for j in 0 to nof_inputs - 1 loop
-- Create our permutation pair by using inverse indices (j,i) and (i,j)
- v_output_index_mat(v_out_index,0) := v_input_index_mat(i,j);
- v_output_index_mat(v_out_index,1) := v_input_index_mat(j,i);
+ v_output_index_mat(v_out_index, 0) := v_input_index_mat(i, j);
+ v_output_index_mat(v_out_index, 1) := v_input_index_mat(j, i);
if v_duplicates = 0 then
-- We created a unique pair. Keep incrementing the index.
v_out_index := v_out_index + 1;
@@ -141,8 +141,8 @@ package body corr_permutor_pkg is
-----------------------------------------------------------------------------
for i in 0 to nof_folding_cycles - 1 loop
for j in 0 to c_nof_outputs - 1 loop
- v_result(i,j)(0) := v_output_index_mat(i * c_nof_outputs + j,0);
- v_result(i,j)(1) := v_output_index_mat(i * c_nof_outputs + j,1);
+ v_result(i, j)(0) := v_output_index_mat(i * c_nof_outputs + j, 0);
+ v_result(i, j)(1) := v_output_index_mat(i * c_nof_outputs + j, 1);
end loop;
end loop;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
index 2b5d9722394319eb1919df99a2ca358d57f4c41c..fba0cee47a98d976ba5690ee7f5890c58b0cd3d4 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
@@ -145,7 +145,7 @@ begin
u_correlator_dev : entity work.correlator_dev
generic map (
- g_data_w => g_data_w ,
+ g_data_w => g_data_w,
g_nof_inputs => g_nof_inputs,
g_nof_mults => g_nof_mults,
g_nof_cycles => g_nof_cycles,
diff --git a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
index abd88be8522a176d72b78603322584ca6b1586d7..fcc9dd4fec3fba854ce1deaf67672d4f3ea6cf24 100644
--- a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
@@ -59,7 +59,7 @@ architecture rtl of fft_lfsr is
signal s2 : std_logic_vector(c_len - 1 downto 0);
signal nxt_s2 : std_logic_vector(c_len - 1 downto 0);
begin
- p_reg : process(rst,clk)
+ p_reg : process(rst, clk)
begin
if rst = '1' then
s1 <= g_seed1;
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
index b6932b339421322cb62512d534f0f27211180962..500b07e8b6b3f4604f1c70b802801cb80d4d9a2c 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
@@ -106,11 +106,11 @@ begin
clk => clk,
wr_dat => ctrl_sosi.bsn,
wr_req => ctrl_sosi.sop,
- wr_ful => open ,
+ wr_ful => open,
rd_dat => bsn,
rd_req => r.sop_dly(0),
- rd_emp => open ,
- rd_val => open ,
+ rd_emp => open,
+ rd_val => open,
usedw => open
);
@@ -130,11 +130,11 @@ begin
clk => clk,
wr_dat => ctrl_sosi.err,
wr_req => ctrl_sosi.sop,
- wr_ful => open ,
+ wr_ful => open,
rd_dat => err,
rd_req => r.sop_dly(1),
- rd_emp => open ,
- rd_val => open ,
+ rd_emp => open,
+ rd_val => open,
usedw => open
);
@@ -154,7 +154,7 @@ begin
clk => clk,
wr_dat => ctrl_sosi.bsn,
wr_req => ctrl_sosi.sync,
- wr_ful => open ,
+ wr_ful => open,
rd_dat => rd_dat_i,
rd_req => rd_req_i,
rd_emp => open,
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
index b72b7933e8381dbadabd3af3bb971795798e2b7d..427857a5484369c98a451b7a2a9199361ab81490 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
@@ -472,10 +472,10 @@ package body tb_fft_pkg is
read(v_input_line, v_val(v_index)); -- valid
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,1)); -- real
+ read(v_input_line, v_data(v_index, 1)); -- real
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,2)); -- imag
+ read(v_input_line, v_data(v_index, 2)); -- imag
v_index := v_index + 1;
end loop;
proc_common_close_file(v_file_status, v_in_file); -- Close the file
@@ -517,10 +517,10 @@ package body tb_fft_pkg is
exit when v_index = in_file_data'high + 1;
readline(v_in_file, v_input_line);
- read(v_input_line, v_data(v_index,1)); -- real
+ read(v_input_line, v_data(v_index, 1)); -- real
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,2)); -- imag
+ read(v_input_line, v_data(v_index, 2)); -- imag
v_index := v_index + 1;
end loop;
proc_common_close_file(v_file_status, v_in_file); -- Close the file
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
index e48519e06488aa21fd264b6990cbbb25c3c8c8de..c63fe86633cea2b3e49524b9258334c70404abbc 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
@@ -46,7 +46,7 @@ architecture tb of tb_tb_fft_r2_wide is
constant c_fft_wb4_complex : t_fft := ( true, false, false, 0, 4, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
constant c_fft_wb1_complex : t_fft := ( true, false, false, 0, 1, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
- constant c_fft_wb64_complex : t_fft := ( true, false, false, 0,64, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
+ constant c_fft_wb64_complex : t_fft := ( true, false, false, 0, 64, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
constant c_diff_margin : natural := 2;
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
index d2225c2df6b4b7af24e4316dfaabc98dc952020b..fd571740a75cbbce0c13fd507b00911075eae0b2 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
@@ -183,32 +183,32 @@ begin
-- Normal increment, both offset and step.
if g_sim_type = 0 then
for J in 0 to g_nof_channels - 1 loop
- fs_offset_matrix(I,J) <= I + 10 + J;
- fs_step_matrix(I,J) <= 2**(g_fs_step_w - 1) - 1 - g_nof_channels + J;
+ fs_offset_matrix(I, J) <= I + 10 + J;
+ fs_step_matrix(I, J) <= 2**(g_fs_step_w - 1) - 1 - g_nof_channels + J;
end loop;
end if;
-- Increment where sum reaches maximum and wraps.
if g_sim_type = 1 then
for J in 0 to g_nof_channels - 1 loop
- fs_offset_matrix(I,J) <= 2**g_fs_offset_w - 1;
- fs_step_matrix(I,J) <= 2**(g_fs_step_w - 1) - 1 - g_nof_channels + J;
+ fs_offset_matrix(I, J) <= 2**g_fs_offset_w - 1;
+ fs_step_matrix(I, J) <= 2**(g_fs_step_w - 1) - 1 - g_nof_channels + J;
end loop;
end if;
-- Decrease the step and offset
if g_sim_type = 2 then
for J in 0 to g_nof_channels - 1 loop
- fs_offset_matrix(I,J) <= 2**(g_fs_offset_w / 2) + J - I;
- fs_step_matrix(I,J) <= -1 * 2**(g_fs_step_w - 1) + J;
+ fs_offset_matrix(I, J) <= 2**(g_fs_offset_w / 2) + J - I;
+ fs_step_matrix(I, J) <= -1 * 2**(g_fs_step_w - 1) + J;
end loop;
end if;
-- Decrease where sum reaches minimum and wraps
if g_sim_type = 3 then
for J in 0 to g_nof_channels - 1 loop
- fs_offset_matrix(I,J) <= 1;
- fs_step_matrix(I,J) <= -1 * 2**(g_fs_step_w - 1);
+ fs_offset_matrix(I, J) <= 1;
+ fs_step_matrix(I, J) <= -1 * 2**(g_fs_step_w - 1);
end loop;
end if;
end loop;
@@ -223,7 +223,7 @@ begin
ram_diag_bg_mosi <= c_mem_mosi_rst;
proc_common_wait_some_cycles(mm_clk, 10);
for I in 0 to g_nof_channels - 1 loop
- proc_mem_mm_bus_wr( I, TO_SINT(TO_SVEC(bg_data_arr_im(I),g_in_dat_w) & TO_SVEC(bg_data_arr_re(I),g_in_dat_w)), mm_clk, ram_diag_bg_mosi);
+ proc_mem_mm_bus_wr( I, TO_SINT(TO_SVEC(bg_data_arr_im(I), g_in_dat_w) & TO_SVEC(bg_data_arr_re(I), g_in_dat_w)), mm_clk, ram_diag_bg_mosi);
end loop;
proc_common_wait_some_cycles(mm_clk, 80);
proc_mem_mm_bus_wr( 0, 1, mm_clk, reg_diag_bg_mosi);
@@ -242,7 +242,7 @@ begin
for K in 0 to 20 loop
for I in 0 to c_nof_sync_periods - 1 loop
for J in 0 to g_nof_channels - 1 loop
- proc_mem_mm_bus_wr( J, fs_step_matrix(I,J), mm_clk, ram_fringe_stop_step_mosi);
+ proc_mem_mm_bus_wr( J, fs_step_matrix(I, J), mm_clk, ram_fringe_stop_step_mosi);
end loop;
-- wait until the next sync interval
proc_common_wait_some_pulses(dp_clk, bg_sosi_arr(0).sync, 1);
@@ -266,7 +266,7 @@ begin
for K in 0 to 20 loop
for I in 0 to c_nof_sync_periods - 1 loop
for J in 0 to g_nof_channels - 1 loop
- proc_mem_mm_bus_wr( J, fs_offset_matrix(I,J), mm_clk, ram_fringe_stop_offset_mosi);
+ proc_mem_mm_bus_wr( J, fs_offset_matrix(I, J), mm_clk, ram_fringe_stop_offset_mosi);
end loop;
-- wait until the next sync interval
proc_common_wait_some_pulses(dp_clk, bg_sosi_arr(0).sync, 1);
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
index 51e20a0fa1ab482958301b4cd0ced1fa3fd39d5d..4e003ef01ba899d8184658a4d2efc98bcd6f2326 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
@@ -73,79 +73,79 @@ architecture tb of tb_iquv is
signal valid_enable : std_logic := '0';
-- expected data values
- constant i_nint8_exp_arr : t_integer_arr(0 to 35) := (140,1100,3084,6092,
- 140,1100,3084,6092,
- 140,1100,3084,6092,
- 140,1100,3084,6092,
- 280,2200,6168,12184,
- 280,2200,6168,12184,
- 560,4400,12336,24368,
- 84864,84864,84864,84864,
- 134086688,134086688,134086688,134086688);
- constant q_nint8_exp_arr : t_integer_arr(0 to 35) := (140,1100,3084,6092,
+ constant i_nint8_exp_arr : t_integer_arr(0 to 35) := (140, 1100, 3084, 6092,
+ 140, 1100, 3084, 6092,
+ 140, 1100, 3084, 6092,
+ 140, 1100, 3084, 6092,
+ 280, 2200, 6168, 12184,
+ 280, 2200, 6168, 12184,
+ 560, 4400, 12336, 24368,
+ 84864, 84864, 84864, 84864,
+ 134086688, 134086688, 134086688, 134086688);
+ constant q_nint8_exp_arr : t_integer_arr(0 to 35) := (140, 1100, 3084, 6092,
- 140, -1100, -3084, -6092,
- 140,1100,3084,6092,
+ 140, 1100, 3084, 6092,
- 140, -1100, -3084, -6092,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
- 77440, -77440, -77440, -77440,
- 0,0,0,0);
- constant u_nint8_exp_arr : t_integer_arr(0 to 35) := (0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 280,2200,6168,12184,
- 280,2200,6168,12184,
- 560,4400,12336,24368,
+ 0, 0, 0, 0);
+ constant u_nint8_exp_arr : t_integer_arr(0 to 35) := (0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 280, 2200, 6168, 12184,
+ 280, 2200, 6168, 12184,
+ 560, 4400, 12336, 24368,
- 16640, -16640, -16640, -16640,
- 134086688, -134086688, -134086688, -134086688);
- constant v_nint8_exp_arr : t_integer_arr(0 to 35) := (0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
+ constant v_nint8_exp_arr : t_integer_arr(0 to 35) := (0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
- 30464, -30464, -30464, -30464,
- 0,0,0,0);
+ 0, 0, 0, 0);
- constant i_nint16_exp_arr : t_integer_arr(0 to 35) := (1240,9176,25304,49624,
- 1240,9176,25304,49624,
- 1240,9176,25304,49624,
- 1240,9176,25304,49624,
- 2480,18352,50608,99248,
- 2480,18352,50608,99248,
- 4960,36704,101216,198496,
- 169728,169728,169728,169728,
- 268173376,268173376,268173376,268173376);
- constant q_nint16_exp_arr : t_integer_arr(0 to 35) := (1240,9176,25304,49624,
+ constant i_nint16_exp_arr : t_integer_arr(0 to 35) := (1240, 9176, 25304, 49624,
+ 1240, 9176, 25304, 49624,
+ 1240, 9176, 25304, 49624,
+ 1240, 9176, 25304, 49624,
+ 2480, 18352, 50608, 99248,
+ 2480, 18352, 50608, 99248,
+ 4960, 36704, 101216, 198496,
+ 169728, 169728, 169728, 169728,
+ 268173376, 268173376, 268173376, 268173376);
+ constant q_nint16_exp_arr : t_integer_arr(0 to 35) := (1240, 9176, 25304, 49624,
- 1240, -9176, -25304, -49624,
- 1240,9176,25304,49624,
+ 1240, 9176, 25304, 49624,
- 1240, -9176, -25304, -49624,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
- 154880, -154880, -154880, -154880,
- 0,0,0,0);
- constant u_nint16_exp_arr : t_integer_arr(0 to 35) := (0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 2480,18352,50608,99248,
- 2480,18352,50608,99248,
- 4960,36704,101216,198496,
+ 0, 0, 0, 0);
+ constant u_nint16_exp_arr : t_integer_arr(0 to 35) := (0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 2480, 18352, 50608, 99248,
+ 2480, 18352, 50608, 99248,
+ 4960, 36704, 101216, 198496,
- 33280, -33280, -33280, -33280,
- 268173376, -268173376, -268173376, -268173376);
- constant v_nint16_exp_arr : t_integer_arr(0 to 35) := (0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
- 0,0,0,0,
+ constant v_nint16_exp_arr : t_integer_arr(0 to 35) := (0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
- 60928, -60928, -60928, -60928,
- 0,0,0,0);
+ 0, 0, 0, 0);
begin
dp_clk <= not dp_clk or tb_end after clk_period / 2;
dp_rst <= '0' after clk_period * 10;
@@ -295,19 +295,19 @@ begin
if rising_edge(dp_clk) then
if diag_out_valid = '1' then
if g_nof_int = 8 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w - 1), c_lsb_w - 1, true)) report "Error: wrong result in I out DUT" severity ERROR;
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true)) report "Error: wrong result in I out DUT" severity ERROR;
--REPORT "I exp = " & integer'image(to_uint(s_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w-1), c_lsb_w-1, TRUE)));
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index),c_word_w), c_lsb_w)) report "Error: wrong result in Q out DUT" severity ERROR;
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index),c_word_w), c_lsb_w)) report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index),c_word_w), c_lsb_w)) report "Error: wrong result in V out DUT" severity ERROR;
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in Q out DUT" severity ERROR;
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in U out DUT" severity ERROR;
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in V out DUT" severity ERROR;
elsif g_nof_int = 16 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w - 1), c_lsb_w - 1, true)) report "Error: wrong result in I out DUT" severity ERROR;
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true)) report "Error: wrong result in I out DUT" severity ERROR;
--REPORT "I expected = " & integer'image(to_uint(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w-1), c_lsb_w-1, TRUE)));
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_word_w), c_lsb_w)) report "Error: wrong result in Q out DUT" severity ERROR;
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in Q out DUT" severity ERROR;
--REPORT "Q expected = " & integer'image(to_sint(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_word_w), c_lsb_w)));
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index),c_word_w), c_lsb_w)) report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index),c_word_w), c_lsb_w)) report "Error: wrong result in V out DUT" severity ERROR;
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in U out DUT" severity ERROR;
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_word_w), c_lsb_w)) report "Error: wrong result in V out DUT" severity ERROR;
end if;
report "I = " & integer'image(to_uint(i_out.data)) & ", Q = " & integer'image(to_sint(q_out.data)) &
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
index 1060e8f869e95eeff71bbfe4a1e311650fb74d39..a6c889350984ab4cff6096f1eebeb2696376caf6 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
@@ -233,36 +233,36 @@ begin
if rising_edge(dp_clk) then
if diag_out_valid = '1' then
if g_use_accum = true and g_nof_int = 8 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w - 1), c_lsb_w - 1, true))
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true))
report "Error: wrong result in I out DUT" severity ERROR;
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in Q out DUT" severity ERROR;
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in V out DUT" severity ERROR;
--REPORT "I exp = " & integer'image(to_uint(s_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w-1), c_lsb_w-1, TRUE)));
elsif g_use_accum = true and g_nof_int = 16 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w - 1), c_lsb_w - 1, true))
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true))
report "Error: wrong result in I out DUT" severity ERROR;
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in Q out DUT" severity ERROR;
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in V out DUT" severity ERROR;
--REPORT "I expected = " & integer'image(to_uint(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w-1), c_lsb_w-1, TRUE)));
--REPORT "Q expected = " & integer'image(to_sint(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_word_w), c_lsb_w)));
elsif g_use_accum = false then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_noint_exp_arr(v_index),c_fsd_w - 1), c_lsb_w - 1, true))
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_noint_exp_arr(v_index), c_fsd_w - 1), c_lsb_w - 1, true))
report "Error: wrong result in I out DUT" severity ERROR;
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_noint_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_noint_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in Q out DUT" severity ERROR;
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_noint_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_noint_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_noint_exp_arr(v_index),c_fsd_w), c_lsb_w, true))
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_noint_exp_arr(v_index), c_fsd_w), c_lsb_w, true))
report "Error: wrong result in V out DUT" severity ERROR;
--REPORT "U expected = " & integer'image(to_sint(s_round(TO_SVEC(u_noint_exp_arr(v_index),c_fsd_w), c_lsb_w, TRUE)));
--REPORT "U actual = " & integer'image(to_sint(u_out.data));
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
index 6b3e8f6cd12ab7b8c7e643ba398e4fac7d7b481f..a411df293f3916d62097743afdbe9c352439ff7d 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
@@ -81,23 +81,23 @@ architecture tb of tb_iquv_iab is
signal valid_enable : std_logic := '0';
-- expected data values
- constant i_nint8_exp_arr : t_integer_arr(0 to 7) := (164340,125340,110340,119340,
- 3142644,3142644,3142644,3142644);
+ constant i_nint8_exp_arr : t_integer_arr(0 to 7) := (164340, 125340, 110340, 119340,
+ 3142644, 3142644, 3142644, 3142644);
constant q_nint8_exp_arr : t_integer_arr(0 to 7) := (-81708, -59208, -43908, -35808,
- 0,0,0,0);
+ 0, 0, 0, 0);
constant u_nint8_exp_arr : t_integer_arr(0 to 7) := (2160, -14340, -30840, -47340,
- 1571328, -1571328, -1571328, -1571328);
- constant v_nint8_exp_arr : t_integer_arr(0 to 7) := (5904,13404,11304, -396,
- 0,0,0,0);
+ constant v_nint8_exp_arr : t_integer_arr(0 to 7) := (5904, 13404, 11304, -396,
+ 0, 0, 0, 0);
- constant i_nint16_exp_arr : t_integer_arr(0 to 7) := (144840,114840,180840,342840,
- 3142656,3142656,3142656,3142656);
+ constant i_nint16_exp_arr : t_integer_arr(0 to 7) := (144840, 114840, 180840, 342840,
+ 3142656, 3142656, 3142656, 3142656);
constant q_nint16_exp_arr : t_integer_arr(0 to 7) := (-70452, -39852, -38052, -65052,
- 0,0,0,0);
+ 0, 0, 0, 0);
constant u_nint16_exp_arr : t_integer_arr(0 to 7) := (-6096, -39096, -72096, -105096,
- 1571328, -1571328, -1571328, -1571328);
- constant v_nint16_exp_arr : t_integer_arr(0 to 7) := (9660,5460, -37140, -118140,
- 0,0,0,0);
+ constant v_nint16_exp_arr : t_integer_arr(0 to 7) := (9660, 5460, -37140, -118140,
+ 0, 0, 0, 0);
begin
dp_clk <= not dp_clk or tb_end after clk_period / 2;
dp_rst <= '0' after clk_period * 10;
@@ -198,19 +198,19 @@ begin
if rising_edge(dp_clk) then
if diag_out_valid = '1' then
if g_nof_int = 8 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w), c_lsb_w, c_clip, c_even)) report "Error: wrong result in I out DUT" severity ERROR;
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_w), c_lsb_w, c_clip, c_even)) report "Error: wrong result in I out DUT" severity ERROR;
--REPORT "I exp = " & integer'image(to_uint(s_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_w), c_lsb_w, c_clip)));
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index),c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in Q out DUT" severity ERROR;
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index),c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index),c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in V out DUT" severity ERROR;
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in Q out DUT" severity ERROR;
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in U out DUT" severity ERROR;
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in V out DUT" severity ERROR;
elsif g_nof_int = 16 then
- assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w), c_lsb_w, c_clip, c_even)) report "Error: wrong result in I out DUT" severity ERROR;
+ assert TO_UINT(i_out.data) = TO_UINT(u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_w), c_lsb_w, c_clip, c_even)) report "Error: wrong result in I out DUT" severity ERROR;
--REPORT "I expected = " & integer'image(to_uint(u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_w), c_lsb_w, c_clip, c_even)));
- assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in Q out DUT" severity ERROR;
+ assert TO_SINT(q_out.data) = TO_SINT(s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in Q out DUT" severity ERROR;
--REPORT "Q expected = " & integer'image(to_sint(s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_word_w), c_lsb_w, c_wrap, c_even)));
- assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index),c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in U out DUT" severity ERROR;
- assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index),c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in V out DUT" severity ERROR;
+ assert TO_SINT(u_out.data) = TO_SINT(s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in U out DUT" severity ERROR;
+ assert TO_SINT(v_out.data) = TO_SINT(s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_word_w), c_lsb_w, c_wrap, c_even)) report "Error: wrong result in V out DUT" severity ERROR;
end if;
report "I = " & integer'image(to_uint(i_out.data)) & ", Q = " & integer'image(to_sint(q_out.data)) &
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
index 981d9fb509aea364b8f53ba877a25ef0d56c2650..5a42db7fffda169cb2e96a7608cb2b733f57c035 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
@@ -254,21 +254,21 @@ begin
activestream_dly <= activestream; -- make sure we capture the last output valid of each cycle
-- Integration is done in the IQUV
if g_use_accum = false and g_nof_int = 8 then
- i_expected_iquv := u_round(TO_UVEC(i_nint8_exp_arr(v_index),c_fsd_iquv_w - 1), c_lsb_iquv_w - 1, true);
- q_expected_iquv := s_round(TO_SVEC(q_nint8_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
- u_expected_iquv := s_round(TO_SVEC(u_nint8_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
- v_expected_iquv := s_round(TO_SVEC(v_nint8_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
+ i_expected_iquv := u_round(TO_UVEC(i_nint8_exp_arr(v_index), c_fsd_iquv_w - 1), c_lsb_iquv_w - 1, true);
+ q_expected_iquv := s_round(TO_SVEC(q_nint8_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
+ u_expected_iquv := s_round(TO_SVEC(u_nint8_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
+ v_expected_iquv := s_round(TO_SVEC(v_nint8_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
elsif g_use_accum = false and g_nof_int = 16 then
- i_expected_iquv := u_round(TO_UVEC(i_nint16_exp_arr(v_index),c_fsd_iquv_w - 1), c_lsb_iquv_w - 1, true);
- q_expected_iquv := s_round(TO_SVEC(q_nint16_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
- u_expected_iquv := s_round(TO_SVEC(u_nint16_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
- v_expected_iquv := s_round(TO_SVEC(v_nint16_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
+ i_expected_iquv := u_round(TO_UVEC(i_nint16_exp_arr(v_index), c_fsd_iquv_w - 1), c_lsb_iquv_w - 1, true);
+ q_expected_iquv := s_round(TO_SVEC(q_nint16_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
+ u_expected_iquv := s_round(TO_SVEC(u_nint16_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
+ v_expected_iquv := s_round(TO_SVEC(v_nint16_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
-- Integration is done in the IAB
elsif g_use_accum = true then
- i_expected_iquv := u_round(TO_UVEC(i_noint_exp_arr(v_index),c_fsd_iquv_w - 1), c_lsb_iquv_w - 1, true);
- q_expected_iquv := s_round(TO_SVEC(q_noint_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
- u_expected_iquv := s_round(TO_SVEC(u_noint_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
- v_expected_iquv := s_round(TO_SVEC(v_noint_exp_arr(v_index),c_fsd_iquv_w), c_lsb_iquv_w, true);
+ i_expected_iquv := u_round(TO_UVEC(i_noint_exp_arr(v_index), c_fsd_iquv_w - 1), c_lsb_iquv_w - 1, true);
+ q_expected_iquv := s_round(TO_SVEC(q_noint_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
+ u_expected_iquv := s_round(TO_SVEC(u_noint_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
+ v_expected_iquv := s_round(TO_SVEC(v_noint_exp_arr(v_index), c_fsd_iquv_w), c_lsb_iquv_w, true);
end if;
if activestream_dly = c_allstreams then
i_expected_iab := TO_UVEC(to_uint(i_expected_iquv) * c_allstreams * c_nof_iab_int, c_fsd_w);
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
index 1dac5bc00bd01bffeca324bec34d6ee80ef24a4c..b0b53840667a62ce384e1e610f202e8ad27f9fee 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
@@ -196,10 +196,10 @@ begin
read(v_input_line, v_val(v_index)); -- valid
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,1)); -- real
+ read(v_input_line, v_data(v_index, 1)); -- real
read(v_input_line, v_comma);
- read(v_input_line, v_data(v_index,2)); -- imag
+ read(v_input_line, v_data(v_index, 2)); -- imag
v_index := v_index + 1;
end loop;
write(v_log_line, string'("finished reading stimuli file"));
@@ -302,10 +302,10 @@ begin
read(v_golden_line, v_val(v_index)); -- valid
read(v_golden_line, v_comma);
- read(v_golden_line, v_data(v_index,1)); -- real
+ read(v_golden_line, v_data(v_index, 1)); -- real
read(v_golden_line, v_comma);
- read(v_golden_line, v_data(v_index,2)); -- imag
+ read(v_golden_line, v_data(v_index, 2)); -- imag
v_index := v_index + 1;
end loop;
write(v_log_line, string'("finished reading golden file"));
@@ -321,8 +321,8 @@ begin
gold_index <= gold_index + 1 when rising_edge(clk) and out_val = '1';
flip_index <= (gold_index / g_nof_points) * g_nof_points + flip(gold_index mod g_nof_points, c_nof_points_w);
gold_sync <= gold_file_sync(gold_index);
- gold_re <= gold_file_data(gold_index,1) when g_use_reorder = true else gold_file_data(flip_index,1);
- gold_im <= gold_file_data(gold_index,2) when g_use_reorder = true else gold_file_data(flip_index,2);
+ gold_re <= gold_file_data(gold_index, 1) when g_use_reorder = true else gold_file_data(flip_index, 1);
+ gold_im <= gold_file_data(gold_index, 2) when g_use_reorder = true else gold_file_data(flip_index, 2);
-- Verify the output of the DUT with the expected output from the golden reference file
p_verify_output : process(clk)
diff --git a/libraries/dsp/st/src/vhdl/st_calc.vhd b/libraries/dsp/st/src/vhdl/st_calc.vhd
index 0dbe35431973bf2a2560e1328e13a3a4ec731abe..975873680f67daf7181c4f7db94d5468e5b3eeb1 100644
--- a/libraries/dsp/st/src/vhdl/st_calc.vhd
+++ b/libraries/dsp/st/src/vhdl/st_calc.vhd
@@ -129,7 +129,7 @@ architecture str of st_calc is
signal out_adr_m : std_logic_vector(c_adr_w - 1 downto 0);
begin
- regs: process(rst,clk)
+ regs: process(rst, clk)
begin
if rst = '1' then
reg_ar <= (others => '0');
diff --git a/libraries/dsp/st/src/vhdl/st_ctrl.vhd b/libraries/dsp/st/src/vhdl/st_ctrl.vhd
index 9824c127b13a3f93082cb71672f5d71400dcac58..31f21de4f3ff99409fea7ba98ee8c2751702f36b 100644
--- a/libraries/dsp/st/src/vhdl/st_ctrl.vhd
+++ b/libraries/dsp/st/src/vhdl/st_ctrl.vhd
@@ -127,7 +127,7 @@ begin
end generate;
-- registers
- regs: process(rst,clk)
+ regs: process(rst, clk)
begin
if rst = '1' then
i_rd_adr <= (others => '0');
@@ -177,7 +177,7 @@ begin
end if;
end process;
- wr_ctrl: process(i_wr_adr,dly_val,dly_sync)
+ wr_ctrl: process(i_wr_adr, dly_val, dly_sync)
begin
nxt_wr_adr <= i_wr_adr;
if dly_sync(c_tin_wr) = '1' then
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
index 2f9d05977c95c9e92ff4ce590ccb28ea7e3dcc51..cfa99b7379b28c11e7a1c16f60d10e54a58694e8 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
@@ -26,7 +26,7 @@
-- to RAM and can be read by MM.
-- --------------------------------------------------------------------------
-library IEEE,common_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
index 8d4fc6a96510274df76bd64cf90481d7ff28a6cb..0cfa0fe6231dc3d81c9bf2dbca26b7e5b261d7d0 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
@@ -28,7 +28,7 @@
-- out_sosi_arr. In_sosi.sync is passed on to out_sosi.
-- --------------------------------------------------------------------------
-library IEEE,common_lib, dp_lib;
+library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
diff --git a/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
index 0813eb85dc3b7d3baffc5a5ab3718da786f20607..43e3f21b01e093414ca411c6513a365b6c1dc579 100644
--- a/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
@@ -330,12 +330,12 @@ gen_vary_wg_integer_freq : if c_gen_vary_wg_integer_freq generate
u_2037 : entity work.tb_verify_pfb_wg generic map (2037, "WPFB", 37.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
u_2061 : entity work.tb_verify_pfb_wg generic map (2061, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
u_2064 : entity work.tb_verify_pfb_wg generic map (2064, "WPFB", 64.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2117 : entity work.tb_verify_pfb_wg generic map (2117, "WPFB",117.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2128 : entity work.tb_verify_pfb_wg generic map (2128, "WPFB",128.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2256 : entity work.tb_verify_pfb_wg generic map (2256, "WPFB",256.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2257 : entity work.tb_verify_pfb_wg generic map (2257, "WPFB",257.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2373 : entity work.tb_verify_pfb_wg generic map (2373, "WPFB",373.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_2503 : entity work.tb_verify_pfb_wg generic map (2503, "WPFB",503.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2117 : entity work.tb_verify_pfb_wg generic map (2117, "WPFB", 117.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2128 : entity work.tb_verify_pfb_wg generic map (2128, "WPFB", 128.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2256 : entity work.tb_verify_pfb_wg generic map (2256, "WPFB", 256.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2257 : entity work.tb_verify_pfb_wg generic map (2257, "WPFB", 257.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2373 : entity work.tb_verify_pfb_wg generic map (2373, "WPFB", 373.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_2503 : entity work.tb_verify_pfb_wg generic map (2503, "WPFB", 503.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
-- Results:
-- g_subband_index_a
@@ -550,12 +550,12 @@ end generate;
-- 2021_jan_11
gen_vary_g_amplitude_a : if c_gen_vary_g_amplitude_a generate
- u_760 : entity work.tb_verify_pfb_wg generic map (760, "WPFB", 61.0, 61.0, 1.0 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18, 1.0
- u_761 : entity work.tb_verify_pfb_wg generic map (761, "WPFB", 61.0, 61.0, 0.5 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_762 : entity work.tb_verify_pfb_wg generic map (762, "WPFB", 61.0, 61.0, 0.25 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_763 : entity work.tb_verify_pfb_wg generic map (763, "WPFB", 61.0, 61.0, 0.125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_764 : entity work.tb_verify_pfb_wg generic map (764, "WPFB", 61.0, 61.0, 0.0625 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
- u_765 : entity work.tb_verify_pfb_wg generic map (765, "WPFB", 61.0, 61.0, 0.03125 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_760 : entity work.tb_verify_pfb_wg generic map (760, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18, 1.0
+ u_761 : entity work.tb_verify_pfb_wg generic map (761, "WPFB", 61.0, 61.0, 0.5, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_762 : entity work.tb_verify_pfb_wg generic map (762, "WPFB", 61.0, 61.0, 0.25, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_763 : entity work.tb_verify_pfb_wg generic map (763, "WPFB", 61.0, 61.0, 0.125, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_764 : entity work.tb_verify_pfb_wg generic map (764, "WPFB", 61.0, 61.0, 0.0625, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
+ u_765 : entity work.tb_verify_pfb_wg generic map (765, "WPFB", 61.0, 61.0, 0.03125, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
u_766 : entity work.tb_verify_pfb_wg generic map (766, "WPFB", 61.0, 61.0, 0.015625, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
--Results:
--tb-761 . wpfb_measured_proc_gain_a_dB = 6.11 [dB]
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
index c8be3118e2f27f0620b78c0b61b8bc9a4027507a..654192f40f6ada64d54bb9bbecbf8fa824635d3a 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
@@ -568,9 +568,9 @@ begin
if (v_spectra_cnt < c_nof_spectra_to_output_file) then
for K in 0 to g_wpfb.wb_factor - 1 loop
for L in 0 to c_nof_bins - 1 loop
- write(v_line, v_out_re_matrix(K,L));
+ write(v_line, v_out_re_matrix(K, L));
write(v_line, string'(","));
- write(v_line, v_out_im_matrix(K,L));
+ write(v_line, v_out_im_matrix(K, L));
writeline(v_output, v_line);
end loop;
end loop;
diff --git a/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd b/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
index 23e4366d9dd0ae043f83ceb9639b098bba36a19e..59157863fd745c627de52b76ff45e881a57f6653 100644
--- a/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
@@ -74,7 +74,7 @@ architecture rtl of aduh_mean_sum is
begin
sum <= i_sum;
- regs : process(rst,clk)
+ regs : process(rst, clk)
begin
if rst = '1' then
i_sum <= (others => '0');
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
index 23773da0a6501691d47ea9729e3fdfc2a58d168b..39e96514bac6a2622e1608dfc6ca941b74d53e1b 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
@@ -210,7 +210,7 @@ begin
dbg_dat( 7 downto 0) <= offset_binary(be_sync & TO_UVEC(r.sync_phase, 4));
dbg_dat(15 downto 8) <= offset_binary(TO_UVEC(r.lock_state, 8));
dbg_dat(23 downto 16) <= offset_binary( wb_cnt( 7 downto 0));
- dbg_dat(31 downto 24) <= offset_binary(RESIZE_UVEC(wb_cnt(c_wb_cnt_w - 1 downto 8),8));
+ dbg_dat(31 downto 24) <= offset_binary(RESIZE_UVEC(wb_cnt(c_wb_cnt_w - 1 downto 8), 8));
end process;
-- Registers
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
index 6140c2af10c0223f8835cb838f58141ca5b1965a..33684e3688afc5026e41081c4391baa7ec808949 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
@@ -105,7 +105,7 @@ begin
test_pattern_en <= '1', '0' after 5 us, '1' after 6 us;
dp_val <= '1', '0' after 15 us, '1' after 16 us;
verify_wrong <= '0', '1' after 5.5 us, '0' after 6.5 us, '1' after 15.5 us, '0' after 16.5 us;
- verify_ok <= '0', '1' after 1 us, '0' after 4 us, '1' after 8 us , '0' after 9 us, '1' after 11 us , '0' after 14 us, '1' after 18 us;
+ verify_ok <= '0', '1' after 1 us, '0' after 4 us, '1' after 8 us, '0' after 9 us, '1' after 11 us, '0' after 14 us, '1' after 18 us;
a_verify_res_ack <= '0', '1' after 7 us, '0' after 7 us + c_dp_clk_period, '1' after 10 us, '0' after 10 us + c_dp_clk_period, '1' after 17 us, '0' after 17 us + c_dp_clk_period;
b_verify_res_ack <= '0', '1' after 7 us, '0' after 7 us + c_dp_clk_period, '1' after 10 us, '0' after 10 us + c_dp_clk_period, '1' after 17 us, '0' after 17 us + c_dp_clk_period;
tb_end <= '0', '1' after 20 us;
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index b657a74bb8e3d7b884274c140ea9af064956a173..1e1bb093fd441fc69a196c2165f8eb8e398b9888 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -251,7 +251,7 @@ architecture str of io_ddr is
constant c_mem_reg_adr_w : natural := 2;
constant c_mem_reg_dat_w : natural := 32;
constant c_mem_reg_nof_data : natural := 4;
- constant c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_adr_w , c_mem_reg_dat_w , c_mem_reg_nof_data, 'X');
+ constant c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_adr_w, c_mem_reg_dat_w, c_mem_reg_nof_data, 'X');
signal ctlr_dvr_miso : t_mem_ctlr_miso;
signal ctlr_dvr_mosi : t_mem_ctlr_mosi;
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 912ae3b3eb5ccc6b9f54f6eea6ee3842351e523f..814d64c3fb4bce5f6be965155fec62b2aab2ecb5 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -294,7 +294,7 @@ begin
for R in 0 to g_nof_repeat - 1 loop
proc_common_wait_some_cycles(dvr_clk, 1);
for I in c_ctlr_address_lo_arr'range loop
- dvr_start_address <= TO_UVEC(c_ctlr_address_lo_arr(I) , c_ctlr_address_w);
+ dvr_start_address <= TO_UVEC(c_ctlr_address_lo_arr(I), c_ctlr_address_w);
dvr_nof_data <= TO_UVEC(c_ctlr_nof_address_arr(I), c_ctlr_address_w);
-- START ACCESS
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index 664d68451b79dc659ed4b483e4c3b1f15046c7b4..19797cbbf6831f7347f693bee9675f9d51525ea3 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -75,14 +75,14 @@ begin
u_cross_domain : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, true, 5 ns, 1, 2500, 1, 2, 3, 1, "VAL") port map (tb_end_vec(5));
u_mixed_width : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 8, 2500, 1, 3, 2, 1, "VAL") port map (tb_end_vec(6));
- u_wr_burst_size_0 : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 4, 2,10, 3, 3, 2, "VAL") port map (tb_end_vec(7));
- u_wr_burst_size_1 : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 4, 1,10, 1, 1, 2, "VAL") port map (tb_end_vec(8));
+ u_wr_burst_size_0 : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 4, 2, 10, 3, 3, 2, "VAL") port map (tb_end_vec(7));
+ u_wr_burst_size_1 : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 4, 1, 10, 1, 1, 2, "VAL") port map (tb_end_vec(8));
u_cross_dvr_to_faster_ctlr : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 20 ns, 1, 2500, 1, 1, 4, 1, "VAL") port map (tb_end_vec(9));
u_cross_dvr_to_slower_ctlr : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 1 ns, 1, 2500, 1, 1, 4, 1, "VAL") port map (tb_end_vec(10));
- u_sequencer_1_16 : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 4, 64,10, 1,16, 1, "VAL") port map (tb_end_vec(11));
- u_sequencer_16_1 : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 4, 64,10,16, 1, 1, "VAL") port map (tb_end_vec(12));
+ u_sequencer_1_16 : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 4, 64, 10, 1, 16, 1, "VAL") port map (tb_end_vec(11));
+ u_sequencer_16_1 : entity work.tb_io_ddr generic map (false, c_technology, c_tech_ddr3, c_tech_ddr4, false, false, 5 ns, 4, 64, 10, 16, 1, 1, "VAL") port map (tb_end_vec(12));
end generate;
-- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model.
diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index 0798866d0fb50015b3fad9619f1ba5f6c357993a..fbace9696cfc116d36b81999fd1d9e50631ed4ed 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -147,7 +147,7 @@ architecture str of ddr3 is
signal local_cal_success : std_logic;
signal local_cal_fail : std_logic;
- constant c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, 1 , 32 , 1, 'X');
+ constant c_mem_reg_io_ddr : t_c_mem := (c_mem_reg_rd_latency, 1, 32, 1, 'X');
signal mm_reg_io_ddr : std_logic_vector(31 downto 0);
signal term_ctrl_out : t_tech_ddr3_phy_terminationcontrol;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd b/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
index 77dc5117a99f21672b57d83657b4d3d2ab0bc5a5..d6f2dccfbe06bc25b86e4db17df1d9f756f6bd1d 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
@@ -197,7 +197,7 @@ begin
-- Perform any remaining writes in a burst
nxt_state <= s_wr_burst;
nxt_req_burst_cycles <= TO_UVEC(wr_burst_size-1, c_ddr3_ctlr_maxburstsize_w); -- Forward the required nof burst cycles (-1 as we've done the 1st in this state already) to burst state
- i_ctlr_burst_size <= TO_UVEC(wr_burst_size , c_ddr3_ctlr_maxburstsize_w);
+ i_ctlr_burst_size <= TO_UVEC(wr_burst_size, c_ddr3_ctlr_maxburstsize_w);
end if; -- ELSE: there is only 1 word, so no need for remaining burst
nxt_cur_address <= INCR_UVEC(cur_address, unsigned(i_ctlr_burst_size) * c_ddr3_ctlr_rsl);
-- IF UNSIGNED(i_ctlr_burst_size) = 1 THEN -- Prevents FSM from going into this state again too soon (reg_addresses_rem invalid)
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
index 1c6b86fceee59f6e3323959a2570408782acf5cf..7909a2d68922b9044c750a5b63eabd4ad238ce82 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
@@ -334,7 +334,7 @@ begin
clk => dp_clk,
wr_dat => snk_in_arr(0).bsn,
wr_req => wr_req,
- wr_ful => open ,
+ wr_ful => open,
rd_dat => rd_dat_i,
rd_req => rd_req_i,
rd_emp => open,
diff --git a/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd b/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
index 02b167448fe219cdd3b5f72fb60974a197e074f0..ff522f418fa937a6d32c8ebcdf5cd454b19b45d3 100644
--- a/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
+++ b/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
@@ -112,7 +112,7 @@ begin
begin
if rst = '1' then
state <= Idle;
- ihl <= to_unsigned(0,ihl'length);
+ ihl <= to_unsigned(0, ihl'length);
elsif (rising_edge(clk)) then
i_src_out <= snk_in;
case state is
diff --git a/libraries/io/eth/src/vhdl/eth_statistics.vhd b/libraries/io/eth/src/vhdl/eth_statistics.vhd
index 1282286c2294bc7addafcf80414ee802f8fe5ca3..f145decb108b4a998daa8692e36903a257f4b32f 100644
--- a/libraries/io/eth/src/vhdl/eth_statistics.vhd
+++ b/libraries/io/eth/src/vhdl/eth_statistics.vhd
@@ -104,7 +104,7 @@ begin
mm_sla_in => c_mem_mosi_rst,
- tx_mac_in => ('0','0','0','0','0'),
+ tx_mac_in => ('0', '0', '0', '0', '0'),
tx_snk_clk => eth_clk,
tx_snk_in => c_dp_sosi_rst,
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
index 22a401dde7a9a6baebb9b51dae8b5ac60456f4f0..e241e09243b17c3908c362f005bf0236ba8a45c5 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
@@ -51,8 +51,8 @@ architecture tb of tb_eth_IHL_to_20 is
signal src_out : t_dp_sosi;
type int_arr is array (natural range <>) of integer;
- constant c_IHL_to_test : int_arr(1 to 11) := (5,6,7,8,9,10,11,12,13,14,15);
- constant c_len_to_test : int_arr(1 to 5) := (0,1,16,20,3000);
+ constant c_IHL_to_test : int_arr(1 to 11) := (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+ constant c_len_to_test : int_arr(1 to 5) := (0, 1, 16, 20, 3000);
procedure gen_eth_frame (constant IHL : natural;
constant UDP_payload_len : natural;
@@ -71,9 +71,9 @@ architecture tb of tb_eth_IHL_to_20 is
snk_in.data <= RESIZE_DP_DATA(X"00000800");
wait until rising_edge(clk);
snk_in.data <= RESIZE_DP_DATA(X"4" & -- IPv4 header
- TO_UVEC(IHL,c_network_ip_header_length_w) &
+ TO_UVEC(IHL, c_network_ip_header_length_w) &
X"00" &
- TO_UVEC((IHL + UDP_payload_len + 2) * 4,c_network_ip_total_length_w));
+ TO_UVEC((IHL + UDP_payload_len + 2) * 4, c_network_ip_total_length_w));
wait until rising_edge(clk);
snk_in.data <= RESIZE_DP_DATA(X"00004000");
wait until rising_edge(clk);
@@ -85,17 +85,17 @@ architecture tb of tb_eth_IHL_to_20 is
wait until rising_edge(clk);
for I in 6 to IHL loop
- snk_in.data <= RESIZE_DP_DATA(X"BAD000" & TO_UVEC(I,c_network_ip_header_length_w)); -- optionnal option word
+ snk_in.data <= RESIZE_DP_DATA(X"BAD000" & TO_UVEC(I, c_network_ip_header_length_w)); -- optionnal option word
wait until rising_edge(clk);
end loop;
snk_in.data <= RESIZE_DP_DATA(X"10FA10FA"); -- UDP header
wait until rising_edge(clk);
- snk_in.data <= RESIZE_DP_DATA(TO_UVEC((UDP_payload_len + 2) * 4,c_network_udp_total_length_w) & X"0000");
+ snk_in.data <= RESIZE_DP_DATA(TO_UVEC((UDP_payload_len + 2) * 4, c_network_udp_total_length_w) & X"0000");
wait until rising_edge(clk);
for I in 0 to UDP_payload_len - 1 loop -- UDP payload
- snk_in.data <= RESIZE_DP_DATA(X"BEEF" & TO_UVEC(I,16));
+ snk_in.data <= RESIZE_DP_DATA(X"BEEF" & TO_UVEC(I, 16));
wait until rising_edge(clk);
end loop;
@@ -127,9 +127,9 @@ architecture tb of tb_eth_IHL_to_20 is
-- IPv4 header
wait until falling_edge(clk) and src_out.valid = '1';
assert src_out.data(31 downto 0) = X"4" &
- TO_UVEC(c_IHL,c_network_ip_header_length_w) &
+ TO_UVEC(c_IHL, c_network_ip_header_length_w) &
X"00" &
- TO_UVEC((c_IHL + UDP_payload_len + 2) * 4,c_network_ip_total_length_w)
+ TO_UVEC((c_IHL + UDP_payload_len + 2) * 4, c_network_ip_total_length_w)
report "Wrong Version / IHL / Total Length" severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
@@ -146,13 +146,13 @@ architecture tb of tb_eth_IHL_to_20 is
wait until falling_edge(clk) and src_out.valid = '1';
assert src_out.data(31 downto 0) = X"10FA10FA" report "Wrong UDP ports" severity FAILURE;
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = TO_UVEC((UDP_payload_len + 2) * 4,c_network_udp_total_length_w) &
+ assert src_out.data(31 downto 0) = TO_UVEC((UDP_payload_len + 2) * 4, c_network_udp_total_length_w) &
X"0000"
report "Wrong UDP length / CRC" severity FAILURE;
-- UDP payload
for I in 0 to UDP_payload_len - 1 loop
wait until falling_edge(clk) and src_out.valid = '1';
- assert src_out.data(31 downto 0) = X"BEEF" & TO_UVEC(I,16) report "Wrong UDP Payload" severity FAILURE;
+ assert src_out.data(31 downto 0) = X"BEEF" & TO_UVEC(I, 16) report "Wrong UDP Payload" severity FAILURE;
-- ASSERT src_out.data(31 downto 0) = X"BEEF" & TO_UVEC(I,16) REPORT "Wrong UDP Payload: 0xBEEF" & TO_UVEC(I,16)'IMAGE SEVERITY FAILURE;
end loop;
@@ -173,7 +173,7 @@ begin
wait for 50 ns; wait until rising_edge(clk);
gen_eth_frame (c_IHL_to_test(IHL_n),
c_len_to_test(len_n),
- clk,snk_in);
+ clk, snk_in);
end loop;
end loop;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
index ad83dbe15cc888c3e90ef2a0b07a9270c368fb6e..90f4db2db3cc412c23250a260d7d611cefada628 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
@@ -263,7 +263,7 @@ begin
proc_mem_mm_bus_wr(I * 2, bg_ctrl_arr(I).samples_per_packet, mm_clk, reg_dp_split_copi);
-- Prepare the BG
- proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate) , mm_clk, reg_bg_ctrl_copi);
+ proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate), mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 2, bg_ctrl_arr(I).blocks_per_sync, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 3, bg_ctrl_arr(I).gapsize, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 4, bg_ctrl_arr(I).mem_low_adrs, mm_clk, reg_bg_ctrl_copi);
diff --git a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
index 008ab87c72ab37d9ac480f1211e722d771e04c68..9a2227bd265021f79c059c570aab26056f9759d9 100644
--- a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
+++ b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
@@ -62,7 +62,7 @@ architecture str of fpga_sense is
constant c_mem_reg_temp_adr_w : natural := 1;
constant c_mem_reg_temp_dat_w : natural := 32;
constant c_mem_reg_temp_nof_data : natural := 1;
- constant c_mem_reg_temp_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_temp_adr_w , c_mem_reg_temp_dat_w , c_mem_reg_temp_nof_data, 'X');
+ constant c_mem_reg_temp_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_temp_adr_w, c_mem_reg_temp_dat_w, c_mem_reg_temp_nof_data, 'X');
-- temp = (693 * adc)/1024 - 265 => adc = (temp + 265)*1024/693
constant c_temp_high_raw : std_logic_vector(9 downto 0) := TO_UVEC(((g_temp_high + 265) * 1024) / 693, 10);
@@ -71,7 +71,7 @@ architecture str of fpga_sense is
constant c_mem_reg_voltage_adr_w : natural := 1;
constant c_mem_reg_voltage_dat_w : natural := 32;
constant c_mem_reg_voltage_nof_data : natural := 1;
- constant c_mem_reg_voltage_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_voltage_adr_w , c_mem_reg_voltage_dat_w , c_mem_reg_voltage_nof_data, 'X');
+ constant c_mem_reg_voltage_data : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_voltage_adr_w, c_mem_reg_voltage_dat_w, c_mem_reg_voltage_nof_data, 'X');
signal mm_reg_temp_data : std_logic_vector(c_mem_reg_temp_dat_w - 1 downto 0);
signal temp_data : std_logic_vector(9 downto 0);
@@ -107,7 +107,7 @@ begin
if mm_rst = '1' then
mm_reg_temp_data <= (others => '0');
elsif falling_edge(eoc) then
- mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w);
+ mm_reg_temp_data <= RESIZE_UVEC(temp_data, c_mem_reg_temp_dat_w);
end if;
end process;
@@ -116,7 +116,7 @@ begin
no_tech_fpga_temp_sens: if g_sim = true generate
-- temp = (693 * adc)/1024 - 265 => adc = (temp + 265)*1024/693
temp_data <= TO_UVEC(458, temp_data'length); -- choose temp = 45 degrees so adc temp_data = 458
- mm_reg_temp_data <= RESIZE_UVEC(temp_data,c_mem_reg_temp_dat_w);
+ mm_reg_temp_data <= RESIZE_UVEC(temp_data, c_mem_reg_temp_dat_w);
end generate;
u_reg_map : entity common_lib.common_reg_r_w_dc
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
index d5d2e4237df93e7ff9e5d7de9f99aeb2bff2688c..75b0de52baf547c8751ca3cd1e6c573484a8ac7c 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
@@ -92,28 +92,28 @@ package i2c_dev_unb2_pkg is
constant c_i2c_unb2_sens_expected_mask_read_all : std_logic_vector := RESIZE_UVEC("001010101010101010101010101010101010101010101", c_word_w);
constant c_i2c_unb2_sens_nof_result_data_read_all : natural := 22;
constant c_i2c_unb2_sens_protocol_list_read_all : t_nat_natural_arr := (
- SMBUS_READ_BYTE , I2C_UNB2_SENS_TEMP_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_DCDC_BMR456_ADR, PMBUS_REG_READ_VIN,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_DCDC_BMR456_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_DCDC_BMR456_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_PIM_PIM4328PD_ADR, PMBUS_REG_READ_VIN,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_PIM_PIM4328PD_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_PIM_PIM4328PD_ADR, PMBUS_REG_READ_VCAP,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_TEMP_MAX1617_ADR, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_DCDC_BMR456_ADR, PMBUS_REG_READ_VIN,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_DCDC_BMR456_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_DCDC_BMR456_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_PIM_PIM4328PD_ADR, PMBUS_REG_READ_VIN,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_PIM_PIM4328PD_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_PIM_PIM4328PD_ADR, PMBUS_REG_READ_VCAP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_1V2_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_3V3_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_CLK_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP0_BMR464_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_SENS_QSFP1_BMR464_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_END
);
@@ -122,24 +122,24 @@ package i2c_dev_unb2_pkg is
constant c_i2c_unb2_pmbus_expected_mask_read_all : std_logic_vector := RESIZE_UVEC("0010101010101010101010101010101010101", c_word_w);
constant c_i2c_unb2_pmbus_nof_result_data_read_all : natural := 18;
constant c_i2c_unb2_pmbus_protocol_list_read_all : t_nat_natural_arr := (
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
- SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CORE_BMR464_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_VCCRAM_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR0_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_TCVR1_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_CTRL_BMR461_ADR, PMBUS_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_VOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_IOUT,
+ SMBUS_READ_BYTE, I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_END
);
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
index fd7b8dacf9f1069549faa1b5e7f7eebe9e5cd00d..3f09ab494a53800d2f63cd9c9dd951ab273f9529 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
@@ -62,10 +62,10 @@ package i2c_dev_unb_pkg is
constant c_i2c_unb_max6652_expected_mask_read_config : std_logic_vector := RESIZE_UVEC("001010101", c_word_w);
constant c_i2c_unb_max6652_nof_result_data_read_config : natural := 4;
constant c_i2c_unb_max6652_protocol_list_read_config : t_nat_natural_arr := (
- SMBUS_READ_BYTE , I2C_UNB_MAX6652_ADR, MAX6652_REG_READ_VIN_2_5,
- SMBUS_READ_BYTE , I2C_UNB_MAX6652_ADR, MAX6652_REG_READ_VIN_3_3,
- SMBUS_READ_BYTE , I2C_UNB_MAX6652_ADR, MAX6652_REG_READ_VCC,
- SMBUS_READ_BYTE , I2C_UNB_MAX6652_ADR, MAX6652_REG_READ_TEMP,
+ SMBUS_READ_BYTE, I2C_UNB_MAX6652_ADR, MAX6652_REG_READ_VIN_2_5,
+ SMBUS_READ_BYTE, I2C_UNB_MAX6652_ADR, MAX6652_REG_READ_VIN_3_3,
+ SMBUS_READ_BYTE, I2C_UNB_MAX6652_ADR, MAX6652_REG_READ_VCC,
+ SMBUS_READ_BYTE, I2C_UNB_MAX6652_ADR, MAX6652_REG_READ_TEMP,
SMBUS_WRITE_BYTE, I2C_UNB_MAX6652_ADR, MAX6652_REG_CONFIG, MAX6652_CONFIG_LINE_FREQ_SEL + MAX6652_CONFIG_START,
SMBUS_C_END
);
diff --git a/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd b/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
index 79d5aab2f4f54d6b0a7bb6f32036f8c809b7bd28..de81c1a39632ecdb7facbd03745296425b4f55a2 100644
--- a/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
@@ -88,7 +88,7 @@ begin
prot_done <= not prev_smbus_st_idle and smbus_st_idle;
list_end <= smbus_st_end or pend_st_end;
- regs: process(rst,clk)
+ regs: process(rst, clk)
begin
if rst = '1' then
i_busy <= '0';
diff --git a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
index 725394f4f1118906c9393cbb2c6b9e80320b74d2..f97f2d8bf034230021303be713d0962c669f80bb 100644
--- a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
@@ -173,7 +173,7 @@ begin
nrst <= not rst;
- p_srst : process(rst,clk)
+ p_srst : process(rst, clk)
begin
if rst = '1' then
srst <= (others => '1');
@@ -320,7 +320,7 @@ begin
end if;
end process;
- get_op : process(pid,pix,op,rdy)
+ get_op : process(pid, pix, op, rdy)
begin
nxt_pix <= pix;
nxt_op_val <= '1';
@@ -433,7 +433,7 @@ begin
rdy <= '1';
else
i2c_write <= '1';
- i2c_dat_in <= std_logic_vector(conv_unsigned(cnt,8));
+ i2c_dat_in <= std_logic_vector(conv_unsigned(cnt, 8));
end if;
when OP_WR_DAT =>
diff --git a/libraries/io/i2c/src/vhdl/i2cslave.vhd b/libraries/io/i2c/src/vhdl/i2cslave.vhd
index 17f2ffc61d05f31c794032a85f6d5161080f8088..8e569daa16a9d99bc79427b86d4f9c891eb42257 100644
--- a/libraries/io/i2c/src/vhdl/i2cslave.vhd
+++ b/libraries/io/i2c/src/vhdl/i2cslave.vhd
@@ -55,7 +55,7 @@ architecture rtl of i2cslave is
end if;
end;
- type state is (reset,read_addr,read_data,write_data,acknowledge,nacknowledge,wacknowledge,wnacknowledge);
+ type state is (reset, read_addr, read_data, write_data, acknowledge, nacknowledge, wacknowledge, wnacknowledge);
-- Start of g_rx_filter related declarations
constant c_meta_len : natural := 3; -- use 3 FF to tackle meta stability between SCL and clk domain
diff --git a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
index 8164e1904075ccf4b1000a7e98026b5186f75cff..bef185e0f393ec951f92ecc2c551f13289285000 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
@@ -96,7 +96,7 @@ begin
begin
if rising_edge(rd_req) then
case cmd is -- only model some read cmd
- when MAX1617_CMD_READ_REMOTE_TEMP => rd_dat <= std_logic_vector(to_signed(temp,8));
+ when MAX1617_CMD_READ_REMOTE_TEMP => rd_dat <= std_logic_vector(to_signed(temp, 8));
when MAX1617_CMD_READ_CONFIG => rd_dat <= config_reg;
when MAX1617_CMD_READ_STATUS => rd_dat <= status_reg;
when MAX1617_CMD_READ_REMOTE_HIGH => rd_dat <= temp_hi_reg;
diff --git a/libraries/io/i2c/tb/vhdl/dev_max6652.vhd b/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
index 02ddc416d49acd6c94d6e782d873cfe966bb4670..c234fc5fb06e2bcf33b3e55845205cb2e9dc540f 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
@@ -96,11 +96,11 @@ begin
begin
if rising_edge(rd_req) then
case cmd is -- only model read V and read temp
- when c_cmd_read_2v5 => rd_dat <= std_logic_vector(to_unsigned(volt_2v5,8));
- when c_cmd_read_12v => rd_dat <= std_logic_vector(to_unsigned(volt_12v,8));
- when c_cmd_read_3v3 => rd_dat <= std_logic_vector(to_unsigned(volt_3v3,8));
- when c_cmd_read_vcc => rd_dat <= std_logic_vector(to_unsigned(volt_vcc,8));
- when c_cmd_read_temp => rd_dat <= std_logic_vector(to_signed(temp,8));
+ when c_cmd_read_2v5 => rd_dat <= std_logic_vector(to_unsigned(volt_2v5, 8));
+ when c_cmd_read_12v => rd_dat <= std_logic_vector(to_unsigned(volt_12v, 8));
+ when c_cmd_read_3v3 => rd_dat <= std_logic_vector(to_unsigned(volt_3v3, 8));
+ when c_cmd_read_vcc => rd_dat <= std_logic_vector(to_unsigned(volt_vcc, 8));
+ when c_cmd_read_temp => rd_dat <= std_logic_vector(to_signed(temp, 8));
when c_cmd_config => rd_dat <= config_reg;
when others => rd_dat <= (others => '1');
end case;
diff --git a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
index aff2b064be12a3b3f7156ab08baaf4de5d2f18a9..485275578ca91a1958a852a9de1b643f2514b445 100644
--- a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
@@ -94,12 +94,12 @@ begin
begin
if rising_edge(rd_req) then
case cmd is -- only model some read cmd
- when PMBUS_REG_READ_VOUT_MODE => rd_dat <= std_logic_vector(to_signed(vout_mode,8));
- when PMBUS_REG_READ_VIN => rd_dat <= std_logic_vector(to_signed(vin,8));
- when PMBUS_REG_READ_VOUT => rd_dat <= std_logic_vector(to_signed(vout,8));
- when PMBUS_REG_READ_IOUT => rd_dat <= std_logic_vector(to_signed(iout,8));
- when PMBUS_REG_READ_VCAP => rd_dat <= std_logic_vector(to_signed(vcap,8));
- when PMBUS_REG_READ_TEMP => rd_dat <= std_logic_vector(to_signed(temp,8));
+ when PMBUS_REG_READ_VOUT_MODE => rd_dat <= std_logic_vector(to_signed(vout_mode, 8));
+ when PMBUS_REG_READ_VIN => rd_dat <= std_logic_vector(to_signed(vin, 8));
+ when PMBUS_REG_READ_VOUT => rd_dat <= std_logic_vector(to_signed(vout, 8));
+ when PMBUS_REG_READ_IOUT => rd_dat <= std_logic_vector(to_signed(iout, 8));
+ when PMBUS_REG_READ_VCAP => rd_dat <= std_logic_vector(to_signed(vcap, 8));
+ when PMBUS_REG_READ_TEMP => rd_dat <= std_logic_vector(to_signed(temp, 8));
when others => rd_dat <= (others => '1');
end case;
end if;
diff --git a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
index 89472e640474856072cbbdda960b356f12ff9f69..64e467438dfe769b9818e47a148af3f65a3acdc4 100644
--- a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
+++ b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
@@ -68,7 +68,7 @@ architecture beh of i2c_slv_device is
signal rd_next : std_logic := '0'; -- behavioral
signal dev_state : t_dev_state := ST_IDLE; -- behavioral
- type state is (reset,read_addr,read_data,write_data,acknowledge,nacknowledge,wacknowledge,wnacknowledge);
+ type state is (reset, read_addr, read_data, write_data, acknowledge, nacknowledge, wacknowledge, wnacknowledge);
signal RST : std_logic; -- behavioral
signal CTRL_REG : std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0);
@@ -155,7 +155,7 @@ begin
CTRL_REG <= i_ctrl_reg;
startcontrol:
- process(SDA,SCL,streset,RST)
+ process(SDA, SCL, streset, RST)
begin
if falling_edge(SDA) then
if strong(SCL) = '1' then
@@ -171,7 +171,7 @@ begin
end process;
stopcontrol:
- process(SDA,SCL,streset,RST)
+ process(SDA, SCL, streset, RST)
begin
if rising_edge(SDA) then
if strong(SCL) = '1' then
@@ -187,7 +187,7 @@ begin
end process;
control: -- i2c slave
- process(SCL,RST)
+ process(SCL, RST)
begin
if RST = '1' then
--reset input connected to bit 17 of CTRL register, hence default for CTRL[17] must be '0' so RST will act as a spike.
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
index 436888b8d3a79181214f690079912fd20ddede55..ca4e441e2acaee04493e6acf9692f9daf00add12 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
@@ -71,27 +71,27 @@ architecture tb of tb_i2c_master is
constant c_temp_high : natural := 127;
constant c_protocol_list : t_nat_natural_arr := (
- SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_VIN_2_5,
- SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_VIN_3_3,
- SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_VCC,
- SMBUS_READ_BYTE , ADR_MAX6652 , MAX6652_REG_READ_TEMP,
- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX6652, MAX6652_REG_READ_VIN_2_5,
+ SMBUS_READ_BYTE, ADR_MAX6652, MAX6652_REG_READ_VIN_3_3,
+ SMBUS_READ_BYTE, ADR_MAX6652, MAX6652_REG_READ_VCC,
+ SMBUS_READ_BYTE, ADR_MAX6652, MAX6652_REG_READ_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX1617_BP, MAX1617_CMD_READ_REMOTE_TEMP,
-- For debugging, use AP temp fields in RSR to read other info from the sensor, e.g.:
-- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_STATUS,
-- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_CONFIG,
-- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_HIGH,
-- SMBUS_READ_BYTE , ADR_MAX1617_BP , MAX1617_CMD_READ_REMOTE_LOW,
- SMBUS_READ_BYTE , ADR_MAX1617_AP0, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ADR_MAX1617_AP1, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ADR_MAX1617_AP2, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_READ_BYTE , ADR_MAX1617_AP3, MAX1617_CMD_READ_REMOTE_TEMP,
- SMBUS_WRITE_BYTE, ADR_MAX6652 , MAX6652_REG_CONFIG, MAX6652_CONFIG_LINE_FREQ_SEL + MAX6652_CONFIG_START,
- SMBUS_WRITE_BYTE, ADR_MAX1617_BP , MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
+ SMBUS_READ_BYTE, ADR_MAX1617_AP0, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX1617_AP1, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX1617_AP2, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_READ_BYTE, ADR_MAX1617_AP3, MAX1617_CMD_READ_REMOTE_TEMP,
+ SMBUS_WRITE_BYTE, ADR_MAX6652, MAX6652_REG_CONFIG, MAX6652_CONFIG_LINE_FREQ_SEL + MAX6652_CONFIG_START,
+ SMBUS_WRITE_BYTE, ADR_MAX1617_BP, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP0, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP1, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP2, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP3, MAX1617_CMD_WRITE_CONFIG, MAX1617_CONFIG_ID + MAX1617_CONFIG_THERM,
- SMBUS_WRITE_BYTE, ADR_MAX1617_BP , MAX1617_CMD_WRITE_REMOTE_HIGH, c_temp_high,
+ SMBUS_WRITE_BYTE, ADR_MAX1617_BP, MAX1617_CMD_WRITE_REMOTE_HIGH, c_temp_high,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP0, MAX1617_CMD_WRITE_REMOTE_HIGH, c_temp_high,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP1, MAX1617_CMD_WRITE_REMOTE_HIGH, c_temp_high,
SMBUS_WRITE_BYTE, ADR_MAX1617_AP2, MAX1617_CMD_WRITE_REMOTE_HIGH, c_temp_high,
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd b/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
index 1307590caddc8ce3bc549c28c6640277698e9711..c48b86aea25b927b00f438ed3150fd3d92d6823b 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
@@ -95,22 +95,22 @@ tbsda : process
wait for 200 ns; -- initial time to let the fpga set up things
--I2C write sequence (from master to slave)
- SDA <= 'H', '0' after 30 ns, '0' after 60 ns,'0' after 110 ns,'0' after 160 ns,'0' after 210 ns,'0' after 260 ns,'0' after 310 ns,'H' after 360 ns,'0' after 410 ns;
+ SDA <= 'H', '0' after 30 ns, '0' after 60 ns, '0' after 110 ns, '0' after 160 ns, '0' after 210 ns, '0' after 260 ns, '0' after 310 ns, 'H' after 360 ns, '0' after 410 ns;
-- start sent address: 0000001, sent rw=0
--the previous is evaluated at time = 0
wait for 452 ns; -- next lines are evaluated 450 ns later
SDA <= 'Z'; -- time for slave to acknowledge
wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','H' after 10 ns, '0' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns; -- sent first data byte
+ SDA <= 'Z', 'H' after 10 ns, '0' after 60 ns, 'H' after 110 ns, '0' after 160 ns, 'H' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns; -- sent first data byte
wait for 400 ns;
SDA <= 'Z'; -- time for slave to acknowledge
wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent second data byte
+ SDA <= 'Z', '0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns, 'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent second data byte
wait for 400 ns;
SDA <= 'Z'; -- time for slave to acknowledge
wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent third data byte
+ SDA <= 'Z', '0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns, 'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent third data byte
wait for 400 ns;
SDA <= 'Z'; -- time for slave to nacknowledge
@@ -125,19 +125,19 @@ tbsda : process
--time is 1500ns + 450ns
--I2C read sequence (from slave to master)
- SDA <= 'H', '0' after 30 ns, '0' after 60 ns,'0' after 110 ns,'0' after 160 ns,'0' after 210 ns,'0' after 260 ns,'0' after 310 ns,'H' after 360 ns,'H' after 410 ns;
+ SDA <= 'H', '0' after 30 ns, '0' after 60 ns, '0' after 110 ns, '0' after 160 ns, '0' after 210 ns, '0' after 260 ns, '0' after 310 ns, 'H' after 360 ns, 'H' after 410 ns;
-- start sent address: 0000001 sent rw=1
wait for 450 ns; -- next lines are evaluated 450 ns later
SDA <= 'Z'; -- time for slave to acknowledge address
wait for 505 ns;
- SDA <= '0','Z' after 30 ns; -- acknowledge first byte
+ SDA <= '0', 'Z' after 30 ns; -- acknowledge first byte
wait for 500 ns;
- SDA <= '0','Z' after 30 ns; -- acknowledge second byte
+ SDA <= '0', 'Z' after 30 ns; -- acknowledge second byte
--time is 2455ns + 450ns
wait for 505 ns; -- on purpose the nack is given 100 ns later
- SDA <= 'H','Z' after 50 ns; -- nacknowledge third byte
+ SDA <= 'H', 'Z' after 50 ns; -- nacknowledge third byte
wait for 125 ns; -- WAIT 2.5 clk to give stop command
SDA <= 'H'; -- stop
wait for 15 ns; -- to get in line with falling clk edge
@@ -153,17 +153,17 @@ tbsda : process
wait for 50 ns;
--I2C sequence for another slave
- SDA <= 'H', '0' after 30 ns, 'H' after 60 ns,'0' after 110 ns,'0' after 160 ns,'0' after 210 ns,'0' after 260 ns,'0' after 310 ns,'0' after 360 ns,'0' after 410 ns;
+ SDA <= 'H', '0' after 30 ns, 'H' after 60 ns, '0' after 110 ns, '0' after 160 ns, '0' after 210 ns, '0' after 260 ns, '0' after 310 ns, '0' after 360 ns, '0' after 410 ns;
-- start sent address: 0000001, sent rw=0
--the previous is evaluated at time = 0
wait for 450 ns; -- next lines are evaluated 450 ns later
SDA <= 'Z'; -- time for slave to acknowledge
wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','0' after 10 ns, '0' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns; -- sent first data byte
+ SDA <= 'Z', '0' after 10 ns, '0' after 60 ns, 'H' after 110 ns, '0' after 160 ns, 'H' after 210 ns, 'H' after 260 ns, 'H' after 310 ns, '0' after 360 ns; -- sent first data byte
wait for 400 ns;
SDA <= 'Z'; -- time for slave to acknowledge
wait for 50 ns; -- WAIT 1 clk cycle
- SDA <= 'Z','0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns,'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent second data byte
+ SDA <= 'Z', '0' after 10 ns, 'H' after 60 ns, 'H' after 110 ns, '0' after 160 ns, 'H' after 210 ns, '0' after 260 ns, 'H' after 310 ns, 'H' after 360 ns; -- sent second data byte
wait for 400 ns;
SDA <= 'Z'; -- time for slave to nacknowledge
wait for 80 ns; -- WAIT 1.5 clk cycle
diff --git a/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd b/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
index 4c9e5def3024890c445e8b8da1f2ea674fdf18f6..77b6f927d3f04ff334c84607b8a417a1b01f8175 100644
--- a/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
@@ -65,7 +65,7 @@ architecture rtl of mdio_ctlr is
exec_complete : std_logic;
end record;
- signal r , nxt_r : t_reg;
+ signal r, nxt_r : t_reg;
begin
p_comb : process(rst, r, mdio_done)
variable v : t_reg;
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
index 0eabcfe6ead66301f0a9e626b85ca3ab4fcebf96..d87e158536a65b55c7c99d9d59515ebeed215c56 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
@@ -198,8 +198,8 @@ begin
generic map (
g_nof_input => c_nof_mux_streams,
g_sel_ctrl_invert => true,
- g_fifo_size => array_init(0,c_nof_mux_streams), -- no FIFO used but must match g_nof_input
- g_fifo_fill => array_init(0,c_nof_mux_streams) -- no FIFO used but must match g_nof_input
+ g_fifo_size => array_init(0, c_nof_mux_streams), -- no FIFO used but must match g_nof_input
+ g_fifo_fill => array_init(0, c_nof_mux_streams) -- no FIFO used but must match g_nof_input
)
port map (
clk => dp_clk,
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index 239d898990220c5899e0eebf5e454569e68a87e0..813a76c810b79579db1b68dfbc7b33729f287822 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -352,7 +352,7 @@ begin
-- ST
tx_snk_in_arr => dp_fifo_fill_tx_src_out_arr, -- 64 bit data @ 156 MHz
- tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr ,
+ tx_snk_out_arr => dp_fifo_fill_tx_src_in_arr,
rx_src_out_arr => mac_10g_src_out_arr, -- 64 bit data @ 156 MHz
rx_src_in_arr => mac_10g_src_in_arr,
diff --git a/libraries/technology/ddr/sim_ddr.vhd b/libraries/technology/ddr/sim_ddr.vhd
index 5d719ed9d9f770ec3def88939edfe9088297ccf5..87c5148566c123bb1cd6113dd7e9982421fe48bf 100644
--- a/libraries/technology/ddr/sim_ddr.vhd
+++ b/libraries/technology/ddr/sim_ddr.vhd
@@ -130,8 +130,8 @@ begin
sim_clk <= ref_clk;
sim_rst <= ref_rst;
- ctlr_miso.done <= '0' , '1' after 1 ns;
- ctlr_miso.cal_ok <= '0' , '1' after 1 ns;
+ ctlr_miso.done <= '0', '1' after 1 ns;
+ ctlr_miso.cal_ok <= '0', '1' after 1 ns;
ctlr_miso.cal_fail <= '0';
p_mem_access : process(sim_clk)
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index 0fe623e8c3d2707d72a609251024b21b5086d09c..2cdc46f846f984ab206786c8d743814f7906fbf1 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -192,8 +192,8 @@ package tech_ddr_pkg is
afi_reset_n : std_logic;
end record;
- constant c_tech_ddr3_phy_terminationcontrol_x : t_tech_ddr3_phy_terminationcontrol := ((others => 'X'), (others => 'X'),'X','X','X','X','X','X','X', (others => 'X'), 'X', 'X', 'X');
- constant c_tech_ddr3_phy_terminationcontrol_rst : t_tech_ddr3_phy_terminationcontrol := ((others => '0'), (others => '0'),'0','0','0','0','0','0','0', (others => '0'), '0', '0', '0');
+ constant c_tech_ddr3_phy_terminationcontrol_x : t_tech_ddr3_phy_terminationcontrol := ((others => 'X'), (others => 'X'), 'X', 'X', 'X', 'X', 'X', 'X', 'X', (others => 'X'), 'X', 'X', 'X');
+ constant c_tech_ddr3_phy_terminationcontrol_rst : t_tech_ddr3_phy_terminationcontrol := ((others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0', '0', (others => '0'), '0', '0', '0');
constant c_tech_ddr3_phy_in_x : t_tech_ddr3_phy_in := ('X', 'X', 'X');
constant c_tech_ddr4_phy_in_x : t_tech_ddr4_phy_in := ('X', 'X');
diff --git a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
index fc6617c765cf6177599a987ff14b82b243b2e408..4658634dd1844bfc9b53e6ce20277a0ea7119b1f 100644
--- a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
+++ b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
@@ -156,7 +156,7 @@ architecture str of ip_arria10_eth_10g is
constant c_mem_reg_eth10g_adr_w : natural := 1;
constant c_mem_reg_eth10g_dat_w : natural := 32;
constant c_mem_reg_eth10g_nof_data : natural := 1;
- constant c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
+ constant c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w, c_mem_reg_eth10g_dat_w, c_mem_reg_eth10g_nof_data, 'X');
signal reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels - 1 downto 0);
signal reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels - 1 downto 0);
diff --git a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
index 647e77e35d41dd54ac94d3a24f3570e455abb9a0..8137f69ba9439f327a8f03160875db89572a72c8 100644
--- a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
@@ -162,7 +162,7 @@ architecture str of ip_arria10_e1sg_eth_10g is
constant c_mem_reg_eth10g_adr_w : natural := 1;
constant c_mem_reg_eth10g_dat_w : natural := 32;
constant c_mem_reg_eth10g_nof_data : natural := 1;
- constant c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
+ constant c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w, c_mem_reg_eth10g_dat_w, c_mem_reg_eth10g_nof_data, 'X');
signal reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels - 1 downto 0);
signal reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels - 1 downto 0);
diff --git a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
index 9c31185e837f0babb2f7bf4b5f57a1342dc319d2..c85e9cd5ab89cbc814947c164e7befa9bfcec01e 100644
--- a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
@@ -162,7 +162,7 @@ architecture str of ip_arria10_e2sg_eth_10g is
constant c_mem_reg_eth10g_adr_w : natural := 1;
constant c_mem_reg_eth10g_dat_w : natural := 32;
constant c_mem_reg_eth10g_nof_data : natural := 1;
- constant c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
+ constant c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w, c_mem_reg_eth10g_dat_w, c_mem_reg_eth10g_nof_data, 'X');
signal reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels - 1 downto 0);
signal reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels - 1 downto 0);
diff --git a/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd b/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
index 45ca9acdf0dae35089a7dfcbd9176212350b850c..7a9f5079e1aa81a77251a66cfaff10ed2137d936 100644
--- a/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
@@ -159,7 +159,7 @@ architecture str of ip_arria10_e3sge3_eth_10g is
constant c_mem_reg_eth10g_adr_w : natural := 1;
constant c_mem_reg_eth10g_dat_w : natural := 32;
constant c_mem_reg_eth10g_nof_data : natural := 1;
- constant c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
+ constant c_mem_reg_eth10g : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w, c_mem_reg_eth10g_dat_w, c_mem_reg_eth10g_nof_data, 'X');
signal reg_eth10g_mosi_arr : t_mem_mosi_arr(g_nof_channels - 1 downto 0);
signal reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels - 1 downto 0);
diff --git a/libraries/technology/jesd204b/tech_jesd204b_tx.vhd b/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
index e3f634e00f4b7c69b149c126ebdd084897f877cc..70ba75e8538f912f84e8a3f2cdeab371e0cf7068 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
@@ -101,52 +101,52 @@ begin
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : ip_arria10_e1sg_jesd204b_tx
port map(
- csr_cf => csr_cf ,
- csr_cs => csr_cs ,
- csr_f => csr_f ,
- csr_hd => csr_hd ,
- csr_k => csr_k ,
- csr_l => csr_l ,
- csr_lane_powerdown => csr_lane_powerdown ,
- csr_m => csr_m ,
- csr_n => csr_n ,
- csr_np => csr_np ,
- csr_s => csr_s ,
- csr_tx_testmode => csr_tx_testmode ,
- csr_tx_testpattern_a => csr_tx_testpattern_a ,
- csr_tx_testpattern_b => csr_tx_testpattern_b ,
- csr_tx_testpattern_c => csr_tx_testpattern_c ,
- csr_tx_testpattern_d => csr_tx_testpattern_d ,
- dev_sync_n => dev_sync_n ,
- jesd204_tx_avs_chipselect => jesd204_tx_avs_chipselect ,
- jesd204_tx_avs_address => jesd204_tx_avs_address ,
- jesd204_tx_avs_read => jesd204_tx_avs_read ,
- jesd204_tx_avs_readdata => jesd204_tx_avs_readdata ,
+ csr_cf => csr_cf,
+ csr_cs => csr_cs,
+ csr_f => csr_f,
+ csr_hd => csr_hd,
+ csr_k => csr_k,
+ csr_l => csr_l,
+ csr_lane_powerdown => csr_lane_powerdown,
+ csr_m => csr_m,
+ csr_n => csr_n,
+ csr_np => csr_np,
+ csr_s => csr_s,
+ csr_tx_testmode => csr_tx_testmode,
+ csr_tx_testpattern_a => csr_tx_testpattern_a,
+ csr_tx_testpattern_b => csr_tx_testpattern_b,
+ csr_tx_testpattern_c => csr_tx_testpattern_c,
+ csr_tx_testpattern_d => csr_tx_testpattern_d,
+ dev_sync_n => dev_sync_n,
+ jesd204_tx_avs_chipselect => jesd204_tx_avs_chipselect,
+ jesd204_tx_avs_address => jesd204_tx_avs_address,
+ jesd204_tx_avs_read => jesd204_tx_avs_read,
+ jesd204_tx_avs_readdata => jesd204_tx_avs_readdata,
jesd204_tx_avs_waitrequest => jesd204_tx_avs_waitrequest,
- jesd204_tx_avs_write => jesd204_tx_avs_write ,
- jesd204_tx_avs_writedata => jesd204_tx_avs_writedata ,
- jesd204_tx_avs_clk => jesd204_tx_avs_clk ,
- jesd204_tx_avs_rst_n => jesd204_tx_avs_rst_n ,
- jesd204_tx_dlb_data => jesd204_tx_dlb_data ,
- jesd204_tx_dlb_kchar_data => jesd204_tx_dlb_kchar_data ,
- jesd204_tx_frame_error => jesd204_tx_frame_error ,
- jesd204_tx_frame_ready => jesd204_tx_frame_ready ,
- jesd204_tx_int => jesd204_tx_int ,
- jesd204_tx_link_data => jesd204_tx_link_data ,
- jesd204_tx_link_valid => jesd204_tx_link_valid ,
- jesd204_tx_link_ready => jesd204_tx_link_ready ,
- mdev_sync_n => mdev_sync_n ,
- pll_locked => pll_locked ,
- somf => somf ,
- sync_n => sync_n ,
- sysref => sysref ,
- tx_analogreset => tx_analogreset ,
- tx_bonding_clocks => tx_bonding_clocks ,
- tx_cal_busy => tx_cal_busy ,
- tx_digitalreset => tx_digitalreset ,
- tx_serial_data => tx_serial_data ,
- txlink_clk => txlink_clk ,
- txlink_rst_n_reset_n => txlink_rst_n_reset_n ,
+ jesd204_tx_avs_write => jesd204_tx_avs_write,
+ jesd204_tx_avs_writedata => jesd204_tx_avs_writedata,
+ jesd204_tx_avs_clk => jesd204_tx_avs_clk,
+ jesd204_tx_avs_rst_n => jesd204_tx_avs_rst_n,
+ jesd204_tx_dlb_data => jesd204_tx_dlb_data,
+ jesd204_tx_dlb_kchar_data => jesd204_tx_dlb_kchar_data,
+ jesd204_tx_frame_error => jesd204_tx_frame_error,
+ jesd204_tx_frame_ready => jesd204_tx_frame_ready,
+ jesd204_tx_int => jesd204_tx_int,
+ jesd204_tx_link_data => jesd204_tx_link_data,
+ jesd204_tx_link_valid => jesd204_tx_link_valid,
+ jesd204_tx_link_ready => jesd204_tx_link_ready,
+ mdev_sync_n => mdev_sync_n,
+ pll_locked => pll_locked,
+ somf => somf,
+ sync_n => sync_n,
+ sysref => sysref,
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks,
+ tx_cal_busy => tx_cal_busy,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => tx_serial_data,
+ txlink_clk => txlink_clk,
+ txlink_rst_n_reset_n => txlink_rst_n_reset_n,
txphy_clk => txphy_clk
);
end generate;
@@ -154,52 +154,52 @@ begin
gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
u0 : ip_arria10_e2sg_jesd204b_tx
port map(
- csr_cf => csr_cf ,
- csr_cs => csr_cs ,
- csr_f => csr_f ,
- csr_hd => csr_hd ,
- csr_k => csr_k ,
- csr_l => csr_l ,
- csr_lane_powerdown => csr_lane_powerdown ,
- csr_m => csr_m ,
- csr_n => csr_n ,
- csr_np => csr_np ,
- csr_s => csr_s ,
- csr_tx_testmode => csr_tx_testmode ,
- csr_tx_testpattern_a => csr_tx_testpattern_a ,
- csr_tx_testpattern_b => csr_tx_testpattern_b ,
- csr_tx_testpattern_c => csr_tx_testpattern_c ,
- csr_tx_testpattern_d => csr_tx_testpattern_d ,
- dev_sync_n => dev_sync_n ,
- jesd204_tx_avs_chipselect => jesd204_tx_avs_chipselect ,
- jesd204_tx_avs_address => jesd204_tx_avs_address ,
- jesd204_tx_avs_read => jesd204_tx_avs_read ,
- jesd204_tx_avs_readdata => jesd204_tx_avs_readdata ,
+ csr_cf => csr_cf,
+ csr_cs => csr_cs,
+ csr_f => csr_f,
+ csr_hd => csr_hd,
+ csr_k => csr_k,
+ csr_l => csr_l,
+ csr_lane_powerdown => csr_lane_powerdown,
+ csr_m => csr_m,
+ csr_n => csr_n,
+ csr_np => csr_np,
+ csr_s => csr_s,
+ csr_tx_testmode => csr_tx_testmode,
+ csr_tx_testpattern_a => csr_tx_testpattern_a,
+ csr_tx_testpattern_b => csr_tx_testpattern_b,
+ csr_tx_testpattern_c => csr_tx_testpattern_c,
+ csr_tx_testpattern_d => csr_tx_testpattern_d,
+ dev_sync_n => dev_sync_n,
+ jesd204_tx_avs_chipselect => jesd204_tx_avs_chipselect,
+ jesd204_tx_avs_address => jesd204_tx_avs_address,
+ jesd204_tx_avs_read => jesd204_tx_avs_read,
+ jesd204_tx_avs_readdata => jesd204_tx_avs_readdata,
jesd204_tx_avs_waitrequest => jesd204_tx_avs_waitrequest,
- jesd204_tx_avs_write => jesd204_tx_avs_write ,
- jesd204_tx_avs_writedata => jesd204_tx_avs_writedata ,
- jesd204_tx_avs_clk => jesd204_tx_avs_clk ,
- jesd204_tx_avs_rst_n => jesd204_tx_avs_rst_n ,
- jesd204_tx_dlb_data => jesd204_tx_dlb_data ,
- jesd204_tx_dlb_kchar_data => jesd204_tx_dlb_kchar_data ,
- jesd204_tx_frame_error => jesd204_tx_frame_error ,
- jesd204_tx_frame_ready => jesd204_tx_frame_ready ,
- jesd204_tx_int => jesd204_tx_int ,
- jesd204_tx_link_data => jesd204_tx_link_data ,
- jesd204_tx_link_valid => jesd204_tx_link_valid ,
- jesd204_tx_link_ready => jesd204_tx_link_ready ,
- mdev_sync_n => mdev_sync_n ,
- pll_locked => pll_locked ,
- somf => somf ,
- sync_n => sync_n ,
- sysref => sysref ,
- tx_analogreset => tx_analogreset ,
- tx_bonding_clocks => tx_bonding_clocks ,
- tx_cal_busy => tx_cal_busy ,
- tx_digitalreset => tx_digitalreset ,
- tx_serial_data => tx_serial_data ,
- txlink_clk => txlink_clk ,
- txlink_rst_n_reset_n => txlink_rst_n_reset_n ,
+ jesd204_tx_avs_write => jesd204_tx_avs_write,
+ jesd204_tx_avs_writedata => jesd204_tx_avs_writedata,
+ jesd204_tx_avs_clk => jesd204_tx_avs_clk,
+ jesd204_tx_avs_rst_n => jesd204_tx_avs_rst_n,
+ jesd204_tx_dlb_data => jesd204_tx_dlb_data,
+ jesd204_tx_dlb_kchar_data => jesd204_tx_dlb_kchar_data,
+ jesd204_tx_frame_error => jesd204_tx_frame_error,
+ jesd204_tx_frame_ready => jesd204_tx_frame_ready,
+ jesd204_tx_int => jesd204_tx_int,
+ jesd204_tx_link_data => jesd204_tx_link_data,
+ jesd204_tx_link_valid => jesd204_tx_link_valid,
+ jesd204_tx_link_ready => jesd204_tx_link_ready,
+ mdev_sync_n => mdev_sync_n,
+ pll_locked => pll_locked,
+ somf => somf,
+ sync_n => sync_n,
+ sysref => sysref,
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks,
+ tx_cal_busy => tx_cal_busy,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => tx_serial_data,
+ txlink_clk => txlink_clk,
+ txlink_rst_n_reset_n => txlink_rst_n_reset_n,
txphy_clk => txphy_clk
);
end generate;