diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_0.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_0.hex
index d8f6ab3364f009637f19bd46bd285e126570b6be..5edea8e39f6c590d953666a9bfda898073badcdd 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_0.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_0.hex
@@ -1,129 +1,129 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_1.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_1.hex
index da50c33174b95ecb7b86c92bac03f76d38c72169..45ec9087243ad9e3d4c770821d95e891cc941980 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_1.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_1.hex
@@ -1,129 +1,129 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_10.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_10.hex
index 027090fabf4a8f4ec316d682b2235cf7c858c078..9e941da2756970fb7eee230a6c324aa2be6fd13c 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_10.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_10.hex
@@ -1,129 +1,129 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_11.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_11.hex
index 11fc8913ee7d86db6bbc505d9f40671d4067e438..f6f91a212755e11fce90b0c08f5fecf4d517ea58 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_11.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_11.hex
@@ -1,112 +1,112 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_2.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_2.hex
index 0adad86e248395ab11847597d29586d3f60f6638..52c6bf83ef17e1b33c6ddfa56d85ba299bfe381e 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_2.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_2.hex
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_3.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_3.hex
index 1803927d096a6ceab4654dab405b3a1a78194531..05fcfecb6088a91c0db33e7b9b7e9ef18be24e96 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_3.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_3.hex
@@ -1,129 +1,129 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_4.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_4.hex
index 1d4954a472c0b72c786fb22e89fe81c03374d1f7..bf03ea8030993598ac76bb82500dadeb4cc53830 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_4.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_4.hex
@@ -1,129 +1,129 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_5.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_5.hex
index 66d419b13d04390a67abb0da5b986eab5655305b..c5d589edb5727b80e2a71b3527152acbaf70513f 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_5.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_5.hex
@@ -1,129 +1,129 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_6.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_6.hex
index 87647a3da6963c897cc5fee42e35a486053aea8d..61aba45901e9ea13732758c53825be25b4000909 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_6.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_6.hex
@@ -1,121 +1,121 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_7.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_7.hex
index 9941f486333edf146352431473cee5b31051d99d..c574559e78263ca1ae1b1cc116216260312cf28b 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_7.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_7.hex
@@ -1,129 +1,129 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_8.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_8.hex
index c22e6f076aa4f5f76198005cfa4a80cdbbc9461f..f4d72160bb8848d775762cb5c4f7dcc75459b3da 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_8.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_8.hex
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_9.hex b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_9.hex
index 51db9b0c339f3c92c599fa1a5fc582a17985de6d..db53e757576b72c05985ede3b231f14fa24e1d4d 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_9.hex
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/hex/composite_signals_9.hex
@@ -1,129 +1,129 @@
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diff --git a/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd b/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
index 528bb01945d75901c19f017c266615a68ed47bd1..e00e32a71cc3a4641735e289e4c31ad53c802296 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+++ b/applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
@@ -48,21 +48,28 @@ USE bf_lib.bf_pkg.ALL;
-- . The incpoming beamlets (3x 10GbE from fn_beamformer) are distributed among the 8 FPGAs per board; each FPGA correlates
-- 1/8th of the beamlets.
-- Remarks:
+-- . URGENT:
+-- . We need 9b filter coefficients before we can synthesize! --FIXME
+-- . How are we going to (re)map fn_beamformer's 176-word beamlet blocks onto the 128-word blocks wanted by the WPFB? --FIXME
+-- . Other:
+-- . Synthesis incl. mesh terminals went OK but used 96% of the logic resources.
+-- . We need to add data buffers to monitor the incoming 3 (times 4 bf_units) streams (determine which bits are toggling etc). --FIXME
+-- . Keep an eye on the FIXME marks.
ENTITY apertif_unb1_correlator IS
GENERIC (
g_design_name : STRING := "apertif_unb1_correlator";
- g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_use_bg : BOOLEAN := FALSE; -- Overridden (TRUE) by TB but still a valid synthesis option; this replaces the 10GbE input stage with block gens.
+ g_sim : BOOLEAN := FALSE; -- Overridden by TB
+ g_sim_fast : BOOLEAN := TRUE; -- TRUE = fast accumulator model and no inter-channel delay in the correlator output stream.
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
- g_use_dumb_mesh_terminals : BOOLEAN := FALSE;-- Add dumb mesh terminals to the design. Non-functional, for synthesis results only.
- g_offload_bg : BOOLEAN := FALSE;-- Bypass everything; use only a block-gen->dp_offload_tx.
- g_no_dsp : BOOLEAN := FALSE -- True = bypass WPFB, bypass correlator multipliers+accumulators.
- ); -- . Correlator does output correctly sized DP packets.
- PORT ( -- . Used to verify/validate data path from 10GbE receivers to 1GbE offload.
+ g_use_dumb_mesh_terminals : BOOLEAN := FALSE -- Add dumb mesh terminals to the design. Non-functional, for synthesis results only.
+ );
+ PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
@@ -123,9 +130,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
-- Firmware version x.y
CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 2);
-- Enable block generators
- CONSTANT c_use_bg : BOOLEAN := g_sim;
-
- CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, sel_a_b(c_use_bg, 0, 1), 0, 0, 0, 0, 0, 1);
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, sel_a_b(g_use_bg, 0, 1), 0, 0, 0, 0, 0, 1);
CONSTANT c_nof_10GbE_streams : NATURAL := 3; -- The number of 10G input streams
CONSTANT c_nof_bf_modules : NATURAL := c_bf.nof_bf_units; -- We have 4 BF modules here because each sending fn_beamformer design has 4 bf units.
@@ -133,7 +138,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
-- BSN Alignern + FIFO's
CONSTANT c_block_period : NATURAL := 256;
- CONSTANT c_block_size : NATURAL := 176;
+ CONSTANT c_block_size : NATURAL := 176; --FIXME: current fn_beamformer output block size.
CONSTANT c_bsn_align_latency : NATURAL := 3;
CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
@@ -148,10 +153,9 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
CONSTANT c_nof_input_folds : NATURAL := 1;
CONSTANT c_nof_input_streams : NATURAL := c_nof_inputs / pow2(c_nof_input_folds);
CONSTANT c_nof_pre_mult_folds : NATURAL := 1;
- CONSTANT c_complex_data_w : NATURAL := 8;
- CONSTANT c_conjugate : BOOLEAN := TRUE;
+ CONSTANT c_conjugate : BOOLEAN := TRUE; --FIXME: Used for verification/validation (phase shifts) in first stages but should be set to FALSE for final version.
CONSTANT c_nof_channels : NATURAL := 64;
- CONSTANT c_integration_period : NATURAL := 12207; --sel_a_b(g_sim, 0, 12207);
+ CONSTANT c_integration_period : NATURAL := 12207;
CONSTANT c_nof_visibilities : NATURAL := (c_nof_inputs*(c_nof_inputs+1))/2;
-- . Inter Channel Delay:
-- . With no inter channel output delay, channels are output back-to-back, creating a short full valid burst of 64 channels (12.8 Gbps burst, 158Mbps on average).
@@ -160,18 +164,17 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
-- . 8192 channels/sec = 128 * 64 channels * 300 visibilities
-- . No inter channel delay: 128 * (19200 valid cycles + 1543300 invalid cycles =) 1562500 cycles/sec = 200M cycles/sec
-- . With inter channel delay: 128 * 64 channels * (300 valid cycles + 24114 invalid cycles =) 24414 cycles/sec = 199.999.488 cycles/sec (less than 200M so we're fast enough)
- CONSTANT c_inter_channel_delay : NATURAL := sel_a_b(g_sim, 4400, 24114); -- ^^^^^--- 24414= 2*integration period.
- -- 4400=~5.5x faster than 157Mbps = 860Mbps burst for sim (but still 157Mbps on average)
-
+ CONSTANT c_inter_channel_delay : NATURAL := sel_a_b(g_sim, sel_a_b(g_sim_fast, 0, 4400), 24114); -- ^^^^^--- 24414= 2*integration period.
+ -- 4400=~5.5x faster than 157Mbps = 860Mbps burst for sim (but still 157Mbps on average)
-- WPFB
CONSTANT c_wpfb_wb_factor : NATURAL := 1; -- = default 1, wideband factor
CONSTANT c_wpfb_nof_wb_streams : NATURAL := c_nof_input_streams; -- = 1, the number of parallel wideband streams. The fi
CONSTANT c_wpfb_nof_chan : NATURAL := 1; -- = default 0, defines the number of channels (=time-m
CONSTANT c_wpfb_nof_points : NATURAL := 64; -- = 1024, N point FFT
CONSTANT c_wpfb_nof_taps : NATURAL := 8; -- = 8 nof taps n the filter
- CONSTANT c_wpfb_coef_w : NATURAL := 9;
- CONSTANT c_wpfb_in_dat_w : NATURAL := 8; --6; -- = 8, number of input bits
- CONSTANT c_wpfb_out_dat_w : NATURAL := 14; --12; -- = 14, number of output bits: in_dat_w + natural((cei
+ CONSTANT c_wpfb_coef_w : NATURAL := 18; --FIXME: 9b does not work; needs updated coefficient files.
+ CONSTANT c_wpfb_in_dat_w : NATURAL := 8; --FIXME: should be 6b at some point
+ CONSTANT c_wpfb_out_dat_w : NATURAL := 9; --FIXME: Could be wider but is currently 9b to avoid the need for quantization: 9b -> mult -> 18b -> accu -> 32b at the corr output.
CONSTANT c_wpfb_use_separate : BOOLEAN := FALSE; -- = false for complex input, true for two real inputs
CONSTANT c_wpfb_use_reorder : BOOLEAN := FALSE;
@@ -183,8 +186,8 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
CONSTANT c_wpfb_coefs_file_prefix : STRING := "mif/coefs_wide1_p64_t8";
-- Block generator
- CONSTANT c_bg_block_size : NATURAL := 88; --c_nof_channels*pow2(c_nof_input_folds); --TIJDELIJKE TEST. EERST 128, nu 88. Matcht 256->176 zoals huidige beamformeroutput.
- CONSTANT c_bg_gapsize : NATURAL := 40; --0; --TIJDELIJKE TEST. 128-88=gap van 40.
+ CONSTANT c_bg_block_size : NATURAL := c_nof_channels*pow2(c_nof_input_folds); --128 -- Use 88+40(gap)/128 to match current 176/256 beamlet output of fn_beamformer.
+ CONSTANT c_bg_gapsize : NATURAL := 0; --40
-- Indicate the integration period with the sync. In the correlator, the
-- integration period is forced to a minimum of c_nof_visibilities to
@@ -200,15 +203,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
TO_UVEC( c_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
- -- Block generator for visibility offload testing
- CONSTANT c_offload_bg_ctrl : t_diag_block_gen := ('1', -- enable
- '0', -- enable_sync
- TO_UVEC( 300, c_diag_bg_samples_per_packet_w),
- TO_UVEC( 64, c_diag_bg_blocks_per_sync_w),
- TO_UVEC( 24414-300, c_diag_bg_gapsize_w),
- TO_UVEC( 0, c_diag_bg_mem_low_adrs_w),
- TO_UVEC( 0, c_diag_bg_mem_high_adrs_w),
- TO_UVEC( 0, c_diag_bg_bsn_init_w));
+
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_clk : STD_LOGIC;
@@ -296,7 +291,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
- SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_sosi_rst);
SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10GbE_streams-1 DOWNTO 0);
-- BSN Aligner
@@ -321,6 +316,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL wpfb_snk_in_ctrl : t_dp_sosi;
SIGNAL wpfb_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
SIGNAL wpfb_src_out_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
+ SIGNAL correlator_snk_in_arr : t_dp_sosi_arr(c_nof_input_streams-1 DOWNTO 0);
SIGNAL correlator_src_out_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
-- 1GbE Visibility Offload
@@ -344,687 +340,627 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
BEGIN
- gen_no_offload_bg: IF g_offload_bg=FALSE GENERATE
- -----------------------------------------------------------------------------
- -- Block generators
- -----------------------------------------------------------------------------
- gen_block_gen : IF c_use_bg = TRUE GENERATE
- u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
- GENERIC MAP (
- g_nof_streams => c_nof_input_streams,
- g_buf_dat_w => 2*c_complex_data_w,
- g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
- g_file_name_prefix => "hex/composite_signals",
- g_diag_block_gen_rst => c_bg_ctrl
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr => interleaved_arr
- );
- END GENERATE;
+ -----------------------------------------------------------------------------
+ -- Block generators
+ -----------------------------------------------------------------------------
+ gen_block_gen : IF g_use_bg = TRUE GENERATE
+ u_mms_diag_block_gen : ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP (
+ g_nof_streams => c_nof_input_streams,
+ g_buf_dat_w => 2*c_wpfb_out_dat_w,
+ g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
+ g_file_name_prefix => "hex/composite_signals",
+ g_diag_block_gen_rst => c_bg_ctrl
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- gen_10GbE : IF c_use_bg = FALSE GENERATE
- -----------------------------------------------------------------------------
- -- Interface : 10GbE
- -----------------------------------------------------------------------------
- -- Wire together different types
- gen_wires: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
- unb_xaui_tx_arr(i) <= xaui_tx_arr(i);
- xaui_rx_arr(i) <= unb_xaui_rx_arr(i);
- END GENERATE;
-
- u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
- GENERIC MAP (
- g_nof_xaui => c_nof_10GbE_streams
- )
- PORT MAP (
- xaui_tx_arr => unb_xaui_tx_arr,
- xaui_rx_arr => unb_xaui_rx_arr,
-
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL
- );
-
- u_areset_sa_rst : ENTITY common_lib.common_areset
- GENERIC MAP(
- g_rst_level => '1',
- g_delay_len => 4
- )
- PORT MAP(
- clk => SA_CLK,
- in_rst => '0',
- out_rst => sa_rst
- );
-
- u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
- GENERIC MAP(
- g_sim => g_sim,
- g_sim_level => 1,
- g_nof_macs => c_nof_10GbE_streams,
- g_use_mdio => TRUE
- )
-
- PORT MAP (
- -- Transceiver PLL reference clock
- tr_ref_clk_156 => SA_CLK,
- tr_ref_rst_156 => sa_rst,
-
- -- Calibration & reconfig clock
- cal_rec_clk => mm_clk,
-
- -- MM interface
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
-
- xaui_mosi => reg_tr_xaui_mosi,
- xaui_miso => reg_tr_xaui_miso,
-
- mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams-1 DOWNTO 0),
- mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams-1 DOWNTO 0),
-
- -- DP interface
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- src_out_arr => dp_offload_rx_snk_in_arr,
- src_in_arr => dp_offload_rx_snk_out_arr,
-
- -- Serial XAUI IO
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr,
-
- -- MDIO interface
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
- );
-
- -----------------------------------------------------------------------------
- -- RX: dp_offload_rx
- -----------------------------------------------------------------------------
- u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
- GENERIC MAP (
- g_nof_streams => c_nof_10GbE_streams,
- g_data_w => c_xgmii_data_w,
- g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
- g_remove_crc => TRUE,
- g_crc_nof_words => 1
- )
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
-
- snk_in_arr => dp_offload_rx_snk_in_arr,
- snk_out_arr => dp_offload_rx_snk_out_arr,
-
- src_out_arr => dp_offload_rx_src_out_arr,
- src_in_arr => dp_offload_rx_src_in_arr,
-
- hdr_fields_out_arr => hdr_fields_out_arr
- );
-
- gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
- dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
- dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
-
- dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
- dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
- dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
- dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
- dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- RX: BSN alignment
- -----------------------------------------------------------------------------
- gen_dp_fifo_fill: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
- u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
- GENERIC MAP (
- g_data_w => c_xgmii_data_w,
- g_bsn_w => c_dp_stream_bsn_w,
- g_channel_w => c_dp_stream_channel_w,
- g_use_bsn => TRUE,
- g_use_channel => TRUE,
- g_use_error => TRUE,
- g_use_sync => TRUE,
- g_fifo_fill => c_dp_fifo_fill,
- g_fifo_size => c_dp_fifo_size
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => dp_offload_rx_src_in_arr(i),
- snk_in => dp_offload_rx_restored_src_out_arr(i),
-
- src_in => dp_fifo_fill_src_in_arr(i),
- src_out => dp_fifo_fill_src_out_arr(i)
- );
- END GENERATE;
-
- u_dp_bsn_align : ENTITY dp_lib.dp_bsn_align
- GENERIC MAP (
- g_block_size => c_block_size,
- g_block_period => c_block_period,
- g_nof_input => c_nof_10GbE_streams,
- g_xoff_timeout => c_bsn_align_xoff_timeout,
- g_sop_timeout => c_bsn_align_sop_timeout,
- g_bsn_latency => c_bsn_align_latency,
- g_bsn_request_pipeline => 2
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out_arr => dp_fifo_fill_src_in_arr,
- snk_in_arr => dp_fifo_fill_src_out_arr,
-
- src_in_arr => dp_bsn_align_src_in_arr,
- src_out_arr => dp_bsn_align_src_out_arr
- );
-
- -----------------------------------------------------------------------------
- -- Rewire: for each input stream, extract the 4 concatenated BF output streams
- -- and assign them to the interleaved array.
- -----------------------------------------------------------------------------
- p_extract_bf_streams : PROCESS(dp_bsn_align_src_out_arr)
- BEGIN
- FOR i IN 0 TO c_nof_10GbE_streams-1 LOOP
- FOR j IN 0 TO c_nof_bf_modules-1 LOOP
- interleaved_arr(i*c_nof_bf_modules + j) <= dp_bsn_align_src_out_arr(i); -- SOSI ctrl
- interleaved_arr(i*c_nof_bf_modules + j).data <= (OTHERS=>'0');
- interleaved_arr(i*c_nof_bf_modules + j).im <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w));
- interleaved_arr(i*c_nof_bf_modules + j).re <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w-1 DOWNTO c_nof_complex*j*c_compl_dat_w));
- END LOOP;
- END LOOP;
- END PROCESS;
- END GENERATE;
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ out_sosi_arr => interleaved_arr
+ );
+ END GENERATE;
+ gen_10GbE : IF g_use_bg = FALSE GENERATE
-----------------------------------------------------------------------------
- -- RX: BSN monitors at several stages in the stream
+ -- Interface : 10GbE
-----------------------------------------------------------------------------
- u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+ -- Wire together different types
+ gen_wires: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ unb_xaui_tx_arr(i) <= xaui_tx_arr(i);
+ xaui_rx_arr(i) <= unb_xaui_rx_arr(i);
+ END GENERATE;
+
+ u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
GENERIC MAP (
- g_nof_streams => 5,
- g_log_first_bsn => TRUE
+ g_nof_xaui => c_nof_10GbE_streams
)
PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- reg_mosi => reg_bsn_monitor_mosi,
- reg_miso => reg_bsn_monitor_miso,
+ xaui_tx_arr => unb_xaui_tx_arr,
+ xaui_rx_arr => unb_xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
+
+ u_areset_sa_rst : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ PORT MAP(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_streams,
+ g_use_mdio => TRUE
+ )
+
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- in_siso_arr => dp_bsn_monitor_in_siso_arr,
- in_sosi_arr => dp_bsn_monitor_in_sosi_arr
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+
+ -- Serial XAUI IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ -- MDIO interface
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
);
-
- -- 0) Monitor the BSN-aligned output
- dp_bsn_monitor_in_sosi_arr(0) <= dp_bsn_align_src_out_arr(0);
- dp_bsn_monitor_in_siso_arr(0) <= dp_bsn_align_src_in_arr(0);
- -- 1) Monitor the rewired/reinterleaver stage output / WPFB input
- dp_bsn_monitor_in_sosi_arr(1) <= wpfb_snk_in_arr(0);
- dp_bsn_monitor_in_siso_arr(1) <= c_dp_siso_rdy;
- -- 2) Monitor the WPFB output / correlator input
- dp_bsn_monitor_in_sosi_arr(2) <= wpfb_src_out_arr(0);
- dp_bsn_monitor_in_siso_arr(2) <= c_dp_siso_rdy;
- -- 3) Monitor the correlator output / visibility offload input
- dp_bsn_monitor_in_sosi_arr(3) <= correlator_src_out_arr(0);
- dp_bsn_monitor_in_siso_arr(3) <= c_dp_siso_rdy;
- -- 3) Monitor the correlator output / visibility offload input
- dp_bsn_monitor_in_sosi_arr(4) <= dp_offload_tx_src_out_arr(0);
- dp_bsn_monitor_in_siso_arr(4) <= dp_offload_tx_src_in_arr(0);
-
+
-----------------------------------------------------------------------------
- -- Beamlet routing from 10GbE inputs T2..T0 to unfolder correlator inputs 23..0: ***48 VISIBILITY VERSION***
- -- . Beamlet indices between parentheses ()
- -- . Stream indices between brackets []
- --
- -- T2(B6,B7)--[11]--deinter-[1]--(T2,B7)--[23] [23]--(T2,B7)--[1]-reinter-[11]--(T1,B7),(T2,B7)--unfold-[1]--(T2,B7)-->[23]
- -- \[0]--(T2,B6)--[22] [15]--(T1,B7)--[0]/ \[0]--(T1,B7)-->[22]
- -- (B4,B5)--[10]--deinter-[1]--(T2,B5)--[21] [07]--(T0,B7)--[1]-reinter-[10]--(T2,B6),(T0,B7)--unfold-[1]--(T0,B7)-->[21]
- -- \[0]--(T2,B4)--[20] [22]--(T2,B6)--[0]/ \[0]--(T2,B6)-->[20]
- -- (B2,B3)--[09]--deinter-[1]--(T2,B3)--[19] [14]--(T1,B6)--[1]-reinter-[09]--(T0,B6),(T1,B6)--unfold-[1]--(T1,B6)-->[19]
- -- \[0]--(T2,B2)--[18] [06]--(T0,B6)--[0]/ \[0]--(T0,B6)-->[18]
- -- (B0,B1)--[08]--deinter-[1]--(T2,B1)--[17] [21]--(T2,B5)--[1]-reinter-[08]--(T1,B5),(T2,B5)--unfold-[1]--(T2,B5)-->[17]
- -- \[0]--(T2,B0)--[16] [13]--(T1,B5)--[0]/ \[0]--(T1,B5)-->[16]
- -- T1(B6,B7)--[07]--deinter-[1]--(T1,B7)--[15] [05]--(T0,B5)--[1]-reinter-[07]--(T2,B4),(T0,B5)--unfold-[1]--(T0,B5)-->[15]
- -- \[0]--(T1,B6)--[14] [20]--(T2,B4)--[0]/ \[0]--(T2,B4)-->[14]
- -- (B4,B5)--[06]--deinter-[1]--(T1,B5)--[13] [12]--(T1,B4)--[1]-reinter-[06]--(T0,B4),(T1,B4)--unfold-[1]--(T1,B4)-->[13]
- -- \[0]--(T1,B4)--[12]\/[04]--(T0,B4)--[0]/ \[0]--(T0,B4)-->[12]
- -- (B2,B3)--[05]--deinter-[1]--(T1,B3)--[11]/\[19]--(T2,B3)--[1]-reinter-[05]--(T1,B3),(T2,B3)--unfold-[1]--(T2,B3)-->[11]
- -- \[0]--(T1,B2)--[10] [11]--(T1,B3)--[0]/ \[0]--(T1,B3)-->[10]
- -- (B0,B1)--[04]--deinter-[1]--(T1,B1)--[09] [03]--(T0,B3)--[1]-reinter-[04]--(T2,B2),(T0,B3)--unfold-[1]--(T0,B3)-->[09]
- -- \[0]--(T1,B0)--[08] [18]--(T2,B2)--[0]/ \[0]--(T2,B2)-->[08]
- -- T0(B6,B7)--[03]--deinter-[1]--(T0,B7)--[07] [10]--(T1,B2)--[1]-reinter-[03]--(T0,B2),(T1,B2)--unfold-[1]--(T1,B2)-->[07]
- -- \[0]--(T0,B6)--[06] [02]--(T0,B2)--[0]/ \[0]--(T0,B2)-->[06]
- -- (B4,B5)--[02]--deinter-[1]--(T0,B5)--[05] [17]--(T2,B1)--[1]-reinter-[02]--(T1,B1),(T2,B1)--unfold-[1]--(T2,B1)-->[05]
- -- \[0]--(T0,B4)--[04] [09]--(T1,B1)--[0]/ \[0]--(T1,B1)-->[04]
- -- (B2,B3)--[01]--deinter-[1]--(T0,B3)--[03] [01]--(T0,B1)--[1]-reinter-[01]--(T2,B0),(T0,B1)--unfold-[1]--(T0,B1)-->[03]
- -- \[0]--(T0,B2)--[02] [16]--(T2,B0)--[0]/ \[0]--(T2,B0)-->[02]
- -- (B0,B1)--[00]--deinter-[1]--(T0,B1)--[01] [08]--(T1,B0)--[1]-reinter-[00]--(T0,B0),(T1,B0)--unfold-[1]--(T1,B0)-->[01]
- -- \[0]--(T0,B0)--[00] [00]--(T0,B0)--[0]/ \[0]--(T0,B0)-->[00]
- -- ^ ^ ^ ^ ^
- -- interleaved_arr | reinterleave_in_arr | Unfolded correlator inputs
- -- deinterleaved_arr reinterleave_out_arr,wpfb_out_arr,correlator_snk_in_arr
- -----------------------------------------------------------------------------
-
+ -- RX: dp_offload_rx
-----------------------------------------------------------------------------
- -- Beamlet routing from 10GbE inputs T2..T0 to unfolder correlator inputs 23..0: ***FINAL MESH VERSION***
- -- . Beamlet indices between parentheses () The exact indices depend on FPGA index--FIXME
- -- . Stream indices between brackets [] / To do: Also BSN align these 24 streams --FIXME
- -- [<-----------/------------>] /
- -- T2(B6,B7)--[11]--deinter-[1]--(T2,B7)--[23]--MESH_TX[3][2] MESH_RX[3][2]--[23]--(T23,B0)--[1]-reinter-[11]--(T22,B0),(T23,B0)--unfold-[1]--(T23,B0)-->[23]
- -- \[0]--(T2,B6)--[22]--MESH_TX[3][1] MESH_RX[3][1]--[22]--(T22,B0)--[0]/ \[0]--(T22,B0)-->[22]
- -- (B4,B5)--[10]--deinter-[1]--(T2,B5)--[21]--MESH_TX[3][0] MESH_RX[3][0]--[21]--(T21,B0)--[1]-reinter-[10]--(T20,B0),(T21,B0)--unfold-[1]--(T21,B0)-->[21]
- -- \[0]--(T2,B4)--[20]--MESH_TX[2][2] MESH_RX[2][2]--[20]--(T10,B0)--[0]/ \[0]--(T20,B0)-->[20]
- -- (B2,B3)--[09]--deinter-[1]--(T2,B3)--[19]--MESH_TX[2][1] MESH_RX[2][1]--[19]--(T19,B0)--[1]-reinter-[09]--(T18,B0),(T19,B0)--unfold-[1]--(T19,B0)-->[19]
- -- \[0]--(T2,B2)--[18]--MESH_TX[2][0] MESH_RX[2][0]--[18]--(T18,B0)--[0]/ \[0]--(T18,B0)-->[18]
- -- (B0,B1)--[08]--deinter-[1]--(T2,B1)--[17]--MESH_TX[1][2] MESH_RX[1][2]--[17]--(T17,B0)--[1]-reinter-[08]--(T16,B0),(T17,B0)--unfold-[1]--(T17,B0)-->[17]
- -- \[0]--(T2,B0)--[16]--MESH_TX[1][1] MESH_RX[1][1]--[16]--(T16,B0)--[0]/ \[0]--(T16,B0)-->[16]
- -- T1(B6,B7)--[07]--deinter-[1]--(T1,B7)--[15]--MESH_TX[1][0] MESH_RX[1][0]--[15]--(T15,B0)--[1]-reinter-[07]--(T14,B0),(T15,B0)--unfold-[1]--(T15,B0)-->[15]
- -- \[0]--(T1,B6)--[14]--MESH_TX[0][2] MESH_RX[0][2]--[14]--(T14,B0)--[0]/ \[0]--(T14,B0)-->[14]
- -- (B4,B5)--[06]--deinter-[1]--(T1,B5)--[13]--MESH_TX[0][1] MESH_RX[0][1]--[13]--(T13,B0)--[1]-reinter-[06]--(T12,B0),(T13,B0)--unfold-[1]--(T13,B0)-->[13]
- -- \[0]--(T1,B4)--[12]--MESH_TX[0][0]\/MESH_RX[0][0]--[12]--(T12,B0)--[0]/ \[0]--(T12,B0)-->[12]
- -- (B2,B3)--[05]--deinter-[1]--(T1,B3)--[11]--MESH_TX[3][2]/\MESH_RX[3][2]--[11]--(T11,B0)--[1]-reinter-[05]--(T10,B0),(T11,B0)--unfold-[1]--(T11,B0)-->[11]
- -- \[0]--(T1,B2)--[10]--MESH_TX[3][1] MESH_RX[3][1]--[10]--(T10,B0)--[0]/ \[0]--(T10,B0)-->[10]
- -- (B0,B1)--[04]--deinter-[1]--(T1,B1)--[09]--MESH_TX[3][0] MESH_RX[3][0]--[09]--(T09,B0)--[1]-reinter-[04]--(T08,B0),(T09,B0)--unfold-[1]--(T09,B0)-->[09]
- -- \[0]--(T1,B0)--[08]--MESH_TX[2][2] MESH_RX[2][2]--[08]--(T08,B0)--[0]/ \[0]--(T08,B0)-->[08]
- -- T0(B6,B7)--[03]--deinter-[1]--(T0,B7)--[07]--MESH_TX[2][1] MESH_RX[2][1]--[07]--(T07,B0)--[1]-reinter-[03]--(T06,B0),(T07,B0)--unfold-[1]--(T07,B0)-->[07]
- -- \[0]--(T0,B6)--[06]--MESH_TX[2][0] MESH_RX[2][0]--[06]--(T06,B0)--[0]/ \[0]--(T06,B0)-->[06]
- -- (B4,B5)--[02]--deinter-[1]--(T0,B5)--[05]--MESH_TX[1][2] MESH_RX[1][2]--[05]--(T05,B0)--[1]-reinter-[02]--(T04,B0),(T05,B0)--unfold-[1]--(T05,B0)-->[05]
- -- \[0]--(T0,B4)--[04]--MESH_TX[1][1] MESH_RX[1][1]--[04]--(T04,B0)--[0]/ \[0]--(T04,B0)-->[04]
- -- (B2,B3)--[01]--deinter-[1]--(T0,B3)--[03]--MESH_TX[1][0] MESH_RX[1][0]--[03]--(T03,B0)--[1]-reinter-[01]--(T02,B0),(T03,B0)--unfold-[1]--(T03,B0)-->[03]
- -- \[0]--(T0,B2)--[02]--MESH_TX[0][2] MESH_RX[0][2]--[02]--(T02,B0)--[0]/ \[0]--(T02,B0)-->[02]
- -- (B0,B1)--[00]--deinter-[1]--(T0,B1)--[01]--MESH_TX[0][1] MESH_RX[0][1]--[01]--(T01,B0)--[1]-reinter-[00]--(T00,B0),(T01,B0)--unfold-[1]--(T01,B0)-->[01] -- Note that we're also TX'ing the locally RX'ed telescope inputs T0..T2 as
- -- \[0]--(T0,B0)--[00]--MESH_TX[0][0] MESH_RX[0][0]--[00]--(T00,B0)--[0]/ \[0]--(T00,B0)-->[00] -- it appears to be easier with the re-interleaving and BSN alignment.
- -- ^ ^ ^ ^ ^
- -- interleaved_arr | mesh_tx_snk_in_2arr | Unfolded correlator inputs
- -- deinterleaved_arr reinterleave_out_arr,wpfb_out_arr,correlator_snk_in_arr
- -----------------------------------------------------------------------------
-
- gen_deinterleave_snk_in_arr: IF g_use_dumb_mesh_terminals=FALSE GENERATE
- dp_pipeline_snk_in <= interleaved_arr(0);
- dp_deinterleave_snk_in_arr <= interleaved_arr;
+ u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
+ GENERIC MAP (
+ g_nof_streams => c_nof_10GbE_streams,
+ g_data_w => c_xgmii_data_w,
+ g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
+ g_remove_crc => TRUE,
+ g_crc_nof_words => 1
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
+
+ gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
+ dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
+
+ dp_offload_rx_restored_src_out_arr(i).data <= dp_offload_rx_src_out_arr(i).data;
+ dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
END GENERATE;
- gen_deinterleave : FOR i IN 0 TO c_nof_10GbE_streams*c_nof_bf_modules-1 GENERATE
- u_deinterleave : ENTITY dp_lib.dp_deinterleave
+ -----------------------------------------------------------------------------
+ -- RX: BSN alignment
+ -----------------------------------------------------------------------------
+ gen_dp_fifo_fill: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
GENERIC MAP (
- g_nof_out => 2,
- g_block_size => 1,
- g_dat_w => c_nof_complex*c_wpfb_in_dat_w,
- g_use_ctrl => FALSE,
- g_align_out => TRUE,
- g_use_complex => c_use_complex
+ g_data_w => c_xgmii_data_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_use_bsn => TRUE,
+ g_use_channel => TRUE,
+ g_use_error => TRUE,
+ g_use_sync => TRUE,
+ g_fifo_fill => c_dp_fifo_fill,
+ g_fifo_size => c_dp_fifo_size
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_deinterleave_snk_in_arr(i),
- src_out_arr => deinterleaved_arr(2*i+1 DOWNTO 2*i)
- );
- END GENERATE;
-
- p_reorder_array : PROCESS(deinterleaved_arr)
- BEGIN
- FOR i IN 0 TO 2*c_nof_bf_modules-1 LOOP
- FOR j IN 0 TO c_nof_10GbE_streams-1 LOOP
- reinterleave_in_arr(i*c_nof_10GbE_streams + j) <= deinterleaved_arr(j*2*c_nof_bf_modules + i);
- END LOOP;
- END LOOP;
- END PROCESS;
+ rst => dp_rst,
+ clk => dp_clk,
- gen_reinterleave : FOR i IN 0 TO c_nof_10GbE_streams*c_nof_bf_modules-1 GENERATE
- u_reinterleave : ENTITY dp_lib.dp_reinterleave
- GENERIC MAP (
- g_nof_in => 2,
- g_deint_block_size => 1,
- g_nof_out => 1,
- g_inter_block_size => 1,
- g_use_ctrl => FALSE,
- g_dat_w => c_nof_complex*c_wpfb_in_dat_w,
- g_use_complex => c_use_complex,
- g_align_out => TRUE
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- snk_in_arr => reinterleave_in_arr(2*i+1 DOWNTO 2*i),
- src_out_arr => reinterleave_out_arr(i DOWNTO i)
+ snk_out => dp_offload_rx_src_in_arr(i),
+ snk_in => dp_offload_rx_restored_src_out_arr(i),
+
+ src_in => dp_fifo_fill_src_in_arr(i),
+ src_out => dp_fifo_fill_src_out_arr(i)
);
END GENERATE;
- u_st_ctrl_pipe : ENTITY dp_lib.dp_pipeline
- GENERIC MAP(
- g_pipeline => 3 -- 0 for wires, > 0 for registers,
+ u_dp_bsn_align : ENTITY dp_lib.dp_bsn_align
+ GENERIC MAP (
+ g_block_size => c_block_size,
+ g_block_period => c_block_period,
+ g_nof_input => c_nof_10GbE_streams,
+ g_xoff_timeout => c_bsn_align_xoff_timeout,
+ g_sop_timeout => c_bsn_align_sop_timeout,
+ g_bsn_latency => c_bsn_align_latency,
+ g_bsn_request_pipeline => 2
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- -- ST sink
- snk_in => dp_pipeline_snk_in, --interleaved_arr(0),
- -- ST source
- src_out => wpfb_snk_in_ctrl
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out_arr => dp_fifo_fill_src_in_arr,
+ snk_in_arr => dp_fifo_fill_src_out_arr,
+
+ src_in_arr => dp_bsn_align_src_in_arr,
+ src_out_arr => dp_bsn_align_src_out_arr
);
-
- p_add_st_ctrl : PROCESS(reinterleave_out_arr, wpfb_snk_in_ctrl)
+
+ -----------------------------------------------------------------------------
+ -- Rewire: for each input stream, extract the 4 concatenated BF output streams
+ -- and assign them to the interleaved array.
+ -----------------------------------------------------------------------------
+ p_extract_bf_streams : PROCESS(dp_bsn_align_src_out_arr)
BEGIN
- FOR i IN 0 TO c_nof_input_streams-1 LOOP
--- wpfb_snk_in_arr(i) <= wpfb_snk_in_ctrl; -- SOSI ctrl
--- wpfb_snk_in_arr(i).data <= reinterleave_out_arr(i).data;
--- wpfb_snk_in_arr(i).im <= reinterleave_out_arr(i).im;
--- wpfb_snk_in_arr(i).re <= reinterleave_out_arr(i).re;
- dp_block_gen_snk_in_arr(i) <= wpfb_snk_in_ctrl; -- SOSI ctrl
- dp_block_gen_snk_in_arr(i).data <= reinterleave_out_arr(i).data;
- dp_block_gen_snk_in_arr(i).im <= reinterleave_out_arr(i).im;
- dp_block_gen_snk_in_arr(i).re <= reinterleave_out_arr(i).re;
+ FOR i IN 0 TO c_nof_10GbE_streams-1 LOOP
+ FOR j IN 0 TO c_nof_bf_modules-1 LOOP
+ interleaved_arr(i*c_nof_bf_modules + j) <= dp_bsn_align_src_out_arr(i); -- SOSI ctrl
+ interleaved_arr(i*c_nof_bf_modules + j).data <= (OTHERS=>'0');
+ interleaved_arr(i*c_nof_bf_modules + j).im <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w+c_compl_dat_w DOWNTO c_nof_complex*j*c_compl_dat_w+c_compl_dat_w));
+ interleaved_arr(i*c_nof_bf_modules + j).re <= RESIZE_DP_DSP_DATA(dp_bsn_align_src_out_arr(i).data( (c_nof_complex*j+1)*c_compl_dat_w-1 DOWNTO c_nof_complex*j*c_compl_dat_w));
+ END LOOP;
END LOOP;
END PROCESS;
-
- -----------------------------------------------------------------------------
- -- Preliminary mesh terminals to explore resource usage of final design:
- -- . With g_use_dumb_mesh_terminals=TRUE, the mesh terminals:
- -- . Transmit 21/24 beamlets to the other 7 FPGAs via the mesh.
- -- . Receive 21/24 beamlets from the other FPGAs via the mesh.
- -- . These are DUMB terminals because this will synthesize but not
- -- functionally work because the lack of alignment and proper rewiring.
- -- . FOR EXPLORATION OF RESOURCE UTILIZATION ONLY!
- -----------------------------------------------------------------------------
- gen_terminals_mesh : if g_use_dumb_mesh_terminals=TRUE GENERATE
-
- mesh_tx_snk_in_2arr(0)(0) <= interleaved_arr(0);
- mesh_tx_snk_in_2arr(0)(1) <= interleaved_arr(1);
- mesh_tx_snk_in_2arr(0)(2) <= interleaved_arr(2);
- mesh_tx_snk_in_2arr(1)(0) <= interleaved_arr(3);
- mesh_tx_snk_in_2arr(1)(1) <= interleaved_arr(4);
- mesh_tx_snk_in_2arr(1)(2) <= interleaved_arr(5);
- mesh_tx_snk_in_2arr(2)(0) <= interleaved_arr(6);
- mesh_tx_snk_in_2arr(2)(1) <= interleaved_arr(7);
- mesh_tx_snk_in_2arr(2)(2) <= interleaved_arr(8);
- mesh_tx_snk_in_2arr(3)(0) <= interleaved_arr(9);
- mesh_tx_snk_in_2arr(3)(1) <= interleaved_arr(10);
- mesh_tx_snk_in_2arr(3)(2) <= interleaved_arr(11);
-
- dp_deinterleave_snk_in_arr(0) <= mesh_rx_src_out_2arr(0)(0);
- dp_deinterleave_snk_in_arr(1) <= mesh_rx_src_out_2arr(0)(1);
- dp_deinterleave_snk_in_arr(2) <= mesh_rx_src_out_2arr(0)(2);
- dp_deinterleave_snk_in_arr(3) <= mesh_rx_src_out_2arr(1)(0);
- dp_deinterleave_snk_in_arr(4) <= mesh_rx_src_out_2arr(1)(1);
- dp_deinterleave_snk_in_arr(5) <= mesh_rx_src_out_2arr(1)(2);
- dp_deinterleave_snk_in_arr(6) <= mesh_rx_src_out_2arr(2)(0);
- dp_deinterleave_snk_in_arr(7) <= mesh_rx_src_out_2arr(2)(1);
- dp_deinterleave_snk_in_arr(8) <= mesh_rx_src_out_2arr(2)(2);
- dp_deinterleave_snk_in_arr(9) <= mesh_rx_src_out_2arr(3)(0);
- dp_deinterleave_snk_in_arr(10) <= mesh_rx_src_out_2arr(3)(1);
- dp_deinterleave_snk_in_arr(11) <= mesh_rx_src_out_2arr(3)(2);
-
- dp_pipeline_snk_in <= mesh_rx_src_out_2arr(0)(0);
-
- u_terminals_mesh : ENTITY unb1_board_lib.unb1_board_terminals_mesh
- GENERIC MAP (
- g_sim => g_sim,
- g_sim_level => 1,
- -- System
- g_node_type => e_fn,
- g_nof_bus => 4,
- -- User
- g_usr_use_complex => c_use_complex,
- g_usr_data_w => 16,
- g_usr_frame_len => 176,
- g_usr_nof_streams => 4, -- Actually 3 but has to be 4 to prevent errors.
- -- Phy
- g_phy_nof_serial => 3,
- g_phy_gx_mbps => 6250,
- g_phy_rx_fifo_size => 176,
- g_phy_ena_reorder => TRUE,
- -- Tx
- g_use_tx => TRUE,
- g_tx_input_use_fifo => TRUE,
- -- Rx
- g_use_rx => TRUE,
- g_rx_output_use_fifo => TRUE,
- g_rx_output_fifo_size => 176,
- g_rx_output_fifo_fill => 0,
- g_rx_timeout_w => 0,
- -- Monitoring
- g_mon_select => 0
- )
- PORT MAP (
- chip_id => ID(2 DOWNTO 0),
-
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
--- dp_sync => dp_pps,
- tr_clk => SB_clk,
- cal_clk => mm_clk,
-
- -- Received beamlets from other nodes
--- rx_usr_siso_2arr => mesh_rx_src_in_2arr,
- rx_usr_sosi_2arr => mesh_rx_src_out_2arr,
-
- -- Beamlets transmitted to other nodes
--- tx_usr_siso_2arr => mesh_tx_snk_out_2arr,
- tx_usr_sosi_2arr => mesh_tx_snk_in_2arr,
-
- -- Mesh interface level (4 nodes)(4 lanes)
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr
-
- -- MM Control
--- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
--- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
--- reg_diagnostics_mosi => reg_diagnostics_mosi,
--- reg_diagnostics_miso => reg_diagnostics_miso,
--- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
--- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
- );
+ END GENERATE;
- u_unb1_board_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
- PORT MAP (
- tx_serial_2arr => tx_serial_2arr,
- rx_serial_2arr => rx_serial_2arr,
-
- -- Serial I/O
- FN_BN_0_TX => FN_BN_0_TX,
- FN_BN_0_RX => FN_BN_0_RX,
- FN_BN_1_TX => FN_BN_1_TX,
- FN_BN_1_RX => FN_BN_1_RX,
- FN_BN_2_TX => FN_BN_2_TX,
- FN_BN_2_RX => FN_BN_2_RX,
- FN_BN_3_TX => FN_BN_3_TX,
- FN_BN_3_RX => FN_BN_3_RX
- );
+ -----------------------------------------------------------------------------
+ -- RX: BSN monitors at several stages in the stream
+ -----------------------------------------------------------------------------
+ u_dp_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+ GENERIC MAP (
+ g_nof_streams => 5,
+ g_log_first_bsn => TRUE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_bsn_monitor_mosi,
+ reg_miso => reg_bsn_monitor_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ in_siso_arr => dp_bsn_monitor_in_siso_arr,
+ in_sosi_arr => dp_bsn_monitor_in_sosi_arr
+ );
- END GENERATE;
+ -- 0) Monitor the BSN-aligned output
+ dp_bsn_monitor_in_sosi_arr(0) <= dp_bsn_align_src_out_arr(0);
+ dp_bsn_monitor_in_siso_arr(0) <= dp_bsn_align_src_in_arr(0);
+ -- 1) Monitor the rewired/reinterleaver stage output / WPFB input
+ dp_bsn_monitor_in_sosi_arr(1) <= wpfb_snk_in_arr(0);
+ dp_bsn_monitor_in_siso_arr(1) <= c_dp_siso_rdy;
+ -- 2) Monitor the WPFB output / correlator input
+ dp_bsn_monitor_in_sosi_arr(2) <= wpfb_src_out_arr(0);
+ dp_bsn_monitor_in_siso_arr(2) <= c_dp_siso_rdy;
+ -- 3) Monitor the correlator output / visibility offload input
+ dp_bsn_monitor_in_sosi_arr(3) <= correlator_src_out_arr(0);
+ dp_bsn_monitor_in_siso_arr(3) <= c_dp_siso_rdy;
+ -- 3) Monitor the correlator output / visibility offload input
+ dp_bsn_monitor_in_sosi_arr(4) <= dp_offload_tx_src_out_arr(0);
+ dp_bsn_monitor_in_siso_arr(4) <= dp_offload_tx_src_in_arr(0);
- -----------------------------------------------------------------------------
- -- WPFB
- -----------------------------------------------------------------------------
- gen_wpfb_unit : IF g_no_dsp=FALSE GENERATE
-
- -- Workaround: WPFB unit wants 128-word blocks; we're getting 176 word blocks (current fn_beamformer output without transpose).
- -- => Re-tag the blocks with 128-word SOP and EOP.
- gen_dp_block_gen : FOR i IN 0 TO c_nof_input_streams-1 GENERATE
- u_dp_block_gen: ENTITY dp_lib.dp_block_gen
- GENERIC MAP (
- g_use_src_in => FALSE,
- g_nof_data => 128,
- g_nof_blk_per_sync => 1 -- don't care
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_block_gen_snk_in_arr(i),
-
- src_out => dp_block_gen_src_out_arr(i)
- );
- END GENERATE;
- -- Workaround: WPFB unit seems to want uninterrupted blocks.
- gen_dp_fifo_fill: FOR i IN 0 TO c_nof_input_streams-1 GENERATE
- u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
- GENERIC MAP (
- g_data_w => 2*c_wpfb_in_dat_w,
- g_use_complex => TRUE,
- g_use_bsn => FALSE, --FIXME
- g_use_channel => FALSE,
- g_use_error => FALSE,
- g_use_sync => FALSE,
- g_fifo_fill => 128,
- g_fifo_size => 2*128 + 20 -- Two blocks plus extra margin
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => dp_block_gen_src_out_arr(i),
-
- src_in => c_dp_siso_rdy,
- src_out => wpfb_snk_in_arr(i)
- );
- END GENERATE;
-
- u_wpfb_unit : ENTITY wpfb_lib.wpfb_unit
- GENERIC MAP(
- g_wpfb => c_wpfb,
- g_stats_ena => FALSE,
- g_use_bg => FALSE,
- g_file_index_arr => array_init(0, 128, 1),
- g_coefs_file_prefix => c_wpfb_coefs_file_prefix
- )
- PORT MAP(
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- ram_fil_coefs_mosi => ram_fil_coefs_mosi,
- ram_fil_coefs_miso => ram_fil_coefs_miso,
- ram_st_sst_mosi => c_mem_mosi_rst,
- ram_st_sst_miso => OPEN,
- reg_bg_ctrl_mosi => c_mem_mosi_rst,
- reg_bg_ctrl_miso => OPEN,
- ram_bg_data_mosi => c_mem_mosi_rst,
- ram_bg_data_miso => OPEN,
- in_sosi_arr => wpfb_snk_in_arr,
- out_sosi_arr => wpfb_src_out_arr
- );
- END GENERATE;
-
- no_wpfb_unit : IF g_no_dsp=TRUE GENERATE
- wpfb_src_out_arr <= wpfb_snk_in_arr;
- END GENERATE;
-
- -----------------------------------------------------------------------------
- -- Stream recorder to record the WPFB output stream to a file
- -----------------------------------------------------------------------------
- u_dp_stream_rec_play_wpfb_unit : ENTITY dp_lib.dp_stream_rec_play
+ -----------------------------------------------------------------------------
+ -- Beamlet routing from 10GbE inputs T2..T0 to unfolder correlator inputs 23..0: ***48 VISIBILITY VERSION***
+ -- . Beamlet indices between parentheses ()
+ -- . Stream indices between brackets []
+ --
+ -- T2(B6,B7)--[11]--deinter-[1]--(T2,B7)--[23] [23]--(T2,B7)--[1]-reinter-[11]--(T1,B7),(T2,B7)--unfold-[1]--(T2,B7)-->[23]
+ -- \[0]--(T2,B6)--[22] [15]--(T1,B7)--[0]/ \[0]--(T1,B7)-->[22]
+ -- (B4,B5)--[10]--deinter-[1]--(T2,B5)--[21] [07]--(T0,B7)--[1]-reinter-[10]--(T2,B6),(T0,B7)--unfold-[1]--(T0,B7)-->[21]
+ -- \[0]--(T2,B4)--[20] [22]--(T2,B6)--[0]/ \[0]--(T2,B6)-->[20]
+ -- (B2,B3)--[09]--deinter-[1]--(T2,B3)--[19] [14]--(T1,B6)--[1]-reinter-[09]--(T0,B6),(T1,B6)--unfold-[1]--(T1,B6)-->[19]
+ -- \[0]--(T2,B2)--[18] [06]--(T0,B6)--[0]/ \[0]--(T0,B6)-->[18]
+ -- (B0,B1)--[08]--deinter-[1]--(T2,B1)--[17] [21]--(T2,B5)--[1]-reinter-[08]--(T1,B5),(T2,B5)--unfold-[1]--(T2,B5)-->[17]
+ -- \[0]--(T2,B0)--[16] [13]--(T1,B5)--[0]/ \[0]--(T1,B5)-->[16]
+ -- T1(B6,B7)--[07]--deinter-[1]--(T1,B7)--[15] [05]--(T0,B5)--[1]-reinter-[07]--(T2,B4),(T0,B5)--unfold-[1]--(T0,B5)-->[15]
+ -- \[0]--(T1,B6)--[14] [20]--(T2,B4)--[0]/ \[0]--(T2,B4)-->[14]
+ -- (B4,B5)--[06]--deinter-[1]--(T1,B5)--[13] [12]--(T1,B4)--[1]-reinter-[06]--(T0,B4),(T1,B4)--unfold-[1]--(T1,B4)-->[13]
+ -- \[0]--(T1,B4)--[12]\/[04]--(T0,B4)--[0]/ \[0]--(T0,B4)-->[12]
+ -- (B2,B3)--[05]--deinter-[1]--(T1,B3)--[11]/\[19]--(T2,B3)--[1]-reinter-[05]--(T1,B3),(T2,B3)--unfold-[1]--(T2,B3)-->[11]
+ -- \[0]--(T1,B2)--[10] [11]--(T1,B3)--[0]/ \[0]--(T1,B3)-->[10]
+ -- (B0,B1)--[04]--deinter-[1]--(T1,B1)--[09] [03]--(T0,B3)--[1]-reinter-[04]--(T2,B2),(T0,B3)--unfold-[1]--(T0,B3)-->[09]
+ -- \[0]--(T1,B0)--[08] [18]--(T2,B2)--[0]/ \[0]--(T2,B2)-->[08]
+ -- T0(B6,B7)--[03]--deinter-[1]--(T0,B7)--[07] [10]--(T1,B2)--[1]-reinter-[03]--(T0,B2),(T1,B2)--unfold-[1]--(T1,B2)-->[07]
+ -- \[0]--(T0,B6)--[06] [02]--(T0,B2)--[0]/ \[0]--(T0,B2)-->[06]
+ -- (B4,B5)--[02]--deinter-[1]--(T0,B5)--[05] [17]--(T2,B1)--[1]-reinter-[02]--(T1,B1),(T2,B1)--unfold-[1]--(T2,B1)-->[05]
+ -- \[0]--(T0,B4)--[04] [09]--(T1,B1)--[0]/ \[0]--(T1,B1)-->[04]
+ -- (B2,B3)--[01]--deinter-[1]--(T0,B3)--[03] [01]--(T0,B1)--[1]-reinter-[01]--(T2,B0),(T0,B1)--unfold-[1]--(T0,B1)-->[03]
+ -- \[0]--(T0,B2)--[02] [16]--(T2,B0)--[0]/ \[0]--(T2,B0)-->[02]
+ -- (B0,B1)--[00]--deinter-[1]--(T0,B1)--[01] [08]--(T1,B0)--[1]-reinter-[00]--(T0,B0),(T1,B0)--unfold-[1]--(T1,B0)-->[01]
+ -- \[0]--(T0,B0)--[00] [00]--(T0,B0)--[0]/ \[0]--(T0,B0)-->[00]
+ -- ^ ^ ^ ^ ^
+ -- interleaved_arr | reinterleave_in_arr | Unfolded correlator inputs
+ -- deinterleaved_arr reinterleave_out_arr,wpfb_out_arr,correlator_snk_in_arr
+ -----------------------------------------------------------------------------
+
+ -----------------------------------------------------------------------------
+ -- Beamlet routing from 10GbE inputs T2..T0 to unfolder correlator inputs 23..0: ***FINAL MESH VERSION***
+ -- . Beamlet indices between parentheses () The exact indices depend on FPGA index--FIXME
+ -- . Stream indices between brackets [] / To do: Also BSN align these 24 streams --FIXME
+ -- [<-----------/------------>] /
+ -- T2(B6,B7)--[11]--deinter-[1]--(T2,B7)--[23]--MESH_TX[3][2] MESH_RX[3][2]--[23]--(T23,B0)--[1]-reinter-[11]--(T22,B0),(T23,B0)--unfold-[1]--(T23,B0)-->[23]
+ -- \[0]--(T2,B6)--[22]--MESH_TX[3][1] MESH_RX[3][1]--[22]--(T22,B0)--[0]/ \[0]--(T22,B0)-->[22]
+ -- (B4,B5)--[10]--deinter-[1]--(T2,B5)--[21]--MESH_TX[3][0] MESH_RX[3][0]--[21]--(T21,B0)--[1]-reinter-[10]--(T20,B0),(T21,B0)--unfold-[1]--(T21,B0)-->[21]
+ -- \[0]--(T2,B4)--[20]--MESH_TX[2][2] MESH_RX[2][2]--[20]--(T10,B0)--[0]/ \[0]--(T20,B0)-->[20]
+ -- (B2,B3)--[09]--deinter-[1]--(T2,B3)--[19]--MESH_TX[2][1] MESH_RX[2][1]--[19]--(T19,B0)--[1]-reinter-[09]--(T18,B0),(T19,B0)--unfold-[1]--(T19,B0)-->[19]
+ -- \[0]--(T2,B2)--[18]--MESH_TX[2][0] MESH_RX[2][0]--[18]--(T18,B0)--[0]/ \[0]--(T18,B0)-->[18]
+ -- (B0,B1)--[08]--deinter-[1]--(T2,B1)--[17]--MESH_TX[1][2] MESH_RX[1][2]--[17]--(T17,B0)--[1]-reinter-[08]--(T16,B0),(T17,B0)--unfold-[1]--(T17,B0)-->[17]
+ -- \[0]--(T2,B0)--[16]--MESH_TX[1][1] MESH_RX[1][1]--[16]--(T16,B0)--[0]/ \[0]--(T16,B0)-->[16]
+ -- T1(B6,B7)--[07]--deinter-[1]--(T1,B7)--[15]--MESH_TX[1][0] MESH_RX[1][0]--[15]--(T15,B0)--[1]-reinter-[07]--(T14,B0),(T15,B0)--unfold-[1]--(T15,B0)-->[15]
+ -- \[0]--(T1,B6)--[14]--MESH_TX[0][2] MESH_RX[0][2]--[14]--(T14,B0)--[0]/ \[0]--(T14,B0)-->[14]
+ -- (B4,B5)--[06]--deinter-[1]--(T1,B5)--[13]--MESH_TX[0][1] MESH_RX[0][1]--[13]--(T13,B0)--[1]-reinter-[06]--(T12,B0),(T13,B0)--unfold-[1]--(T13,B0)-->[13]
+ -- \[0]--(T1,B4)--[12]--MESH_TX[0][0]\/MESH_RX[0][0]--[12]--(T12,B0)--[0]/ \[0]--(T12,B0)-->[12]
+ -- (B2,B3)--[05]--deinter-[1]--(T1,B3)--[11]--MESH_TX[3][2]/\MESH_RX[3][2]--[11]--(T11,B0)--[1]-reinter-[05]--(T10,B0),(T11,B0)--unfold-[1]--(T11,B0)-->[11]
+ -- \[0]--(T1,B2)--[10]--MESH_TX[3][1] MESH_RX[3][1]--[10]--(T10,B0)--[0]/ \[0]--(T10,B0)-->[10]
+ -- (B0,B1)--[04]--deinter-[1]--(T1,B1)--[09]--MESH_TX[3][0] MESH_RX[3][0]--[09]--(T09,B0)--[1]-reinter-[04]--(T08,B0),(T09,B0)--unfold-[1]--(T09,B0)-->[09]
+ -- \[0]--(T1,B0)--[08]--MESH_TX[2][2] MESH_RX[2][2]--[08]--(T08,B0)--[0]/ \[0]--(T08,B0)-->[08]
+ -- T0(B6,B7)--[03]--deinter-[1]--(T0,B7)--[07]--MESH_TX[2][1] MESH_RX[2][1]--[07]--(T07,B0)--[1]-reinter-[03]--(T06,B0),(T07,B0)--unfold-[1]--(T07,B0)-->[07]
+ -- \[0]--(T0,B6)--[06]--MESH_TX[2][0] MESH_RX[2][0]--[06]--(T06,B0)--[0]/ \[0]--(T06,B0)-->[06]
+ -- (B4,B5)--[02]--deinter-[1]--(T0,B5)--[05]--MESH_TX[1][2] MESH_RX[1][2]--[05]--(T05,B0)--[1]-reinter-[02]--(T04,B0),(T05,B0)--unfold-[1]--(T05,B0)-->[05]
+ -- \[0]--(T0,B4)--[04]--MESH_TX[1][1] MESH_RX[1][1]--[04]--(T04,B0)--[0]/ \[0]--(T04,B0)-->[04]
+ -- (B2,B3)--[01]--deinter-[1]--(T0,B3)--[03]--MESH_TX[1][0] MESH_RX[1][0]--[03]--(T03,B0)--[1]-reinter-[01]--(T02,B0),(T03,B0)--unfold-[1]--(T03,B0)-->[03]
+ -- \[0]--(T0,B2)--[02]--MESH_TX[0][2] MESH_RX[0][2]--[02]--(T02,B0)--[0]/ \[0]--(T02,B0)-->[02]
+ -- (B0,B1)--[00]--deinter-[1]--(T0,B1)--[01]--MESH_TX[0][1] MESH_RX[0][1]--[01]--(T01,B0)--[1]-reinter-[00]--(T00,B0),(T01,B0)--unfold-[1]--(T01,B0)-->[01] -- Note that we're also TX'ing the locally RX'ed telescope inputs T0..T2 as
+ -- \[0]--(T0,B0)--[00]--MESH_TX[0][0] MESH_RX[0][0]--[00]--(T00,B0)--[0]/ \[0]--(T00,B0)-->[00] -- it appears to be easier with the re-interleaving and BSN alignment.
+ -- ^ ^ ^ ^ ^
+ -- interleaved_arr | mesh_tx_snk_in_2arr | Unfolded correlator inputs
+ -- deinterleaved_arr reinterleave_out_arr,wpfb_out_arr,correlator_snk_in_arr
+ -----------------------------------------------------------------------------
+
+ gen_deinterleave_snk_in_arr: IF g_use_dumb_mesh_terminals=FALSE GENERATE
+ dp_pipeline_snk_in <= interleaved_arr(0);
+ dp_deinterleave_snk_in_arr <= interleaved_arr;
+ END GENERATE;
+
+ gen_deinterleave : FOR i IN 0 TO c_nof_10GbE_streams*c_nof_bf_modules-1 GENERATE
+ u_deinterleave : ENTITY dp_lib.dp_deinterleave
GENERIC MAP (
- g_sim => TRUE,
- g_pass_through => FALSE,
- g_rec_not_play => TRUE,
- g_rec_play_file => "../../../applications/apertif/designs/apertif_unb1_correlator/tb/rec/wpfb_src_out_arr0.rec",
- g_record_invalid => FALSE
+ g_nof_out => 2,
+ g_block_size => 1,
+ g_dat_w => c_nof_complex*c_wpfb_in_dat_w,
+ g_use_ctrl => FALSE,
+ g_align_out => TRUE,
+ g_use_complex => c_use_complex
)
PORT MAP (
- dp_clk => dp_clk,
- snk_in => wpfb_src_out_arr(0),
- snk_out => OPEN,
- src_out => OPEN,
- src_in => c_dp_siso_rdy
- );
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_deinterleave_snk_in_arr(i),
+ src_out_arr => deinterleaved_arr(2*i+1 DOWNTO 2*i)
+ );
+ END GENERATE;
+
+ p_reorder_array : PROCESS(deinterleaved_arr)
+ BEGIN
+ FOR i IN 0 TO 2*c_nof_bf_modules-1 LOOP
+ FOR j IN 0 TO c_nof_10GbE_streams-1 LOOP
+ reinterleave_in_arr(i*c_nof_10GbE_streams + j) <= deinterleaved_arr(j*2*c_nof_bf_modules + i);
+ END LOOP;
+ END LOOP;
+ END PROCESS;
- -----------------------------------------------------------------------------
- -- Correlator
- -----------------------------------------------------------------------------
- u_correlator : ENTITY correlator_lib.correlator
+ gen_reinterleave : FOR i IN 0 TO c_nof_10GbE_streams*c_nof_bf_modules-1 GENERATE
+ u_reinterleave : ENTITY dp_lib.dp_reinterleave
GENERIC MAP (
- g_nof_input_streams => c_nof_input_streams,
- g_input_unfold_factor => c_nof_input_folds,
- g_nof_pre_mult_folds => c_nof_pre_mult_folds,
- g_data_w => 14, --c_complex_data_w,
- g_conjugate => c_conjugate,
- g_nof_channels => c_nof_channels,
- g_integration_period => c_integration_period,
- g_inter_channel_delay => c_inter_channel_delay,
- g_sim_fast_acc_model => FALSE,
- g_no_dsp => g_no_dsp
+ g_nof_in => 2,
+ g_deint_block_size => 1,
+ g_nof_out => 1,
+ g_inter_block_size => 1,
+ g_use_ctrl => FALSE,
+ g_dat_w => c_nof_complex*c_wpfb_in_dat_w,
+ g_use_complex => c_use_complex,
+ g_align_out => TRUE
)
PORT MAP (
- clk => dp_clk,
rst => dp_rst,
-
- snk_in_arr => wpfb_src_out_arr,
- src_out_arr => correlator_src_out_arr
+ clk => dp_clk,
+ snk_in_arr => reinterleave_in_arr(2*i+1 DOWNTO 2*i),
+ src_out_arr => reinterleave_out_arr(i DOWNTO i)
);
-
- -----------------------------------------------------------------------------
- -- Wire complex fields into data field
- -- . Real & imag. Real part is at the MS end so is put on the (1GbE) line first.
- -----------------------------------------------------------------------------
- p_wires_complex : PROCESS(correlator_src_out_arr)
- BEGIN
- dp_fifo_dc_mixed_widths_snk_in <= correlator_src_out_arr(0);
- dp_fifo_dc_mixed_widths_snk_in.data(64-1 DOWNTO 0) <= correlator_src_out_arr(0).re(64/2-1 DOWNTO 0) & correlator_src_out_arr(0).im(64/2-1 DOWNTO 0);
- END PROCESS;
-
END GENERATE;
+
+ u_st_ctrl_pipe : ENTITY dp_lib.dp_pipeline
+ GENERIC MAP(
+ g_pipeline => 3 -- 0 for wires, > 0 for registers,
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ -- ST sink
+ snk_in => dp_pipeline_snk_in, --interleaved_arr(0),
+ -- ST source
+ src_out => wpfb_snk_in_ctrl
+ );
+
+ p_add_st_ctrl : PROCESS(reinterleave_out_arr, wpfb_snk_in_ctrl)
+ BEGIN
+ FOR i IN 0 TO c_nof_input_streams-1 LOOP
+ wpfb_snk_in_arr(i) <= wpfb_snk_in_ctrl; -- SOSI ctrl
+ wpfb_snk_in_arr(i).data <= reinterleave_out_arr(i).data;
+ wpfb_snk_in_arr(i).im <= reinterleave_out_arr(i).im;
+ wpfb_snk_in_arr(i).re <= reinterleave_out_arr(i).re;
+ END LOOP;
+ END PROCESS;
-----------------------------------------------------------------------------
- -- Block generator in counter mode feeding dp_offload_tx
+ -- Preliminary mesh terminals to explore resource usage of final design:
+ -- . With g_use_dumb_mesh_terminals=TRUE, the mesh terminals:
+ -- . Transmit 21/24 beamlets to the other 7 FPGAs via the mesh.
+ -- . Receive 21/24 beamlets from the other FPGAs via the mesh.
+ -- . These are DUMB terminals because this will synthesize but not
+ -- functionally work because the lack of alignment and proper rewiring.
+ -- . FOR EXPLORATION OF RESOURCE UTILIZATION ONLY!
-----------------------------------------------------------------------------
- gen_mms_diag_block_gen_offload : IF g_offload_bg = TRUE GENERATE
- u_mms_diag_block_gen_offload : ENTITY diag_lib.mms_diag_block_gen
+ gen_terminals_mesh : if g_use_dumb_mesh_terminals=TRUE GENERATE
+ mesh_tx_snk_in_2arr(0)(0) <= interleaved_arr(0);
+ mesh_tx_snk_in_2arr(0)(1) <= interleaved_arr(1);
+ mesh_tx_snk_in_2arr(0)(2) <= interleaved_arr(2);
+ mesh_tx_snk_in_2arr(1)(0) <= interleaved_arr(3);
+ mesh_tx_snk_in_2arr(1)(1) <= interleaved_arr(4);
+ mesh_tx_snk_in_2arr(1)(2) <= interleaved_arr(5);
+ mesh_tx_snk_in_2arr(2)(0) <= interleaved_arr(6);
+ mesh_tx_snk_in_2arr(2)(1) <= interleaved_arr(7);
+ mesh_tx_snk_in_2arr(2)(2) <= interleaved_arr(8);
+ mesh_tx_snk_in_2arr(3)(0) <= interleaved_arr(9);
+ mesh_tx_snk_in_2arr(3)(1) <= interleaved_arr(10);
+ mesh_tx_snk_in_2arr(3)(2) <= interleaved_arr(11);
+
+ dp_deinterleave_snk_in_arr(0) <= mesh_rx_src_out_2arr(0)(0);
+ dp_deinterleave_snk_in_arr(1) <= mesh_rx_src_out_2arr(0)(1);
+ dp_deinterleave_snk_in_arr(2) <= mesh_rx_src_out_2arr(0)(2);
+ dp_deinterleave_snk_in_arr(3) <= mesh_rx_src_out_2arr(1)(0);
+ dp_deinterleave_snk_in_arr(4) <= mesh_rx_src_out_2arr(1)(1);
+ dp_deinterleave_snk_in_arr(5) <= mesh_rx_src_out_2arr(1)(2);
+ dp_deinterleave_snk_in_arr(6) <= mesh_rx_src_out_2arr(2)(0);
+ dp_deinterleave_snk_in_arr(7) <= mesh_rx_src_out_2arr(2)(1);
+ dp_deinterleave_snk_in_arr(8) <= mesh_rx_src_out_2arr(2)(2);
+ dp_deinterleave_snk_in_arr(9) <= mesh_rx_src_out_2arr(3)(0);
+ dp_deinterleave_snk_in_arr(10) <= mesh_rx_src_out_2arr(3)(1);
+ dp_deinterleave_snk_in_arr(11) <= mesh_rx_src_out_2arr(3)(2);
+
+ dp_pipeline_snk_in <= mesh_rx_src_out_2arr(0)(0);
+
+ u_terminals_mesh : ENTITY unb1_board_lib.unb1_board_terminals_mesh
GENERIC MAP (
- g_nof_streams => 1,
- g_use_tx_seq => TRUE,
- g_use_bg_buffer_ram => FALSE,
- g_buf_dat_w => 64,
- g_seq_dat_w => 64,
- g_diag_block_gen_rst => c_offload_bg_ctrl
+ g_sim => g_sim,
+ g_sim_level => 1,
+ -- System
+ g_node_type => e_fn,
+ g_nof_bus => 4,
+ -- User
+ g_usr_use_complex => c_use_complex,
+ g_usr_data_w => 16,
+ g_usr_frame_len => 176, --FIXME: current fn_beamformer output. Mismatch with expected (by WPFB) back-to-back 128 word blocks.
+ g_usr_nof_streams => 4, -- Actually 3 but has to be 4 to prevent errors.
+ -- Phy
+ g_phy_nof_serial => 3,
+ g_phy_gx_mbps => 6250,
+ g_phy_rx_fifo_size => 176,
+ g_phy_ena_reorder => TRUE,
+ -- Tx
+ g_use_tx => TRUE,
+ g_tx_input_use_fifo => TRUE,
+ -- Rx
+ g_use_rx => TRUE,
+ g_rx_output_use_fifo => TRUE,
+ g_rx_output_fifo_size => 176, --FIXME: current fn_beamformer output. Mismatch with expected (by WPFB) back-to-back 128 word blocks.
+ g_rx_output_fifo_fill => 0,
+ g_rx_timeout_w => 0,
+ -- Monitoring
+ g_mon_select => 0
)
PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- out_sosi_arr(0) => dp_fifo_dc_mixed_widths_snk_in
+ chip_id => ID(2 DOWNTO 0),
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+-- dp_sync => dp_pps,
+ tr_clk => SB_clk,
+ cal_clk => mm_clk,
+
+ -- Received beamlets from other nodes
+-- rx_usr_siso_2arr => mesh_rx_src_in_2arr,
+ rx_usr_sosi_2arr => mesh_rx_src_out_2arr,
+
+ -- Beamlets transmitted to other nodes
+-- tx_usr_siso_2arr => mesh_tx_snk_out_2arr,
+ tx_usr_sosi_2arr => mesh_tx_snk_in_2arr,
+
+ -- Mesh interface level (4 nodes)(4 lanes)
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr
+
+ -- MM Control
+-- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+-- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+-- reg_diagnostics_mosi => reg_diagnostics_mosi,
+-- reg_diagnostics_miso => reg_diagnostics_miso,
+-- ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
+-- ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
+ );
+
+ u_unb1_board_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
+ PORT MAP (
+ tx_serial_2arr => tx_serial_2arr,
+ rx_serial_2arr => rx_serial_2arr,
+
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
);
+ END GENERATE; -- g_use_dumb_mesh_terminals
+
+ -----------------------------------------------------------------------------
+ -- WPFB
+ -----------------------------------------------------------------------------
+ u_wpfb_unit : ENTITY wpfb_lib.wpfb_unit
+ GENERIC MAP(
+ g_wpfb => c_wpfb,
+ g_stats_ena => FALSE,
+ g_use_bg => FALSE,
+ g_file_index_arr => array_init(0, 128, 1),
+ g_coefs_file_prefix => c_wpfb_coefs_file_prefix
+ )
+ PORT MAP(
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ ram_fil_coefs_mosi => ram_fil_coefs_mosi,
+ ram_fil_coefs_miso => ram_fil_coefs_miso,
+ ram_st_sst_mosi => c_mem_mosi_rst,
+ ram_st_sst_miso => OPEN,
+ reg_bg_ctrl_mosi => c_mem_mosi_rst,
+ reg_bg_ctrl_miso => OPEN,
+ ram_bg_data_mosi => c_mem_mosi_rst,
+ ram_bg_data_miso => OPEN,
+ in_sosi_arr => wpfb_snk_in_arr,
+ out_sosi_arr => wpfb_src_out_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- Workaround for simulation: the first WPFB output block is not usable! --FIXME
+ -- Forward only blocks with BSN 5+
+ -----------------------------------------------------------------------------
+ gen_bsn_filter : IF g_sim = TRUE GENERATE
+ p_bsn_filter : PROCESS(wpfb_snk_in_arr)
+ BEGIN
+ correlator_snk_in_arr <= (OTHERS=>c_dp_sosi_rst);
+ IF TO_UINT(wpfb_src_out_arr(0).bsn)>=5 THEN
+ correlator_snk_in_arr <= wpfb_src_out_arr;
+ END IF;
+ END PROCESS;
+ END GENERATE;
+
+ gen_connect : IF g_sim = FALSE GENERATE
+ correlator_snk_in_arr <= wpfb_src_out_arr;
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- Stream recorder to record the WPFB output stream to a file
+ -----------------------------------------------------------------------------
+ u_dp_stream_rec_play_wpfb_unit : ENTITY dp_lib.dp_stream_rec_play
+ GENERIC MAP (
+ g_sim => TRUE,
+ g_pass_through => FALSE,
+ g_rec_not_play => TRUE,
+ g_rec_play_file => "../../../applications/apertif/designs/apertif_unb1_correlator/tb/rec/wpfb_src_out_arr0.rec",
+ g_record_invalid => FALSE
+ )
+ PORT MAP (
+ dp_clk => dp_clk,
+ snk_in => wpfb_src_out_arr(0),
+ snk_out => OPEN,
+ src_out => OPEN,
+ src_in => c_dp_siso_rdy
+ );
+
+ -----------------------------------------------------------------------------
+ -- Correlator
+ -----------------------------------------------------------------------------
+ u_correlator : ENTITY correlator_lib.correlator
+ GENERIC MAP (
+ g_nof_input_streams => c_nof_input_streams,
+ g_input_unfold_factor => c_nof_input_folds,
+ g_nof_pre_mult_folds => c_nof_pre_mult_folds,
+ g_data_w => c_wpfb_out_dat_w,
+ g_conjugate => c_conjugate,
+ g_nof_channels => c_nof_channels,
+ g_integration_period => c_integration_period,
+ g_inter_channel_delay => c_inter_channel_delay,
+ g_sim_fast_acc_model => g_sim_fast
+ )
+ PORT MAP (
+ clk => dp_clk,
+ rst => dp_rst,
+
+ snk_in_arr => correlator_snk_in_arr,
+ src_out_arr => correlator_src_out_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- Wire complex fields into data field
+ -- . Real & imag. Real part is at the MS end so is put on the (1GbE) line first.
+ -- . For fast simulation, we output all channels back-to-back and write them to
+ -- a file (dp_stream_rec_play). In that case we don't want to use (and overload)
+ -- the visibility offload stage.
+ -----------------------------------------------------------------------------
+ gen_wires_complex : IF g_sim=FALSE or g_sim_fast=FALSE GENERATE
+ p_wires_complex : PROCESS(correlator_src_out_arr)
+ BEGIN
+ dp_fifo_dc_mixed_widths_snk_in <= correlator_src_out_arr(0);
+ dp_fifo_dc_mixed_widths_snk_in.data(64-1 DOWNTO 0) <= correlator_src_out_arr(0).re(64/2-1 DOWNTO 0) & correlator_src_out_arr(0).im(64/2-1 DOWNTO 0);
+ END PROCESS;
END GENERATE;
-----------------------------------------------------------------------------
@@ -1076,21 +1012,23 @@ BEGIN
-- Stream recorder to record the correlator output stream to a file
-- . The data buffer can only take snapshots.
-----------------------------------------------------------------------------
- u_dp_stream_rec_play_correlator : ENTITY dp_lib.dp_stream_rec_play
- GENERIC MAP (
- g_sim => TRUE,
- g_pass_through => FALSE,
- g_rec_not_play => TRUE,
- g_rec_play_file => "../../../applications/apertif/designs/apertif_unb1_correlator/tb/rec/correlator_src_out_arr0.rec",
- g_record_invalid => FALSE
- )
- PORT MAP (
- dp_clk => dp_clk,
- snk_in => correlator_src_out_arr(0),
- snk_out => OPEN,
- src_out => OPEN,
- src_in => c_dp_siso_rdy
- );
+ gen_dp_stream_rec_play_correlator : IF g_sim=TRUE GENERATE
+ u_dp_stream_rec_play_correlator : ENTITY dp_lib.dp_stream_rec_play
+ GENERIC MAP (
+ g_sim => TRUE,
+ g_pass_through => FALSE,
+ g_rec_not_play => TRUE,
+ g_rec_play_file => "../../../applications/apertif/designs/apertif_unb1_correlator/tb/rec/correlator_src_out_arr0.rec",
+ g_record_invalid => FALSE
+ )
+ PORT MAP (
+ dp_clk => dp_clk,
+ snk_in => correlator_src_out_arr(0),
+ snk_out => OPEN,
+ src_out => OPEN,
+ src_in =>