From 8fde0254ab6d3f707df5b2ee7605bc0a421fc88b Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 26 Mar 2015 07:23:31 +0000
Subject: [PATCH] Read back BG settings after it has been enabled, to check
that BG enable is recognized in the dp_clk domain.
---
applications/unb1_reorder/tb/python/tc_unb1_reorder.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/applications/unb1_reorder/tb/python/tc_unb1_reorder.py b/applications/unb1_reorder/tb/python/tc_unb1_reorder.py
index fb8df72ff9..8792209388 100644
--- a/applications/unb1_reorder/tb/python/tc_unb1_reorder.py
+++ b/applications/unb1_reorder/tb/python/tc_unb1_reorder.py
@@ -163,9 +163,6 @@ if __name__ == "__main__":
# Write setting for the block generator:
bg.write_block_gen_settings(samplesPerPacket=c_frame_size, blocksPerSync=g_nof_blocks, gapSize=c_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
- # Read back the setting for the block generator:
- bg.read_block_gen_settings()
-
# Write the stimuli to the block generator and enable the block generator
if c_write_block_gen == True:
for i in range(c_bg_nof_streams):
@@ -185,6 +182,9 @@ if __name__ == "__main__":
# Enable the blockgenerator
bg.write_enable()
+ # Read back the setting for the block generator to check that the BG enable has reached the dp_clk domain.
+ bg.read_block_gen_settings()
+
# Wait until the DDR3 model is initialized.
if tc.sim == True:
do_until_gt(io.simIO.getSimTime, ms_retry=1000, val=110000, s_timeout=13600) # 110000
--
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