diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
index 8857119f97f65eb7d8f28db300a5fa1e060c2a50..73a7e8b70e384fdaf79d4170010427073a69853b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
@@ -69,6 +69,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+ CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
@@ -76,16 +77,16 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
- CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_block_per_sync : NATURAL := 7; -- use short interval to speed up simulation
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
- CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
+ CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value, due to WG rounding
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
-- WG
- CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_bsn_start_wg : NATURAL := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT c_ampl_sp_0 : NATURAL := c_sdp_FS_adc/2; -- = 0.5 * FS, so in number of lsb
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
@@ -107,6 +108,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
SIGNAL tb_clk : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+ SIGNAL pps_rst : STD_LOGIC := '1';
+ SIGNAL gen_pps : STD_LOGIC := '0';
+
-- WG
SIGNAL dbg_c_exp_wg_power_sp_0 : REAL := c_exp_wg_power_sp_0;
SIGNAL sp_samples : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0);
@@ -116,9 +120,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_adc IS
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
- SIGNAL pps : STD_LOGIC := '0';
SIGNAL ext_pps : STD_LOGIC := '0';
- SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
@@ -161,9 +163,9 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
- jesd204b_sysref <= pps;
- ext_pps <= pps;
+ proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, gen_pps);
+ jesd204b_sysref <= gen_pps;
+ ext_pps <= gen_pps;
------------------------------------------------------------------------------
-- DUT
@@ -181,7 +183,7 @@ BEGIN
PORT MAP (
-- GENERAL
CLK => ext_clk,
- PPS => pps,
+ PPS => ext_pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
@@ -230,15 +232,17 @@ BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
- proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+
+ -- Release PPS pulser, to get first PPS now and to start BSN source
+ WAIT FOR 1 us;
+ pps_rst <= '0';
----------------------------------------------------------------------------
-- Enable WG
@@ -265,9 +269,11 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ ----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
+ ----------------------------------------------------------------------------
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync*2, -- this is the wait until condition
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index 13c10090a51a778b667f3f99b32412fa1b07edad..cb7a197ecec74c7e8ca28de2c24cba95f84afb87 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -375,9 +375,13 @@ BEGIN
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
- u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ -- Must use exact g_mm_rd_latency = 1 instead of default 2, because JESD204B IP forces rddata = 0 after it has been read
+ u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
PORT MAP(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+ u_mm_file_pio_jesd_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
+ PORT MAP(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+
u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
index 1b2814376d6cc37507ad76435846f6dbf15fbdd2..ae6e4816942e867c8ed21c7f6dcf59681e4a9987 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
@@ -9,10 +9,11 @@ hdl_lib_technology = ip_arria10_e2sg
test_bench_files =
tb_lofar2_unb2c_sdp_station_adc.vhd
+ tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
regression_test_vhdl =
tb_lofar2_unb2c_sdp_station_adc.vhd
-
+ tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
[modelsim_project_file]
modelsim_copy_files =
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
index 70cc4fc665584d56982fa5701e5e15ce49fc0492..db6251833565e9b480a8b46f26f5dd77b74bcff6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
@@ -69,6 +69,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0);
+ CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
@@ -76,16 +77,16 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
CONSTANT c_tb_clk_period : TIME := 100 ps; -- use fast tb_clk to speed up M&C
- CONSTANT c_nof_block_per_sync : NATURAL := 16;
+ CONSTANT c_nof_block_per_sync : NATURAL := 7; -- use short interval to speed up simulation
CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
CONSTANT c_pps_period : NATURAL := c_nof_clk_per_sync;
- CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value
+ CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value, due to WG rounding
CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
-- WG
- CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_bsn_start_wg : NATURAL := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT c_ampl_sp_0 : NATURAL := c_sdp_FS_adc/2; -- = 0.5 * FS, so in number of lsb
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
@@ -107,6 +108,9 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
SIGNAL tb_clk : STD_LOGIC := '0';
SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+ SIGNAL pps_rst : STD_LOGIC := '1';
+ SIGNAL gen_pps : STD_LOGIC := '0';
+
-- WG
SIGNAL dbg_c_exp_wg_power_sp_0 : REAL := c_exp_wg_power_sp_0;
SIGNAL sp_samples : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0);
@@ -116,9 +120,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc IS
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
- SIGNAL pps : STD_LOGIC := '0';
- SIGNAL ext_pps : STD_LOGIC := '0';
- SIGNAL pps_rst : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
@@ -151,9 +153,9 @@ BEGIN
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
- proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
- jesd204b_sysref <= pps;
- ext_pps <= pps;
+ proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, gen_pps);
+ jesd204b_sysref <= gen_pps;
+ ext_pps <= gen_pps;
------------------------------------------------------------------------------
-- DUT
@@ -171,7 +173,7 @@ BEGIN
PORT MAP (
-- GENERAL
CLK => ext_clk,
- PPS => pps,
+ PPS => ext_pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
@@ -212,16 +214,18 @@ BEGIN
-- Wait for DUT power up after reset
WAIT FOR 1 us;
- proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
----------------------------------------------------------------------------
-- Enable BS
----------------------------------------------------------------------------
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk);
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, 0, tb_clk); -- Init BSN = 0
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
- mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+ -- Release PPS pulser, to get first PPS now and to start BSN source
+ WAIT FOR 1 us;
+ pps_rst <= '0';
+
----------------------------------------------------------------------------
-- Enable WG
----------------------------------------------------------------------------
@@ -247,9 +251,11 @@ BEGIN
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+ ----------------------------------------------------------------------------
-- Wait for enough WG data and start of sync interval
- mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
- "UNSIGNED", rd_data, ">=", c_nof_block_per_sync*3, -- this is the wait until condition
+ ----------------------------------------------------------------------------
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync*2, -- this is the wait until condition
c_sdp_T_sub, tb_clk);
---------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5cf5c737e6530ee05b3721fe0e4d4a83315656e1
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
@@ -0,0 +1,695 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra, R. van der Walle
+-- Purpose: Self-checking testbench for simulating restart of JESD interface
+-- rx_clk domain input section in lofar2_unb2c_sdp_station_adc
+--
+-- Description:
+-- * Run JESD204B interface
+-- FOR I IN 0 TO c_nof_restarts LOOP
+-- . Run WG and ADUH monitor similar as in tb_lofar2_unb2c_sdp_station_adc
+-- . Reset the AIT rx_clk domain input section via PIO_JESD_CTRL
+-- . Reinit signal input links via JESD204B
+-- END LOOP
+-- * Uses c_si_dis to view signal input disable via JESD_CTRL.
+--
+-- Conclusion:
+-- * JESD_CTRL reset does reset the JESD204B IP and also the rx_clk and rx_rst,
+-- so it is necessary to first stop the BSN source to avoid that corrupted
+-- data blocks will enter the dp_clk domain, due to rx_rst of the rx_clk/
+-- dp_clk domain FIFO.
+-- * JESD204B link reinit does restart the signal input link. For link reinit
+-- it is not necessary to stop the BSN source, because then the rx_clk
+-- remains running and the rx_rst remains inactive.
+-- It is not clear whether both reset and reinit are needed to recover a link,
+-- (e.g. after RCU2 off/on) or whether one of them is enough.
+--
+-- Usage:
+-- > as 7 # default
+-- > as 16 # for detailed debugging of JESD204B IP
+-- > run -a
+--
+-------------------------------------------------------------------------------
+LIBRARY IEEE, common_lib, unb2c_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2c_sdp_station_lib, tech_jesd204b_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE IEEE.MATH_REAL.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE wpfb_lib.wpfb_pkg.ALL;
+USE lofar2_sdp_lib.sdp_pkg.ALL;
+USE tech_jesd204b_lib.tech_jesd204b_pkg.ALL;
+
+ENTITY tb_lofar2_unb2c_sdp_station_adc_jesd IS
+END tb_lofar2_unb2c_sdp_station_adc_jesd;
+
+ARCHITECTURE tb OF tb_lofar2_unb2c_sdp_station_adc_jesd IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0;
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 0);
+ CONSTANT c_init_bsn : NATURAL := 17; -- some recognizable value >= 0
+ CONSTANT c_si_dis : NATURAL := 2; -- disable signal input 2 in range 0:c_sdp_S_pn_1
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
+
+ CONSTANT c_tb_clk_period : TIME := 10 ns;--100 ps; -- use fast tb_clk to speed up M&C
+
+ CONSTANT c_nof_restarts : NATURAL := 1;
+ CONSTANT c_nof_block_per_sync : NATURAL := 7; -- use short interval to speed up simulation
+ CONSTANT c_nof_clk_per_sync : NATURAL := c_nof_block_per_sync*c_sdp_N_fft;
+ CONSTANT c_pps_period : TIME := c_nof_clk_per_sync * c_ext_clk_period;
+
+ CONSTANT c_percentage : REAL := 0.05; -- percentage that actual value may differ from expected value, due to WG rounding
+ CONSTANT c_lo_factor : REAL := 1.0 - c_percentage; -- lower boundary
+ CONSTANT c_hi_factor : REAL := 1.0 + c_percentage; -- higher boundary
+
+ -- Tx JESD
+ CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- <= c_sdp_S_pn = 12
+
+ -- WG
+ CONSTANT c_bsn_start_wg : NATURAL := c_init_bsn + 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
+ CONSTANT c_ampl_sp_0 : NATURAL := c_sdp_FS_adc/2; -- = 0.5 * FS, so in number of lsb
+ CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
+ CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
+ CONSTANT c_exp_wg_power_sp_0 : REAL := REAL(c_ampl_sp_0**2)/2.0 * REAL(c_nof_clk_per_sync);
+
+ -- ADUH
+ CONSTANT c_mon_buffer_nof_samples : NATURAL := 512; --samples per stream
+
+ -- MM
+ CONSTANT c_mm_file_reg_ppsh : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_PPS";
+ CONSTANT c_mm_file_reg_bsn_source_v2 : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
+ CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
+ CONSTANT c_mm_file_reg_diag_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
+ CONSTANT c_mm_file_reg_aduh_mon : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_ADUH_MONITOR";
+ CONSTANT c_mm_file_jesd204b : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "JESD204B";
+ CONSTANT c_mm_file_pio_jesd_ctrl : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "PIO_JESD_CTRL";
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+ SIGNAL tb_clk : STD_LOGIC := '0';
+ SIGNAL rd_data : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
+
+ SIGNAL pps_rst : STD_LOGIC := '1';
+ SIGNAL gen_pps : STD_LOGIC := '0';
+
+ -- WG
+ SIGNAL dbg_c_exp_wg_power_sp_0 : REAL := c_exp_wg_power_sp_0;
+ SIGNAL sp_samples : t_integer_arr(0 TO c_mon_buffer_nof_samples-1) := (OTHERS=>0);
+ SIGNAL sp_sample : INTEGER := 0;
+ SIGNAL sp_power_sum : STD_LOGIC_VECTOR(63 DOWNTO 0);
+ SIGNAL current_bsn_wg : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL ext_pps : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0) := (OTHERS => '0');
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 downto 0);
+
+ -- back transceivers
+ SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR(c_sdp_S_pn-1 downto 0);
+ SIGNAL JESD204B_REFCLK : STD_LOGIC := '1';
+
+ -- jesd204b syncronization signals
+ SIGNAL JESD204B_SYSREF : STD_LOGIC;
+ SIGNAL JESD204B_SYNC_N : STD_LOGIC_VECTOR(c_sdp_N_sync_jesd-1 DOWNTO 0);
+
+ -- Tx jesd204b source
+ CONSTANT c_tx_avs_clk_period : TIME := 20 ns;
+
+ SIGNAL mm_rst : STD_LOGIC := '1';
+ SIGNAL tx_avs_clk : STD_LOGIC := '0';
+ SIGNAL tx_avs_rst_n : STD_LOGIC := '0';
+
+ SIGNAL txlink_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL dev_sync_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+
+ SIGNAL tx_avs_chipselect : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL tx_avs_address : t_slv_8_arr(c_nof_jesd204b_tx-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
+ SIGNAL tx_avs_read : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL tx_avs_readdata : t_slv_32_arr(c_nof_jesd204b_tx-1 DOWNTO 0);
+
+ SIGNAL txphy_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL txlink_rst_n : STD_LOGIC;
+ SIGNAL tx_analogreset : STD_LOGIC_VECTOR(0 downto 0);
+ SIGNAL tx_digitalreset : STD_LOGIC_VECTOR(0 downto 0);
+ SIGNAL tx_bonding_clocks : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
+ SIGNAL bonding_clock_0 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_1 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_2 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_3 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_4 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_5 : STD_LOGIC := '0';
+ SIGNAL pll_locked : STD_LOGIC_VECTOR(0 downto 0);
+
+ SIGNAL jesd204b_tx_link_data_arr : t_slv_32_arr(c_nof_jesd204b_tx-1 DOWNTO 0);
+ SIGNAL jesd204b_tx_link_valid : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 DOWNTO 0);
+ SIGNAL jesd204b_tx_link_ready : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 DOWNTO 0);
+ SIGNAL jesd204b_tx_frame_ready : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 DOWNTO 0);
+
+ SIGNAL jesd204b_sync_adc_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 DOWNTO 0);
+
+ -- Rx jesd204b IP registers
+ SIGNAL reg_jesd204b_rx_err_enable : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL reg_jesd204b_rx_err_link_reinit : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL reg_jesd204b_rx_syncn_sysref_ctrl : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ SIGNAL reg_jesd204b_rx_err0 : STD_LOGIC_VECTOR(tech_jesd204b_field_rx_err0_w-1 DOWNTO 0);
+ SIGNAL reg_jesd204b_rx_err1 : STD_LOGIC_VECTOR(tech_jesd204b_field_rx_err1_w-1 DOWNTO 0);
+ SIGNAL reg_jesd204b_csr_rbd_count : STD_LOGIC_VECTOR(tech_jesd204b_field_csr_rbd_count_w-1 DOWNTO 0);
+ SIGNAL reg_jesd204b_csr_dev_syncn : STD_LOGIC_VECTOR(tech_jesd204b_field_csr_dev_syncn_w-1 DOWNTO 0);
+
+ -- Rx jesd204b ctrl register
+ SIGNAL pio_jesd_ctrl : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL pio_jesd_ctrl_enable : STD_LOGIC_VECTOR(c_sdp_jesd_ctrl_enable_w-1 DOWNTO 0);
+ SIGNAL pio_jesd_ctrl_reset : STD_LOGIC;
+
+ -- Debug signals to track progress of p_stimuli in Wave Window
+ SIGNAL dbg_restart : NATURAL := 0;
+ SIGNAL dbg_bsn_source_en : STD_LOGIC := '0';
+ SIGNAL dbg_jesd_ctrl_reset : STD_LOGIC := '0';
+ SIGNAL dbg_read_jesd204b : STD_LOGIC := '0';
+ SIGNAL dbg_link_reinit : STD_LOGIC := '0';
+
+ -- Read JESD204B IP status per signal input c_si
+ PROCEDURE proc_read_jesd204b(c_si : IN NATURAL;
+ SIGNAL rd_clk : IN STD_LOGIC;
+ SIGNAL rd_data : INOUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL dbg_read : OUT STD_LOGIC;
+ SIGNAL rx_err_enable : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL rx_err_link_reinit : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL rx_syncn_sysref_ctrl : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL rx_err0 : OUT STD_LOGIC_VECTOR(tech_jesd204b_field_rx_err0_w-1 DOWNTO 0);
+ SIGNAL rx_err1 : OUT STD_LOGIC_VECTOR(tech_jesd204b_field_rx_err1_w-1 DOWNTO 0);
+ SIGNAL csr_rbd_count : OUT STD_LOGIC_VECTOR(tech_jesd204b_field_csr_rbd_count_w-1 DOWNTO 0);
+ SIGNAL csr_dev_syncn : OUT STD_LOGIC_VECTOR(tech_jesd204b_field_csr_dev_syncn_w-1 DOWNTO 0)) IS
+ CONSTANT c_offset : NATURAL := c_si * tech_jesd204b_port_span;
+ BEGIN
+ dbg_read <= '1';
+ mmf_mm_bus_rd(c_mm_file_jesd204b, 2, c_offset + tech_jesd204b_field_rx_err_enable_adr, rd_data, rd_clk);
+ rx_err_enable <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_jesd204b, c_offset + tech_jesd204b_field_rx_err_link_reinit_adr, rd_data, rd_clk);
+ rx_err_link_reinit <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_jesd204b, c_offset + tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, rd_data, rd_clk);
+ rx_syncn_sysref_ctrl <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_jesd204b, c_offset + tech_jesd204b_field_rx_err0_adr, rd_data, rd_clk);
+ rx_err0 <= rd_data(tech_jesd204b_field_rx_err0_hi DOWNTO tech_jesd204b_field_rx_err0_lo);
+ mmf_mm_bus_rd(c_mm_file_jesd204b, c_offset + tech_jesd204b_field_rx_err1_adr, rd_data, rd_clk);
+ rx_err1 <= rd_data(tech_jesd204b_field_rx_err1_hi DOWNTO tech_jesd204b_field_rx_err1_lo);
+ mmf_mm_bus_rd(c_mm_file_jesd204b, c_offset + tech_jesd204b_field_csr_rbd_count_adr, rd_data, rd_clk);
+ csr_rbd_count <= rd_data(tech_jesd204b_field_csr_rbd_count_hi DOWNTO tech_jesd204b_field_csr_rbd_count_lo);
+ mmf_mm_bus_rd(c_mm_file_jesd204b, c_offset + tech_jesd204b_field_csr_dev_syncn_adr, rd_data, rd_clk);
+ csr_dev_syncn <= rd_data(tech_jesd204b_field_csr_dev_syncn_hi DOWNTO tech_jesd204b_field_csr_dev_syncn_lo);
+ dbg_read <= '0';
+ END;
+
+ PROCEDURE proc_read_jesd204b_arr(SIGNAL rd_clk : IN STD_LOGIC;
+ SIGNAL rd_data : INOUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL dbg_read : OUT STD_LOGIC;
+ SIGNAL rx_err_enable : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL rx_err_link_reinit : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL rx_syncn_sysref_ctrl : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL rx_err0 : OUT STD_LOGIC_VECTOR(tech_jesd204b_field_rx_err0_w-1 DOWNTO 0);
+ SIGNAL rx_err1 : OUT STD_LOGIC_VECTOR(tech_jesd204b_field_rx_err1_w-1 DOWNTO 0);
+ SIGNAL csr_rbd_count : OUT STD_LOGIC_VECTOR(tech_jesd204b_field_csr_rbd_count_w-1 DOWNTO 0);
+ SIGNAL csr_dev_syncn : OUT STD_LOGIC_VECTOR(tech_jesd204b_field_csr_dev_syncn_w-1 DOWNTO 0)) IS
+ BEGIN
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ proc_read_jesd204b(I, rd_clk, rd_data, dbg_read,
+ rx_err_enable,
+ rx_err_link_reinit,
+ rx_syncn_sysref_ctrl,
+ rx_err0,
+ rx_err1,
+ csr_rbd_count,
+ csr_dev_syncn);
+ END LOOP;
+ END;
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk(0) <= NOT eth_clk(0) AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+ JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(10, c_nof_clk_per_sync, '1', pps_rst, ext_clk, gen_pps);
+ JESD204B_SYSREF <= gen_pps;
+ ext_pps <= gen_pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT with JESD204B Rx
+ ------------------------------------------------------------------------------
+ u_lofar_unb2c_sdp_station_adc : ENTITY lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2c_sdp_station_adc",
+ g_design_note => "",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr,
+ g_bsn_nof_clk_per_sync => c_nof_clk_per_sync,
+ g_scope_selected_subband => NATURAL(c_subband_sp_0)
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => ext_pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
+ JESD204B_REFCLK => JESD204B_REFCLK,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => JESD204B_SYSREF,
+ JESD204B_SYNC_N => JESD204B_SYNC_N
+ );
+
+ -----------------------------------------------------------------------------
+ -- Use a JESD204b Tx instance to model the ADCs
+ -- . copied from tb_tech_jesd204b.vhd
+ -----------------------------------------------------------------------------
+
+ -- Clocks and resets
+ tx_avs_clk <= NOT tx_avs_clk AFTER c_tx_avs_clk_period/2;
+
+ mm_rst <= '1', '0' after 800 ns;
+ tx_avs_rst_n <= '0', '1' after 23500 ns;
+ tx_analogreset(0) <= '1', '0' after 18500 ns;
+ tx_digitalreset(0) <= '1', '0' after 23000 ns;
+ txlink_rst_n <= '0', '1' after 25500 ns;
+ pll_locked(0) <= '0', '1' after 1000 ns;
+
+ -- Create bonding clocks
+ bonding_clock_5 <= not bonding_clock_5 after 250 ps;
+ bonding_clock_4 <= not bonding_clock_4 after 250 ps;
+ bonding_clock_3 <= not bonding_clock_3 after 500 ps;
+ bonding_clock_2 <= not bonding_clock_2 after 500 ps;
+ bonding_clock_0 <= not bonding_clock_0 after 2500 ps;
+
+ bonding_clock_1_process : process
+ begin
+ bonding_clock_1 <= '0';
+ wait for 4000 ps;
+ bonding_clock_1 <= '1';
+ wait for 1000 ps;
+ end process;
+
+ tx_bonding_clocks(5) <= transport bonding_clock_5 after 4890 ps;
+ tx_bonding_clocks(4) <= transport bonding_clock_4 after 4640 ps;
+ tx_bonding_clocks(3) <= transport bonding_clock_3 after 4920 ps;
+ tx_bonding_clocks(2) <= transport bonding_clock_2 after 4930 ps;
+ tx_bonding_clocks(1) <= transport bonding_clock_1 after 7490 ps;
+ tx_bonding_clocks(0) <= transport bonding_clock_0 after 4000 ps;
+
+ gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
+ -- Tb DAC
+ u_tech_jesd204b_tx : ENTITY tech_jesd204b_lib.tech_jesd204b_tx
+ PORT MAP (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, --out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), --out
+ jesd204_tx_avs_chipselect => tx_avs_chipselect(i),
+ jesd204_tx_avs_address => tx_avs_address(i),
+ jesd204_tx_avs_read => tx_avs_read(i),
+ jesd204_tx_avs_readdata => tx_avs_readdata(i),
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => tx_avs_clk,
+ jesd204_tx_avs_rst_n => tx_avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
+ mdev_sync_n => dev_sync_n(i), --in
+ pll_locked => pll_locked, --in
+ sync_n => jesd204b_sync_adc_n(i), --in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => JESD204B_SERIAL_DATA(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => JESD204B_SYSREF
+ );
+
+ -- One JESD204B_SYNC_N per RCU2
+ jesd204b_sync_adc_n(i) <= JESD204B_SYNC_N(i / c_sdp_S_rcu);
+
+ -- Generate same test pattern for all ADC
+ p_tx_data : PROCESS (JESD204B_REFCLK, mm_rst)
+ VARIABLE v_data : INTEGER := 0;
+ VARIABLE v_even_sample : BOOLEAN := TRUE;
+ BEGIN
+ IF mm_rst = '1' THEN
+ jesd204b_tx_link_data_arr(i) <= (others => '0');
+ jesd204b_tx_link_valid(i) <= '0';
+ txlink_clk(i) <= '0';
+ v_data := 0;
+ v_even_sample := TRUE;
+ ELSIF rising_edge(JESD204B_REFCLK) THEN
+ txlink_clk(i) <= not txlink_clk(i);
+
+ -- Incrementing data in c_sdp_W_adc_jesd = 16 bits
+ -- . use range c_sdp_W_adc_jesd-1 to avoid simulation warnings:
+ -- Warning: NUMERIC_STD.TO_SIGNED: vector truncated
+ -- Time: 164635 ns Iteration: 0 Region: /tb_lofar2_unb2c_sdp_station_adc_jesd/gen_jesd204b_tx(2)
+ v_data := (v_data + 1) MOD 2**(c_sdp_W_adc_jesd-1);
+
+ -- Frame the data to 32 bits at half the rate
+ IF jesd204b_tx_link_ready(i) = '0' THEN
+ v_even_sample := TRUE;
+ ELSE
+ v_even_sample := not v_even_sample;
+ END IF;
+ IF v_even_sample = TRUE THEN
+ jesd204b_tx_link_data_arr(i)(c_sdp_W_adc_jesd-1 downto 0) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
+ jesd204b_tx_link_valid(i) <= '0';
+ ELSE
+ jesd204b_tx_link_data_arr(i)(2*c_sdp_W_adc_jesd-1 downto c_sdp_W_adc_jesd) <= TO_SVEC(v_data, c_sdp_W_adc_jesd);
+ jesd204b_tx_link_valid(i) <= '1';
+ END IF;
+ END IF;
+ END PROCESS;
+
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- MM slave accesses via file IO
+ ------------------------------------------------------------------------------
+ tb_clk <= NOT tb_clk AFTER c_tb_clk_period/2; -- Testbench MM clock
+
+ p_mm_stimuli : PROCESS
+ VARIABLE v_offset : NATURAL;
+ VARIABLE v_word : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ VARIABLE v_int : INTEGER;
+ VARIABLE v_bsn : NATURAL;
+ VARIABLE v_sp_power_sum_0 : REAL;
+ VARIABLE v_sp_subband_power : REAL;
+ VARIABLE v_W, v_T, v_U, v_S, v_B : NATURAL; -- array indicies
+ BEGIN
+ dbg_restart <= 0;
+ FOR REP IN 0 TO c_nof_restarts LOOP
+ -- Wait for DUT power up after reset or after AIT rx_clk domain restart
+ WAIT FOR 1 us;
+
+ ----------------------------------------------------------------------------
+ -- Enable BS
+ ----------------------------------------------------------------------------
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2, c_init_bsn, tb_clk); -- Init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3, 0, tb_clk); -- Write high part activates the init BSN
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BS at PPS
+
+ -- Release PPS pulser, to get first PPS now and to start BSN source
+ WAIT FOR 1 us;
+ pps_rst <= '0';
+ dbg_bsn_source_en <= '1'; -- marker in wave window
+
+ ---------------------------------------------------------------------------
+ -- Read JESD_CTRL register
+ ---------------------------------------------------------------------------
+ -- Note: pio_jesd_ctrl_enable works in fact as disable, so '0' enables
+ -- signal input and '1' disables it, and read yields
+ -- pio_jesd_ctrl = 0.
+ mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
+ pio_jesd_ctrl <= rd_data;
+ pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w-1 DOWNTO 0);
+ pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
+
+ ----------------------------------------------------------------------------
+ -- Enable WG
+ ----------------------------------------------------------------------------
+ -- 0 : mode[7:0] --> off=0, calc=1, repeat=2, single=3)
+ -- nof_samples[31:16] --> <= c_ram_wg_size=1024
+ -- 1 : phase[15:0]
+ -- 2 : freq[30:0]
+ -- 3 : ampl[16:0]
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0, 1024*2**16 + 1, tb_clk); -- nof_samples, mode calc
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1, INTEGER( 0.0 * c_diag_wg_phase_unit), tb_clk); -- phase offset in degrees
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0 + c_wg_freq_offset) * c_sdp_wg_subband_freq_unit), tb_clk); -- freq
+ mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3, INTEGER(REAL(c_ampl_sp_0) * c_sdp_wg_ampl_lsb), tb_clk); -- ampl
+
+ -- Read current BSN
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO 0), tb_clk);
+ mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ -- Write scheduler BSN to trigger start of WG at next block
+ v_bsn := TO_UINT(current_bsn_wg) + 2;
+ ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
+ v_bsn := c_bsn_start_wg;
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk); -- first write low then high part
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1, 0, tb_clk); -- assume v_bsn < 2**31-1
+
+ ----------------------------------------------------------------------------
+ -- Wait for enough WG data and start of sync interval
+ ----------------------------------------------------------------------------
+ mmf_mm_wait_until_value(c_mm_file_reg_bsn_scheduler_wg, 0, -- read BSN low
+ "UNSIGNED", rd_data, ">=", c_init_bsn + c_nof_block_per_sync*2, -- this is the wait until condition
+ c_sdp_T_sub, tb_clk);
+
+ ----------------------------------------------------------------------------
+ -- Read JESD204B IP status per signal input
+ ----------------------------------------------------------------------------
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ proc_read_jesd204b(I, tb_clk, rd_data, dbg_read_jesd204b,
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
+ proc_common_wait_some_cycles(tb_clk, 10);
+
+ -----------------------------------------------------------------------
+ -- Verify expected Rx JESD204B IP values for active signal inputs
+ -----------------------------------------------------------------------
+ IF I < c_nof_jesd204b_tx THEN
+ ASSERT UNSIGNED(reg_jesd204b_rx_err_enable) = tech_jesd204b_field_rx_err_enable_reset
+ REPORT "Wrong rx_err_enable_reset: " & INTEGER'IMAGE(TO_SINT(reg_jesd204b_rx_err_enable)) & " /= " & INTEGER'IMAGE(tech_jesd204b_field_rx_err_enable_reset) SEVERITY ERROR;
+ ASSERT UNSIGNED(reg_jesd204b_rx_err_link_reinit) = tech_jesd204b_field_rx_err_link_reinit_reset
+ REPORT "Wrong rx_err_link_reinit_reset: " & INTEGER'IMAGE(TO_SINT(reg_jesd204b_rx_err_link_reinit)) & " /= " & INTEGER'IMAGE(tech_jesd204b_field_rx_err_link_reinit_reset) SEVERITY ERROR;
+ END IF;
+ END LOOP;
+
+ ---------------------------------------------------------------------------
+ -- Read ADUH monitor power sum
+ ---------------------------------------------------------------------------
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 2, rd_data, tb_clk); -- read low part
+ sp_power_sum(31 DOWNTO 0) <= rd_data;
+ mmf_mm_bus_rd(c_mm_file_reg_aduh_mon, 3, rd_data, tb_clk); -- read high part
+ sp_power_sum(63 DOWNTO 32) <= rd_data;
+ proc_common_wait_some_cycles(tb_clk, 1);
+
+ ---------------------------------------------------------------------------
+ -- Verify sp_power_sum
+ ---------------------------------------------------------------------------
+ -- Convert STD_LOGIC_VECTOR sp_power_sum to REAL
+ v_sp_power_sum_0 := REAL(REAL(TO_UINT(sp_power_sum(61 DOWNTO 30)))*REAL(2**30) + REAL(TO_UINT(sp_power_sum(29 DOWNTO 0))));
+
+ ASSERT v_sp_power_sum_0 > c_lo_factor * c_exp_wg_power_sp_0 REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
+ ASSERT v_sp_power_sum_0 < c_hi_factor * c_exp_wg_power_sp_0 REPORT "Wrong SP power for SP 0" SEVERITY ERROR;
+
+ ----------------------------------------------------------------------------
+ -- Restart AIT
+ -- . JESD_CTRL reset stops JESD204B OUT rx_clk and asserts JESD204B OUT
+ -- rx_rst, so it is necessary to stop the BSN source, to ensure that
+ -- the rx_clk/dp_clk domain FIFO runs empty before rx_rst is asserted, so
+ -- that no corrupt data blocks will enter the dp_clk domain.
+ ----------------------------------------------------------------------------
+
+ -- 1) Disable BSN source to allow rx_clk/dp_clk domain FIFO to run empty
+ mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000000#, tb_clk);
+
+ -- . Wait until BSN source has finished last block, use ext_clk as 200 MHz
+ -- equivalent for dp_clk, and wait for > 1 block of c_sdp_N_fft samples
+ proc_common_wait_some_cycles(ext_clk, c_sdp_N_fft * 2);
+ dbg_bsn_source_en <= '0'; -- marker in wave window
+
+ -- 2) Reset via JESD_CTRL c_sdp_jesd_ctrl_reset_bi = 31 and read back
+ -- Note: Awkward way to set MSbit without negative integer warning, using TO_SINT(v_word).
+ dbg_jesd_ctrl_reset <= '1'; -- marker in wave window
+ v_word := (OTHERS => '0');
+ v_word(c_sdp_jesd_ctrl_reset_bi) := '1'; -- reset
+ mmf_mm_bus_wr(c_mm_file_pio_jesd_ctrl, 0, TO_SINT(v_word), tb_clk);
+ proc_common_wait_cross_clock_domain_latency(tb_clk, ext_clk);
+ mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
+ pio_jesd_ctrl <= rd_data;
+ pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w-1 DOWNTO 0);
+ pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
+
+ WAIT FOR 1 us;
+ -- Read Rx JESD_204B IP status during reset
+ proc_read_jesd204b_arr(tb_clk, rd_data, dbg_read_jesd204b,
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
+
+ -- Hold JESD_CTRL reset for > one sync period, so also during a JESD204B_SYSREF pulse,
+ -- to see that JESD_CTRL reset stops JESD204B OUT rx_sysref too.
+ WAIT FOR c_pps_period;
+
+ -- . Re-enable via JESD_CTRL and read back
+ v_word := (OTHERS => '0'); -- release reset
+ v_word(c_si_dis) := '1'; -- disable one signal input
+ mmf_mm_bus_wr(c_mm_file_pio_jesd_ctrl, 0, TO_SINT(v_word), tb_clk);
+ proc_common_wait_cross_clock_domain_latency(tb_clk, ext_clk);
+ mmf_mm_bus_rd(c_mm_file_pio_jesd_ctrl, 0, rd_data, tb_clk);
+ pio_jesd_ctrl <= rd_data;
+ pio_jesd_ctrl_enable <= rd_data(c_sdp_jesd_ctrl_enable_w-1 DOWNTO 0);
+ pio_jesd_ctrl_reset <= rd_data(c_sdp_jesd_ctrl_reset_bi);
+ dbg_jesd_ctrl_reset <= '0'; -- marker in wave window
+
+ -- Wait for a JESD204B_SYSREF pulse
+ WAIT FOR c_pps_period;
+ -- Read Rx JESD_204B IP status
+ proc_read_jesd204b_arr(tb_clk, rd_data, dbg_read_jesd204b,
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
+
+ -- 3) Reinit the JESD204B link per signal input
+ dbg_link_reinit <= '1'; -- marker in wave window
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ v_int := tech_jesd204b_field_rx_syncn_sysref_ctrl_link_reinit +
+ tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_alwayson;
+ mmf_mm_bus_wr(c_mm_file_jesd204b, v_offset + tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, v_int, tb_clk);
+ END LOOP;
+
+ WAIT FOR 1 us;
+ -- Read Rx JESD_204B IP status
+ proc_read_jesd204b_arr(tb_clk, rd_data, dbg_read_jesd204b,
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
+
+ FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+ v_int := tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_alwayson;
+ mmf_mm_bus_wr(c_mm_file_jesd204b, v_offset + tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, v_int, tb_clk);
+ END LOOP;
+ dbg_link_reinit <= '0'; -- marker in wave window
+
+ -- Wait for a JESD204B_SYSREF pulse
+ WAIT FOR c_pps_period;
+ -- Read Rx JESD_204B IP status
+ proc_read_jesd204b_arr(tb_clk, rd_data, dbg_read_jesd204b,
+ reg_jesd204b_rx_err_enable,
+ reg_jesd204b_rx_err_link_reinit,
+ reg_jesd204b_rx_syncn_sysref_ctrl,
+ reg_jesd204b_rx_err0,
+ reg_jesd204b_rx_err1,
+ reg_jesd204b_csr_rbd_count,
+ reg_jesd204b_csr_dev_syncn);
+ -- Count restart loops
+ dbg_restart <= dbg_restart + 1;
+ END LOOP;
+
+ ---------------------------------------------------------------------------
+ -- End Simulation
+ ---------------------------------------------------------------------------
+ WAIT FOR 10 us;
+ sim_done <= '1';
+ proc_common_wait_some_cycles(ext_clk, 100);
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index 5194a4392368001350704206205946a5429255bb..e00b83112f2f0664da42844f6f7231ba8733bccc 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -362,9 +362,13 @@ BEGIN
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_copi, eth1g_reg_cipo );
- u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B")
+ -- Must use exact g_mm_rd_latency = 1 instead of default 2, because JESD204B IP forces rddata = 0 after it has been read
+ u_mm_file_jesd204b : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "JESD204B", '1', 1)
PORT MAP(mm_rst, mm_clk, jesd204b_copi, jesd204b_cipo );
+ u_mm_file_pio_jesd_ctrl : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_JESD_CTRL")
+ PORT MAP(mm_rst, mm_clk, jesd_ctrl_copi, jesd_ctrl_cipo );
+
u_mm_file_reg_dp_shiftram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SHIFTRAM")
PORT MAP(mm_rst, mm_clk, reg_dp_shiftram_copi, reg_dp_shiftram_cipo );
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index cfa0669c9591a4cf79d57b65f837ba2392b0faf3..5b110bfb743ac919ebcbfabb9466f16cb0b9a54e 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -160,7 +160,7 @@ BEGIN
-- in an SDP application assumes that the block timing of the out_sosi_arr(i) only contains
-- complete blocks, so from sop to eop.
- mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(31);
+ mm_rst_internal <= mm_rst OR mm_jesd_ctrl_reg(c_sdp_jesd_ctrl_reset_bi);
gen_jesd_disable : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
END GENERATE;
@@ -172,7 +172,7 @@ BEGIN
u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b
GENERIC MAP(
- g_sim => g_sim,
+ g_sim => FALSE, -- do not use g_sim, because JESD204B IP does support mm_clk in sim
g_nof_streams => c_sdp_S_pn,
g_nof_sync_n => c_sdp_N_sync_jesd,
g_jesd_freq => c_sdp_jesd204b_freq
@@ -512,7 +512,7 @@ BEGIN
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w
GENERIC MAP (
- g_reg => c_sdp_jesd204b_mm_jesd_ctrl_reg,
+ g_reg => c_sdp_mm_jesd_ctrl_reg,
g_init_reg => (OTHERS => '0')
)
PORT MAP (
@@ -520,11 +520,11 @@ BEGIN
clk => mm_clk,
-- control side
wr_en => jesd_ctrl_mosi.wr,
- wr_adr => jesd_ctrl_mosi.address(c_sdp_jesd204b_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
- wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_jesd204b_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
+ wr_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
+ wr_dat => jesd_ctrl_mosi.wrdata(c_sdp_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
rd_en => jesd_ctrl_mosi.rd,
- rd_adr => jesd_ctrl_mosi.address(c_sdp_jesd204b_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
- rd_dat => jesd_ctrl_miso.rddata(c_sdp_jesd204b_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
+ rd_adr => jesd_ctrl_mosi.address(c_sdp_mm_jesd_ctrl_reg.adr_w-1 DOWNTO 0),
+ rd_dat => jesd_ctrl_miso.rddata(c_sdp_mm_jesd_ctrl_reg.dat_w-1 DOWNTO 0),
rd_val => OPEN,
-- data side
out_reg => mm_jesd_ctrl_reg,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index ed38675826507b02c97ade53c867aa9b538aa56e..7fe6896838ac5d2c86cb3e6e0444368a82759418 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -27,7 +27,7 @@
-- References:
-- . [1] https://support.astron.nl/confluence/display/L2M/L3+SDP+Decision%3A+SDP+Parameter+definitions
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, rTwoSDF_lib, fft_lib, filter_lib, wpfb_lib, diag_lib;
+LIBRARY IEEE, common_lib, rTwoSDF_lib, fft_lib, filter_lib, wpfb_lib, diag_lib, tech_jesd204b_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.math_real.ALL;
USE common_lib.common_pkg.ALL;
@@ -39,6 +39,7 @@ USE rTwoSDF_lib.rTwoSDFPkg.ALL;
USE fft_lib.fft_pkg.ALL;
USE filter_lib.fil_pkg.ALL;
USE wpfb_lib.wpfb_pkg.ALL;
+USE tech_jesd204b_lib.tech_jesd204b_pkg.ALL;
PACKAGE sdp_pkg is
-------------------------------------------------
@@ -115,6 +116,9 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_N_clk_per_sync : NATURAL := c_sdp_f_adc_MHz*10**6; -- Default 200M clock cycles per second
CONSTANT c_sdp_N_clk_sync_timeout : NATURAL := c_sdp_f_adc_MHz*10**6 + c_sdp_f_adc_MHz*10**5; -- 10% margin.
CONSTANT c_sdp_N_sync_jesd : NATURAL := c_sdp_S_pn * c_sdp_N_sync_rcu / c_sdp_S_rcu; -- = 4, nof JESD IP sync outputs per PN
+ CONSTANT c_sdp_f_sub_Hz : REAL := REAL(c_sdp_f_adc_MHz * 10**6) / REAL(c_sdp_N_fft);
+ CONSTANT c_sdp_N_int : NATURAL := c_sdp_f_adc_MHz * 10**6; -- nof ADC sample periods per 1 s integration interval
+ CONSTANT c_sdp_N_int_sub : REAL := c_sdp_f_sub_Hz; -- nof subband sample periods per 1 s integration interval
CONSTANT c_sdp_A_pn : NATURAL := c_sdp_S_pn / c_sdp_N_pol; -- = 6 dual pol antenna per PN, is 6 signal input pairs
CONSTANT c_sdp_P_pfb : NATURAL := c_sdp_S_pn / c_sdp_Q_fft; -- = 6 PFB units, for 6 signal input pairs
CONSTANT c_sdp_T_adc : TIME := (10**6 / c_sdp_f_adc_MHz) * 1 ps; -- = 5 ns @ 200MHz
@@ -420,17 +424,19 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_reg_nw_10GbE_mac_addr_w : NATURAL := 13;
CONSTANT c_sdp_reg_nw_10GbE_eth10g_addr_w : NATURAL := 1;
- -- JESD204
+ -- JESD204B
CONSTANT c_sdp_jesd204b_freq : STRING := "200MHz";
- CONSTANT c_sdp_jesd204b_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
+ CONSTANT c_sdp_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
adr_w => 1,
dat_w => c_word_w,
nof_dat => 1,
- init_sl => '0');
+ init_sl => '0'); -- PIO_JESD_CTRL
-- AIT MM address widths
- CONSTANT c_sdp_jesd204b_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 8;
- CONSTANT c_sdp_jesd_ctrl_addr_w : NATURAL := 1;
+ CONSTANT c_sdp_jesd204b_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + tech_jesd204b_port_span_w; -- = 4 + 8
+ CONSTANT c_sdp_jesd_ctrl_addr_w : NATURAL := c_sdp_mm_jesd_ctrl_reg.adr_w; -- = 1
+ CONSTANT c_sdp_jesd_ctrl_reset_bi : NATURAL := 31;
+ CONSTANT c_sdp_jesd_ctrl_enable_w : NATURAL := 31;
CONSTANT c_sdp_reg_bsn_monitor_input_addr_w : NATURAL := 8;
CONSTANT c_sdp_reg_wg_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 2;
CONSTANT c_sdp_ram_wg_addr_w : NATURAL := ceil_log2(c_sdp_S_pn) + 10;
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index aa0f730882561b2ac714e6e7b8d061d00d6e8536..44858d8b7a700ea534716c61e3fd524aa0c70bc1 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -70,20 +70,21 @@ ENTITY ip_arria10_e1sg_jesd204b IS
);
END ip_arria10_e1sg_jesd204b;
-
ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
-- JESD IP constants
- CONSTANT c_jesd204b_mm_addr_w : NATURAL :=8;
- CONSTANT c_jesd204b_rx_data_w : NATURAL :=32;
- CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
- CONSTANT c_jesd204b_rx_somf_w : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
- CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
- CONSTANT c_nof_sync_n_per_group : NATURAL :=sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n);
+ -- . JESD204B MM has 256 bytes = 64 words, so mm_addr_w = 6 would be enough,
+ -- but using mm_addr_w = 8 and span = 256 words is fine too.
+ CONSTANT c_jesd204b_mm_addr_w : NATURAL := 8;
+ CONSTANT c_jesd204b_rx_data_w : NATURAL := 32;
+ CONSTANT c_jesd204b_rx_framer_data_w : NATURAL := c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_jesd204b_rx_somf_w : NATURAL := c_jesd204b_rx_data_w/8; -- One somf bit per octet
+ CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL := c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_nof_sync_n_per_group : NATURAL := sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n);
-- JESD204 control status registers
SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
@@ -131,11 +132,9 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-
-- Component declarations for the IP blocks
-
- component ip_arria10_e1sg_jesd204b_rx_200MHz is
+ component ip_arria10_e1sg_jesd204b_rx_200MHz is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
@@ -233,8 +232,6 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
);
end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
-
-
BEGIN
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e1sg_jesd204b and causes a reset on the rx_rst output.
@@ -252,7 +249,6 @@ BEGIN
jesd204b_avs_clk <= mm_clk;
END GENERATE;
-
gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
@@ -260,10 +256,9 @@ BEGIN
-- The JESD204 IP (rx only)
-----------------------------------------------------------------------------
- gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
- u_ip_arria10_e1sg_jesd204b_rx_200MHz : ip_arria10_e1sg_jesd204b_rx_200MHz
- PORT MAP
- (
+ gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
+ u_ip_arria10_e1sg_jesd204b_rx_200MHz : ip_arria10_e1sg_jesd204b_rx_200MHz
+ PORT MAP (
alldev_lane_aligned => dev_lane_aligned_arr(i),
csr_cf => OPEN,
csr_cs => OPEN,
@@ -311,6 +306,9 @@ BEGIN
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
sysref => jesd204b_sysref_2
);
+
+ -- One cycle rd-rdval latency, waitrequest = '0' fixed
+ jesd204b_miso_arr(i).rdval <= jesd204b_mosi_arr(i).rd WHEN rising_edge(jesd204b_avs_clk);
END GENERATE;
-----------------------------------------------------------------------------
@@ -365,7 +363,6 @@ BEGIN
out_rst => rxframe_rst_arr(i)
);
-
rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
-- synchronize rx_xcvr_ready_in_arr to mm_clk
u_common_async_rx_xcvr_ready : ENTITY common_lib.common_async
@@ -384,7 +381,6 @@ BEGIN
rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
-
-----------------------------------------------------------------------------
-- Minimal deframer (transport layer)
-----------------------------------------------------------------------------
@@ -415,7 +411,7 @@ BEGIN
END IF;
END PROCESS;
- END GENERATE;
+ END GENERATE; -- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
-----------------------------------------------------------------------------
-- Reclock sysref and the sync_n output
@@ -459,7 +455,6 @@ BEGIN
END IF;
END PROCESS;
-
-- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
gen_jesd204b_rx_corepll_freqsel : IF g_jesd_freq = "200MHz" GENERATE
u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz : ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz
@@ -483,7 +478,6 @@ BEGIN
out_rst => mm_core_pll_locked_reg
);
-
-- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
-- Clock set to 100MHz (use rxlink_clk)
@@ -498,24 +492,23 @@ BEGIN
rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
);
- END GENERATE;
+ END GENERATE; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_enable_sync_n : FOR i IN 0 TO g_nof_streams-1 GENERATE
- -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
- -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
- -- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
- -- the sync_n_combined to become unavailable (see gen_group_sync_n).
-
+ -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
+ -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
+ -- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
+ -- the sync_n_combined to become unavailable (see gen_group_sync_n).
- -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
- jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
+ -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
+ jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
END GENERATE;
-----------------------------------------------------------------------------
-- Group the SYNC_N outputs
-----------------------------------------------------------------------------
gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
- jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
+ jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
END GENERATE;
-----------------------------------------------------------------------------
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 9ad874300f414645181cfa5a95d400de1306956b..cf0fd6e3b47648701766d7995c2a946f51a637d4 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -59,7 +59,7 @@ ENTITY ip_arria10_e2sg_jesd204b IS
-- MM Control
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
- jesd204b_disable_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '0');
+ jesd204b_disable_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
jesd204b_mosi : IN t_mem_mosi; -- mm control
jesd204b_miso : OUT t_mem_miso;
@@ -70,20 +70,21 @@ ENTITY ip_arria10_e2sg_jesd204b IS
);
END ip_arria10_e2sg_jesd204b;
-
ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
-- JESD IP constants
- CONSTANT c_jesd204b_mm_addr_w : NATURAL :=8;
- CONSTANT c_jesd204b_rx_data_w : NATURAL :=32;
- CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
- CONSTANT c_jesd204b_rx_somf_w : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
- CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
- CONSTANT c_nof_sync_n_per_group : NATURAL :=sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n);
+ -- . JESD204B MM has 256 bytes = 64 words, so mm_addr_w = 6 would be enough,
+ -- but using mm_addr_w = 8 and span = 256 words is fine too.
+ CONSTANT c_jesd204b_mm_addr_w : NATURAL := 8;
+ CONSTANT c_jesd204b_rx_data_w : NATURAL := 32;
+ CONSTANT c_jesd204b_rx_framer_data_w : NATURAL := c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_jesd204b_rx_somf_w : NATURAL := c_jesd204b_rx_data_w/8; -- One somf bit per octet
+ CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL := c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_nof_sync_n_per_group : NATURAL := sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n);
-- JESD204 control status registers
SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
+ SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
@@ -131,11 +132,9 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL jesd204b_sync_n_enabled_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
SIGNAL jesd204b_sync_n_combined_arr : STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
-
-- Component declarations for the IP blocks
-
- component ip_arria10_e2sg_jesd204b_rx_200MHz is
+ component ip_arria10_e2sg_jesd204b_rx_200MHz is
port (
alldev_lane_aligned : in std_logic := 'X'; -- export
csr_cf : out std_logic_vector(4 downto 0); -- export
@@ -233,8 +232,6 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
);
end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
-
-
BEGIN
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e2sg_jesd204b and causes a reset on the rx_rst output.
@@ -252,7 +249,6 @@ BEGIN
jesd204b_avs_clk <= mm_clk;
END GENERATE;
-
gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
@@ -260,10 +256,9 @@ BEGIN
-- The JESD204 IP (rx only)
-----------------------------------------------------------------------------
- gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
- u_ip_arria10_e2sg_jesd204b_rx_200MHz : ip_arria10_e2sg_jesd204b_rx_200MHz
- PORT MAP
- (
+ gen_jesd204b_rx_freqsel : IF g_jesd_freq = "200MHz" GENERATE
+ u_ip_arria10_e2sg_jesd204b_rx_200MHz : ip_arria10_e2sg_jesd204b_rx_200MHz
+ PORT MAP (
alldev_lane_aligned => dev_lane_aligned_arr(i),
csr_cf => OPEN,
csr_cs => OPEN,
@@ -311,6 +306,9 @@ BEGIN
somf => jesd204b_rx_somf_arr(c_jesd204b_rx_somf_w*i+c_jesd204b_rx_somf_w-1 downto c_jesd204b_rx_somf_w*i),
sysref => jesd204b_sysref_2
);
+
+ -- One cycle rd-rdval latency, waitrequest = '0' fixed
+ jesd204b_miso_arr(i).rdval <= jesd204b_mosi_arr(i).rd WHEN rising_edge(jesd204b_avs_clk);
END GENERATE;
-----------------------------------------------------------------------------
@@ -383,7 +381,6 @@ BEGIN
rxlink_rst_n_arr(i) <= not rxlink_rst_arr(i);
rxframe_rst_n_arr(i) <= not rxframe_rst_arr(i);
-
-----------------------------------------------------------------------------
-- Minimal deframer (transport layer)
-----------------------------------------------------------------------------
@@ -414,7 +411,7 @@ BEGIN
END IF;
END PROCESS;
- END GENERATE;
+ END GENERATE; -- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
-----------------------------------------------------------------------------
-- Reclock sysref and the sync_n output
@@ -458,7 +455,6 @@ BEGIN
END IF;
END PROCESS;
-
-- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
gen_jesd204b_rx_corepll_freqsel : IF g_jesd_freq = "200MHz" GENERATE
u_ip_arria10_e2sg_jesd204b_rx_corepll_200MHz : ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz
@@ -482,7 +478,6 @@ BEGIN
out_rst => mm_core_pll_locked_reg
);
-
-- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
-- Clock set to 100MHz (use rxlink_clk)
@@ -497,24 +492,23 @@ BEGIN
rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
);
- END GENERATE;
+ END GENERATE; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_enable_sync_n : FOR i IN 0 TO g_nof_streams-1 GENERATE
- -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
- -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
- -- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
- -- the sync_n_combined to become unavailable (see gen_group_sync_n).
-
+ -- The sync_n_enabled output is active '0'. For disabled signal inputs the sync_n_enabled output is forced to '1', so that for the disabled (= inactive = not used)
+ -- signal inputs the sync_n_internal from the JESD IP will not pull sync_n_enabled low.
+ -- The purpose of being able to disable inactive signal inputs is that this avoids that one inactive signal input will cause all signal inputs in a group that share
+ -- the sync_n_combined to become unavailable (see gen_group_sync_n).
- -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
- jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
+ -- For disabled channels (in jesd204b_disable_arr), the SYNC_N output will not be used
+ jesd204b_sync_n_enabled_arr(i) <= jesd204b_sync_n_internal_arr(i) OR jesd204b_disable_arr(i);
END GENERATE;
-----------------------------------------------------------------------------
-- Group the SYNC_N outputs
-----------------------------------------------------------------------------
gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
- jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
+ jesd204b_sync_n_combined_arr(i) <= vector_and(jesd204b_sync_n_enabled_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
END GENERATE;
-----------------------------------------------------------------------------
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index 490134d6585a1c4038e1561c1adca5c92f7c3be1..79a8465a5d6c85ac5bb1772d66cc98f605848739 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -12,6 +12,7 @@ synth_files =
tech_jesd204b_component_pkg.vhd
tech_jesd204b_arria10_e1sg.vhd
tech_jesd204b_arria10_e2sg.vhd
+ tech_jesd204b_pkg.vhd
tech_jesd204b.vhd
test_bench_files =
diff --git a/libraries/technology/jesd204b/registermap-jesd-rx.xlsx b/libraries/technology/jesd204b/registermap-jesd-rx.xlsx
new file mode 100644
index 0000000000000000000000000000000000000000..d3140dbbdefb8090558542b5fdf899ea0107f87b
Binary files /dev/null and b/libraries/technology/jesd204b/registermap-jesd-rx.xlsx differ
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index 8653d132d75b96794ef2fd80f55b31f38b6bedcf..5ead9f644645ad6af8a057b81ead9511c6444878 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -39,15 +39,18 @@ USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.tech_jesd204b_component_pkg.ALL;
+USE work.tech_jesd204b_pkg.ALL;
ENTITY tb_tech_jesd204b IS
END tb_tech_jesd204b;
ARCHITECTURE tb OF tb_tech_jesd204b IS
- CONSTANT c_sim : BOOLEAN := TRUE;
+ -- FALSE is use mm_clk in JESD IP, TRUE is use rxlink_clk as mm_clk in JESD IP
+ CONSTANT c_sim : BOOLEAN := FALSE; -- use FALSE as on HW, to verify jesd204b_rddata
CONSTANT c_jesd204b_sampclk_period : TIME := 5 ns;
CONSTANT c_bondingclk_period : TIME := 10 ns;
@@ -108,7 +111,7 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
SIGNAL bonding_clock_5 : STD_LOGIC := '0';
SIGNAL pll_locked : STD_LOGIC_VECTOR(0 downto 0);
- CONSTANT c_mm_clk_period : TIME := 20 ns;
+ CONSTANT c_mm_clk_period : TIME := 20 ns;
SIGNAL mm_clk : STD_LOGIC := '0';
-- Tb
@@ -120,7 +123,8 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
-- JESD
SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
-
+ SIGNAL jesd204b_rddata : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
-- serial transceivers
SIGNAL serial_tx : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
SIGNAL bck_rx : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 downto 0) := (others => '0');
@@ -168,7 +172,6 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
BEGIN
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -178,7 +181,6 @@ BEGIN
jesd204b_disable_arr <= (OTHERS => '0');
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -193,7 +195,6 @@ BEGIN
jesd204b_sysref => jesd204b_sysref_fpga,
jesd204b_sync_n_arr => jesd204b_sync_n_fpga,
-
jesd204b_disable_arr => jesd204b_disable_arr,
rx_sosi_arr => rx_sosi_arr,
@@ -213,7 +214,32 @@ BEGIN
serial_rx_arr => bck_rx(c_nof_streams_jesd204b-1 downto 0)
);
+ p_monitor_jesd204b : PROCESS
+ BEGIN
+ -- Wait until after MM interface reset_out5 = rx_avs_rst_arr in ip_arria10_e2sg_jesd204b has been released
+ WAIT UNTIL sim_done = '1';
+ proc_common_wait_some_cycles(mm_clk, 1); -- align with mm_clk domain
+
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err_enable_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ ASSERT UNSIGNED(jesd204b_rddata) = tech_jesd204b_field_rx_err_enable_reset
+ REPORT "Wrong rx_err_enable_reset: " & INTEGER'IMAGE(TO_SINT(jesd204b_rddata)) & " /= " & INTEGER'IMAGE(tech_jesd204b_field_rx_err_enable_reset) SEVERITY ERROR;
+
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err_link_reinit_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_common_wait_some_cycles(mm_clk, 1);
+ ASSERT UNSIGNED(jesd204b_rddata) = tech_jesd204b_field_rx_err_link_reinit_reset
+ REPORT "Wrong rx_err_link_reinit_reset: " & INTEGER'IMAGE(TO_SINT(jesd204b_rddata)) & " /= " & INTEGER'IMAGE(tech_jesd204b_field_rx_err_link_reinit_reset) SEVERITY ERROR;
+
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_syncn_sysref_ctrl_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err0_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_mem_mm_bus_rd(tech_jesd204b_field_rx_err1_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_mem_mm_bus_rd(tech_jesd204b_field_csr_rbd_count_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ proc_mem_mm_bus_rd(tech_jesd204b_field_csr_dev_syncn_adr, mm_clk, jesd204b_miso, jesd204b_mosi);
+ WAIT;
+ END PROCESS;
+ jesd204b_rddata <= jesd204b_miso.rddata(c_word_w-1 DOWNTO 0);
-----------------------------------------------------------------------------
-- Transport
diff --git a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
index a26e084526fa215b05ed95f4dda79816c5a8d29c..39125f424499c9c9c3793f229d2711024798dfa6 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
+++ b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
@@ -55,9 +55,14 @@ peripherals:
- - {field_name: rx_syncn_sysref_ctrl, mm_width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
- - {field_name: rx_csr_lmfc_offset, mm_width: 8, bit_offset: 12, access_mode: RW, address_offset: 0x54}
- - {field_name: rx_csr_rbd_offset, mm_width: 8, bit_offset: 3, access_mode: RW, address_offset: 0x54}
- - - {field_name: rx_csr_sysref_always_on, mm_width: 1, bit_offset: 1, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_sysref_singled, mm_width: 1, bit_offset: 2, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_sysref_alwayson, mm_width: 1, bit_offset: 1, access_mode: RW, address_offset: 0x54}
+ - - {field_name: rx_csr_link_reinit, mm_width: 1, bit_offset: 0, access_mode: RW, address_offset: 0x54}
+ - - {field_name: ctrl_reserve, mm_width: 32, bit_offset: 0, access_mode: RO, address_offset: 0x58}
- - {field_name: rx_err0, mm_width: 9, bit_offset: 0, access_mode: RW, address_offset: 0x60}
- - {field_name: rx_err1, mm_width: 10, bit_offset: 0, access_mode: RW, address_offset: 0x64}
+ - - {field_name: rx_err_enable, mm_width: 32, bit_offset: 0, access_mode: RW, address_offset: 0x74}
+ - - {field_name: rx_err_link_reinit, mm_width: 32, bit_offset: 0, access_mode: RW, address_offset: 0x78}
- - {field_name: csr_rbd_count, mm_width: 8, bit_offset: 3, access_mode: RO, address_offset: 0x80}
- - {field_name: csr_dev_syncn, mm_width: 1, bit_offset: 0, access_mode: RO, address_offset: 0x80}
- - {field_name: rx_status1, mm_width: 24, bit_offset: 0, access_mode: RW, address_offset: 0x84}
diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd
index d996d3682d5344dbaadd43cf1de9204d669739a2..d284c30a63cf29e13c519e30dd75c1b6e8ae587f 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b.vhd
@@ -135,14 +135,17 @@ BEGIN
g_sim => g_sim,
g_nof_streams => g_nof_streams,
g_nof_sync_n => g_nof_sync_n,
- g_direction => g_direction
+ g_direction => g_direction,
+ g_jesd_freq => g_jesd_freq
)
PORT MAP(
jesd204b_refclk => jesd204b_refclk,
jesd204b_sysref => jesd204b_sysref,
jesd204b_sync_n_arr => jesd204b_sync_n_arr,
- rx_src_out_arr => rx_sosi_arr,
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ rx_src_out_arr => rx_sosi_arr,
rx_clk => rx_clk,
rx_rst => rx_rst,
rx_sysref => rx_sysref,
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
index c6f97ec3e904b49fc32208a0391e7fe7c0b1e229..3eee9c0d838ff6d08fb89e9e5d0e99c19257f423 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
@@ -40,7 +40,8 @@ ENTITY tech_jesd204b_arria10_e2sg IS
g_sim : BOOLEAN := FALSE;
g_nof_streams : NATURAL := 12;
g_nof_sync_n : NATURAL := 12;
- g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : STRING := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_jesd_freq : STRING := "200MHz"
);
PORT (
-- JESD204B external signals
@@ -48,6 +49,8 @@ ENTITY tech_jesd204b_arria10_e2sg IS
jesd204b_sysref : IN STD_LOGIC := '0'; -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk
jesd204b_sync_n_arr : OUT STD_LOGIC_VECTOR(g_nof_sync_n-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+ jesd204b_disable_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+
-- Data to fabric
rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0); -- Parallel data out to fabric
rx_clk : OUT STD_LOGIC := '0'; -- Exported data clock (frame clock) to fabric
@@ -76,14 +79,17 @@ BEGIN
g_sim => g_sim,
g_nof_streams => g_nof_streams,
g_nof_sync_n => g_nof_sync_n,
- g_direction => g_direction
+ g_direction => g_direction,
+ g_jesd_freq => g_jesd_freq
)
PORT MAP(
jesd204b_refclk => jesd204b_refclk,
jesd204b_sysref => jesd204b_sysref,
jesd204b_sync_n_arr => jesd204b_sync_n_arr,
- rx_src_out_arr => rx_src_out_arr,
+ jesd204b_disable_arr => jesd204b_disable_arr,
+
+ rx_src_out_arr => rx_src_out_arr,
rx_clk => rx_clk,
rx_rst => rx_rst,
rx_sysref => rx_sysref,
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index b3eeb7fd74d1395b249ddd07e7cc541a2b6c80fd..aae8250e228204bb0d2622157af1efd60cb5a3eb 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -139,7 +139,8 @@ PACKAGE tech_jesd204b_component_pkg IS
g_sim : BOOLEAN := FALSE;
g_nof_streams : NATURAL := 1;
g_nof_sync_n : NATURAL := 1;
- g_direction : STRING := "RX_ONLY" -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_direction : STRING := "RX_ONLY"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
+ g_jesd_freq : STRING := "200MHz"
);
PORT (
-- JESD204B external signals
@@ -157,6 +158,8 @@ PACKAGE tech_jesd204b_component_pkg IS
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
+ jesd204b_disable_arr : IN STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+
jesd204b_mosi : IN t_mem_mosi; -- mm control
jesd204b_miso : OUT t_mem_miso;
diff --git a/libraries/technology/jesd204b/tech_jesd204b_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1279e699baa38ce62f44d16f77c940699a5ee676
--- /dev/null
+++ b/libraries/technology/jesd204b/tech_jesd204b_pkg.vhd
@@ -0,0 +1,73 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Test bench parameters for the JESD204B IP.
+-- Description:
+-- Remark:
+-- . From:
+-- - registermap-jesd-rx.xlsx
+-- - JESD204B Intel® FPGA IP User Guide, Updated for Intel® Quartus® Prime
+-- Design Suite: 19.4, IP Version: 19.2.0
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, technology_lib;
+USE IEEE.std_logic_1164.ALL;
+
+PACKAGE tech_jesd204b_pkg IS
+
+ -- Intel ARRIA10 IP MM interface
+ -- . JESD204B MM has 256 bytes = 64 words, so span_w = 6 would be enough,
+ -- but using span_w = 8 and span = 256 words is fine too.
+ CONSTANT tech_jesd204b_port_span_w : NATURAL := 8;
+ CONSTANT tech_jesd204b_port_span : NATURAL := 2**tech_jesd204b_port_span_w;
+
+ CONSTANT tech_jesd204b_field_rx_syncn_sysref_ctrl_adr : NATURAL := 16#54# / 4;
+ CONSTANT tech_jesd204b_field_rx_syncn_sysref_ctrl_link_reinit : NATURAL := 1;
+ CONSTANT tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_singled : NATURAL := 2;
+ CONSTANT tech_jesd204b_field_rx_syncn_sysref_ctrl_sysref_alwayson : NATURAL := 4;
+
+ CONSTANT tech_jesd204b_field_rx_err0_adr : NATURAL := 16#60# / 4;
+ CONSTANT tech_jesd204b_field_rx_err0_w : NATURAL := 9;
+ CONSTANT tech_jesd204b_field_rx_err0_lo : NATURAL := 0;
+ CONSTANT tech_jesd204b_field_rx_err0_hi : NATURAL := tech_jesd204b_field_rx_err0_w-1 + tech_jesd204b_field_rx_err0_lo;
+ CONSTANT tech_jesd204b_field_rx_err1_adr : NATURAL := 16#64# / 4;
+ CONSTANT tech_jesd204b_field_rx_err1_w : NATURAL := 10;
+ CONSTANT tech_jesd204b_field_rx_err1_lo : NATURAL := 0;
+ CONSTANT tech_jesd204b_field_rx_err1_hi : NATURAL := tech_jesd204b_field_rx_err1_w-1 + tech_jesd204b_field_rx_err1_lo;
+
+ CONSTANT tech_jesd204b_field_rx_err_enable_adr : NATURAL := 16#74# / 4;
+ CONSTANT tech_jesd204b_field_rx_err_enable_reset : INTEGER := 16#17F9FE#;
+ CONSTANT tech_jesd204b_field_rx_err_link_reinit_adr : NATURAL := 16#78# / 4;
+ CONSTANT tech_jesd204b_field_rx_err_link_reinit_reset : INTEGER := 16#3902#;
+
+ CONSTANT tech_jesd204b_field_csr_rbd_count_adr : NATURAL := 16#80# / 4;
+ CONSTANT tech_jesd204b_field_csr_rbd_count_w : NATURAL := 8;
+ CONSTANT tech_jesd204b_field_csr_rbd_count_lo : NATURAL := 3;
+ CONSTANT tech_jesd204b_field_csr_rbd_count_hi : NATURAL := tech_jesd204b_field_csr_rbd_count_w-1 + tech_jesd204b_field_csr_rbd_count_lo;
+ CONSTANT tech_jesd204b_field_csr_dev_syncn_adr : NATURAL := 16#80# / 4;
+ CONSTANT tech_jesd204b_field_csr_dev_syncn_w : NATURAL := 1;
+ CONSTANT tech_jesd204b_field_csr_dev_syncn_lo : NATURAL := 0;
+ CONSTANT tech_jesd204b_field_csr_dev_syncn_hi : NATURAL := tech_jesd204b_field_csr_dev_syncn_w-1 + tech_jesd204b_field_csr_dev_syncn_lo;
+
+END tech_jesd204b_pkg;
+
+PACKAGE BODY tech_jesd204b_pkg IS
+END tech_jesd204b_pkg;