diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/hdllib.cfg b/boards/uniboard2b/libraries/unb2b_board_10gbe/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..b0c75a7f6bab392db7abcf935d590770056c9a21 --- /dev/null +++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/hdllib.cfg @@ -0,0 +1,17 @@ +hdl_lib_name = unb2b_board_10gbe +hdl_library_clause_name = unb2b_board_10gbe_lib +hdl_lib_uses_synth = common dp technology tech_pll tr_10GbE +hdl_lib_uses_sim = +hdl_lib_technology = ip_arria10_e1sg + +synth_files = + src/vhdl/unb2_board_10gbe.vhd + +test_bench_files = + + +[modelsim_project_file] + + +[quartus_project_file] + diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd new file mode 100644 index 0000000000000000000000000000000000000000..2697eca6757b890e75d53e6227f731d421c0c6b5 --- /dev/null +++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd @@ -0,0 +1,140 @@ +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2015 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_pll_lib, tr_10GbE_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE technology_lib.technology_pkg.ALL; + + +ENTITY unb2_board_10gbe IS + GENERIC ( + g_sim : BOOLEAN := FALSE; + g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model + g_technology : NATURAL := c_tech_arria10; + g_nof_macs : NATURAL; + g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available, + g_tx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed) + g_rx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed) + g_word_alignment_padding : BOOLEAN := FALSE + ); + PORT ( + tr_ref_clk : IN STD_LOGIC := '0'; + + -- MM interface + mm_rst : IN STD_LOGIC; + mm_clk : IN STD_LOGIC; + + reg_mac_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_mac_miso : OUT t_mem_miso; + + reg_eth10g_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- ETH10G (link status register) + reg_eth10g_miso : OUT t_mem_miso; + + reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : IN t_mem_mosi := c_mem_mosi_rst; + reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : OUT t_mem_miso; + + -- DP interface + dp_rst : IN STD_LOGIC := '0'; + dp_clk : IN STD_LOGIC := '0'; + + snk_out_arr : OUT t_dp_siso_arr(g_nof_macs-1 DOWNTO 0); + snk_in_arr : IN t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst); + + src_in_arr : IN t_dp_siso_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy); + src_out_arr : OUT t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0); + + -- Serial IO + serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 downto 0); + serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 downto 0) := (OTHERS=>'0') + ); +END unb2_board_10gbe; + + +ARCHITECTURE str OF unb2_board_10gbe IS + + SIGNAL tr_ref_clk_312 : STD_LOGIC; + SIGNAL tr_ref_clk_156 : STD_LOGIC; + SIGNAL tr_ref_rst_156 : STD_LOGIC; + +BEGIN + u_unb2_board_clk644_pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks + GENERIC MAP ( + g_technology => g_technology + ) + PORT MAP ( + refclk_644 => tr_ref_clk, + rst_in => mm_rst, + clk_156 => tr_ref_clk_156, + clk_312 => tr_ref_clk_312, + rst_156 => tr_ref_rst_156, + rst_312 => OPEN + ); + + + u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE + GENERIC MAP ( + g_technology => g_technology, + g_sim => g_sim, + g_sim_level => 1, + g_nof_macs => g_nof_macs, + g_tx_fifo_fill => g_tx_fifo_fill, + g_tx_fifo_size => g_tx_fifo_size + ) + PORT MAP ( + -- Transceiver PLL reference clock + tr_ref_clk_644 => tr_ref_clk, + tr_ref_clk_312 => tr_ref_clk_312, -- 312.5 MHz for 10GBASE-R + tr_ref_clk_156 => tr_ref_clk_156, -- 156.25 MHz for 10GBASE-R or for XAUI + tr_ref_rst_156 => tr_ref_rst_156, -- for 10GBASE-R or for XAUI + + -- MM interface + mm_rst => mm_rst, + mm_clk => mm_clk, + + reg_mac_mosi => reg_mac_mosi, + reg_mac_miso => reg_mac_miso, + + reg_eth10g_mosi => reg_eth10g_mosi, + reg_eth10g_miso => reg_eth10g_miso, + + reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi => reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi, + reg_ip_arria10_e1sg_phy_10gbase_r_24_miso => reg_ip_arria10_e1sg_phy_10gbase_r_24_miso, + + -- DP interface + dp_rst => dp_rst, + dp_clk => dp_clk, + + src_out_arr => src_out_arr, + src_in_arr => src_in_arr, + + snk_out_arr => snk_out_arr, + snk_in_arr => snk_in_arr, + + -- Serial IO + serial_tx_arr => serial_tx_arr, + serial_rx_arr => serial_rx_arr + ); + +END str;